3,5c3,5
< sim_seconds 47.461935 # Number of seconds simulated
< sim_ticks 47461934895000 # Number of ticks simulated
< final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.496138 # Number of seconds simulated
> sim_ticks 47496138032000 # Number of ticks simulated
> final_tick 47496138032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 231788 # Simulator instruction rate (inst/s)
< host_op_rate 272612 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 12136870284 # Simulator tick rate (ticks/s)
< host_mem_usage 762440 # Number of bytes of host memory used
< host_seconds 3910.56 # Real time elapsed on the host
< sim_insts 906421729 # Number of instructions simulated
< sim_ops 1066065309 # Number of ops (including micro ops) simulated
---
> host_inst_rate 287392 # Simulator instruction rate (inst/s)
> host_op_rate 338020 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15163142641 # Simulator tick rate (ticks/s)
> host_mem_usage 759192 # Number of bytes of host memory used
> host_seconds 3132.34 # Real time elapsed on the host
> sim_insts 900209792 # Number of instructions simulated
> sim_ops 1058792792 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory
< system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 123968 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 99904 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 7981184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 13323912 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 15275072 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 135168 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 122048 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3081152 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 10821968 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 12736320 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 446656 # Number of bytes read from this memory
> system.physmem.bytes_read::total 64147352 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 7981184 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3081152 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 11062336 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 76613760 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 76634344 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 1937 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 1561 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 124706 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 208199 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 238673 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2112 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1907 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 48143 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 169106 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 199005 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6979 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1002328 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1197090 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1199664 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2610 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 2103 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 168039 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 280526 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 321607 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 2846 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2570 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 64872 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 227849 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 268155 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9404 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1350580 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 168039 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 64872 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 232910 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1613052 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
69,93c69,93
< system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1562015 # Number of read requests accepted
< system.physmem.writeReqs 1242432 # Number of write requests accepted
< system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue
< system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 1613486 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1613052 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2610 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 2103 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 168039 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 280960 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 321607 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 2846 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2570 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 64872 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 227850 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 268155 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9404 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2964066 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1002328 # Number of read requests accepted
> system.physmem.writeReqs 1199664 # Number of write requests accepted
> system.physmem.readBursts 1002328 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1199664 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 64118976 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 30016 # Total number of bytes read from write queue
> system.physmem.bytesWritten 76632896 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 64147352 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 76634344 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 469 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
95,126c95,126
< system.physmem.perBankRdBursts::0 93757 # Per bank write bursts
< system.physmem.perBankRdBursts::1 100629 # Per bank write bursts
< system.physmem.perBankRdBursts::2 93977 # Per bank write bursts
< system.physmem.perBankRdBursts::3 99615 # Per bank write bursts
< system.physmem.perBankRdBursts::4 97211 # Per bank write bursts
< system.physmem.perBankRdBursts::5 108899 # Per bank write bursts
< system.physmem.perBankRdBursts::6 95410 # Per bank write bursts
< system.physmem.perBankRdBursts::7 95079 # Per bank write bursts
< system.physmem.perBankRdBursts::8 84413 # Per bank write bursts
< system.physmem.perBankRdBursts::9 140545 # Per bank write bursts
< system.physmem.perBankRdBursts::10 87149 # Per bank write bursts
< system.physmem.perBankRdBursts::11 92128 # Per bank write bursts
< system.physmem.perBankRdBursts::12 89605 # Per bank write bursts
< system.physmem.perBankRdBursts::13 97795 # Per bank write bursts
< system.physmem.perBankRdBursts::14 91413 # Per bank write bursts
< system.physmem.perBankRdBursts::15 93857 # Per bank write bursts
< system.physmem.perBankWrBursts::0 74634 # Per bank write bursts
< system.physmem.perBankWrBursts::1 80843 # Per bank write bursts
< system.physmem.perBankWrBursts::2 76779 # Per bank write bursts
< system.physmem.perBankWrBursts::3 81501 # Per bank write bursts
< system.physmem.perBankWrBursts::4 79021 # Per bank write bursts
< system.physmem.perBankWrBursts::5 86869 # Per bank write bursts
< system.physmem.perBankWrBursts::6 77167 # Per bank write bursts
< system.physmem.perBankWrBursts::7 78926 # Per bank write bursts
< system.physmem.perBankWrBursts::8 71646 # Per bank write bursts
< system.physmem.perBankWrBursts::9 75252 # Per bank write bursts
< system.physmem.perBankWrBursts::10 73334 # Per bank write bursts
< system.physmem.perBankWrBursts::11 76259 # Per bank write bursts
< system.physmem.perBankWrBursts::12 74746 # Per bank write bursts
< system.physmem.perBankWrBursts::13 79667 # Per bank write bursts
< system.physmem.perBankWrBursts::14 75302 # Per bank write bursts
< system.physmem.perBankWrBursts::15 78217 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 52312 # Per bank write bursts
> system.physmem.perBankRdBursts::1 66235 # Per bank write bursts
> system.physmem.perBankRdBursts::2 59334 # Per bank write bursts
> system.physmem.perBankRdBursts::3 65978 # Per bank write bursts
> system.physmem.perBankRdBursts::4 61446 # Per bank write bursts
> system.physmem.perBankRdBursts::5 69476 # Per bank write bursts
> system.physmem.perBankRdBursts::6 59128 # Per bank write bursts
> system.physmem.perBankRdBursts::7 60480 # Per bank write bursts
> system.physmem.perBankRdBursts::8 57677 # Per bank write bursts
> system.physmem.perBankRdBursts::9 110303 # Per bank write bursts
> system.physmem.perBankRdBursts::10 51521 # Per bank write bursts
> system.physmem.perBankRdBursts::11 60498 # Per bank write bursts
> system.physmem.perBankRdBursts::12 54125 # Per bank write bursts
> system.physmem.perBankRdBursts::13 57278 # Per bank write bursts
> system.physmem.perBankRdBursts::14 58648 # Per bank write bursts
> system.physmem.perBankRdBursts::15 57420 # Per bank write bursts
> system.physmem.perBankWrBursts::0 71344 # Per bank write bursts
> system.physmem.perBankWrBursts::1 78863 # Per bank write bursts
> system.physmem.perBankWrBursts::2 73221 # Per bank write bursts
> system.physmem.perBankWrBursts::3 79189 # Per bank write bursts
> system.physmem.perBankWrBursts::4 75543 # Per bank write bursts
> system.physmem.perBankWrBursts::5 82829 # Per bank write bursts
> system.physmem.perBankWrBursts::6 74512 # Per bank write bursts
> system.physmem.perBankWrBursts::7 77237 # Per bank write bursts
> system.physmem.perBankWrBursts::8 71961 # Per bank write bursts
> system.physmem.perBankWrBursts::9 73593 # Per bank write bursts
> system.physmem.perBankWrBursts::10 69363 # Per bank write bursts
> system.physmem.perBankWrBursts::11 76682 # Per bank write bursts
> system.physmem.perBankWrBursts::12 71227 # Per bank write bursts
> system.physmem.perBankWrBursts::13 74509 # Per bank write bursts
> system.physmem.perBankWrBursts::14 73049 # Per bank write bursts
> system.physmem.perBankWrBursts::15 74267 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 64 # Number of times write queue was full causing retry
< system.physmem.totGap 47461932782500 # Total gap between requests
---
> system.physmem.numWrRetry 57 # Number of times write queue was full causing retry
> system.physmem.totGap 47496135919500 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1561985 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1002298 # Read request sizes (log2)
143,168c143,168
< system.physmem.writePktSize::6 1239858 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1197090 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 675393 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 118123 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 43619 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 33801 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 29137 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 27086 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 24475 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 22026 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 18598 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 3546 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1664 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1196 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 985 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 727 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 426 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
191,295c191,295
< system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.wrQLenPdf::15 31163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 38080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 51935 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 55190 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 60170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 62406 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 65836 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 70016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 72724 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 73495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 74816 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 77871 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 75261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 76182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 84001 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 74766 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 69103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 66691 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 3873 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 2118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1059 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 826 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 535 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 498 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 421 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 364 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 377 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 346 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 301 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 220 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 167 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 993836 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 141.624332 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 96.550200 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 190.035765 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 676204 68.04% 68.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 192250 19.34% 87.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 44807 4.51% 91.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 21137 2.13% 94.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 15251 1.53% 95.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 9933 1.00% 96.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5714 0.57% 97.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4523 0.46% 97.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 24017 2.42% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 993836 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 62276 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 16.086984 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 158.174793 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 62273 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 62276 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 62276 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.227134 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.463029 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 8.016188 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 49891 80.11% 80.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 5512 8.85% 88.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 3034 4.87% 93.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 1650 2.65% 96.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 463 0.74% 97.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 302 0.48% 97.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 265 0.43% 98.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 82 0.13% 98.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 283 0.45% 98.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 77 0.12% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 32 0.05% 98.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 49 0.08% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 248 0.40% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 39 0.06% 99.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 31 0.05% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 106 0.17% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 143 0.23% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 4 0.01% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 4 0.01% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 5 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 12 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 5 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads
297c297
< system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
299,308c299,307
< system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads
< system.physmem.totQLat 43176438588 # Total ticks spent queuing
< system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 62276 # Writes before turning the bus around for reads
> system.physmem.totQLat 32552700191 # Total ticks spent queuing
> system.physmem.totMemAccLat 51337556441 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 5009295000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 32492.30 # Average queueing delay per DRAM burst
310,314c309,313
< system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 51242.30 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.35 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.61 # Average system write bandwidth in MiByte/s
316,317c315,316
< system.physmem.busUtil 0.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 0.02 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
319,337c318,336
< system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing
< system.physmem.readRowHits 1247973 # Number of row buffer hits during reads
< system.physmem.writeRowHits 562447 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes
< system.physmem.avgGap 16923811.64 # Average gap between requests
< system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.805156 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states
---
> system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing
> system.physmem.readRowHits 748874 # Number of row buffer hits during reads
> system.physmem.writeRowHits 456536 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 74.75 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 38.13 # Row buffer hit rate for writes
> system.physmem.avgGap 21569622.38 # Average gap between requests
> system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3877765920 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2115844500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 3856171800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3970542240 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1199773763640 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27445246701750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31761057298410 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.708277 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45657180846254 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1586000260000 # Time in different power states
339c338
< system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 252951953746 # Time in different power states
341,351c340,350
< system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.767346 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states
---
> system.physmem_1.actEnergy 3635634240 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1983729000 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 3958266000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3788538480 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1194664304160 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27449728675500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31759975655940 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.685504 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45664625089280 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1586000260000 # Time in different power states
353c352
< system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 245507696970 # Time in different power states
387,391c386,390
< system.cpu0.branchPred.lookups 141158417 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 138061860 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 98120507 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 6229967 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 103103324 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 75422199 # Number of BTB hits
393,395c392,394
< system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 73.152054 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 16055942 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 1103312 # Number of incorrect RAS predictions.
426,443c425,442
< system.cpu0.dtb.walker.walks 283140 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walks 287097 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 287097 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9253 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79328 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 287097 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 287097 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 287097 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 88581 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 87487 98.76% 98.76% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 212 0.24% 99.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 756 0.85% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
445,448c444,446
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 88581 # Table walker service (enqueue to completion) latency
452,455c450,453
< system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 79328 89.55% 89.55% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 9253 10.45% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 88581 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 287097 # Table walker requests started/completed, data/inst
457,458c455,456
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 287097 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 88581 # Table walker requests started/completed, data/inst
460,461c458,459
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 88581 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 375678 # Table walker requests started/completed, data/inst
464,467c462,465
< system.cpu0.dtb.read_hits 90921588 # DTB read hits
< system.cpu0.dtb.read_misses 233548 # DTB read misses
< system.cpu0.dtb.write_hits 80603054 # DTB write hits
< system.cpu0.dtb.write_misses 49592 # DTB write misses
---
> system.cpu0.dtb.read_hits 87655759 # DTB read hits
> system.cpu0.dtb.read_misses 237615 # DTB read misses
> system.cpu0.dtb.write_hits 78096829 # DTB write hits
> system.cpu0.dtb.write_misses 49482 # DTB write misses
470,474c468,472
< system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 36184 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 2196 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 9698 # Number of TLB faults due to prefetch
476,478c474,476
< system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 91155136 # DTB read accesses
< system.cpu0.dtb.write_accesses 80652646 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 11726 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 87893374 # DTB read accesses
> system.cpu0.dtb.write_accesses 78146311 # DTB write accesses
480,482c478,480
< system.cpu0.dtb.hits 171524642 # DTB hits
< system.cpu0.dtb.misses 283140 # DTB misses
< system.cpu0.dtb.accesses 171807782 # DTB accesses
---
> system.cpu0.dtb.hits 165752588 # DTB hits
> system.cpu0.dtb.misses 287097 # DTB misses
> system.cpu0.dtb.accesses 166039685 # DTB accesses
512,530c510,528
< system.cpu0.itb.walker.walks 66290 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 66101 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 66101 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 650 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56681 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 66101 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 66101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 66101 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 57331 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 56305 98.21% 98.21% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 11 0.02% 98.23% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 903 1.58% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
532c530
< system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walkCompletionTime::total 57331 # Table walker service (enqueue to completion) latency
536,538c534,536
< system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 56681 98.87% 98.87% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 650 1.13% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 57331 # Table walker page sizes translated
540,541c538,539
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66101 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66101 # Table walker requests started/completed, data/inst
543,547c541,545
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 252665762 # ITB inst hits
< system.cpu0.itb.inst_misses 66290 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57331 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57331 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 123432 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 246672238 # ITB inst hits
> system.cpu0.itb.inst_misses 66101 # ITB inst misses
554,556c552,554
< system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 25870 # Number of entries that have been flushed from TLB
560c558
< system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 211969 # Number of TLB faults due to permissions restrictions
563,567c561,565
< system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses
< system.cpu0.itb.hits 252665762 # DTB hits
< system.cpu0.itb.misses 66290 # DTB misses
< system.cpu0.itb.accesses 252732052 # DTB accesses
< system.cpu0.numCycles 1081051562 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 246738339 # ITB inst accesses
> system.cpu0.itb.hits 246672238 # DTB hits
> system.cpu0.itb.misses 66101 # DTB misses
> system.cpu0.itb.accesses 246738339 # DTB accesses
> system.cpu0.numCycles 1042581150 # number of cpu cycles simulated
570,576c568,574
< system.cpu0.committedInsts 468741146 # Number of instructions committed
< system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.306287 # CPI: cycles per instruction
< system.cpu0.ipc 0.433597 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 455270721 # Number of instructions committed
> system.cpu0.committedOps 534899361 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 47095692 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 4288 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 93950410811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.290025 # CPI: cycles per instruction
> system.cpu0.ipc 0.436677 # IPC: instructions per cycle
578,585c576,583
< system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed
< system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 5850262 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks.
---
> system.cpu0.kern.inst.quiesce 13221 # number of quiesce instructions executed
> system.cpu0.tickCycles 736979138 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 305602012 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 5679788 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 503.382728 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 157129733 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5680300 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 27.662224 # Average number of references to valid blocks.
587,589c585,587
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.382728 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983169 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.983169 # Average percentage of cache occupancy
591,593c589,591
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 439 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
595,686c593,684
< system.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits
< system.cpu0.dcache.overall_hits::total 158297489 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses
< system.cpu0.dcache.overall_misses::total 6741698 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 334387337 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 334387337 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 80268736 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 80268736 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 72233903 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 72233903 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 277349 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 277349 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 251788 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 251788 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1785654 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1785654 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1744754 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1744754 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 152502639 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 152502639 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 152779988 # number of overall hits
> system.cpu0.dcache.overall_hits::total 152779988 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3412741 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3412741 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 2489296 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 2489296 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686937 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 686937 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801634 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 801634 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154902 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 154902 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194385 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 194385 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 5902037 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 5902037 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 6588974 # number of overall misses
> system.cpu0.dcache.overall_misses::total 6588974 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 58848858500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 58848858500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63605542500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 63605542500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 48599001500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 48599001500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2502004000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2502004000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5451875000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 5451875000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6380500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6380500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 122454401000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 122454401000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 83681477 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 83681477 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 74723199 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 74723199 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964286 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 964286 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1053422 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 1053422 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1940556 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 1940556 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1939139 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 1939139 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 158404676 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 158404676 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 159368962 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 159368962 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040783 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.040783 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033314 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.033314 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.712379 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.712379 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760981 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760981 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079824 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079824 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100243 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100243 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037259 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.037259 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041344 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.041344 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590 # average StoreCondReq miss latency
689,692c687,690
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20747.819948 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 20747.819948 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18584.744909 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 18584.744909 # average overall miss latency
701,790c699,788
< system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks
< system.cpu0.dcache.writebacks::total 5850286 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 5679821 # number of writebacks
> system.cpu0.dcache.writebacks::total 5679821 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423726 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 423726 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1038452 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1038452 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 85 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 85 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41327 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41327 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1462178 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1462178 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1462178 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1462178 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2989015 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 2989015 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1450844 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1450844 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685285 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 685285 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801549 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 801549 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113575 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113575 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194342 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 194342 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4439859 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4439859 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5125144 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5125144 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32143 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63696 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46000579500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46000579500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36719986000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36719986000 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17989395000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17989395000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 47789065000 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 47789065000 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1631247500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1631247500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5254690500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5254690500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6005000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6005000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82720565500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 82720565500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100709960500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 100709960500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6124425500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6124425500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5931269500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5931269500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12055695000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12055695000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035719 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035719 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019416 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019416 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710666 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710666 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760900 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760900 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058527 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058527 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100221 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100221 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028029 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028029 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032159 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.032159 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15389.879107 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15389.879107 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25309.396462 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25309.396462 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26250.968575 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26250.968575 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59620.890301 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59620.890301 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14362.733876 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14362.733876 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27038.367929 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.367929 # average StoreCondReq mshr miss latency
793,802c791,800
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18631.349667 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19650.171878 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19650.171878 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190536.835392 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190536.835392 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187977.989415 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187977.989415 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189269.263376 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189269.263376 # average overall mshr uncacheable latency
804,812c802,810
< system.cpu0.icache.tags.replacements 9594128 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 9549530 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.897064 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 236903550 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 9550042 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 24.806545 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897064 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy
814,816c812,814
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
818,855c816,853
< system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits
< system.cpu0.icache.overall_hits::total 242861120 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses
< system.cpu0.icache.overall_misses::total 9594650 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 502457255 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 502457255 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 236903550 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 236903550 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 236903550 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 236903550 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 236903550 # number of overall hits
> system.cpu0.icache.overall_hits::total 236903550 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 9550052 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 9550052 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 9550052 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 9550052 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 9550052 # number of overall misses
> system.cpu0.icache.overall_misses::total 9550052 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101421985500 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 101421985500 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 101421985500 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 101421985500 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 101421985500 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 101421985500 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 246453602 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 246453602 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 246453602 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 246453602 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 246453602 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 246453602 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038750 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.038750 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038750 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.038750 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038750 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.038750 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10620.045367 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10620.045367 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10620.045367 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10620.045367 # average overall miss latency
864,871c862,869
< system.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks
< system.cpu0.icache.writebacks::total 9594128 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 9549530 # number of writebacks
> system.cpu0.icache.writebacks::total 9549530 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9550052 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 9550052 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 9550052 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 9550052 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 9550052 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 9550052 # number of overall MSHR misses
876,881c874,879
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 96646960000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 96646960000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 96646960000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 96646960000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 96646960000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 96646960000 # number of overall MSHR miss cycles
886,897c884,895
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038750 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.038750 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.038750 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10120.045420 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency
903,905c901,903
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7772165 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7773534 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 1208 # number of redundant prefetches already in prefetch queue
908,974c906,971
< system.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2949800 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5504 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7511 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 526 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.072388 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 520895158 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 520895158 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527427 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 170829 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 698256 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 3866912 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 3866912 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 11575004 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 11575004 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 494 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 494 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 901398 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 901398 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8819397 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 8819397 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2877090 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2877090 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196747 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 196747 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527427 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 170829 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 8819397 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3778488 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 13296141 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527427 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 170829 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 8819397 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3778488 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 13296141 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12512 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8836 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 21348 # number of ReadReq misses
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 991570 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2865211 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16182.470551 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 23591597 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2881428 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 8.187467 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15283.265421 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.779936 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.474522 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 783.950672 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.932816 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003710 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003325 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047849 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.987700 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1265 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14897 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 535 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 58 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 45 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5291 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7937 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 458 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077209 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909241 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 513878817 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 513878817 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 534301 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 171000 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 705301 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 3781367 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 3781367 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 11445215 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 11445215 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 428 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 428 # number of UpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 897370 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 897370 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8796749 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 8796749 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2760570 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2760570 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 203097 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 203097 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 534301 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 171000 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 8796749 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3657940 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 13159990 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 534301 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 171000 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 8796749 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3657940 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 13159990 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12394 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8896 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 21290 # number of ReadReq misses
977,1061c974,1060
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 265863 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 265863 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 207797 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 207797 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295222 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 295222 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 775252 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 775252 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1066801 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1066801 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607029 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 607029 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12512 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8836 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 775252 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1362023 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 2158623 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12512 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8836 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 775252 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1362023 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 2158623 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 555558000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 430868000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 986426000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3493305000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 3493305000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1939943000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1939943000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4477498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4477498 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18708847499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 18708847499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30179302500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30179302500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44632390995 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44632390995 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67815733000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 67815733000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 555558000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 430868000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 30179302500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 63341238494 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 94506966994 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 555558000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 430868000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 30179302500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 63341238494 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 94506966994 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 539939 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179665 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 719604 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3866914 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 3866914 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 11575004 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 11575004 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266357 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 266357 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 207797 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 207797 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196620 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1196620 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9594649 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 9594649 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3943891 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3943891 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803776 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 803776 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 539939 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179665 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 9594649 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5140511 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 15454764 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 539939 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179665 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 9594649 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5140511 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 15454764 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049180 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.029666 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
> system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 263050 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 263050 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 194335 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 194335 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 298989 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 298989 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 753302 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 753302 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1026998 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1026998 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 596103 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 596103 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12394 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8896 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 753302 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1325987 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2100579 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12394 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8896 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 753302 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1325987 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2100579 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 543058500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 406297500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 949356000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3394715000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 3394715000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1886445500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1886445500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5898999 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5898999 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19173654497 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 19173654497 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29218782500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29218782500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41703375488 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41703375488 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 451954500 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 451954500 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 543058500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406297500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29218782500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 60877029985 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 91045168485 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 543058500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 406297500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29218782500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 60877029985 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 91045168485 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 546695 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179896 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 726591 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3781369 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 3781369 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 11445216 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 11445216 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 263478 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 263478 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194335 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 194335 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196359 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1196359 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9550051 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 9550051 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3787568 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3787568 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 799200 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 799200 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 546695 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179896 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 9550051 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 4983927 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 15260569 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 546695 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179896 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 9550051 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 4983927 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 15260569 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049451 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.029301 # miss rate for ReadReq accesses
1064,1065c1063,1066
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998145 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998145 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
> system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998376 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998376 # miss rate for UpgradeReq accesses
1070,1114c1071,1115
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.246713 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.246713 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.080800 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.080800 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270495 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270495 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755222 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755222 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049180 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080800 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264959 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.139674 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049180 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080800 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264959 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.139674 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48762.788592 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46206.951471 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13139.492897 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13139.492897 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9335.760382 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9335.760382 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 497499.777778 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 497499.777778 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63372.131816 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63372.131816 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38928.377482 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38928.377482 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41837.597635 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41837.597635 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 111717.451720 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 111717.451720 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 43781.135934 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 43781.135934 # average overall miss latency
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.249916 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.249916 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078879 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.078879 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.271150 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.271150 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.745875 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.745875 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049451 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078879 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.266053 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.137647 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049451 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078879 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.266053 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.137647 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45671.931205 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44591.639267 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12905.208135 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12905.208135 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9707.183472 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9707.183472 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842714.142857 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842714.142857 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64128.294007 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64128.294007 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38787.607759 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38787.607759 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 40607.065922 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 40607.065922 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 758.181891 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 758.181891 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45671.931205 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38787.607759 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45910.729129 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 43342.891881 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45671.931205 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38787.607759 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45910.729129 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 43342.891881 # average overall miss latency
1123,1148c1124,1146
< system.cpu0.l2cache.writebacks::writebacks 1702054 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1702054 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8173 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 8173 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1611 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1611 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9784 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 9799 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9784 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 9799 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12511 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8833 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 21344 # number of ReadReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 1676207 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1676207 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9778 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 9778 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1426 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1426 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11204 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 11215 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11204 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 11215 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12394 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8894 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 21288 # number of ReadReq MSHR misses
1151,1177c1149,1177
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 812970 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 265863 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 265863 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 207797 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 207797 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 287049 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 287049 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 775241 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 775241 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1065190 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1065190 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 607025 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 607025 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12511 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8833 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 775241 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1352239 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 2148824 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12511 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8833 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 775241 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1352239 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2961794 # number of overall MSHR misses
---
> system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
> system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 800672 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 800672 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 263050 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 263050 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 194335 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 194335 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289211 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 289211 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 753293 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 753293 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1025572 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1025572 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 596100 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 596100 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12394 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8894 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 753293 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1314783 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2089364 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12394 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8894 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 753293 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1314783 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 800672 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2890036 # number of overall MSHR misses
1179,1182c1179,1182
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71839 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84452 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable
1184,1215c1184,1215
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 92887 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 377798500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 858266500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44849426201 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7795522498 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7795522498 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4002040000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4002040000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4147498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4147498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15893166999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15893166999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25527386000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25527386000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38109816995 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38109816995 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64173364000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 116005 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 352893500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 821588000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47791541037 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47791541037 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7826601497 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7826601497 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3792362000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3792362000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5478999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5478999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16008058497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16008058497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 24698519500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 24698519500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 35410416988 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 35410416988 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 41536789000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 41536789000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 352893500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 24698519500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51418475485 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 76938582985 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 352893500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24698519500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51418475485 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47791541037 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 124730124022 # number of overall MSHR miss cycles
1217,1220c1217,1220
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5867073000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12863228000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5694540000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5694540000 # number of WriteReq MSHR uncacheable cycles
1222,1226c1222,1226
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561613000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18557768000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029298 # mshr miss rate for ReadReq accesses
1228a1229,1230
> system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
> system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1231,1232c1233,1234
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998376 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998376 # mshr miss rate for UpgradeReq accesses
1237,1253c1239,1255
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.241743 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.241743 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078878 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270773 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270773 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.745871 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.745871 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136913 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for overall accesses
1255,1285c1257,1287
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189379 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848 # average overall mshr miss latency
1287,1290c1289,1292
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613 # average WriteReq mshr uncacheable latency
1292,1293c1294,1295
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196 # average overall mshr uncacheable latency
1295,1333c1297,1335
< system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 31336515 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16003499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2764 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238925 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238443 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 482 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 888197 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 14329408 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 31554 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 31553 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 5463883 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 11447979 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 3030252 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1046563 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 472775 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352055 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 529438 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1230630 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1206068 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9550052 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4850843 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 854414 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 799200 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28754250 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18474160 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377323 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1153011 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 48758744 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1225720896 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 689935275 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4373560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1921468899 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 7541383 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 23989921 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.106643 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.308724 # Request fanout histogram
1335,1337c1337,1339
< system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 21432051 89.34% 89.34% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 2557388 10.66% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 482 0.00% 100.00% # Request fanout histogram
1341,1342c1343,1344
< system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 23989921 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 31215182485 # Layer occupancy (ticks)
1344c1346
< system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 206081920 # Layer occupancy (ticks)
1346c1348
< system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 14406948660 # Layer occupancy (ticks)
1348c1350
< system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 8156637515 # Layer occupancy (ticks)
1350c1352
< system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 197502349 # Layer occupancy (ticks)
1352c1354
< system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 606443243 # Layer occupancy (ticks)
1354,1358c1356,1360
< system.cpu1.branchPred.lookups 133924240 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 134798362 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 95816419 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 6051956 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 100961028 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 73848042 # Number of BTB hits
1360,1362c1362,1364
< system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 73.145097 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 15861028 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 1023147 # Number of incorrect RAS predictions.
1392,1421c1394,1423
< system.cpu1.dtb.walker.walks 293746 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 282723 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 282723 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10766 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86594 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 282723 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 282723 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 282723 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 97360 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 96095 98.70% 98.70% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 182 0.19% 98.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 912 0.94% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 29 0.03% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.04% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 49 0.05% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 97360 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 86594 88.94% 88.94% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 10766 11.06% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 97360 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 282723 # Table walker requests started/completed, data/inst
1423,1424c1425,1426
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 282723 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97360 # Table walker requests started/completed, data/inst
1426,1427c1428,1429
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97360 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 380083 # Table walker requests started/completed, data/inst
1430,1433c1432,1435
< system.cpu1.dtb.read_hits 86040245 # DTB read hits
< system.cpu1.dtb.read_misses 244355 # DTB read misses
< system.cpu1.dtb.write_hits 75067998 # DTB write hits
< system.cpu1.dtb.write_misses 49391 # DTB write misses
---
> system.cpu1.dtb.read_hits 88221750 # DTB read hits
> system.cpu1.dtb.read_misses 234611 # DTB read misses
> system.cpu1.dtb.write_hits 76459163 # DTB write hits
> system.cpu1.dtb.write_misses 48112 # DTB write misses
1436,1440c1438,1442
< system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 39871 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 1240 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 8073 # Number of TLB faults due to prefetch
1442,1444c1444,1446
< system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 86284600 # DTB read accesses
< system.cpu1.dtb.write_accesses 75117389 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 11018 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 88456361 # DTB read accesses
> system.cpu1.dtb.write_accesses 76507275 # DTB write accesses
1446,1448c1448,1450
< system.cpu1.dtb.hits 161108243 # DTB hits
< system.cpu1.dtb.misses 293746 # DTB misses
< system.cpu1.dtb.accesses 161401989 # DTB accesses
---
> system.cpu1.dtb.hits 164680913 # DTB hits
> system.cpu1.dtb.misses 282723 # DTB misses
> system.cpu1.dtb.accesses 164963636 # DTB accesses
1478,1505c1480,1507
< system.cpu1.itb.walker.walks 65124 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 64693 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 64693 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 526 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55247 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 64693 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 64693 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 64693 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 55773 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 54531 97.77% 97.77% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.79% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 1101 1.97% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.06% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 52 0.09% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 31 0.06% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 55773 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 55247 99.06% 99.06% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 526 0.94% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 55773 # Table walker page sizes translated
1507,1508c1509,1510
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64693 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64693 # Table walker requests started/completed, data/inst
1510,1514c1512,1516
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 239249458 # ITB inst hits
< system.cpu1.itb.inst_misses 65124 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55773 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55773 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 120466 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 241355329 # ITB inst hits
> system.cpu1.itb.inst_misses 64693 # ITB inst misses
1521,1523c1523,1525
< system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 28782 # Number of entries that have been flushed from TLB
1527c1529
< system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 214506 # Number of TLB faults due to permissions restrictions
1530,1534c1532,1536
< system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses
< system.cpu1.itb.hits 239249458 # DTB hits
< system.cpu1.itb.misses 65124 # DTB misses
< system.cpu1.itb.accesses 239314582 # DTB accesses
< system.cpu1.numCycles 947127317 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 241420022 # ITB inst accesses
> system.cpu1.itb.hits 241355329 # DTB hits
> system.cpu1.itb.misses 64693 # DTB misses
> system.cpu1.itb.accesses 241420022 # DTB accesses
> system.cpu1.numCycles 943222184 # number of cpu cycles simulated
1537,1543c1539,1545
< system.cpu1.committedInsts 437680583 # Number of instructions committed
< system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 2.163969 # CPI: cycles per instruction
< system.cpu1.ipc 0.462114 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 444939071 # Number of instructions committed
> system.cpu1.committedOps 523893431 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 46484386 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 5697 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 94049904755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 2.119891 # CPI: cycles per instruction
> system.cpu1.ipc 0.471722 # IPC: instructions per cycle
1545,1653c1547,1655
< system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed
< system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 5225400 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits
< system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses
< system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 5760 # number of quiesce instructions executed
> system.cpu1.tickCycles 722277565 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 220944619 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 5315264 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 430.485039 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 156623393 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5315774 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 29.463892 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8391021559000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.485039 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.840791 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.840791 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 332053228 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 332053228 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 80890555 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 80890555 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 71395384 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 71395384 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 230003 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 230003 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 70856 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 70856 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1784180 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1784180 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762697 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1762697 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 152285939 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 152285939 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 152515942 # number of overall hits
> system.cpu1.dcache.overall_hits::total 152515942 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3470383 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3470383 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 2256465 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 2256465 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 629037 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 629037 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454847 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 454847 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178965 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 178965 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198846 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 198846 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 5726848 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5726848 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 6355885 # number of overall misses
> system.cpu1.dcache.overall_misses::total 6355885 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 57691506500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 57691506500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 50161466000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 50161466000 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17158564500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 17158564500 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2980004000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2980004000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5546868500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5546868500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5779500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5779500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 107852972500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 107852972500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 107852972500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 107852972500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 84360938 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 84360938 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 73651849 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 73651849 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 859040 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 859040 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 525703 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 525703 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1963145 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1963145 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1961543 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1961543 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 158012787 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 158012787 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 158871827 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 158871827 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041137 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.041137 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030637 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.030637 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732256 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732256 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.865217 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.865217 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091162 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091162 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101372 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101372 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036243 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.036243 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040006 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.040006 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27895.298372 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372 # average StoreCondReq miss latency
1656,1659c1658,1661
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18832.868010 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 18832.868010 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 16968.993696 # average overall miss latency
1668,1757c1670,1759
< system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks
< system.cpu1.dcache.writebacks::total 5225429 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41578 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41578 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 34 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::total 34 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1320370 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1320370 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1320370 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1320370 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2986376 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2986376 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1340248 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1340248 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 647394 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 647394 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 450852 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 450852 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117938 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117938 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201137 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 201137 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326624 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4326624 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4974018 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4974018 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 19129 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 36596 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44483005500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 5315289 # number of writebacks
> system.cpu1.dcache.writebacks::total 5315289 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392143 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 392143 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 920496 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 920496 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 60 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 60 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44592 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44592 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1312639 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1312639 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1312639 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1312639 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3078240 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 3078240 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335969 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1335969 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628734 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 628734 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454787 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 454787 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 134373 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 134373 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198802 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 198802 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4414209 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4414209 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5042943 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5042943 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6731 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13933 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46218671000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46218671000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29907223500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29907223500 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14916352500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14916352500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16698306500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16698306500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1935752000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1935752000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344630000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344630000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5479500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5479500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76125894500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 76125894500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91042247000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 91042247000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 839317500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 839317500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1016449500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1016449500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1855767000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1855767000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036489 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018139 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018139 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.731903 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.731903 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.865103 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.865103 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068448 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068448 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101350 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101350 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027936 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027936 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031742 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.031742 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15014.641808 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15014.641808 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22386.165772 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22386.165772 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23724.424796 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23724.424796 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36716.763012 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36716.763012 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14405.810691 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14405.810691 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26884.186276 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26884.186276 # average StoreCondReq mshr miss latency
1760,1769c1762,1771
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555 # average overall mshr uncacheable latency
1771,1779c1773,1781
< system.cpu1.icache.tags.replacements 9231311 # number of replacements
< system.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 9419212 # number of replacements
> system.cpu1.icache.tags.tagsinuse 506.776997 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 231714815 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 9419724 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 24.598896 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8379179578000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.776997 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989799 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.989799 # Average percentage of cache occupancy
1781,1783c1783,1785
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
1785,1822c1787,1824
< system.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits
< system.cpu1.icache.overall_hits::total 229790487 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses
< system.cpu1.icache.overall_misses::total 9231824 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94524443000 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 94524443000 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 94524443000 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 94524443000 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 94524443000 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 94524443000 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 239022311 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 239022311 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 239022311 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 239022311 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 239022311 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 239022311 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038623 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038623 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038623 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10238.978018 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10238.978018 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10238.978018 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 491688802 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 491688802 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 231714815 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 231714815 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 231714815 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 231714815 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 231714815 # number of overall hits
> system.cpu1.icache.overall_hits::total 231714815 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 9419724 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 9419724 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 9419724 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 9419724 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 9419724 # number of overall misses
> system.cpu1.icache.overall_misses::total 9419724 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96182532500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 96182532500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 96182532500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 96182532500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 96182532500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 96182532500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 241134539 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 241134539 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 241134539 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 241134539 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 241134539 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 241134539 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039064 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.039064 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039064 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.039064 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039064 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.039064 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10210.759094 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10210.759094 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10210.759094 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10210.759094 # average overall miss latency
1831,1868c1833,1870
< system.cpu1.icache.writebacks::writebacks 9231311 # number of writebacks
< system.cpu1.icache.writebacks::total 9231311 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9231824 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 9231824 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 9231824 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 9231824 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 9231824 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 9231824 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
< system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency
---
> system.cpu1.icache.writebacks::writebacks 9419212 # number of writebacks
> system.cpu1.icache.writebacks::total 9419212 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9419724 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 9419724 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 9419724 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 9419724 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 9419724 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 9419724 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91472670500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 91472670500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91472670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 91472670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91472670500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 91472670500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039064 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.039064 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.039064 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9710.759094 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency
1870,1872c1872,1874
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7256046 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7256259 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 183 # number of redundant prefetches already in prefetch queue
1875,1941c1877,1942
< system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2326720 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.899780 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 488472501 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 488472501 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 576439 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168221 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 744660 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3264846 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3264846 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 11189694 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 11189694 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 575 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867363 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 867363 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8545306 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 8545306 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2781382 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2781382 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 181539 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 181539 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 576439 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168221 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 8545306 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 925773 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2304751 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13454.881705 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 23669466 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2320587 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 10.199775 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9853632359500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12618.151234 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.761915 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 57.964405 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 717.004151 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.770151 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003770 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003538 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043762 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.821221 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1043 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14722 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 319 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 650 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 71 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8143 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 659 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063660 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898560 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 496871809 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 496871809 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551874 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166024 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 717898 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3295376 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3295376 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 11437109 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 11437109 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 567 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 865133 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 865133 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8732847 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 8732847 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2873391 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2873391 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191011 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 191011 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 551874 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 166024 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 8732847 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3738524 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 13189269 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 551874 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 166024 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 8732847 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3738524 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 13189269 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11967 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8433 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 20400 # number of ReadReq misses
1944,1947c1945,1948
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 223343 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 223343 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201132 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 201132 # number of SCUpgradeReq misses
---
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 222957 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 222957 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 198797 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 198797 # number of SCUpgradeReq misses
1950,2005c1951,2006
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 251639 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 251639 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686518 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 686518 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970013 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 970013 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 267232 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 267232 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12346 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 686518 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1221652 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1929048 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12346 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 686518 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1221652 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1929048 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 599407500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 460132500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1059540000 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3297082000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 3297082000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1852998500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1852998500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4653499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4653499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14739798000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 14739798000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24441807000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24441807000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37974197490 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37974197490 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18803051000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 18803051000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 599407500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 460132500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24441807000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 52713995490 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 78215342490 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 599407500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 460132500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24441807000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 52713995490 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 78215342490 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 588785 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176753 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 765538 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3264847 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3264847 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 11189694 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 11189694 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223918 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 223918 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201132 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 201132 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249481 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 249481 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686877 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 686877 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 967667 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 967667 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 262059 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 262059 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11967 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8433 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 686877 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1217148 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1924425 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11967 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8433 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 686877 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1217148 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1924425 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 548385000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 436726500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 985111500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3348912000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3348912000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1915512500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1915512500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5381000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5381000 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13948272999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 13948272999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24574911500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24574911500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38337752989 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38337752989 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 401272000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 401272000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 548385000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 436726500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24574911500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 52286025988 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 77846048988 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 548385000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 436726500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24574911500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 52286025988 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 77846048988 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 563841 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174457 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 738298 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3295377 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3295377 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 11437109 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 11437109 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223524 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 223524 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198797 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 198797 # number of SCUpgradeReq accesses(hits+misses)
2008,2028c2009,2029
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119002 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1119002 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9231824 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 9231824 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3751395 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3751395 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448771 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 448771 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 588785 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176753 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 9231824 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4870397 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 14867759 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 588785 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176753 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 9231824 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4870397 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 14867759 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048271 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.027272 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1114614 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1114614 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9419724 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 9419724 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3841058 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3841058 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 453070 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 453070 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 563841 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174457 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 9419724 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4955672 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 15113694 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 563841 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174457 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 9419724 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4955672 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 15113694 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048339 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.027631 # miss rate for ReadReq accesses
2031,2032c2032,2033
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997432 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997432 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997463 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997463 # miss rate for UpgradeReq accesses
2037,2081c2038,2082
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224878 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224878 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.074364 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.074364 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258574 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258574 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.595475 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.595475 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048271 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.074364 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250832 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.129747 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048271 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.074364 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250832 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.129747 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 53930.203938 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 50749.113900 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14762.414761 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14762.414761 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9212.847782 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9212.847782 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 930699.800000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 930699.800000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58575.173165 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58575.173165 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35602.572693 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35602.572693 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39148.132540 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39148.132540 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 70362.273231 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 70362.273231 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 40546.084125 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 40546.084125 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.223827 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.223827 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.072919 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.072919 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.251927 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.251927 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.578407 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.578407 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048339 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.072919 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245607 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.127330 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048339 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.072919 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245607 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.127330 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 51787.797937 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48289.779412 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15020.438919 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15020.438919 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9635.520154 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9635.520154 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1076200 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1076200 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55909.159411 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55909.159411 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35777.746962 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35777.746962 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39618.745900 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39618.745900 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1531.227701 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1531.227701 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 51787.797937 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35777.746962 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42957.821060 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 40451.588910 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 51787.797937 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35777.746962 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42957.821060 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 40451.588910 # average overall miss latency
2090,2099c2091,2100
< system.cpu1.l2cache.writebacks::writebacks 1166062 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1166062 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8177 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 8177 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 786 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits
---
> system.cpu1.l2cache.writebacks::writebacks 1133493 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1133493 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6803 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 6803 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 882 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 882 # number of ReadSharedReq MSHR hits
2102,2112c2103,2113
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8963 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 8969 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8963 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 8969 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12346 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 20876 # number of ReadReq MSHR misses
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7685 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 7687 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7685 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 7687 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11967 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8432 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 20399 # number of ReadReq MSHR misses
2115,2120c2116,2121
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 757140 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 223343 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 223343 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201132 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201132 # number of SCUpgradeReq MSHR misses
---
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 726483 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 726483 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 222957 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 222957 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 198797 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 198797 # number of SCUpgradeReq MSHR misses
2123,2190c2124,2191
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243462 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 243462 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686514 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686514 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969227 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969227 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 267229 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 267229 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12346 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686514 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1212689 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1920079 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12346 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686514 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1212689 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2677219 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19221 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 36688 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 408923500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 934255000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45309762891 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7082960998 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7082960998 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3799999000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3799999000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4287499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4287499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11990250000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11990250000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322650500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32101541990 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32101541990 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17199481500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17199481500 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 408923500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322650500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44091791990 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 65348697490 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 408923500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322650500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44091791990 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 110658460381 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2998478000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3010692500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2831799500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2831799500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 242678 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 242678 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686876 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686876 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966785 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966785 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 262056 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 262056 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11967 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8432 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686876 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1209463 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1916738 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11967 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8432 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686876 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1209463 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 726483 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2643221 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6824 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14026 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 386118000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 862701000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38725078481 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38725078481 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7000085492 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7000085492 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3849189999 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3849189999 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4991000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4991000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11472999499 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11472999499 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20453639500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20453639500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32473658989 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32473658989 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13075073000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13075073000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 386118000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20453639500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43946658488 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 65262998988 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 386118000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20453639500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43946658488 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38725078481 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 103988077469 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 785396000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 797733000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 962364500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 962364500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1747760500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1760097500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027630 # mshr miss rate for ReadReq accesses
2195,2196c2196,2197
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997463 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997463 # mshr miss rate for UpgradeReq accesses
2201,2217c2202,2218
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217724 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217724 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.072919 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251698 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251698 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578401 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578401 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.126821 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for overall accesses
2219,2257c2220,2258
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174889 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 998200 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 998200 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47276.636115 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34048.993127 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39341.423766 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 125488.200485 # average overall mshr uncacheable latency
2259,2299c2260,2299
< system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 30305906 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15477606 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 2090955 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2090626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 329 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 826390 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 14176907 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 7202 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 7202 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4434109 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 11439122 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 2886028 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 940232 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 438079 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353355 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 486110 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1143505 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1120857 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9419724 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4894979 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 500608 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 453070 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28258846 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17165188 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 367696 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1190168 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 46981898 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1205697856 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 663528133 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395656 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4510728 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1875132373 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 6705692 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 22548909 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.107052 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.309227 # Request fanout histogram
2301,2303c2301,2303
< system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 20135326 89.30% 89.30% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 2413254 10.70% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 329 0.00% 100.00% # Request fanout histogram
2307,2308c2307,2308
< system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 22548909 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 30147553476 # Layer occupancy (ticks)
2310c2310
< system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 176219861 # Layer occupancy (ticks)
2312c2312
< system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 14133264904 # Layer occupancy (ticks)
2314c2314
< system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7885730738 # Layer occupancy (ticks)
2316c2316
< system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 193298381 # Layer occupancy (ticks)
2318c2318
< system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 626482687 # Layer occupancy (ticks)
2320,2324c2320,2324
< system.iobus.trans_dist::ReadReq 40417 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40417 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136988 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136988 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40387 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40387 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136979 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136979 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47868 # Packet count per connected master and slave (bytes)
2335c2335
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
2337,2339c2337,2339
< system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122958 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231694 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231694 # Packet count per connected master and slave (bytes)
2342,2343c2342,2343
< system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47888 # Cumulative packet size per connected master and slave (bytes)
2354c2354
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
2356,2358c2356,2358
< system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155996 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355128 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7355128 # Cumulative packet size per connected master and slave (bytes)
2361,2362c2361,2362
< system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7513210 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 47188500 # Layer occupancy (ticks)
2364c2364
< system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2366c2366
< system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks)
2368c2368
< system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
2370c2370
< system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
2372c2372
< system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2374c2374
< system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2376c2376
< system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2380c2380
< system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
2384c2384
< system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 26264003 # Layer occupancy (ticks)
2386c2386
< system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36399000 # Layer occupancy (ticks)
2388c2388
< system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 568799211 # Layer occupancy (ticks)
2390c2390
< system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92966000 # Layer occupancy (ticks)
2392c2392
< system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148134000 # Layer occupancy (ticks)
2396,2397c2396,2397
< system.iocache.tags.replacements 115847 # number of replacements
< system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115828 # number of replacements
> system.iocache.tags.tagsinuse 11.305227 # Cycle average of tags in use
2399c2399
< system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115844 # Sample count of references to valid blocks.
2401,2406c2401,2406
< system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9138950806000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.834041 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.471186 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.239628 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.466949 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.706577 # Average percentage of cache occupancy
2410,2411c2410,2411
< system.iocache.tags.tag_accesses 1043151 # Number of tag accesses
< system.iocache.tags.data_accesses 1043151 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1042980 # Number of tag accesses
> system.iocache.tags.data_accesses 1042980 # Number of data accesses
2413,2414c2413,2414
< system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8863 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8900 # number of ReadReq misses
2420,2421c2420,2421
< system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8922 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8863 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8903 # number of demand (read+write) misses
2423,2427c2423,2427
< system.iocache.overall_misses::realview.ide 8882 # number of overall misses
< system.iocache.overall_misses::total 8922 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 8863 # number of overall misses
> system.iocache.overall_misses::total 8903 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5197000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1710789963 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1715986963 # number of ReadReq miss cycles
2430,2437c2430,2437
< system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13562248248 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13562248248 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5566000 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1710789963 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1716355963 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5566000 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1710789963 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1716355963 # number of overall miss cycles
2439,2440c2439,2440
< system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8863 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8900 # number of ReadReq accesses(hits+misses)
2446,2447c2446,2447
< system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8863 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8903 # number of demand (read+write) accesses
2449,2450c2449,2450
< system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8863 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8903 # number of overall (read+write) accesses
2464,2466c2464,2466
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140459.459459 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 193026.059235 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 192807.523933 # average ReadReq miss latency
2469,2477c2469,2477
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.939729 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126768.939729 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 139150 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 192784.001236 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 139150 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 192784.001236 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 35587 # number of cycles access was blocked
2479c2479
< system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3530 # number of cycles access was blocked
2481c2481
< system.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.081303 # average number of cycles each access was blocked
2488,2489c2488,2489
< system.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8863 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8900 # number of ReadReq MSHR misses
2495,2496c2495,2496
< system.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8863 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8903 # number of demand (read+write) MSHR misses
2498,2502c2498,2502
< system.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8863 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8903 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3347000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1267639963 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1270986963 # number of ReadReq MSHR miss cycles
2505,2512c2505,2512
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8211460570 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8211460570 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8206832286 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8206832286 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3566000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1267639963 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1271205963 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3566000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1267639963 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1271205963 # number of overall MSHR miss cycles
2526,2528c2526,2528
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90459.459459 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143026.059235 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 142807.523933 # average ReadReq mshr miss latency
2531,2538c2531,2538
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76710.837938 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76710.837938 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency
2540,2846c2540,2863
< system.l2c.tags.replacements 1465460 # number of replacements
< system.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use
< system.l2c.tags.total_refs 6746847 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 21606.771340 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.937701 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 223.248695 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5669.657556 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6460.370404 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9729.240754 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.294328 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 204.500397 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.050840 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.096491 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.138989 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.961079 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 9038 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 217 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 50396 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 130 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 1705 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 7069 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2486 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 12173 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 35392 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.137909 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003311 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.768982 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 82649960 # Number of tag accesses
< system.l2c.tags.data_accesses 82649960 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 2868119 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2868119 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 181384 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 131978 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 313362 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 45809 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 40059 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 85868 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 200580 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 165707 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 366287 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7480 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5183 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 699361 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 660994 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 342500 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6176 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4038 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 639412 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 580820 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 295958 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 3241922 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 7480 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 5183 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 699361 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 861574 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 342500 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6176 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4038 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 639412 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 746527 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 295958 # number of demand (read+write) hits
< system.l2c.demand_hits::total 3608209 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 7480 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 5183 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 699361 # number of overall hits
< system.l2c.overall_hits::cpu0.data 861574 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 342500 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6176 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4038 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 639412 # number of overall hits
< system.l2c.overall_hits::cpu1.data 746527 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 295958 # number of overall hits
< system.l2c.overall_hits::total 3608209 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 61552 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 61783 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 123335 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 12334 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 11273 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 493827 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 156178 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 650005 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1763 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 75880 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 147884 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2064 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 47101 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 114695 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 237376 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 863201 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 2015 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1763 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 75880 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 641711 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 2405 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 2064 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 47101 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 270873 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 237376 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1513206 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 2015 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1763 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 75880 # number of overall misses
< system.l2c.overall_misses::cpu0.data 641711 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 232018 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 2405 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 2064 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 47101 # number of overall misses
< system.l2c.overall_misses::cpu1.data 270873 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 237376 # number of overall misses
< system.l2c.overall_misses::total 1513206 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1080728500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1074141000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 2154869500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192695000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205559500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 398254500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 68952537500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 21260978999 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 90213516499 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 283038500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248472000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10197968500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 20619201500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 338612000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 290311500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6337057500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 16104459500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 133039008033 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 283038500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 248472000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 10197968500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 89571739000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 338612000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 290311500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 6337057500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 37365438499 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 223252524532 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 283038500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 248472000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 10197968500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 89571739000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 338612000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 290311500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 6337057500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 37365438499 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 223252524532 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2868119 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2868119 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 242936 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 193761 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 436697 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 58143 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 51332 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 109475 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 694407 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 321885 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 1016292 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9495 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6946 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 775241 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 808878 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 574518 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8581 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6102 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 686513 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 695515 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 533334 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 4105123 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 9495 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 6946 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 775241 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1503285 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 574518 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 8581 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6102 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 686513 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 1017400 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 533334 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 5121415 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 9495 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 6946 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 775241 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1503285 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 574518 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 8581 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6102 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 686513 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 1017400 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 533334 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 5121415 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253367 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318862 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.282427 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.212132 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219610 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.215638 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.711149 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.485198 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.639585 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.253815 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097879 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.182826 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.338250 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068609 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164907 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.210274 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.253815 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.097879 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.426872 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.338250 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.068609 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.266240 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.295466 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.253815 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.097879 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.426872 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.338250 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.068609 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.266240 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.295466 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17557.975370 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17385.704806 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 17471.678761 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15623.074428 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18234.675774 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 16870.186809 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139628.933817 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136132.995678 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 138788.957776 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140937.039138 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134396.000264 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139428.210625 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140654.796512 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134541.888707 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140411.173111 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 154122.861342 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 147536.108456 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 147536.108456 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 2227 # number of cycles access was blocked
---
> system.l2c.tags.replacements 1399797 # number of replacements
> system.l2c.tags.tagsinuse 63464.709741 # Cycle average of tags in use
> system.l2c.tags.total_refs 6644913 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1460922 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 4.548438 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 21707.053985 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.735345 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 115.995716 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4966.190479 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 4993.948919 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6019.423287 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.036337 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 317.216521 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3872.812023 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 8822.287754 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12306.009376 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.331223 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001568 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.001770 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.075778 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.076202 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.091849 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003678 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.004840 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.059094 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.134617 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.187775 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.968395 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 10216 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 187 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 50722 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 140 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 3377 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 6697 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 176 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2228 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 13666 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 34520 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.155884 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.002853 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.773956 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 81151228 # Number of tag accesses
> system.l2c.tags.data_accesses 81151228 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 2809703 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2809703 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 181902 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 125777 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 307679 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 42034 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 42908 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 84942 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 62506 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 50661 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 113167 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7522 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5409 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 680705 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 645150 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 332678 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6067 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4079 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 638595 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 567372 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 305148 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 3192725 # number of ReadSharedReq hits
> system.l2c.InvalidateReq_hits::cpu0.data 139615 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::cpu1.data 131240 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::total 270855 # number of InvalidateReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 7522 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 5409 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 680705 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 707656 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 332678 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 6067 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4079 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 638595 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 618033 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 305148 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3305892 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 7522 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 5409 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 680705 # number of overall hits
> system.l2c.overall_hits::cpu0.data 707656 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 332678 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 6067 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4079 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 638595 # number of overall hits
> system.l2c.overall_hits::cpu1.data 618033 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 305148 # number of overall hits
> system.l2c.overall_hits::total 3305892 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 64206 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 62132 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 126338 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 12168 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 12142 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 24310 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 79720 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 52688 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 132408 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1937 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1561 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 72587 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 131602 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 238730 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2112 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1907 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 48281 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 118892 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 199183 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 816792 # number of ReadSharedReq misses
> system.l2c.InvalidateReq_misses::cpu0.data 443932 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::cpu1.data 119113 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::total 563045 # number of InvalidateReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 1937 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1561 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 72587 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 211322 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 238730 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2112 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1907 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 48281 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 171580 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 199183 # number of demand (read+write) misses
> system.l2c.demand_misses::total 949200 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 1937 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1561 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 72587 # number of overall misses
> system.l2c.overall_misses::cpu0.data 211322 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 238730 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2112 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1907 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 48281 # number of overall misses
> system.l2c.overall_misses::cpu1.data 171580 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 199183 # number of overall misses
> system.l2c.overall_misses::total 949200 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1150609000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1077871000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 2228480000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192622500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 197330500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 389953000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 11022660500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 7093820500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 18116481000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 272199000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 220485500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9769762500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 18492608500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 294211000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 267576500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6491475500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 16608783999 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 127469272889 # number of ReadSharedReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu0.data 140111000 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu1.data 126265000 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::total 266376000 # number of InvalidateReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 272199000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 220485500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 9769762500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 29515269000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 294211000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 267576500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6491475500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 23702604499 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 145585753889 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 272199000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 220485500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 9769762500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 29515269000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 294211000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 267576500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6491475500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 23702604499 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 145585753889 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 2809703 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2809703 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 246108 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 187909 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 434017 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 54202 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 55050 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 109252 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 142226 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 103349 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 245575 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9459 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6970 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 753292 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 776752 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 571408 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8179 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5986 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 686876 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 686264 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 504331 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 4009517 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu0.data 583547 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu1.data 250353 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::total 833900 # number of InvalidateReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 9459 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6970 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 753292 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 918978 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 571408 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 8179 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 5986 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 686876 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 789613 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 504331 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4255092 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 9459 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6970 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 753292 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 918978 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 571408 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 8179 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 5986 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 686876 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 789613 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 504331 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4255092 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260885 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330649 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.291090 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.224494 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.220563 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.222513 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.560516 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.509807 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.539175 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.223960 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.096360 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.169426 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.318577 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070291 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173245 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.203713 # miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu0.data 0.760748 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu1.data 0.475780 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::total 0.675195 # miss rate for InvalidateReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.223960 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.096360 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.229953 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.318577 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.070291 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.217296 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.223074 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.223960 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.096360 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.229953 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.318577 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.070291 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.217296 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.223074 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17920.583746 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17348.081504 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 17639.031804 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15830.251479 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16251.894251 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 16040.847388 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138267.191420 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134638.257288 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 136823.160232 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141246.316464 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134593.832229 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140519.205635 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140312.794966 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134451.968683 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139696.396721 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 156060.873379 # average ReadSharedReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 315.613653 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1060.043824 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::total 473.098953 # average InvalidateReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141246.316464 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 134593.832229 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 139669.646322 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140312.794966 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 134451.968683 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 138143.166447 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 153377.321838 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141246.316464 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 134593.832229 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 139669.646322 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140312.794966 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 134451.968683 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 138143.166447 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 153377.321838 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 1015 # number of cycles access was blocked
2848c2865
< system.l2c.blocked::no_mshrs 45 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2850c2867
< system.l2c.avg_blocked_cycles::no_mshrs 49.488889 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 112.777778 # average number of cycles each access was blocked
2854,2919c2871,2934
< system.l2c.writebacks::writebacks 1132908 # number of writebacks
< system.l2c.writebacks::total 1132908 # number of writebacks
< system.l2c.ReadExReq_mshr_hits::cpu1.data 1 # number of ReadExReq MSHR hits
< system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 168 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 159 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 159 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 159 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 364 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 56350 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 56350 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 61552 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 61783 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 123335 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12334 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11273 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 493827 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 156177 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 650004 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1763 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 75712 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147859 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2064 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46942 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 114685 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 862838 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 2015 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 1763 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 75712 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 641686 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 2405 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 2064 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 46942 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 270862 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1512842 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 2015 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 1763 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 75712 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 641686 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 2405 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 2064 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 46942 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 270862 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1512842 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1090140 # number of writebacks
> system.l2c.writebacks::total 1090140 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 179 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 207 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 18 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 427 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 179 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 207 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 427 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 179 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 207 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 427 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 54511 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 54511 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 64206 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 62132 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 126338 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12168 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12142 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 24310 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 79720 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 52688 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 132408 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1937 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1561 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72408 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 131579 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2112 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1907 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 48074 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 118874 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 816365 # number of ReadSharedReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu0.data 443932 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu1.data 119113 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::total 563045 # number of InvalidateReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 1937 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1561 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 72408 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 211299 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2112 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1907 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 48074 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 171562 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 948773 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 1937 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1561 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 72408 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 211299 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2112 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1907 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 48074 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 171562 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 948773 # number of overall MSHR misses
2921,2927c2936,2942
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 19127 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 91058 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38515 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6729 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 91274 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38755 # number of WriteReq MSHR uncacheable
2929,2974c2944,2992
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 36594 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 129573 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4349611999 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4356371498 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 8705983497 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 908986500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 828559000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 1737545500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 64014027660 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 19698809451 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 83712837111 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 230839505 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9421666233 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19137304611 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 269667010 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5848765667 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14956255664 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 124366437860 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 230839505 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 9421666233 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 83151332271 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 269667010 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 5848765667 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 34655065115 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 208079274971 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 230839505 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 9421666233 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 83151332271 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 269667010 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 5848765667 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 34655065115 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 208079274971 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13931 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 130029 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4544765997 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4377476492 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 8922242489 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 896994500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 892131500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1789126000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10225195953 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6566674837 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 16791870790 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 204866519 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9025630028 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17172972916 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 248503510 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5986913295 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 15417511413 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 119251773144 # number of ReadSharedReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 31065864000 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 8291731997 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::total 39357595997 # number of InvalidateReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 204866519 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 9025630028 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 27398168869 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 248503510 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5986913295 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 21984186250 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 136043643934 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 204866519 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 9025630028 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 27398168869 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 248503510 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5986913295 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 21984186250 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 136043643934 # number of overall MSHR miss cycles
2976,2982c2994,3000
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3292793548 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10279000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2654073009 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 11854811557 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3455652022 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2534737541 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5990389563 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5288332558 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10383500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 664180522 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 11860562580 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5157955518 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 839811556 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5997767074 # number of WriteReq MSHR uncacheable cycles
2984,2987c3002,3005
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6748445570 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10279000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5188810550 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 17845201120 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10446288076 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10383500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1503992078 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 17858329654 # number of overall MSHR uncacheable cycles
2990,3073c3008,3097
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.253367 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318862 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.282427 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.212132 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219610 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.215638 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.711149 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.485195 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.639584 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.182795 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164892 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210186 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.295395 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.295395 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70665.648541 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70510.844375 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70588.101488 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73697.624453 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73499.423401 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73602.977930 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129628.448141 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126131.309034 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 128788.187628 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.260885 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.330649 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.291090 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224494 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220563 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222513 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.560516 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.509807 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.539175 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.169396 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173219 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.203607 # mshr miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.760748 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.475780 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::total 0.675195 # mshr miss rate for InvalidateReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.222974 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.222974 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70784.132277 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70454.459731 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70622.002003 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73717.496713 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73474.839400 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.297820 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128263.872968 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124633.215096 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 126819.155867 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130514.541956 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129696.244873 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146076.538245 # average ReadSharedReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69978.879648 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69612.317690 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69901.332925 # average InvalidateReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency
3075,3081c3099,3105
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604 # average WriteReq mshr uncacheable latency
3083,3086c3107,3110
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933 # average overall mshr uncacheable latency
3088,3095c3112,3119
< system.membus.trans_dist::ReadReq 91058 # Transaction distribution
< system.membus.trans_dist::ReadResp 962815 # Transaction distribution
< system.membus.trans_dist::WriteReq 38515 # Transaction distribution
< system.membus.trans_dist::WriteResp 38515 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution
< system.membus.trans_dist::CleanEvict 269903 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 91274 # Transaction distribution
> system.membus.trans_dist::ReadResp 916539 # Transaction distribution
> system.membus.trans_dist::WriteReq 38755 # Transaction distribution
> system.membus.trans_dist::WriteResp 38755 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1197090 # Transaction distribution
> system.membus.trans_dist::CleanEvict 262945 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 440993 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 308067 # Transaction distribution
3097,3102c3121,3126
< system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
< system.membus.trans_dist::ReadExReq 660243 # Transaction distribution
< system.membus.trans_dist::ReadExResp 640684 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
> system.membus.trans_dist::ReadExReq 144406 # Transaction distribution
> system.membus.trans_dist::ReadExResp 127298 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 825265 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 666679 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122958 # Packet count per connected master and slave (bytes)
3104,3110c3128,3134
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27076 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4666640 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4816726 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238694 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238694 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5055420 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155996 # Cumulative packet size per connected master and slave (bytes)
3112,3119c3136,3143
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 621430 # Total snoops (count)
< system.membus.snoop_fanout::samples 4033661 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54152 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133490240 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 133701712 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7291456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7291456 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 140993168 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 609728 # Total snoops (count)
> system.membus.snoop_fanout::samples 3975535 # Request fanout histogram
3124c3148
< system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3975535 100.00% 100.00% # Request fanout histogram
3129,3130c3153,3154
< system.membus.snoop_fanout::total 4033661 # Request fanout histogram
< system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3975535 # Request fanout histogram
> system.membus.reqLayer0.occupancy 110272997 # Layer occupancy (ticks)
3134c3158
< system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 22907496 # Layer occupancy (ticks)
3136c3160
< system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 8443265855 # Layer occupancy (ticks)
3138c3162
< system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 5364054651 # Layer occupancy (ticks)
3140c3164
< system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 45386996 # Layer occupancy (ticks)
3194,3224c3218,3250
< system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3228731 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 12590063 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 6816351 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2112405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 136080 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 123352 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 12728 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 91276 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4889046 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38755 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38755 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 4006843 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 3033326 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 740212 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 393009 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1133221 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 135 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 301958 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 301958 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4804997 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 940884 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 833900 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10292862 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8190937 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 18483799 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255537947 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200300853 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 455838800 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3066288 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 8826957 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.482240 # Request fanout histogram
3226,3228c3252,3254
< system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 5684742 64.40% 64.40% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3129487 35.45% 99.86% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 12728 0.14% 100.00% # Request fanout histogram
3232,3233c3258,3259
< system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 8826957 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 9586281743 # Layer occupancy (ticks)
3235c3261
< system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2585661 # Layer occupancy (ticks)
3237c3263
< system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4723415116 # Layer occupancy (ticks)
3239c3265
< system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 4064152578 # Layer occupancy (ticks)