3,5c3,5
< sim_seconds 47.381683 # Number of seconds simulated
< sim_ticks 47381683294000 # Number of ticks simulated
< final_tick 47381683294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.461935 # Number of seconds simulated
> sim_ticks 47461934895000 # Number of ticks simulated
> final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 169119 # Simulator instruction rate (inst/s)
< host_op_rate 198983 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 9178439782 # Simulator tick rate (ticks/s)
< host_mem_usage 757568 # Number of bytes of host memory used
< host_seconds 5162.28 # Real time elapsed on the host
< sim_insts 873041938 # Number of instructions simulated
< sim_ops 1027205539 # Number of ops (including micro ops) simulated
---
> host_inst_rate 231788 # Simulator instruction rate (inst/s)
> host_op_rate 272612 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 12136870284 # Simulator tick rate (ticks/s)
> host_mem_usage 762440 # Number of bytes of host memory used
> host_seconds 3910.56 # Real time elapsed on the host
> sim_insts 906421729 # Number of instructions simulated
> sim_ops 1066065309 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 75648 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 7273408 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 37833736 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 11654720 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 106816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 96448 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 3691584 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 15254352 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 10772160 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 424448 # Number of bytes read from this memory
< system.physmem.bytes_read::total 87268888 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 7273408 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 3691584 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 10964992 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 68656704 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory
> system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 68677288 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1182 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 113647 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 591165 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 182105 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1669 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1507 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 57681 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 238362 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 168315 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6632 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1363602 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1072761 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory
50,66c50,66
< system.physmem.num_writes::total 1075335 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 1806 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 1597 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 798489 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 245975 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2254 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2036 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 77912 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 321946 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 227349 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8958 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1841828 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 77912 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 231418 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1449014 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s)
69,92c69,92
< system.physmem.bw_write::total 1449448 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1449014 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 1597 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 798923 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 245975 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2254 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2036 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 77912 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 321946 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 227349 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8958 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3291276 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1363603 # Number of read requests accepted
< system.physmem.writeReqs 1075335 # Number of write requests accepted
< system.physmem.readBursts 1363603 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1075335 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 87237120 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue
< system.physmem.bytesWritten 68675712 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 87268952 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 68677288 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1562015 # Number of read requests accepted
> system.physmem.writeReqs 1242432 # Number of write requests accepted
> system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue
> system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue
94,126c94,126
< system.physmem.neitherReadNorWriteReqs 497625 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 80650 # Per bank write bursts
< system.physmem.perBankRdBursts::1 88729 # Per bank write bursts
< system.physmem.perBankRdBursts::2 73569 # Per bank write bursts
< system.physmem.perBankRdBursts::3 80330 # Per bank write bursts
< system.physmem.perBankRdBursts::4 79168 # Per bank write bursts
< system.physmem.perBankRdBursts::5 89219 # Per bank write bursts
< system.physmem.perBankRdBursts::6 76757 # Per bank write bursts
< system.physmem.perBankRdBursts::7 80146 # Per bank write bursts
< system.physmem.perBankRdBursts::8 80110 # Per bank write bursts
< system.physmem.perBankRdBursts::9 145487 # Per bank write bursts
< system.physmem.perBankRdBursts::10 85462 # Per bank write bursts
< system.physmem.perBankRdBursts::11 91495 # Per bank write bursts
< system.physmem.perBankRdBursts::12 74671 # Per bank write bursts
< system.physmem.perBankRdBursts::13 80575 # Per bank write bursts
< system.physmem.perBankRdBursts::14 75276 # Per bank write bursts
< system.physmem.perBankRdBursts::15 81436 # Per bank write bursts
< system.physmem.perBankWrBursts::0 65415 # Per bank write bursts
< system.physmem.perBankWrBursts::1 72062 # Per bank write bursts
< system.physmem.perBankWrBursts::2 62920 # Per bank write bursts
< system.physmem.perBankWrBursts::3 67234 # Per bank write bursts
< system.physmem.perBankWrBursts::4 65543 # Per bank write bursts
< system.physmem.perBankWrBursts::5 71204 # Per bank write bursts
< system.physmem.perBankWrBursts::6 63108 # Per bank write bursts
< system.physmem.perBankWrBursts::7 65618 # Per bank write bursts
< system.physmem.perBankWrBursts::8 64627 # Per bank write bursts
< system.physmem.perBankWrBursts::9 73983 # Per bank write bursts
< system.physmem.perBankWrBursts::10 67070 # Per bank write bursts
< system.physmem.perBankWrBursts::11 71654 # Per bank write bursts
< system.physmem.perBankWrBursts::12 63584 # Per bank write bursts
< system.physmem.perBankWrBursts::13 67795 # Per bank write bursts
< system.physmem.perBankWrBursts::14 63419 # Per bank write bursts
< system.physmem.perBankWrBursts::15 67822 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 93757 # Per bank write bursts
> system.physmem.perBankRdBursts::1 100629 # Per bank write bursts
> system.physmem.perBankRdBursts::2 93977 # Per bank write bursts
> system.physmem.perBankRdBursts::3 99615 # Per bank write bursts
> system.physmem.perBankRdBursts::4 97211 # Per bank write bursts
> system.physmem.perBankRdBursts::5 108899 # Per bank write bursts
> system.physmem.perBankRdBursts::6 95410 # Per bank write bursts
> system.physmem.perBankRdBursts::7 95079 # Per bank write bursts
> system.physmem.perBankRdBursts::8 84413 # Per bank write bursts
> system.physmem.perBankRdBursts::9 140545 # Per bank write bursts
> system.physmem.perBankRdBursts::10 87149 # Per bank write bursts
> system.physmem.perBankRdBursts::11 92128 # Per bank write bursts
> system.physmem.perBankRdBursts::12 89605 # Per bank write bursts
> system.physmem.perBankRdBursts::13 97795 # Per bank write bursts
> system.physmem.perBankRdBursts::14 91413 # Per bank write bursts
> system.physmem.perBankRdBursts::15 93857 # Per bank write bursts
> system.physmem.perBankWrBursts::0 74634 # Per bank write bursts
> system.physmem.perBankWrBursts::1 80843 # Per bank write bursts
> system.physmem.perBankWrBursts::2 76779 # Per bank write bursts
> system.physmem.perBankWrBursts::3 81501 # Per bank write bursts
> system.physmem.perBankWrBursts::4 79021 # Per bank write bursts
> system.physmem.perBankWrBursts::5 86869 # Per bank write bursts
> system.physmem.perBankWrBursts::6 77167 # Per bank write bursts
> system.physmem.perBankWrBursts::7 78926 # Per bank write bursts
> system.physmem.perBankWrBursts::8 71646 # Per bank write bursts
> system.physmem.perBankWrBursts::9 75252 # Per bank write bursts
> system.physmem.perBankWrBursts::10 73334 # Per bank write bursts
> system.physmem.perBankWrBursts::11 76259 # Per bank write bursts
> system.physmem.perBankWrBursts::12 74746 # Per bank write bursts
> system.physmem.perBankWrBursts::13 79667 # Per bank write bursts
> system.physmem.perBankWrBursts::14 75302 # Per bank write bursts
> system.physmem.perBankWrBursts::15 78217 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
< system.physmem.totGap 47381681282500 # Total gap between requests
---
> system.physmem.numWrRetry 64 # Number of times write queue was full causing retry
> system.physmem.totGap 47461932782500 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1363573 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1561985 # Read request sizes (log2)
143,168c143,168
< system.physmem.writePktSize::6 1072761 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 866656 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 332331 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 37458 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 26767 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 22591 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 20794 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 18575 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 16649 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 13953 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2927 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1423 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 882 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 650 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 423 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 256 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 225 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 182 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 162 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1239858 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 973357 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 368872 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 48939 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 35383 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 30040 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 27781 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 24940 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 22435 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 19175 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4270 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1963 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1251 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 910 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 672 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 409 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 353 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 290 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 241 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 109 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 70 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
191,257c191,257
< system.physmem.wrQLenPdf::15 18197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 20578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 39692 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 50721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 56749 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 59564 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 63294 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 64512 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 67826 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 69607 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 74517 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 70375 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 69942 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 75013 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 68273 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 64139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 61949 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1753 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 769 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 679 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 363 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 392 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 316 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 286 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 277 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 149 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 845070 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 184.496716 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 112.937858 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 245.074486 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 518646 61.37% 61.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 158346 18.74% 80.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 53030 6.28% 86.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 28124 3.33% 89.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 18210 2.15% 91.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11789 1.40% 93.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 8638 1.02% 94.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 8488 1.00% 95.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 39799 4.71% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 845070 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60101 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 22.679190 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 352.199560 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 60098 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 73662 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 76578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 77244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 79843 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 84567 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 82434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 83310 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 91239 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 81410 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 76067 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 73611 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 3385 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1421 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 940 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 727 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 568 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 422 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 365 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 390 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 338 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 362 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes
261,282c261,282
< system.physmem.rdPerTurnAround::total 60101 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60101 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.854245 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.273539 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.223401 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 56328 93.72% 93.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 1584 2.64% 96.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 235 0.39% 96.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 339 0.56% 97.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 81 0.13% 97.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 304 0.51% 97.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 166 0.28% 98.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 108 0.18% 98.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 84 0.14% 98.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 101 0.17% 98.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 39 0.06% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 59 0.10% 98.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 433 0.72% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 41 0.07% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 33 0.05% 99.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 91 0.15% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 21 0.03% 99.91% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads
284,303c284,308
< system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 4 0.01% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 60101 # Writes before turning the bus around for reads
< system.physmem.totQLat 33864601554 # Total ticks spent queuing
< system.physmem.totMemAccLat 59422351554 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6815400000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 24844.18 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads
> system.physmem.totQLat 43176438588 # Total ticks spent queuing
> system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst
305,309c310,314
< system.physmem.avgMemAccLat 43594.18 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.84 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s
312c317
< system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
---
> system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
314,332c319,337
< system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
< system.physmem.readRowHits 1093420 # Number of row buffer hits during reads
< system.physmem.writeRowHits 497646 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.22 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 46.38 # Row buffer hit rate for writes
< system.physmem.avgGap 19427177.44 # Average gap between requests
< system.physmem.pageHitRate 65.31 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3178488600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1734294375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5058697800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3454513920 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1187868500820 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27387019861500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31683055542135 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.677294 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45560417443643 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1582178520000 # Time in different power states
---
> system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing
> system.physmem.readRowHits 1247973 # Number of row buffer hits during reads
> system.physmem.writeRowHits 562447 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes
> system.physmem.avgGap 16923811.64 # Average gap between requests
> system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.805156 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states
334c339
< system.physmem_0.memoryStateTime::ACT 239087007607 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states
336,346c341,351
< system.physmem_1.actEnergy 3210233040 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1751615250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 5573178000 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3498901920 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1203743481615 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27373094439750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31685613034695 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.731270 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45537111526279 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1582178520000 # Time in different power states
---
> system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.767346 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states
348c353
< system.physmem_1.memoryStateTime::ACT 262392956221 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states
382,386c387,391
< system.cpu0.branchPred.lookups 132357688 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 93633614 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 5912907 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 98988393 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 72530253 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 141158417 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits
388,390c393,395
< system.cpu0.branchPred.BTBHitPct 73.271472 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 15763072 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 1049472 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions.
421,441c426,445
< system.cpu0.dtb.walker.walks 265700 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 265700 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9033 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73083 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 265700 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 265700 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 265700 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 82116 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 81335 99.05% 99.05% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 195 0.24% 99.29% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 500 0.61% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walks 283140 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
444c448
< system.cpu0.dtb.walker.walkCompletionTime::total 82116 # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency
448,451c452,455
< system.cpu0.dtb.walker.walkPageSizes::4K 73083 89.00% 89.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 9033 11.00% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 82116 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 265700 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst
453,454c457,458
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 265700 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 82116 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst
456,457c460,461
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 82116 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 347816 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst
460,463c464,467
< system.cpu0.dtb.read_hits 86394812 # DTB read hits
< system.cpu0.dtb.read_misses 220998 # DTB read misses
< system.cpu0.dtb.write_hits 74903999 # DTB write hits
< system.cpu0.dtb.write_misses 44702 # DTB write misses
---
> system.cpu0.dtb.read_hits 90921588 # DTB read hits
> system.cpu0.dtb.read_misses 233548 # DTB read misses
> system.cpu0.dtb.write_hits 80603054 # DTB write hits
> system.cpu0.dtb.write_misses 49592 # DTB write misses
466,470c470,474
< system.cpu0.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 37665 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 8673 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch
472,474c476,478
< system.cpu0.dtb.perms_faults 10301 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 86615810 # DTB read accesses
< system.cpu0.dtb.write_accesses 74948701 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 91155136 # DTB read accesses
> system.cpu0.dtb.write_accesses 80652646 # DTB write accesses
476,478c480,482
< system.cpu0.dtb.hits 161298811 # DTB hits
< system.cpu0.dtb.misses 265700 # DTB misses
< system.cpu0.dtb.accesses 161564511 # DTB accesses
---
> system.cpu0.dtb.hits 171524642 # DTB hits
> system.cpu0.dtb.misses 283140 # DTB misses
> system.cpu0.dtb.accesses 171807782 # DTB accesses
508,532c512,532
< system.cpu0.itb.walker.walks 59769 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 59769 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 498 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49758 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 59769 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 59769 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 59769 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 50256 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 46691 92.91% 92.91% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 2859 5.69% 98.60% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-98303 7 0.01% 98.61% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-163839 383 0.76% 99.37% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-196607 254 0.51% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-229375 9 0.02% 99.89% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 25 0.05% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 50256 # Table walker service (enqueue to completion) latency
---
> system.cpu0.itb.walker.walks 66290 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency
536,538c536,538
< system.cpu0.itb.walker.walkPageSizes::4K 49758 99.01% 99.01% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 498 0.99% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 50256 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated
540,541c540,541
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59769 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59769 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst
543,547c543,547
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50256 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50256 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 110025 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 238646690 # ITB inst hits
< system.cpu0.itb.inst_misses 59769 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 252665762 # ITB inst hits
> system.cpu0.itb.inst_misses 66290 # ITB inst misses
554,556c554,556
< system.cpu0.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 27225 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB
560c560
< system.cpu0.itb.perms_faults 203945 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions
563,567c563,567
< system.cpu0.itb.inst_accesses 238706459 # ITB inst accesses
< system.cpu0.itb.hits 238646690 # DTB hits
< system.cpu0.itb.misses 59769 # DTB misses
< system.cpu0.itb.accesses 238706459 # DTB accesses
< system.cpu0.numCycles 1007854766 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses
> system.cpu0.itb.hits 252665762 # DTB hits
> system.cpu0.itb.misses 66290 # DTB misses
> system.cpu0.itb.accesses 252732052 # DTB accesses
> system.cpu0.numCycles 1081051562 # number of cpu cycles simulated
570,576c570,576
< system.cpu0.committedInsts 441362500 # Number of instructions committed
< system.cpu0.committedOps 518398273 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 43962057 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 93756283149 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.283508 # CPI: cycles per instruction
< system.cpu0.ipc 0.437923 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 468741146 # Number of instructions committed
> system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.306287 # CPI: cycles per instruction
> system.cpu0.ipc 0.433597 # IPC: instructions per cycle
578,585c578,585
< system.cpu0.kern.inst.quiesce 5202 # number of quiesce instructions executed
< system.cpu0.tickCycles 710760418 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 297094348 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 5529190 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 480.574807 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 153025870 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5529699 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 27.673454 # Average number of references to valid blocks.
---
> system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed
> system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 5850262 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks.
587,686c587,686
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.574807 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938623 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 325514940 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 325514940 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 79084139 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 79084139 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 69445340 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 69445340 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 251787 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 251787 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143392 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 143392 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1790882 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1790882 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1762255 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1762255 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 148529479 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 148529479 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 148781266 # number of overall hits
< system.cpu0.dcache.overall_hits::total 148781266 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 3438422 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 3438422 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 2286291 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 2286291 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 632969 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 632969 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 749661 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 749661 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167888 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 167888 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194810 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 194810 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 5724713 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 5724713 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 6357682 # number of overall misses
< system.cpu0.dcache.overall_misses::total 6357682 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57301041000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 57301041000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 58503452500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 58503452500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 69078584500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 69078584500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2562226000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2562226000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5482087500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 5482087500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5099500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5099500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 115804493500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 115804493500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 82522561 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 82522561 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 71731631 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 71731631 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 884756 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 884756 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 893053 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 893053 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1958770 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 1958770 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1957065 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 1957065 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 154254192 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 154254192 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 155138948 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 155138948 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041666 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.041666 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031873 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.031873 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715416 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715416 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839436 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.839436 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085711 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085711 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037112 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040981 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.040981 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16664.923910 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.214442 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978934 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.978934 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 346062459 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 346062459 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 83268986 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 83268986 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 74755135 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 74755135 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 273368 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 273368 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 183787 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 183787 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1841830 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1841830 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1806426 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1806426 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 158024121 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 158024121 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 158297489 # number of overall hits
> system.cpu0.dcache.overall_hits::total 158297489 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3569470 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3569470 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 2481271 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 2481271 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 690957 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 690957 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 806074 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 806074 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173924 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 173924 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 207838 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 207838 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 6050741 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 6050741 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 6741698 # number of overall misses
> system.cpu0.dcache.overall_misses::total 6741698 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 62945089000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 62945089000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62898003000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 62898003000 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 71296883500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 71296883500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2825966000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2825966000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5775275000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 5775275000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4714000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4714000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 125843092000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 125843092000 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 125843092000 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 125843092000 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 86838456 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 86838456 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 77236406 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 77236406 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964325 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 964325 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 989861 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 989861 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015754 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.032126 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.716519 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.716519 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.814330 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.814330 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086282 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086282 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103183 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103183 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036878 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.036878 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040849 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.040849 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17634.295568 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 17634.295568 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25349.106567 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 25349.106567 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88449.551158 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88449.551158 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16248.280858 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency
689,692c689,692
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency
701,790c701,790
< system.cpu0.dcache.writebacks::writebacks 5529208 # number of writebacks
< system.cpu0.dcache.writebacks::total 5529208 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 425438 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 425438 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 937459 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 937459 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 53 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 53 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41154 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41154 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 15 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::total 15 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1362897 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1362897 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1362897 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1362897 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3012984 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3012984 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1348832 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1348832 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631309 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 631309 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 749608 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 749608 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126734 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126734 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194795 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 194795 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4361816 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4361816 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 4993125 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 4993125 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15485 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31915 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44936822000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44936822000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34248227000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34248227000 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15688131000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15688131000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 68324152500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 68324152500 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1728085500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1728085500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5286161500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5286161500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5009500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5009500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79185049000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 79185049000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94873180000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 94873180000 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2777500000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2777500000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2891122000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2891122000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5668622000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5668622000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036511 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.713540 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.713540 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.839377 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.839377 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099534 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099534 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028277 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.028277 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032185 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.032185 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks
> system.cpu0.dcache.writebacks::total 5850286 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency
793,802c793,802
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency
804,808c804,808
< system.cpu0.icache.tags.replacements 8961850 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 229474819 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 8962362 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 25.604279 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.replacements 9594128 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks.
810c810
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor
---
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor
814,816c814,816
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id
818,855c818,855
< system.cpu0.icache.tags.tag_accesses 485836753 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 485836753 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 229474819 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 229474819 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 229474819 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 229474819 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 229474819 # number of overall hits
< system.cpu0.icache.overall_hits::total 229474819 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 8962372 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 8962372 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 8962372 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 8962372 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 8962372 # number of overall misses
< system.cpu0.icache.overall_misses::total 8962372 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94471116000 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 94471116000 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 94471116000 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 94471116000 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 94471116000 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 94471116000 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 238437191 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 238437191 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 238437191 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 238437191 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 238437191 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 238437191 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037588 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.037588 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037588 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.037588 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037588 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.037588 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10540.860835 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10540.860835 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits
> system.cpu0.icache.overall_hits::total 242861120 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses
> system.cpu0.icache.overall_misses::total 9594650 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 102613134000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 102613134000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 102613134000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 102613134000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 102613134000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 102613134000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 252455770 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 252455770 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 252455770 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency
864,871c864,871
< system.cpu0.icache.writebacks::writebacks 8961850 # number of writebacks
< system.cpu0.icache.writebacks::total 8961850 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8962372 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 8962372 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 8962372 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 8962372 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 8962372 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 8962372 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 9594128 # number of writebacks
> system.cpu0.icache.writebacks::total 9594128 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9594650 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 9594650 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 9594650 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 9594650 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 9594650 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 9594650 # number of overall MSHR misses
876,881c876,881
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89989930500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 89989930500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89989930500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 89989930500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89989930500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 89989930500 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 97815809000 # number of overall MSHR miss cycles
886,897c886,897
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037588 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.037588 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.037588 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10040.860890 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038005 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency
903,905c903,905
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7773827 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7774021 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 173 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 8065650 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 8066797 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 1004 # number of redundant prefetches already in prefetch queue
908,913c908,913
< system.cpu0.l2cache.prefetcher.pfSpanPage 1015459 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2700718 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16213.055668 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 22438549 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2716794 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 8.259201 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1049003 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2949800 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16165.081558 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 23810069 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2965603 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 8.028745 # Average number of references to valid blocks.
915,977c915,980
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15223.315465 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.903430 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.295505 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 879.541268 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.929157 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003412 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003314 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053683 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.989566 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1224 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14798 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 814 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 215 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 997 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6189 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2013 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074707 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903198 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 488653498 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 488653498 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 497387 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 151168 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 648555 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 3589798 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 3589798 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 10898588 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 10898588 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 348 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 348 # number of UpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 828045 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 828045 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8251361 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 8251361 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2786170 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2786170 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 167822 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 167822 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 497387 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 151168 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 8251361 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3614215 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 12514131 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 497387 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 151168 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 8251361 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3614215 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 12514131 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11281 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7561 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 18842 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256026 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 256026 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 194786 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 194786 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15191.178363 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 63.510017 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 64.560721 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 845.832457 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.927196 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003876 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003940 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051626 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.986638 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1186 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 162 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 909 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 878 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5504 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7511 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 526 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.072388 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 520895158 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 520895158 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527427 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 170829 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 698256 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 3866912 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 3866912 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 11575004 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 11575004 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 494 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 494 # number of UpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 901398 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 901398 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8819397 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 8819397 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2877090 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2877090 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196747 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 196747 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527427 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 170829 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 8819397 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3778488 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 13296141 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527427 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 170829 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 8819397 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3778488 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 13296141 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12512 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8836 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 21348 # number of ReadReq misses
> system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
> system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 265863 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 265863 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 207797 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 207797 # number of SCUpgradeReq misses
980,1035c983,1038
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 272487 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 272487 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 711010 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 711010 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 984601 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 984601 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 580093 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 580093 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11281 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7561 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 711010 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1257088 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1986940 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11281 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7561 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 711010 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1257088 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1986940 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 432507500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 322890000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 755397500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3595898500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 3595898500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1942602000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1942602000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4921998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4921998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 17184690000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 17184690000 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 26717037500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 26717037500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 38302477992 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 38302477992 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 65953326000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 65953326000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 432507500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 322890000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 26717037500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 55487167992 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 82959602992 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 432507500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 322890000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 26717037500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 55487167992 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 82959602992 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 508668 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158729 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 667397 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3589798 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 3589798 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 10898588 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 10898588 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256374 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 256374 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194786 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 194786 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295222 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 295222 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 775252 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 775252 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1066801 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1066801 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 607029 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 607029 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12512 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8836 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 775252 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1362023 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2158623 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12512 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8836 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 775252 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1362023 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2158623 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 555558000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 430868000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 986426000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3493305000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 3493305000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1939943000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1939943000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4477498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4477498 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18708847499 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 18708847499 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 30179302500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 30179302500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44632390995 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44632390995 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67815733000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 67815733000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 555558000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 430868000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 30179302500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 63341238494 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 94506966994 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 555558000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 430868000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 30179302500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 63341238494 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 94506966994 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 539939 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179665 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 719604 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3866914 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 3866914 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 11575004 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 11575004 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266357 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 266357 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 207797 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 207797 # number of SCUpgradeReq accesses(hits+misses)
1038,1060c1041,1065
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1100532 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1100532 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 8962371 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 8962371 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3770771 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3770771 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 747915 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 747915 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 508668 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 158729 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 8962371 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 4871303 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 14501071 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 508668 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 158729 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 8962371 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 4871303 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 14501071 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047635 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.028232 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998643 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998643 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196620 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1196620 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9594649 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 9594649 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3943891 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3943891 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803776 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 803776 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 539939 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179665 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 9594649 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5140511 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 15454764 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 539939 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179665 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 9594649 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5140511 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 15454764 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049180 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.029666 # miss rate for ReadReq accesses
> system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
> system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998145 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998145 # miss rate for UpgradeReq accesses
1065,1110c1070,1115
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.247596 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.247596 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079333 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079333 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261114 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261114 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.775614 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.775614 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047635 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079333 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258060 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.137020 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047635 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079333 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258060 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.137020 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42704.668695 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40091.152744 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14045.052065 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14045.052065 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9973.006274 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9973.006274 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 546888.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 546888.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63066.091226 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63066.091226 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37576.176847 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37576.176847 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38901.522538 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38901.522538 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113694.400725 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113694.400725 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42704.668695 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37576.176847 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44139.446079 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 41752.444962 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42704.668695 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37576.176847 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44139.446079 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 41752.444962 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.246713 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.246713 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.080800 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.080800 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.270495 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.270495 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.755222 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.755222 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049180 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080800 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264959 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.139674 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023173 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049180 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080800 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264959 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.139674 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48762.788592 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 46206.951471 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13139.492897 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13139.492897 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9335.760382 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9335.760382 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 497499.777778 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 497499.777778 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63372.131816 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63372.131816 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38928.377482 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38928.377482 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41837.597635 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41837.597635 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 111717.451720 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 111717.451720 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 43781.135934 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 44402.014066 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48762.788592 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38928.377482 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46505.263490 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 43781.135934 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1112c1117
< system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1114c1119
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1118,1144c1123,1156
< system.cpu0.l2cache.writebacks::writebacks 1535075 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1535075 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5686 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 5686 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1129 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1129 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6815 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 6824 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6815 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 6824 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11281 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7559 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 18840 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 764184 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 764184 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256026 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 256026 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 194786 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 194786 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.writebacks::writebacks 1702054 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1702054 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8173 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 8173 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1611 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1611 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 4 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9784 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 9799 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9784 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 9799 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12511 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8833 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 21344 # number of ReadReq MSHR misses
> system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
> system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 812970 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 265863 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 265863 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 207797 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 207797 # number of SCUpgradeReq MSHR misses
1147,1165c1159,1177
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 266801 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 266801 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 711003 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 711003 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 983472 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 983472 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 580093 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 580093 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11281 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7559 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 711003 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1250273 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1980116 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11281 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7559 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 711003 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1250273 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 764184 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2744300 # number of overall MSHR misses
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 287049 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 287049 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 775241 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 775241 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1065190 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1065190 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 607025 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 607025 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12511 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8833 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 775241 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1352239 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2148824 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12511 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8833 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 775241 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1352239 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 812970 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2961794 # number of overall MSHR misses
1167,1170c1179,1182
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 67794 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 71839 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable
1172,1203c1184,1215
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84224 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 277497500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 642319000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35765340066 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7977745499 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7977745499 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3820823499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3820823499 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4591998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4591998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14771566500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14771566500 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 22450783500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22450783500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32316263992 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32316263992 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 62472768000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 62472768000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277497500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22450783500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 47087830492 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 70180932992 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277497500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22450783500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 47087830492 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 105946273058 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 92887 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 377798500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 858266500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44849426201 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7795522498 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7795522498 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4002040000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4002040000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4147498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4147498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15893166999 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15893166999 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25527386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25527386000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38109816995 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38109816995 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64173364000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles
1205,1208c1217,1220
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2653464500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9649619500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2767850000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2767850000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles
1210,1214c1222,1228
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5421314500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12417469500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028229 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
> system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
1217,1218c1231,1232
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998643 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998643 # mshr miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses
1223,1239c1237,1253
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.242429 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.242429 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079332 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260815 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260815 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.775614 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.775614 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136550 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses
1241,1271c1255,1285
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189248 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 510222 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 510222 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency
1273,1276c1287,1290
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency
1278,1279c1292,1293
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency
1281,1319c1295,1333
< system.cpu0.toL2Bus.snoop_filter.tot_requests 29837081 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15255646 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2671 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 2145858 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2145409 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 449 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 816702 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 13639128 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 16430 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 16430 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 5128977 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 10898588 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 2922524 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 983530 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 456186 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 346923 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 512261 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1174017 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1108975 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8962372 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4744543 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 755832 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 747915 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26989618 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17891664 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 337201 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1079102 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 46297585 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1150395968 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671911459 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1269832 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4069344 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1827646603 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 7092856 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 22718303 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.108382 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.310926 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram
1321,1323c1335,1337
< system.cpu0.toL2Bus.snoop_fanout::0 20256496 89.16% 89.16% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 2461358 10.83% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 449 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram
1327,1328c1341,1342
< system.cpu0.toL2Bus.snoop_fanout::total 22718303 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 29677749987 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks)
1330c1344
< system.cpu0.toL2Bus.snoopLayer0.occupancy 177431926 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks)
1332c1346
< system.cpu0.toL2Bus.respLayer0.occupancy 13525621280 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks)
1334c1348
< system.cpu0.toL2Bus.respLayer1.occupancy 7933800899 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks)
1336c1350
< system.cpu0.toL2Bus.respLayer2.occupancy 178529385 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks)
1338c1352
< system.cpu0.toL2Bus.respLayer3.occupancy 570584194 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks)
1340,1344c1354,1358
< system.cpu1.branchPred.lookups 131141392 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 92458444 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 6313157 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 97645974 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 70218111 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 133924240 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits
1346,1348c1360,1362
< system.cpu1.branchPred.BTBHitPct 71.910913 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 15567912 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 1046402 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions.
1378,1396c1392,1410
< system.cpu1.dtb.walker.walks 286101 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 286101 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9457 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80855 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 286101 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 286101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 286101 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 90312 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 89271 98.85% 98.85% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 163 0.18% 99.03% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 728 0.81% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 35 0.04% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 43 0.05% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 28 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walks 293746 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency
1398c1412
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1400c1414
< system.cpu1.dtb.walker.walkCompletionTime::total 90312 # Table walker service (enqueue to completion) latency
---
> system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency
1404,1407c1418,1421
< system.cpu1.dtb.walker.walkPageSizes::4K 80855 89.53% 89.53% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 9457 10.47% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 90312 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 286101 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst
1409,1410c1423,1424
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 286101 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90312 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst
1412,1413c1426,1427
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90312 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 376413 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst
1416,1419c1430,1433
< system.cpu1.dtb.read_hits 84597106 # DTB read hits
< system.cpu1.dtb.read_misses 236435 # DTB read misses
< system.cpu1.dtb.write_hits 75395592 # DTB write hits
< system.cpu1.dtb.write_misses 49666 # DTB write misses
---
> system.cpu1.dtb.read_hits 86040245 # DTB read hits
> system.cpu1.dtb.read_misses 244355 # DTB read misses
> system.cpu1.dtb.write_hits 75067998 # DTB write hits
> system.cpu1.dtb.write_misses 49391 # DTB write misses
1422,1426c1436,1440
< system.cpu1.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 35920 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 1878 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 8819 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch
1428,1430c1442,1444
< system.cpu1.dtb.perms_faults 11434 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 84833541 # DTB read accesses
< system.cpu1.dtb.write_accesses 75445258 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 86284600 # DTB read accesses
> system.cpu1.dtb.write_accesses 75117389 # DTB write accesses
1432,1434c1446,1448
< system.cpu1.dtb.hits 159992698 # DTB hits
< system.cpu1.dtb.misses 286101 # DTB misses
< system.cpu1.dtb.accesses 160278799 # DTB accesses
---
> system.cpu1.dtb.hits 161108243 # DTB hits
> system.cpu1.dtb.misses 293746 # DTB misses
> system.cpu1.dtb.accesses 161401989 # DTB accesses
1464,1483c1478,1499
< system.cpu1.itb.walker.walks 70499 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 70499 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 664 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63113 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 70499 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 70499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 70499 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 63777 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 62694 98.30% 98.30% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 8 0.01% 98.31% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 977 1.53% 99.85% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.03% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 63777 # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walks 65124 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency
1487,1489c1503,1505
< system.cpu1.itb.walker.walkPageSizes::4K 63113 98.96% 98.96% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 664 1.04% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 63777 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated
1491,1492c1507,1508
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 70499 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 70499 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst
1494,1498c1510,1514
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63777 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63777 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 134276 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 232338774 # ITB inst hits
< system.cpu1.itb.inst_misses 70499 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 239249458 # ITB inst hits
> system.cpu1.itb.inst_misses 65124 # ITB inst misses
1505,1507c1521,1523
< system.cpu1.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 25488 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB
1511c1527
< system.cpu1.itb.perms_faults 208774 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions
1514,1518c1530,1534
< system.cpu1.itb.inst_accesses 232409273 # ITB inst accesses
< system.cpu1.itb.hits 232338774 # DTB hits
< system.cpu1.itb.misses 70499 # DTB misses
< system.cpu1.itb.accesses 232409273 # DTB accesses
< system.cpu1.numCycles 934140798 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses
> system.cpu1.itb.hits 239249458 # DTB hits
> system.cpu1.itb.misses 65124 # DTB misses
> system.cpu1.itb.accesses 239314582 # DTB accesses
> system.cpu1.numCycles 947127317 # number of cpu cycles simulated
1521,1525c1537,1541
< system.cpu1.committedInsts 431679438 # Number of instructions committed
< system.cpu1.committedOps 508807266 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 44929639 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 4564 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 93829974504 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
---
> system.cpu1.committedInsts 437680583 # Number of instructions committed
> system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1529,1540c1545,1556
< system.cpu1.kern.inst.quiesce 13472 # number of quiesce instructions executed
< system.cpu1.tickCycles 702823433 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 231317365 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 5070717 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 459.449189 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 152180192 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5071229 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 30.008543 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.449189 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897362 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.897362 # Average percentage of cache occupancy
---
> system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed
> system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 5225400 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy
1542,1544c1558,1560
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id
1546,1637c1562,1653
< system.cpu1.dcache.tags.tag_accesses 322309894 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 322309894 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 77705355 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 77705355 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 70371137 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 70371137 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 247594 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 247594 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 180643 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 180643 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624088 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1624088 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1588942 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1588942 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 148076492 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 148076492 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 148324086 # number of overall hits
< system.cpu1.dcache.overall_hits::total 148324086 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 3222913 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 3222913 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 2183254 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 2183254 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 592382 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 592382 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 513289 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 513289 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 153645 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 153645 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187516 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 187516 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 5406167 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 5406167 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 5998549 # number of overall misses
< system.cpu1.dcache.overall_misses::total 5998549 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52049628500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 52049628500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 47596189000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 47596189000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20614887000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 20614887000 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2521232500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2521232500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5224495500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 5224495500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4869500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4869500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 99645817500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 99645817500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 99645817500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 99645817500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 80928268 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 80928268 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 72554391 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 72554391 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 839976 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 839976 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 693932 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 693932 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1777733 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1777733 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1776458 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1776458 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 153482659 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 153482659 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 154322635 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 154322635 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039824 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.039824 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030091 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.030091 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.705237 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.705237 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739682 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739682 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086427 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086427 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105556 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105556 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035223 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.035223 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038870 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.038870 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16149.870785 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 16149.870785 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21800.573364 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21800.573364 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40162.339345 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 40162.339345 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16409.466628 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16409.466628 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27861.598477 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27861.598477 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits
> system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses
> system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2730537500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2730537500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5515974000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5515974000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4942500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4942500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 107635946500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 107635946500 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 107635946500 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 107635946500 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1937375 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935851 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1935851 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 154415439 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 154415439 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 155298160 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 155298160 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040982 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.040982 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031547 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.031547 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.733727 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.733727 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.767180 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.767180 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082336 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082336 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103919 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103919 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036570 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.036570 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040533 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.040533 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16561.467603 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16561.467603 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22756.808276 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 22756.808276 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 47160.133951 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 47160.133951 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17117.640237 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17117.640237 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27419.329824 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27419.329824 # average StoreCondReq miss latency
1640,1643c1656,1659
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18431.879278 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 18431.879278 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16611.653502 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 16611.653502 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19060.750994 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency
1652,1741c1668,1757
< system.cpu1.dcache.writebacks::writebacks 5070732 # number of writebacks
< system.cpu1.dcache.writebacks::total 5070732 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 348629 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 348629 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 899898 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 899898 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 110 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 110 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43396 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43396 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 20 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::total 20 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1248527 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1248527 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1248527 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1248527 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2874284 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2874284 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1283356 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1283356 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 591957 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 591957 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 513179 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 513179 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 110249 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 110249 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187496 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 187496 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4157640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4157640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4749597 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4749597 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22695 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44342 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41633767000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41633767000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28169318500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28169318500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14402198000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14402198000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20089556500 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20089556500 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1594381500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1594381500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035777500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035777500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4638000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4638000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69803085500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 69803085500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84205283500 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 84205283500 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4145895000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4145895000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4016889500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4016889500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8162784500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8162784500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035516 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035516 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017688 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017688 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.704731 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.704731 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739523 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739523 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062017 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062017 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105545 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105545 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027089 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.027089 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030777 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.030777 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks
> system.cpu1.dcache.writebacks::total 5225429 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41578 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41578 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 34 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::total 34 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1320370 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1320370 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1320370 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1320370 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2986376 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2986376 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1340248 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1340248 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 647394 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 647394 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 450852 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 450852 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117938 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117938 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201137 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 201137 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4326624 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4326624 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4974018 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4974018 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 19129 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 36596 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44483005500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44483005500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30789351000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30789351000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15729879000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15729879000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20808027500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20808027500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1765421000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1765421000 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5312775000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5312775000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4745500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4745500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75272356500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 75272356500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91002235500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 91002235500 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3151598000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.028019 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.032029 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14895.313082 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14895.313082 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22972.875916 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22972.875916 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24297.227036 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24297.227036 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 46152.678706 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 46152.678706 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14969.060015 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14969.060015 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26413.713041 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26413.713041 # average StoreCondReq mshr miss latency
1744,1753c1760,1769
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16789.112453 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16789.112453 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17728.932265 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17728.932265 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182678.783873 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182678.783873 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185563.334411 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185563.334411 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184086.971720 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169624.978531 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167079.393923 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167079.393923 # average overall mshr uncacheable latency
1755,1763c1771,1779
< system.cpu1.icache.tags.replacements 9965841 # number of replacements
< system.cpu1.icache.tags.tagsinuse 506.684865 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 222156193 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 9966353 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 22.290621 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684865 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 9231311 # number of replacements
> system.cpu1.icache.tags.tagsinuse 506.694166 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 229790487 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 9231823 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 24.891128 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8386495264000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.694166 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989637 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.989637 # Average percentage of cache occupancy
1765,1767c1781,1783
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id
1769,1806c1785,1822
< system.cpu1.icache.tags.tag_accesses 474211445 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 474211445 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 222156193 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 222156193 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 222156193 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 222156193 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 222156193 # number of overall hits
< system.cpu1.icache.overall_hits::total 222156193 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 9966353 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 9966353 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 9966353 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 9966353 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 9966353 # number of overall misses
< system.cpu1.icache.overall_misses::total 9966353 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 101175482500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 101175482500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 101175482500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 101175482500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 101175482500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 101175482500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 232122546 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 232122546 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 232122546 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 232122546 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 232122546 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 232122546 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.042936 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.042936 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.042936 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.042936 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.042936 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.042936 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10151.705694 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10151.705694 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10151.705694 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10151.705694 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 487276445 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 487276445 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 229790487 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 229790487 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 229790487 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 229790487 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 229790487 # number of overall hits
> system.cpu1.icache.overall_hits::total 229790487 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 9231824 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 9231824 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 9231824 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 9231824 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 9231824 # number of overall misses
> system.cpu1.icache.overall_misses::total 9231824 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94524443000 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 94524443000 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 94524443000 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 94524443000 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 94524443000 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 94524443000 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 239022311 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 239022311 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 239022311 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 239022311 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 239022311 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 239022311 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038623 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038623 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038623 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10238.978018 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10238.978018 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10238.978018 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10238.978018 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10238.978018 # average overall miss latency
1815,1822c1831,1838
< system.cpu1.icache.writebacks::writebacks 9965841 # number of writebacks
< system.cpu1.icache.writebacks::total 9965841 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9966353 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 9966353 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 9966353 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 9966353 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 9966353 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 9966353 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 9231311 # number of writebacks
> system.cpu1.icache.writebacks::total 9231311 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9231824 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 9231824 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 9231824 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 9231824 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 9231824 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 9231824 # number of overall MSHR misses
1827,1832c1843,1848
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 96192306000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 96192306000 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 96192306000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 96192306000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 96192306000 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 96192306000 # number of overall MSHR miss cycles
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 89908531500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 89908531500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 89908531500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 89908531500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 89908531500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 89908531500 # number of overall MSHR miss cycles
1837,1848c1853,1864
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.042936 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.042936 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.042936 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9651.705694 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
---
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038623 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9738.978072 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency
1854,1856c1870,1872
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 6510084 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 6511152 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 939 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue
1859,2015c1875,2032
< system.cpu1.l2cache.prefetcher.pfSpanPage 783896 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2135895 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13423.461637 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 24573645 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2151628 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 11.420954 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 9991507442000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.598025 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.072993 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 692.984620 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.768421 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004460 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.042296 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.819303 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 945 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14692 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 44 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1194 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8241 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057678 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896729 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 506241329 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 506241329 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551867 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186859 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 738726 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3212995 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3212995 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 11821046 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 11821046 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 371 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 371 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 838525 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 838525 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 9300099 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 9300099 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698124 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2698124 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 249185 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 249185 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 551867 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186859 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 9300099 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3536649 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 13575474 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 551867 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186859 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 9300099 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3536649 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 13575474 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10809 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8103 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 18912 # number of ReadReq misses
< system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
< system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204693 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 204693 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187493 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 187493 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 242458 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 242458 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 666254 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 666254 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 877979 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 877979 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 262039 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 262039 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10809 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8103 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 666254 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1120437 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1805603 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10809 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8103 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 666254 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1120437 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1805603 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 470190500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 378267000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 848457500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3269531500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 3269531500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1816771500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1816771500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4553499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4553499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12943476999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 12943476999 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 25012449000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 25012449000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34434512490 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34434512490 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17540729000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 17540729000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 470190500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 378267000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 25012449000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 47377989489 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 73238895989 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 470190500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 378267000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 25012449000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 47377989489 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 73238895989 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 562676 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 194962 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 757638 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3212997 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3212997 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 11821046 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 11821046 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205064 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 205064 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187493 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 187493 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1080983 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1080983 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9966353 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 9966353 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3576103 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3576103 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 511224 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 511224 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 562676 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 194962 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 9966353 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4657086 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 15381077 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 562676 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 194962 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 9966353 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4657086 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 15381077 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041562 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.024962 # miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
< system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998191 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998191 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2326720 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13467.956369 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 23154784 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2342909 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 9.882921 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9860254327500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.584174 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 60.491814 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 58.201363 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 750.679017 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.768957 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003692 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003552 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.045818 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.822019 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1395 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14742 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 404 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 859 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 122 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.899780 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 488472501 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 488472501 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 576439 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168221 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 744660 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3264846 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3264846 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 11189694 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 11189694 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 575 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 575 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867363 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 867363 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8545306 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 8545306 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2781382 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2781382 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 181539 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 181539 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 576439 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168221 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 8545306 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3648745 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 12938711 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 576439 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168221 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 8545306 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3648745 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 12938711 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12346 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8532 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 20878 # number of ReadReq misses
> system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
> system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 223343 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 223343 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 201132 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 201132 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 251639 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 251639 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686518 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 686518 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970013 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 970013 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 267232 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 267232 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12346 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8532 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 686518 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1221652 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1929048 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12346 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8532 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 686518 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1221652 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1929048 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 599407500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 460132500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1059540000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3297082000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3297082000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1852998500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1852998500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4653499 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4653499 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14739798000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 14739798000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24441807000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24441807000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37974197490 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37974197490 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18803051000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 18803051000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 599407500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 460132500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24441807000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 52713995490 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 78215342490 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 599407500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 460132500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24441807000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 52713995490 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 78215342490 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 588785 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176753 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 765538 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3264847 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3264847 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 11189694 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 11189694 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223918 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 223918 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201132 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 201132 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1119002 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1119002 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9231824 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 9231824 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3751395 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3751395 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448771 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 448771 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 588785 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176753 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 9231824 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4870397 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 14867759 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 588785 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176753 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 9231824 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4870397 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 14867759 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048271 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.027272 # miss rate for ReadReq accesses
> system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
> system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997432 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997432 # miss rate for UpgradeReq accesses
2020,2064c2037,2081
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224294 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224294 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.066850 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.066850 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245513 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245513 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.512572 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.512572 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.041562 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.066850 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240588 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.117391 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.041562 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.066850 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240588 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.117391 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46682.339874 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44863.446489 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15972.854470 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15972.854470 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9689.809753 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9689.809753 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1517833 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1517833 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53384.408842 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53384.408842 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37541.911943 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37541.911943 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39220.200586 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39220.200586 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66939.383069 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66939.383069 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 40562.015010 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 40562.015010 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224878 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224878 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.074364 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.074364 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.258574 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.258574 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.595475 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.595475 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048271 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.074364 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.250832 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.129747 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020969 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048271 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.074364 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.250832 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.129747 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 53930.203938 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 50749.113900 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14762.414761 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14762.414761 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9212.847782 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9212.847782 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 930699.800000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 930699.800000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58575.173165 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58575.173165 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35602.572693 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35602.572693 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39148.132540 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39148.132540 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 70362.273231 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 70362.273231 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 40546.084125 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 48550.745181 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 53930.203938 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35602.572693 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43149.764000 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 40546.084125 # average overall miss latency
2073,2122c2090,2141
< system.cpu1.l2cache.writebacks::writebacks 1050489 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1050489 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5853 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 5853 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1181 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1181 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7034 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 7045 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7034 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 7045 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10809 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8100 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 18909 # number of ReadReq MSHR misses
< system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
< system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 706258 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 706258 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204693 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 204693 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 187493 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 187493 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 236605 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 236605 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 666246 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 666246 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 876798 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 876798 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 262039 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 262039 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10809 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8100 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 666246 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1113403 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1798558 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10809 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8100 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 666246 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1113403 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 706258 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2504816 # number of overall MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 1166062 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1166062 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8177 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 8177 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 786 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 786 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8963 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 8969 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8963 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 8969 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12346 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8530 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 20876 # number of ReadReq MSHR misses
> system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
> system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 757140 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 223343 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 223343 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 201132 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 201132 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243462 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 243462 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686514 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686514 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969227 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969227 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 267229 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 267229 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12346 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8530 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686514 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1212689 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1920079 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12346 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8530 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686514 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1212689 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 757140 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2677219 # number of overall MSHR misses
2124,2127c2143,2146
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22787 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 19129 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 19221 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17467 # number of WriteReq MSHR uncacheable
2129,2160c2148,2179
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44434 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329621500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 734958000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32803670450 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6637113997 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6637113997 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3625235500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3625235500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4217499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4217499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10699007999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10699007999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 21014773500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 21014773500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29089304990 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29089304990 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15968495000 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15968495000 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329621500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 21014773500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39788312989 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 61538044489 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329621500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 21014773500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39788312989 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 94341714939 # number of overall MSHR miss cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 36596 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 36688 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 408923500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 934255000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45309762891 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7082960998 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7082960998 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3799999000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3799999000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4287499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4287499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11990250000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11990250000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322650500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322650500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32101541990 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32101541990 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 17199481500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 17199481500 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 408923500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322650500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44091791990 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 65348697490 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 525331500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 408923500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322650500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44091791990 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45309762891 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 110658460381 # number of overall MSHR miss cycles
2162,2165c2181,2184
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3964210500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3976425000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3854486000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3854486000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2998478000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3010692500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2831799500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2831799500 # number of WriteReq MSHR uncacheable cycles
2167,2173c2186,2192
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7818696500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7830911000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024958 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
< system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
> system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
2176,2177c2195,2196
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998191 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998191 # mshr miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997432 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997432 # mshr miss rate for UpgradeReq accesses
2182,2198c2201,2217
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218879 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218879 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.066850 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245183 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245183 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.512572 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.512572 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.116933 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses
2200,2230c2219,2249
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.162850 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1405833 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1405833 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796 # average overall mshr miss latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency
2232,2235c2251,2254
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427 # average WriteReq mshr uncacheable latency
---
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency
2237,2238c2256,2257
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency
2240,2278c2259,2299
< system.cpu1.toL2Bus.snoop_filter.tot_requests 30858357 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15723821 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 1980391 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1980008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 383 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 850137 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 14487242 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 21647 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 21647 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4268815 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 11821046 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 2688015 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 913599 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 423664 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342986 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 458900 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1168045 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1089891 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9966353 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4640105 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 517058 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 511224 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 29897221 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16450144 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405579 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179409 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 47932353 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1275569664 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 629289128 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1559696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4501408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1910919896 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 6428198 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 22587485 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.100846 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.301181 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram
2280,2282c2301,2303
< system.cpu1.toL2Bus.snoop_fanout::0 20310003 89.92% 89.92% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 2277099 10.08% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 383 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram
2286,2287c2307,2308
< system.cpu1.toL2Bus.snoop_fanout::total 22587485 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 30765191484 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks)
2289c2310
< system.cpu1.toL2Bus.snoopLayer0.occupancy 188815582 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks)
2291c2312
< system.cpu1.toL2Bus.respLayer0.occupancy 14953353610 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks)
2293c2314
< system.cpu1.toL2Bus.respLayer1.occupancy 7474900412 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks)
2295c2316
< system.cpu1.toL2Bus.respLayer2.occupancy 210684864 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks)
2297c2318
< system.cpu1.toL2Bus.respLayer3.occupancy 616864733 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks)
2299,2303c2320,2324
< system.iobus.trans_dist::ReadReq 40414 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40414 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136987 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136987 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47846 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40417 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40417 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136988 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136988 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes)
2316,2318c2337,2339
< system.iobus.pkt_count_system.bridge.master::total 122988 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231734 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231734 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes)
2321,2322c2342,2343
< system.iobus.pkt_count::total 354802 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47866 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes)
2335,2337c2356,2358
< system.iobus.pkt_size_system.bridge.master::total 156003 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355288 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7355288 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes)
2340,2341c2361,2362
< system.iobus.pkt_size::total 7513377 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 47239500 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks)
2343c2364
< system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks)
2345c2366
< system.iobus.reqLayer2.occupancy 315000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
2349c2370
< system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
2351c2372
< system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks)
2353c2374
< system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
2355c2376
< system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
2357c2378
< system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2361c2382
< system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
2363c2384
< system.iobus.reqLayer23.occupancy 26112500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks)
2365c2386
< system.iobus.reqLayer24.occupancy 36405000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks)
2367c2388
< system.iobus.reqLayer25.occupancy 566670204 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks)
2369c2390
< system.iobus.respLayer0.occupancy 92988000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks)
2371c2392
< system.iobus.respLayer3.occupancy 148174000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks)
2375,2385c2396,2406
< system.iocache.tags.replacements 115848 # number of replacements
< system.iocache.tags.tagsinuse 11.264479 # Cycle average of tags in use
< system.iocache.tags.total_refs 11 # Total number of references to valid blocks.
< system.iocache.tags.sampled_refs 115864 # Sample count of references to valid blocks.
< system.iocache.tags.avg_refs 0.000095 # Average number of references to valid blocks.
< system.iocache.tags.warmup_cycle 9145999585000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.415083 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.849396 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.463443 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.240587 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.704030 # Average percentage of cache occupancy
---
> system.iocache.tags.replacements 115847 # number of replacements
> system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use
> system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
> system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks.
> system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
> system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy
2389,2392c2410,2411
< system.iocache.tags.tag_accesses 1043144 # Number of tag accesses
< system.iocache.tags.data_accesses 1043144 # Number of data accesses
< system.iocache.WriteLineReq_hits::realview.ide 6 # number of WriteLineReq hits
< system.iocache.WriteLineReq_hits::total 6 # number of WriteLineReq hits
---
> system.iocache.tags.tag_accesses 1043151 # Number of tag accesses
> system.iocache.tags.data_accesses 1043151 # Number of data accesses
2394,2395c2413,2414
< system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses
2398,2399c2417,2418
< system.iocache.WriteLineReq_misses::realview.ide 106978 # number of WriteLineReq misses
< system.iocache.WriteLineReq_misses::total 106978 # number of WriteLineReq misses
---
> system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
> system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2401,2402c2420,2421
< system.iocache.demand_misses::realview.ide 8883 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8923 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8922 # number of demand (read+write) misses
2404,2408c2423,2427
< system.iocache.overall_misses::realview.ide 8883 # number of overall misses
< system.iocache.overall_misses::total 8923 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5243500 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1665415552 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1670659052 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 8882 # number of overall misses
> system.iocache.overall_misses::total 8922 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles
2411,2418c2430,2437
< system.iocache.WriteLineReq_miss_latency::realview.ide 14002624152 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 14002624152 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5612500 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1665415552 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1671028052 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5612500 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1665415552 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1671028052 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles
2420,2421c2439,2440
< system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses)
2427,2428c2446,2447
< system.iocache.demand_accesses::realview.ide 8883 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8923 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses
2430,2431c2449,2450
< system.iocache.overall_accesses::realview.ide 8883 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8923 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses
2437,2438c2456,2457
< system.iocache.WriteLineReq_miss_rate::realview.ide 0.999944 # miss rate for WriteLineReq accesses
< system.iocache.WriteLineReq_miss_rate::total 0.999944 # miss rate for WriteLineReq accesses
---
> system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
> system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2445,2447c2464,2466
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 187293.615695 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency
2450,2458c2469,2477
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 187271.999552 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 187271.999552 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 35141 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked
2460c2479
< system.iocache.blocked::no_mshrs 3655 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked
2462c2481
< system.iocache.avg_blocked_cycles::no_mshrs 9.614501 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked
2466,2467c2485,2486
< system.iocache.writebacks::writebacks 106943 # number of writebacks
< system.iocache.writebacks::total 106943 # number of writebacks
---
> system.iocache.writebacks::writebacks 106950 # number of writebacks
> system.iocache.writebacks::total 106950 # number of writebacks
2469,2470c2488,2489
< system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses
2473,2474c2492,2493
< system.iocache.WriteLineReq_mshr_misses::realview.ide 106978 # number of WriteLineReq MSHR misses
< system.iocache.WriteLineReq_mshr_misses::total 106978 # number of WriteLineReq MSHR misses
---
> system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
> system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2476,2477c2495,2496
< system.iocache.demand_mshr_misses::realview.ide 8883 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8923 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses
2479,2483c2498,2502
< system.iocache.overall_mshr_misses::realview.ide 8883 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8923 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3393500 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1221265552 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1224659052 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles
2486,2493c2505,2512
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8653724152 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8653724152 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3612500 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1221265552 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1224878052 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3612500 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1221265552 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1224878052 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8211460570 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8211460570 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles
2499,2500c2518,2519
< system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999944 # mshr miss rate for WriteLineReq accesses
< system.iocache.WriteLineReq_mshr_miss_rate::total 0.999944 # mshr miss rate for WriteLineReq accesses
---
> system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
> system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2507,2509c2526,2528
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency
2512,2519c2531,2538
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency
2521,2525c2540,2544
< system.l2c.tags.replacements 1253630 # number of replacements
< system.l2c.tags.tagsinuse 63075.564404 # Cycle average of tags in use
< system.l2c.tags.total_refs 6221998 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1313632 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.736485 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1465460 # number of replacements
> system.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use
> system.l2c.tags.total_refs 6746847 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks.
2527,2827c2546,2846
< system.l2c.tags.occ_blocks::writebacks 23067.685004 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.868876 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 206.473413 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5441.439609 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 6307.681817 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8428.958067 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.047033 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 198.225362 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 4720.872050 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 6856.377655 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7560.935517 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.351985 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002241 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.003151 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.083030 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.096248 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.128616 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002137 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.003025 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.072035 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.104620 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.115371 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.962457 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 9537 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 50225 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 233 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 325 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 1551 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 7383 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 11674 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 35545 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.145523 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.766373 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 75571866 # Number of tag accesses
< system.l2c.tags.data_accesses 75571866 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 2585563 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2585563 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 160084 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 122219 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 282303 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 41093 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 37320 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 78413 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 164973 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 176191 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 341164 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5942 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3808 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 649495 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 595249 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 326607 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6405 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4811 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 608519 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 523825 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 313790 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 3038451 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 5942 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 3808 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 649495 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 760222 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 326607 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6405 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4811 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 608519 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 700016 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 313790 # number of demand (read+write) hits
< system.l2c.demand_hits::total 3379615 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 5942 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 3808 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 649495 # number of overall hits
< system.l2c.overall_hits::cpu0.data 760222 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 326607 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6405 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4811 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 608519 # number of overall hits
< system.l2c.overall_hits::cpu1.data 700016 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 313790 # number of overall hits
< system.l2c.overall_hits::total 3379615 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 64947 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 58762 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 123709 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 12100 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 11098 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 23198 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 478835 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 137880 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 616715 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1182 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 61507 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 116953 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 182171 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1669 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1507 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 57727 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 105504 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 168487 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 698045 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1182 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 61507 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 595788 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 182171 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1669 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1507 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 57727 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 243384 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 168487 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1314760 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1182 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 61507 # number of overall misses
< system.l2c.overall_misses::cpu0.data 595788 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 182171 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1669 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1507 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 57727 # number of overall misses
< system.l2c.overall_misses::cpu1.data 243384 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 168487 # number of overall misses
< system.l2c.overall_misses::total 1314760 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1164704000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1071145000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 2235849000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 211169000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187264500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 398433500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 66775651499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 18645271000 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 85420922499 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 186837000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 167036500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8232186000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 16101034000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 234710500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 209918500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7713073500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 14641394000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 104705937820 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 186837000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 167036500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 8232186000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 82876685499 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 234710500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 209918500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 7713073500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 33286665000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 190126860319 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 186837000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 167036500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 8232186000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 82876685499 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 234710500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 209918500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 7713073500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 33286665000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 190126860319 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2585563 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2585563 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 225031 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 180981 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 406012 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 53193 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 48418 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 101611 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 643808 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 314071 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 957879 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7280 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4990 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 711002 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 712202 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 508778 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8074 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6318 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 666246 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 629329 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 482277 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3736496 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 7280 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4990 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 711002 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1356010 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 508778 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 8074 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6318 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 666246 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 943400 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 482277 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4694375 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 7280 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4990 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 711002 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1356010 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 508778 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 8074 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6318 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 666246 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 943400 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 482277 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4694375 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.288614 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.324686 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.304693 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.227474 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.229212 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.228302 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.743754 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.439009 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.643834 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.236874 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.086507 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164213 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.238525 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086645 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167645 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.186818 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.236874 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.086507 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.439368 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.238525 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.086645 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.257986 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.280071 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.236874 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.086507 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.439368 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.238525 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.086645 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.257986 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.280071 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17933.145488 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18228.532045 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 18073.454640 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17451.983471 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16873.715985 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 17175.338391 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139454.408093 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 135228.249202 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 138509.558709 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141316.835871 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 133841.448941 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137670.978940 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139295.620438 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133612.928093 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138775.724143 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 149998.836493 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141316.835871 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 133841.448941 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 139104.321502 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139295.620438 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 133612.928093 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 136766.036387 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 144609.556359 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141316.835871 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 133841.448941 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 139104.321502 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139295.620438 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 133612.928093 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 136766.036387 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 144609.556359 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 2084 # number of cycles access was blocked
---
> system.l2c.tags.occ_blocks::writebacks 21606.771340 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.937701 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 223.248695 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 5669.657556 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 6460.370404 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9729.240754 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 163.294328 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 204.500397 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3331.837675 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 6323.626930 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9108.802265 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.329693 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002501 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.003407 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.086512 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.098577 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148456 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002492 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.003120 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.050840 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.096491 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.138989 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.961079 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 9038 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 217 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 50396 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 130 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 134 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 1705 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 7069 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 187 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2486 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 12173 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 35392 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.137909 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.003311 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.768982 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 82649960 # Number of tag accesses
> system.l2c.tags.data_accesses 82649960 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 2868119 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2868119 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 181384 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 131978 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 313362 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 45809 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 40059 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 85868 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 200580 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 165707 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 366287 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7480 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5183 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 699361 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 660994 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 342500 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6176 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4038 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 639412 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 580820 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 295958 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 3241922 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 7480 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 5183 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 699361 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 861574 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 342500 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 6176 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4038 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 639412 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 746527 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 295958 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3608209 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 7480 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 5183 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 699361 # number of overall hits
> system.l2c.overall_hits::cpu0.data 861574 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 342500 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 6176 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4038 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 639412 # number of overall hits
> system.l2c.overall_hits::cpu1.data 746527 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 295958 # number of overall hits
> system.l2c.overall_hits::total 3608209 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 61552 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 61783 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 123335 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 12334 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 11273 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 23607 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 493827 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 156178 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 650005 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1763 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 75880 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 147884 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2064 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 47101 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 114695 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 237376 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 863201 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 2015 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1763 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 75880 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 641711 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2405 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 2064 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 47101 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 270873 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 237376 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1513206 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 2015 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1763 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 75880 # number of overall misses
> system.l2c.overall_misses::cpu0.data 641711 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 232018 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2405 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 2064 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 47101 # number of overall misses
> system.l2c.overall_misses::cpu1.data 270873 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 237376 # number of overall misses
> system.l2c.overall_misses::total 1513206 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1080728500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1074141000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 2154869500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192695000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 205559500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 398254500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 68952537500 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 21260978999 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 90213516499 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 283038500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248472000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10197968500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 20619201500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 338612000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 290311500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6337057500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 16104459500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 133039008033 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 283038500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 248472000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 10197968500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 89571739000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 338612000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 290311500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6337057500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 37365438499 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 223252524532 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 283038500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 248472000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 10197968500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 89571739000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38762108448 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 338612000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 290311500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6337057500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 37365438499 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39857778585 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 223252524532 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 2868119 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2868119 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 242936 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 193761 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 436697 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 58143 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 51332 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 109475 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 694407 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 321885 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 1016292 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9495 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6946 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 775241 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 808878 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 574518 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8581 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6102 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 686513 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 695515 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 533334 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 4105123 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 9495 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 6946 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 775241 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1503285 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 574518 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 8581 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6102 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 686513 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 1017400 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 533334 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 5121415 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 9495 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 6946 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 775241 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1503285 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 574518 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 8581 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6102 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 686513 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 1017400 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 533334 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 5121415 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253367 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318862 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.282427 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.212132 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.219610 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.215638 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.711149 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.485198 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.639585 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.253815 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097879 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.182826 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.338250 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.068609 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164907 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.210274 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.253815 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.097879 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.426872 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.338250 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.068609 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.266240 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.295466 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.212217 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.253815 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.097879 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.426872 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403848 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.280270 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.338250 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.068609 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.266240 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.445079 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.295466 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17557.975370 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17385.704806 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 17471.678761 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15623.074428 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18234.675774 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 16870.186809 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139628.933817 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136132.995678 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 138788.957776 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140937.039138 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134396.000264 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139428.210625 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140654.796512 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134541.888707 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140411.173111 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 154122.861342 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 147536.108456 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140465.756824 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140937.039138 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 134396.000264 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 139582.676625 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 167065.091708 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140795.010395 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140654.796512 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 134541.888707 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 137944.492434 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167909.892260 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 147536.108456 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 2227 # number of cycles access was blocked
2829c2848
< system.l2c.blocked::no_mshrs 32 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 45 # number of cycles access was blocked
2831c2850
< system.l2c.avg_blocked_cycles::no_mshrs 65.125000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 49.488889 # average number of cycles each access was blocked
2835,2898c2854,2919
< system.l2c.writebacks::writebacks 965818 # number of writebacks
< system.l2c.writebacks::total 965818 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 143 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 157 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 129 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 82 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 512 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 143 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 157 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 129 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 82 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 512 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 143 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 157 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 129 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 82 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 512 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 48026 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 48026 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 64947 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 58762 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 123709 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12100 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11098 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 23198 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 478835 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 137880 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 616715 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1337 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1182 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 61364 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 116796 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1669 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1507 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57598 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 105422 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 697533 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 1337 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 1182 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 61364 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 595631 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1669 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1507 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 57598 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 243302 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1314248 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 1337 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 1182 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 61364 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 595631 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1669 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1507 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 57598 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 243302 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1314248 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1132908 # number of writebacks
> system.l2c.writebacks::total 1132908 # number of writebacks
> system.l2c.ReadExReq_mshr_hits::cpu1.data 1 # number of ReadExReq MSHR hits
> system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 168 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 159 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 10 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 363 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 159 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 159 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 364 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 56350 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 56350 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 61552 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 61783 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 123335 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12334 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11273 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 23607 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 493827 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 156177 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 650004 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2015 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1763 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 75712 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 147859 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2405 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2064 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46942 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 114685 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 862838 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 2015 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1763 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 75712 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 641686 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2405 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 2064 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 46942 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 270862 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1512842 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 2015 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1763 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 75712 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 641686 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 232018 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2405 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 2064 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 46942 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 270862 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 237375 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1512842 # number of overall MSHR misses
2900c2921
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable
2902,2906c2923,2927
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22693 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 90579 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38077 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 19127 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 91058 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17467 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38515 # number of WriteReq MSHR uncacheable
2908c2929
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses
2910,2953c2931,2974
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 44340 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 128656 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4765672001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4320405502 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 9086077503 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 924485500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 848848000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 1773333500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 61987301499 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17266471000 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 79253772499 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 155216500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7602474500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14909949000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 194848500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7122979500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13576100500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 97666151820 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 155216500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 7602474500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 76897250499 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 194848500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 7122979500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 30842571500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 176919924319 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 155216500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 7602474500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 76897250499 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 194848500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 7122979500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 30842571500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 176919924319 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 36594 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 129573 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4349611999 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4356371498 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 8705983497 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 908986500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 828559000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1737545500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 64014027660 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 19698809451 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 83712837111 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 230839505 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9421666233 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19137304611 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 269667010 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5848765667 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14956255664 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 124366437860 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 230839505 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 9421666233 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 83151332271 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 269667010 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5848765667 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 34655065115 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 208079274971 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 262887003 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 230839505 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 9421666233 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 83151332271 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36441216300 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 314557509 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 269667010 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5848765667 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 34655065115 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37483278358 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 208079274971 # number of overall MSHR miss cycles
2955c2976
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2374540500 # number of ReadReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3292793548 # number of ReadReq MSHR uncacheable cycles
2957,2961c2978,2982
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3555600500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 11838086000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2488343500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3486351500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5974695000 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2654073009 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 11854811557 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3455652022 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2534737541 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5990389563 # number of WriteReq MSHR uncacheable cycles
2963c2984
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4862884000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6748445570 # number of overall MSHR uncacheable cycles
2965,2966c2986,2987
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7041952000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 17812781000 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5188810550 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 17845201120 # number of overall MSHR uncacheable cycles
2969,3052c2990,3073
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.288614 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324686 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.304693 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.227474 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.229212 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228302 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743754 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.439009 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.643834 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.163993 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167515 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.186681 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.279962 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.279962 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73377.861964 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73523.799428 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73447.182525 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76403.760331 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76486.574158 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76443.378740 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129454.408093 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 125228.249202 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 128509.558709 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127658.044796 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128778.627801 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140016.532293 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.253367 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318862 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.282427 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.212132 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.219610 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.215638 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.711149 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.485195 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.639584 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.182795 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164892 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210186 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.295395 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.295395 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70665.648541 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70510.844375 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70588.101488 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73697.624453 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73499.423401 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73602.977930 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129628.448141 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126131.309034 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 128788.187628 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency
3054c3075
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251 # average ReadReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency
3056,3060c3077,3081
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency
3062c3083
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency
3064,3065c3085,3086
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency
3067,3075c3088,3096
< system.membus.trans_dist::ReadReq 90579 # Transaction distribution
< system.membus.trans_dist::ReadResp 797028 # Transaction distribution
< system.membus.trans_dist::WriteReq 38077 # Transaction distribution
< system.membus.trans_dist::WriteResp 38077 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1072761 # Transaction distribution
< system.membus.trans_dist::CleanEvict 234796 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 432847 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 303767 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 155875 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 91058 # Transaction distribution
> system.membus.trans_dist::ReadResp 962815 # Transaction distribution
> system.membus.trans_dist::WriteReq 38515 # Transaction distribution
> system.membus.trans_dist::WriteResp 38515 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution
> system.membus.trans_dist::CleanEvict 269903 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3077,3082c3098,3102
< system.membus.trans_dist::ReadExReq 628014 # Transaction distribution
< system.membus.trans_dist::ReadExResp 607752 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 706453 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106976 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 106976 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122988 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadExReq 660243 # Transaction distribution
> system.membus.trans_dist::ReadExResp 640684 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes)
3084,3090c3104,3110
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24302 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4826718 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4974060 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342886 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 342886 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5316946 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156003 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes)
3092,3099c3112,3119
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48604 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 148677184 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 148883115 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268800 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7268800 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 156151915 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 604039 # Total snoops (count)
< system.membus.snoop_fanout::samples 3616779 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 621430 # Total snoops (count)
> system.membus.snoop_fanout::samples 4033661 # Request fanout histogram
3104c3124
< system.membus.snoop_fanout::1 3616779 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram
3109,3110c3129,3130
< system.membus.snoop_fanout::total 3616779 # Request fanout histogram
< system.membus.reqLayer0.occupancy 110163500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 4033661 # Request fanout histogram
> system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks)
3114c3134
< system.membus.reqLayer2.occupancy 20375999 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks)
3116c3136
< system.membus.reqLayer5.occupancy 7677665405 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks)
3118c3138
< system.membus.respLayer2.occupancy 7558802547 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks)
3120c3140
< system.membus.respLayer3.occupancy 229140974 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks)
3174,3204c3194,3224
< system.toL2Bus.snoop_filter.tot_requests 11857284 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 6410159 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 2032721 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 132920 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 118959 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 13961 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 90581 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4604579 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38077 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38077 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 3658344 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1620073 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 706187 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 382180 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1088365 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1100091 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1100091 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4521240 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 106976 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8903542 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7167245 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 16070787 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267379155 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202223448 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 469602603 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 2985982 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 8314965 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.369241 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.486066 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3228731 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram
3206,3208c3226,3228
< system.toL2Bus.snoop_fanout::0 5258700 63.24% 63.24% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 3042304 36.59% 99.83% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 13961 0.17% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram
3212,3213c3232,3233
< system.toL2Bus.snoop_fanout::total 8314965 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 8970776631 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks)
3215c3235
< system.toL2Bus.snoopLayer0.occupancy 2598924 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks)
3217c3237
< system.toL2Bus.respLayer0.occupancy 5002984602 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks)
3219c3239
< system.toL2Bus.respLayer1.occupancy 4113788553 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks)