Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11103:38f6188421e0 ) new ( 11138:a611a23c8cc2 )

full compact

3,5c3,5
< sim_seconds 47.482239 # Number of seconds simulated
< sim_ticks 47482239150000 # Number of ticks simulated
< final_tick 47482239150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.464182 # Number of seconds simulated
> sim_ticks 47464181819000 # Number of ticks simulated
> final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 126606 # Simulator instruction rate (inst/s)
< host_op_rate 148916 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6789587746 # Simulator tick rate (ticks/s)
< host_mem_usage 767628 # Number of bytes of host memory used
< host_seconds 6993.39 # Real time elapsed on the host
< sim_insts 885402765 # Number of instructions simulated
< sim_ops 1041431052 # Number of ops (including micro ops) simulated
---
> host_inst_rate 165089 # Simulator instruction rate (inst/s)
> host_op_rate 194182 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 9130718670 # Simulator tick rate (ticks/s)
> host_mem_usage 773696 # Number of bytes of host memory used
> host_seconds 5198.30 # Real time elapsed on the host
> sim_insts 858179266 # Number of instructions simulated
> sim_ops 1009414094 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 88704 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 71680 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 8153920 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 42330888 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 14734656 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 154368 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 137408 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2906176 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 14216400 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 12693312 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 441664 # Number of bytes read from this memory
< system.physmem.bytes_read::total 95929176 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 8153920 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2906176 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 11060096 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 76090688 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory
> system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 76111272 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 1386 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 1120 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 127405 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 661433 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 230229 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 2412 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 2147 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 45409 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 222144 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 198333 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6901 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1498919 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1188917 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 1191491 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 1868 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 1510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 171726 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 891510 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 310319 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 3251 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2894 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 61206 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 299405 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 267328 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9302 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2020317 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 171726 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 61206 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 232931 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1602508 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 226886 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1586 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 74342 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 180196 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 74342 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1349757 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69,92c69,92
< system.physmem.bw_write::total 1602942 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1602508 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 1868 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 1510 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 171726 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 891943 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 310319 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2894 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 61206 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 299405 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 267328 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9302 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3623259 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1498919 # Number of read requests accepted
< system.physmem.writeReqs 1191491 # Number of write requests accepted
< system.physmem.readBursts 1498919 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1191491 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 95891200 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 39616 # Total number of bytes read from write queue
< system.physmem.bytesWritten 76109696 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 95929176 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 76111272 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 619 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1350190 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1349757 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 1803 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 1613 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 144970 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 791709 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 226886 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1586 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 1443 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 74342 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 285629 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 180196 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9187 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3069119 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1274831 # Number of read requests accepted
> system.physmem.writeReqs 1003591 # Number of write requests accepted
> system.physmem.readBursts 1274831 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1003591 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 81546816 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue
> system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 81587544 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 64085672 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue
94,126c94,126
< system.physmem.neitherReadNorWriteReqs 217911 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 89027 # Per bank write bursts
< system.physmem.perBankRdBursts::1 94433 # Per bank write bursts
< system.physmem.perBankRdBursts::2 86611 # Per bank write bursts
< system.physmem.perBankRdBursts::3 92371 # Per bank write bursts
< system.physmem.perBankRdBursts::4 85965 # Per bank write bursts
< system.physmem.perBankRdBursts::5 91989 # Per bank write bursts
< system.physmem.perBankRdBursts::6 84150 # Per bank write bursts
< system.physmem.perBankRdBursts::7 94780 # Per bank write bursts
< system.physmem.perBankRdBursts::8 85741 # Per bank write bursts
< system.physmem.perBankRdBursts::9 143775 # Per bank write bursts
< system.physmem.perBankRdBursts::10 89074 # Per bank write bursts
< system.physmem.perBankRdBursts::11 90853 # Per bank write bursts
< system.physmem.perBankRdBursts::12 89498 # Per bank write bursts
< system.physmem.perBankRdBursts::13 91267 # Per bank write bursts
< system.physmem.perBankRdBursts::14 94459 # Per bank write bursts
< system.physmem.perBankRdBursts::15 94307 # Per bank write bursts
< system.physmem.perBankWrBursts::0 73359 # Per bank write bursts
< system.physmem.perBankWrBursts::1 78327 # Per bank write bursts
< system.physmem.perBankWrBursts::2 72063 # Per bank write bursts
< system.physmem.perBankWrBursts::3 77110 # Per bank write bursts
< system.physmem.perBankWrBursts::4 71233 # Per bank write bursts
< system.physmem.perBankWrBursts::5 76219 # Per bank write bursts
< system.physmem.perBankWrBursts::6 70290 # Per bank write bursts
< system.physmem.perBankWrBursts::7 78154 # Per bank write bursts
< system.physmem.perBankWrBursts::8 70631 # Per bank write bursts
< system.physmem.perBankWrBursts::9 75804 # Per bank write bursts
< system.physmem.perBankWrBursts::10 71232 # Per bank write bursts
< system.physmem.perBankWrBursts::11 74262 # Per bank write bursts
< system.physmem.perBankWrBursts::12 72932 # Per bank write bursts
< system.physmem.perBankWrBursts::13 74472 # Per bank write bursts
< system.physmem.perBankWrBursts::14 77093 # Per bank write bursts
< system.physmem.perBankWrBursts::15 76033 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 221043 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 69298 # Per bank write bursts
> system.physmem.perBankRdBursts::1 80196 # Per bank write bursts
> system.physmem.perBankRdBursts::2 71590 # Per bank write bursts
> system.physmem.perBankRdBursts::3 80518 # Per bank write bursts
> system.physmem.perBankRdBursts::4 76240 # Per bank write bursts
> system.physmem.perBankRdBursts::5 80771 # Per bank write bursts
> system.physmem.perBankRdBursts::6 77164 # Per bank write bursts
> system.physmem.perBankRdBursts::7 81418 # Per bank write bursts
> system.physmem.perBankRdBursts::8 74880 # Per bank write bursts
> system.physmem.perBankRdBursts::9 125815 # Per bank write bursts
> system.physmem.perBankRdBursts::10 65333 # Per bank write bursts
> system.physmem.perBankRdBursts::11 79047 # Per bank write bursts
> system.physmem.perBankRdBursts::12 75605 # Per bank write bursts
> system.physmem.perBankRdBursts::13 79656 # Per bank write bursts
> system.physmem.perBankRdBursts::14 77605 # Per bank write bursts
> system.physmem.perBankRdBursts::15 79033 # Per bank write bursts
> system.physmem.perBankWrBursts::0 58028 # Per bank write bursts
> system.physmem.perBankWrBursts::1 64393 # Per bank write bursts
> system.physmem.perBankWrBursts::2 59641 # Per bank write bursts
> system.physmem.perBankWrBursts::3 64677 # Per bank write bursts
> system.physmem.perBankWrBursts::4 61513 # Per bank write bursts
> system.physmem.perBankWrBursts::5 65147 # Per bank write bursts
> system.physmem.perBankWrBursts::6 63058 # Per bank write bursts
> system.physmem.perBankWrBursts::7 64825 # Per bank write bursts
> system.physmem.perBankWrBursts::8 60547 # Per bank write bursts
> system.physmem.perBankWrBursts::9 63081 # Per bank write bursts
> system.physmem.perBankWrBursts::10 56749 # Per bank write bursts
> system.physmem.perBankWrBursts::11 64053 # Per bank write bursts
> system.physmem.perBankWrBursts::12 61964 # Per bank write bursts
> system.physmem.perBankWrBursts::13 65797 # Per bank write bursts
> system.physmem.perBankWrBursts::14 62586 # Per bank write bursts
> system.physmem.perBankWrBursts::15 65266 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 28 # Number of times write queue was full causing retry
< system.physmem.totGap 47482237279500 # Total gap between requests
---
> system.physmem.numWrRetry 59 # Number of times write queue was full causing retry
> system.physmem.totGap 47464179840500 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1498889 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1274801 # Read request sizes (log2)
143,166c143,166
< system.physmem.writePktSize::6 1188917 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 923724 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 366189 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 46304 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 33513 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 28479 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 26369 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 23870 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 21021 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 18560 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 4392 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1922 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1132 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 878 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 593 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 355 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 308 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 261 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 112 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1001017 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 816238 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 315854 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 31830 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 23000 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 19787 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 18192 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 16305 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 14624 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 12016 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2281 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1222 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 783 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 615 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 453 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 252 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 201 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 148 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
191,232c191,232
< system.physmem.wrQLenPdf::15 16928 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 19684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 43592 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 56076 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 62915 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 66422 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 68359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 72568 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 74023 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 77349 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 76686 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 79204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 77889 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 78555 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 85240 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 78371 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 74036 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 70191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 1636 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 826 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 662 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 577 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 466 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 452 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 473 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 362 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 335 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 290 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 275 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 229 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 196 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 15348 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 17874 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 37266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 47521 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 53574 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 55971 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 59005 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 60181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 62652 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 62838 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 63556 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 68208 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 65188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 65181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 70319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 65705 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 61499 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 58334 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1919 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 620 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 493 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 457 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 375 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 321 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 358 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 322 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 237 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 264 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 344 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 339 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 227 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 143 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see
234,257c234,257
< system.physmem.wrQLenPdf::58 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 68 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 84 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 913839 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 188.217382 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 115.370572 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 246.881339 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 545143 59.65% 59.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 181104 19.82% 79.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 60696 6.64% 86.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 30627 3.35% 89.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 20207 2.21% 91.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 12827 1.40% 93.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 9718 1.06% 94.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 9868 1.08% 95.22% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 43649 4.78% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 913839 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 67807 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 22.096303 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 333.350943 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 67804 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::58 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 84 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 193 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 760858 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 191.403705 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 116.807820 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 448904 59.00% 59.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 151841 19.96% 78.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 50675 6.66% 85.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 27026 3.55% 89.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 17061 2.24% 91.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 11068 1.45% 92.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8074 1.06% 93.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 8214 1.08% 95.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 760858 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 56148 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 56145 99.99% 99.99% # Reads before turning the bus around for writes
261,285c261,285
< system.physmem.rdPerTurnAround::total 67807 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 67807 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.538219 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.057457 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 6.559402 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 64146 94.60% 94.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 1206 1.78% 96.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 504 0.74% 97.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 212 0.31% 97.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 312 0.46% 97.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 493 0.73% 98.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 138 0.20% 98.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 37 0.05% 98.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 37 0.05% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 40 0.06% 98.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 31 0.05% 99.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 23 0.03% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 428 0.63% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 42 0.06% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 41 0.06% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 38 0.06% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 18 0.03% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 4 0.01% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads
287,303c287,305
< system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 4 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 20 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 3 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 6 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 67807 # Writes before turning the bus around for reads
< system.physmem.totQLat 45254251156 # Total ticks spent queuing
< system.physmem.totMemAccLat 73347376156 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 7491500000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 30203.73 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads
> system.physmem.totQLat 34002300770 # Total ticks spent queuing
> system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst
305,309c307,311
< system.physmem.avgMemAccLat 48953.73 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.02 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.02 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
311,312c313,314
< system.physmem.busUtil 0.03 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 0.02 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
314,332c316,334
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing
< system.physmem.readRowHits 1205783 # Number of row buffer hits during reads
< system.physmem.writeRowHits 567891 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.48 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 47.75 # Row buffer hit rate for writes
< system.physmem.avgGap 17648699.37 # Average gap between requests
< system.physmem.pageHitRate 66.00 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3440351880 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1877176125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5610742800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3866972400 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1186805359620 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27448283421000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31751192752785 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.696261 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45662122488643 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1585536160000 # Time in different power states
---
> system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing
> system.physmem.readRowHits 1026298 # Number of row buffer hits during reads
> system.physmem.writeRowHits 488335 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes
> system.physmem.avgGap 20832040.70 # Average gap between requests
> system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.645246 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states
334c336
< system.physmem_0.memoryStateTime::ACT 234575955107 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states
336,346c338,348
< system.physmem_1.actEnergy 3468270960 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1892409750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6075934800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3839134320 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3101308728960 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1190698585875 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27444868310250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31752151374915 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.716450 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45656375341719 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1585536160000 # Time in different power states
---
> system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.668617 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states
348c350
< system.physmem_1.memoryStateTime::ACT 240323289781 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states
379,386c381,388
< system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
< system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
< system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
< system.cpu0.branchPred.lookups 141674450 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 99862421 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 6468001 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 105068912 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 76755781 # Number of BTB hits
---
> system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
> system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
> system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
> system.cpu0.branchPred.lookups 135703894 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits
388,390c390,392
< system.cpu0.branchPred.BTBHitPct 73.052799 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 16951451 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 1146227 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions.
421,453c423,451
< system.cpu0.dtb.walker.walks 285287 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 285287 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10160 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74871 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walkWaitTime::samples 285287 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0 285287 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 285287 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 85031 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 19876.756712 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 18427.446368 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 12146.929549 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-32767 81330 95.65% 95.65% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3040 3.58% 99.22% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-98303 313 0.37% 99.59% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-131071 238 0.28% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.03% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-229375 17 0.02% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::229376-262143 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-294911 13 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 85031 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 669754704 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0 669754704 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 669754704 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 74871 88.05% 88.05% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 10160 11.95% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 85031 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 285287 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 277006 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst
455,456c453,454
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 285287 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85031 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst
458,459c456,457
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85031 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 370318 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst
462,465c460,463
< system.cpu0.dtb.read_hits 92463041 # DTB read hits
< system.cpu0.dtb.read_misses 237707 # DTB read misses
< system.cpu0.dtb.write_hits 80598198 # DTB write hits
< system.cpu0.dtb.write_misses 47580 # DTB write misses
---
> system.cpu0.dtb.read_hits 88941283 # DTB read hits
> system.cpu0.dtb.read_misses 229899 # DTB read misses
> system.cpu0.dtb.write_hits 77314134 # DTB write hits
> system.cpu0.dtb.write_misses 47107 # DTB write misses
468,472c466,470
< system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 37525 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 1680 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 10312 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch
474,476c472,474
< system.cpu0.dtb.perms_faults 10309 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 92700748 # DTB read accesses
< system.cpu0.dtb.write_accesses 80645778 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 89171182 # DTB read accesses
> system.cpu0.dtb.write_accesses 77361241 # DTB write accesses
478,480c476,478
< system.cpu0.dtb.hits 173061239 # DTB hits
< system.cpu0.dtb.misses 285287 # DTB misses
< system.cpu0.dtb.accesses 173346526 # DTB accesses
---
> system.cpu0.dtb.hits 166255417 # DTB hits
> system.cpu0.dtb.misses 277006 # DTB misses
> system.cpu0.dtb.accesses 166532423 # DTB accesses
510,541c508,539
< system.cpu0.itb.walker.walks 62168 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 62168 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 557 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49936 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walkWaitTime::samples 62168 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0 62168 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 62168 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 50493 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 22007.793159 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 20271.994764 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 13773.268921 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 46934 92.95% 92.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 2907 5.76% 98.71% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-98303 206 0.41% 99.12% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::98304-131071 384 0.76% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.02% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-196607 12 0.02% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::360448-393215 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 50493 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 669040204 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 669040204 100.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 669040204 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 49936 98.90% 98.90% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 557 1.10% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 50493 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 67964 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated
543,544c541,542
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62168 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62168 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst
546,550c544,548
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50493 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50493 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 112661 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 254201587 # ITB inst hits
< system.cpu0.itb.inst_misses 62168 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 243132835 # ITB inst hits
> system.cpu0.itb.inst_misses 67964 # ITB inst misses
557,559c555,557
< system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 26890 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB
563c561
< system.cpu0.itb.perms_faults 207950 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions
566,570c564,568
< system.cpu0.itb.inst_accesses 254263755 # ITB inst accesses
< system.cpu0.itb.hits 254201587 # DTB hits
< system.cpu0.itb.misses 62168 # DTB misses
< system.cpu0.itb.accesses 254263755 # DTB accesses
< system.cpu0.numCycles 1026940097 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses
> system.cpu0.itb.hits 243132835 # DTB hits
> system.cpu0.itb.misses 67964 # DTB misses
> system.cpu0.itb.accesses 243200799 # DTB accesses
> system.cpu0.numCycles 1024570142 # number of cpu cycles simulated
573,579c571,577
< system.cpu0.committedInsts 473675073 # Number of instructions committed
< system.cpu0.committedOps 555986446 # Number of ops (including micro ops) committed
< system.cpu0.discardedOps 46253045 # Number of ops (including micro ops) which were discarded before commit
< system.cpu0.numFetchSuspends 4767 # Number of times Execute suspended instruction fetching
< system.cpu0.quiesceCycles 93938653200 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.cpi 2.168026 # CPI: cycles per instruction
< system.cpu0.ipc 0.461249 # IPC: instructions per cycle
---
> system.cpu0.committedInsts 453671847 # Number of instructions committed
> system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed
> system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit
> system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
> system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.cpi 2.258395 # CPI: cycles per instruction
> system.cpu0.ipc 0.442792 # IPC: instructions per cycle
581,592c579,590
< system.cpu0.kern.inst.quiesce 15947 # number of quiesce instructions executed
< system.cpu0.tickCycles 756887334 # Number of cycles that the object actually ticked
< system.cpu0.idleCycles 270052763 # Total number of cycles that the object has spent stopped
< system.cpu0.dcache.tags.replacements 5859905 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 507.688861 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 164189310 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 5860417 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 28.016660 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 4974406000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.688861 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991580 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.991580 # Average percentage of cache occupancy
---
> system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed
> system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked
> system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped
> system.cpu0.dcache.tags.replacements 5606815 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy
594,596c592,594
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
598,689c596,687
< system.cpu0.dcache.tags.tag_accesses 349055381 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 349055381 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 84695912 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 84695912 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 74803438 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 74803438 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 285827 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 285827 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 206325 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 206325 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1857926 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1857926 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1831957 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1831957 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 159499350 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 159499350 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 159785177 # number of overall hits
< system.cpu0.dcache.overall_hits::total 159785177 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 3661656 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 3661656 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 2387103 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 2387103 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 659778 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 659778 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 802996 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 802996 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167218 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 167218 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191201 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 191201 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 6048759 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 6048759 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 6708537 # number of overall misses
< system.cpu0.dcache.overall_misses::total 6708537 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54989546000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 54989546000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45746153500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 45746153500 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55227374500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 55227374500 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2454584500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 2454584500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4061452500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4061452500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2247500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2247500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 100735699500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 100735699500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 100735699500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 100735699500 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 88357568 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 88357568 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 77190541 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 77190541 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 945605 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 945605 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1009321 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 1009321 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2025144 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2025144 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023158 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2023158 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 165548109 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 165548109 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 166493714 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 166493714 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041441 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.041441 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030925 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.030925 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.697731 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.697731 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.795580 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.795580 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082571 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082571 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094506 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094506 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036538 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.036538 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040293 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.040293 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15017.671239 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15017.671239 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19163.879187 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 19163.879187 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 68776.649572 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 68776.649572 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14678.949037 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14678.949037 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21241.795283 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21241.795283 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 153315707 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 153315707 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 153568738 # number of overall hits
> system.cpu0.dcache.overall_hits::total 153568738 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 3470214 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 3470214 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 2296821 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 2296821 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 622517 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 622517 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 787681 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 787681 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168627 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 168627 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185724 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 185724 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 5767035 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 5767035 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 6389552 # number of overall misses
> system.cpu0.dcache.overall_misses::total 6389552 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57404903000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 57404903000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 53218814500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 53218814500 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 70624877500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 70624877500 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2615349000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 2615349000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4471340500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4471340500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4645500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4645500 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 110623717500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 110623717500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 110623717500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 110623717500 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 85014217 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 85014217 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 74068525 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 74068525 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 875548 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 875548 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 917684 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 917684 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 1986862 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1984839 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 1984839 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 159082742 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 159082742 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 159958290 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 159958290 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040819 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.040819 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031009 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.031009 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.711003 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.711003 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.858336 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.858336 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084871 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084871 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093571 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093571 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036252 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.036252 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039945 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.039945 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16542.179531 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 16542.179531 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23170.640855 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 23170.640855 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 89661.776150 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 89661.776150 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15509.669270 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15509.669270 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24075.189529 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24075.189529 # average StoreCondReq miss latency
692,695c690,693
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16653.944966 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 16653.944966 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15016.045898 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 15016.045898 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19182.078399 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19182.078399 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17313.219691 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 17313.219691 # average overall miss latency
704,793c702,791
< system.cpu0.dcache.writebacks::writebacks 3953843 # number of writebacks
< system.cpu0.dcache.writebacks::total 3953843 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 461349 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 461349 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 989528 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 989528 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 101 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43137 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43137 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 40 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1450877 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1450877 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1450877 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1450877 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3200307 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3200307 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1397575 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1397575 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 654192 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 654192 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 802895 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 802895 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124081 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124081 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191161 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 191161 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4597882 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4597882 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5252074 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5252074 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32791 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65643 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43347515000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43347515000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25679741500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25679741500 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14396564000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14396564000 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54417843000 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54417843000 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1641270500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1641270500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3869107000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3869107000 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2035000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2035000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69027256500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 69027256500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83423820500 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 83423820500 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5925160000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5925160000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5714063000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5714063000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11639223000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11639223000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036220 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036220 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018106 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018106 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.691824 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.691824 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.795480 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.795480 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061270 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061270 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094486 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094486 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027774 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027774 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031545 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031545 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13544.798983 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13544.798983 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18374.499759 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18374.499759 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22006.634138 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22006.634138 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 67777.035602 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 67777.035602 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13227.411933 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13227.411933 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20240.043733 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20240.043733 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 3758761 # number of writebacks
> system.cpu0.dcache.writebacks::total 3758761 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423304 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 423304 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 954060 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 954060 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 67 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 67 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43006 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43006 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 59 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1377364 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1377364 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1377364 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1377364 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3046910 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3046910 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342761 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1342761 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 616851 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 616851 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 787614 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 787614 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125621 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125621 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185665 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 185665 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 4389671 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 4389671 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5006522 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5006522 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14625 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30107 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45015119500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45015119500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30226463500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30226463500 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15766385500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15766385500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 69831148500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 69831148500 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1724289500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1724289500 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4281874000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4281874000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4478500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4478500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75241583000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 75241583000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 91007968500 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 91007968500 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2444404000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency
796,805c794,803
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15012.837759 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15012.837759 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15883.976597 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15883.976597 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180694.702815 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180694.702815 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173933.489590 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173933.489590 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177310.954710 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177310.954710 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency
807,815c805,813
< system.cpu0.icache.tags.replacements 10143465 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.926573 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 243844472 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 10143977 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 24.038350 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 29838959000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.926573 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999857 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 9688574 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy
817,819c815,817
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
821,858c819,856
< system.cpu0.icache.tags.tag_accesses 518120904 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 518120904 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 243844472 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 243844472 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 243844472 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 243844472 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 243844472 # number of overall hits
< system.cpu0.icache.overall_hits::total 243844472 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 10143987 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 10143987 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 10143987 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 10143987 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 10143987 # number of overall misses
< system.cpu0.icache.overall_misses::total 10143987 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100406017500 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 100406017500 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 100406017500 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 100406017500 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 100406017500 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 100406017500 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 253988459 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 253988459 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 253988459 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 253988459 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 253988459 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 253988459 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039939 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.039939 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039939 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.039939 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039939 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.039939 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.082233 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.082233 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 9898.082233 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.082233 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 9898.082233 # average overall miss latency
---
> system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 233226662 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 233226662 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 233226662 # number of overall hits
> system.cpu0.icache.overall_hits::total 233226662 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 9689087 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 9689087 # number of overall misses
> system.cpu0.icache.overall_misses::total 9689087 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 100299166000 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 100299166000 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 242915749 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 242915749 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency
867,902c865,900
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10143987 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 10143987 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 10143987 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 10143987 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 10143987 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 10143987 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.ReadReq_mshr_uncacheable::total 52292 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses
< system.cpu0.icache.overall_mshr_uncacheable_misses::total 52292 # number of overall MSHR uncacheable misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95334024500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 95334024500 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95334024500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 95334024500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95334024500 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 95334024500 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4777780500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4777780500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 4777780500 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039939 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.039939 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039939 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.039939 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9398.082283 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9398.082283 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 9398.082283 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 91367.331523 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91367.331523 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 91367.331523 # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9689087 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 9689087 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 9689087 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 9689087 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 9689087 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 9689087 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95454623000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 95454623000 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95454623000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 95454623000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95454623000 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 95454623000 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7413401000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7413401000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 7413401000 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039887 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.039887 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039887 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.039887 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9851.766529 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9851.766529 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 9851.766529 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141723.240743 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency
904,906c902,904
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 7957449 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 7958709 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 1099 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 7463777 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 7463951 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 154 # number of redundant prefetches already in prefetch queue
909,1071c907,1063
< system.cpu0.l2cache.prefetcher.pfSpanPage 1036699 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2852729 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16231.938482 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 28072062 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2868819 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 9.785233 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 27361359000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 6837.547665 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 84.005962 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.461189 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5084.590207 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3169.997386 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 963.336073 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.417331 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005127 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005643 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.310339 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.193481 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.058797 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.990719 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1316 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14706 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 636 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1121 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2596 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5686 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5177 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080322 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.897583 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 536564472 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 536564472 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494323 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 145712 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 640035 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 3953840 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 3953840 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 100741 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 100741 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34053 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 34053 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 910402 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 910402 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9335111 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 9335111 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2958514 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 2958514 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 184784 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 184784 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494323 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 145712 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 9335111 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 3868916 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 13844062 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 494323 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 145712 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 9335111 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 3868916 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 13844062 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11152 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7425 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 18577 # number of ReadReq misses
< system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
< system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 135342 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 135342 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 157102 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 157102 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262550 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 262550 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 808875 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 808875 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019727 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1019727 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 616671 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 616671 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11152 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7425 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 808875 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1282277 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 2109729 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11152 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7425 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 808875 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1282277 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 2109729 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 358336500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 254237500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 612574000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2939782500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 2939782500 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3277538000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3277538000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1967998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1967998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13250524998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 13250524998 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24450345500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24450345500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34035221991 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34035221991 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 51883476000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 51883476000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 358336500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 254237500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24450345500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 47285746989 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 72348666489 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 358336500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 254237500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24450345500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 47285746989 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 72348666489 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 505475 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 153137 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 658612 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 3953841 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 3953841 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236083 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 236083 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191155 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 191155 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1172952 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1172952 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10143986 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 10143986 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3978241 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 3978241 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 801455 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 801455 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 505475 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 153137 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 10143986 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5151193 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 15953791 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 505475 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 153137 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 10143986 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5151193 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 15953791 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022062 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048486 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.028206 # miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.573281 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.573281 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.821857 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.821857 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1020305 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2664787 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15957.113648 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 26864509 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2680682 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 10.021520 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 6872.215886 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 83.268968 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 86.677569 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4373.710312 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3617.876682 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 923.364231 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.419447 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005082 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005290 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.266950 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.220818 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056358 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.973945 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1328 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14509 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 565 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 693 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 52 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 15 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4763 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8150 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 382 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081055 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 513598249 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 513598249 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 486721 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 161483 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 648204 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 3758761 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 3758761 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 96787 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 96787 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34850 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 34850 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 870093 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 870093 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8916496 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 8916496 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2811099 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 2811099 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 212338 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 212338 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 486721 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 161483 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 8916496 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 3681192 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 13245892 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 486721 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 161483 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 8916496 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 3681192 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 13245892 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11149 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7679 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 18828 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134429 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 134429 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 150813 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 150813 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 252885 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 252885 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 772590 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 772590 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 977962 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 977962 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 573862 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 573862 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11149 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7679 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 772590 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1230847 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2022265 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11149 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7679 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 772590 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1230847 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2022265 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 426258000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 324009000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 750267000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4100217500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 4100217500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3583690499 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3583690499 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4385000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4385000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16205618499 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 16205618499 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27749596500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27749596500 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 38364944997 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 38364944997 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67134826000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 67134826000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 426258000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 324009000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27749596500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 54570563496 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 83070426996 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 426258000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 324009000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27749596500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 54570563496 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 83070426996 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 497870 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 169162 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 667032 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 3758761 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 3758761 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231216 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 231216 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 185663 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 185663 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1122978 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1122978 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9689086 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 9689086 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3789061 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 3789061 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 786200 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 786200 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 497870 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 169162 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 9689086 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 4912039 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 15268157 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 497870 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 169162 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 9689086 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 4912039 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 15268157 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045394 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.028227 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.581400 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.581400 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.812294 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.812294 # miss rate for SCUpgradeReq accesses
1074,1119c1066,1111
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.223837 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.223837 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079739 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079739 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.256326 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.256326 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.769439 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.769439 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022062 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048486 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079739 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.248928 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.132240 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022062 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048486 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079739 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.248928 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.132240 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32132.039096 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 34240.740741 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32974.861388 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21721.139779 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21721.139779 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20862.484246 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20862.484246 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 327999.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 327999.666667 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50468.577406 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50468.577406 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 30227.594499 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 30227.594499 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 33376.797899 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 33376.797899 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 84134.775269 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 84134.775269 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32132.039096 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 34240.740741 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30227.594499 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36876.390194 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 34292.871970 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32132.039096 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 34240.740741 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30227.594499 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36876.390194 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 34292.871970 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.225191 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.225191 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079738 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079738 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.258101 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.258101 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729919 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729919 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045394 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079738 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250578 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.132450 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022393 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045394 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079738 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250578 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.132450 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42194.165907 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39848.470363 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 30500.989370 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 30500.989370 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 23762.477366 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 23762.477366 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2192500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2192500 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64082.956676 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64082.956676 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35917.623190 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35917.623190 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39229.484374 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39229.484374 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 116987.753153 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 116987.753153 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 41077.913625 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38232.845995 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42194.165907 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35917.623190 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44335.781373 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 41077.913625 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 189 # number of cycles access was blocked
1121c1113
< system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1123c1115
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 189 # average number of cycles each access was blocked
1127,1132c1119,1125
< system.cpu0.l2cache.writebacks::writebacks 1435907 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1435907 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7822 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 7822 # number of ReadExReq MSHR hits
---
> system.cpu0.l2cache.writebacks::writebacks 1318085 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1318085 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5018 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 5018 # number of ReadExReq MSHR hits
1135,1137c1128,1133
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 800 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 800 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1141 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1141 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
1139,1141c1135,1138
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8622 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 8630 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6159 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 6170 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
1143,1229c1140,1222
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8622 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 8630 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11152 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7424 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 18576 # number of ReadReq MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 115899 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 115899 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 744785 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 744785 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 135342 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 135342 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 157102 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 157102 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 254728 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 254728 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 808868 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 808868 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018927 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018927 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 616671 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 616671 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11152 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7424 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 808868 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1273655 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 2101099 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11152 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7424 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 808868 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1273655 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 744785 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2845884 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85083 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32852 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 117935 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209670500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 501095000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33786234533 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33786234533 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2742370498 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2742370498 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2416828000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2416828000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1703998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1703998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10773413498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10773413498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19596844500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19596844500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 27840391991 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 27840391991 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 48183450000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 48183450000 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209670500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19596844500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 38613805489 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 58711744989 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 291424500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209670500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19596844500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 38613805489 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33786234533 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 92497979522 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5662672500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10022117000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5467648500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5467648500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4359444500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11130321000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15489765500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028205 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
< system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6159 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 6170 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11148 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7676 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 18824 # number of ReadReq MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 109829 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 109829 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 670532 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 134429 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 134429 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 150813 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 150813 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247867 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 247867 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 772583 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 772583 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 976821 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 976821 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 573859 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 573859 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11148 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7676 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 772583 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1224688 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2016095 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11148 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7676 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 772583 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1224688 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 670532 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2686627 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 66934 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 15482 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 82416 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 277905000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 637268000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 33195033631 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4709210494 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4709210494 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2870671499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2870671499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4013000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4013000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13996811499 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13996811499 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23113725500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23113725500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32421419997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32421419997 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 63691409500 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 63691409500 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277905000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23113725500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46418231496 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 70169224996 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 359363000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277905000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23113725500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46418231496 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 33195033631 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 103364258627 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2327318500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9322247500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2417234500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2417234500 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4744553000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11739482000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028221 # mshr miss rate for ReadReq accesses
1234,1237c1227,1230
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.573281 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.573281 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.821857 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821857 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.581400 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.581400 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812294 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.812294 # mshr miss rate for SCUpgradeReq accesses
1240,1256c1233,1249
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217168 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217168 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079739 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.256125 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.256125 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.769439 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.769439 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247254 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131699 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022062 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048479 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079739 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247254 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220723 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220723 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses
1258,1296c1251,1289
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178383 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26975.398363 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45363.741930 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20262.523814 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20262.523814 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15383.814337 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15383.814337 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 283999.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 283999.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42293.793764 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42293.793764 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 24227.493856 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27323.244934 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27323.244934 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 78134.775269 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 78134.775269 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27943.350118 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26132.039096 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28242.254849 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24227.493856 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30317.319438 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45363.741930 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32502.371679 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172689.838675 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117792.238167 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166432.743821 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166432.743821 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83367.331523 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169558.383986 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 131341.548311 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency
1298,1329c1291,1329
< system.cpu0.toL2Bus.trans_dist::ReadReq 878258 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 15087550 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 32852 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 7538926 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 15047066 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 979875 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 473443 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 345382 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 491005 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1529585 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1182209 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10143987 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6286308 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 908183 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 801455 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30533828 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18915495 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 338792 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1107688 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 50895803 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 652561728 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 589425738 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1225096 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4043800 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1247256362 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 11033818 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 44172113 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.260955 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.439155 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram
1331,1333c1331,1333
< system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 32645184 73.90% 73.90% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 11526929 26.10% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram
1335c1335
< system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1337,1338c1337,1338
< system.cpu0.toL2Bus.snoop_fanout::total 44172113 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 20686801483 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks)
1340c1340
< system.cpu0.toL2Bus.snoopLayer0.occupancy 184431489 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks)
1342c1342
< system.cpu0.toL2Bus.respLayer0.occupancy 15296388050 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks)
1344c1344
< system.cpu0.toL2Bus.respLayer1.occupancy 8393036752 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks)
1346c1346
< system.cpu0.toL2Bus.respLayer2.occupancy 185661487 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks)
1348c1348
< system.cpu0.toL2Bus.respLayer3.occupancy 602239946 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks)
1350,1354c1350,1354
< system.cpu1.branchPred.lookups 126920633 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 90998639 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 5685011 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 95306954 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 70103943 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 123013748 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits
1356,1358c1356,1358
< system.cpu1.branchPred.BTBHitPct 73.555958 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 14523133 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 944517 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions.
1388,1415c1388,1416
< system.cpu1.dtb.walker.walks 273163 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 273163 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10101 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 83297 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walkWaitTime::samples 273163 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0 273163 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 273163 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 93398 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 20769.759524 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 18788.534327 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 16072.129923 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 92090 98.60% 98.60% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1102 1.18% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 44 0.05% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 68 0.07% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 64 0.07% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 93398 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples -1497259648 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0 -1497259648 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total -1497259648 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 83297 89.18% 89.18% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 10101 10.82% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 93398 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 273163 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 261280 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst
1417,1418c1418,1419
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 273163 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93398 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst
1420,1421c1421,1422
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93398 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 366561 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst
1424,1427c1425,1428
< system.cpu1.dtb.read_hits 80454143 # DTB read hits
< system.cpu1.dtb.read_misses 224980 # DTB read misses
< system.cpu1.dtb.write_hits 71458601 # DTB write hits
< system.cpu1.dtb.write_misses 48183 # DTB write misses
---
> system.cpu1.dtb.read_hits 79147380 # DTB read hits
> system.cpu1.dtb.read_misses 216729 # DTB read misses
> system.cpu1.dtb.write_hits 70165250 # DTB write hits
> system.cpu1.dtb.write_misses 44551 # DTB write misses
1430,1434c1431,1435
< system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 37844 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 998 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 7832 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch
1436,1438c1437,1439
< system.cpu1.dtb.perms_faults 11981 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 80679123 # DTB read accesses
< system.cpu1.dtb.write_accesses 71506784 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 79364109 # DTB read accesses
> system.cpu1.dtb.write_accesses 70209801 # DTB write accesses
1440,1442c1441,1443
< system.cpu1.dtb.hits 151912744 # DTB hits
< system.cpu1.dtb.misses 273163 # DTB misses
< system.cpu1.dtb.accesses 152185907 # DTB accesses
---
> system.cpu1.dtb.hits 149312630 # DTB hits
> system.cpu1.dtb.misses 261280 # DTB misses
> system.cpu1.dtb.accesses 149573910 # DTB accesses
1472,1498c1473,1499
< system.cpu1.itb.walker.walks 69906 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 69906 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 595 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61795 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walkWaitTime::samples 69906 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0 69906 100.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 69906 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 62390 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 23626.751082 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 21282.847568 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 17788.570372 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 60952 97.70% 97.70% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 1278 2.05% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.13% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 15 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 62390 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples -1498102148 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 -1498102148 100.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total -1498102148 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 61795 99.05% 99.05% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 595 0.95% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 62390 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walks 64423 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated
1500,1501c1501,1502
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69906 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69906 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst
1503,1507c1504,1508
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62390 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62390 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 132296 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 226287653 # ITB inst hits
< system.cpu1.itb.inst_misses 69906 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 219650463 # ITB inst hits
> system.cpu1.itb.inst_misses 64423 # ITB inst misses
1514,1516c1515,1517
< system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 26941 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB
1520c1521
< system.cpu1.itb.perms_faults 214530 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions
1523,1527c1524,1528
< system.cpu1.itb.inst_accesses 226357559 # ITB inst accesses
< system.cpu1.itb.hits 226287653 # DTB hits
< system.cpu1.itb.misses 69906 # DTB misses
< system.cpu1.itb.accesses 226357559 # DTB accesses
< system.cpu1.numCycles 843613035 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses
> system.cpu1.itb.hits 219650463 # DTB hits
> system.cpu1.itb.misses 64423 # DTB misses
> system.cpu1.itb.accesses 219714886 # DTB accesses
> system.cpu1.numCycles 870330668 # number of cpu cycles simulated
1530,1536c1531,1537
< system.cpu1.committedInsts 411727692 # Number of instructions committed
< system.cpu1.committedOps 485444606 # Number of ops (including micro ops) committed
< system.cpu1.discardedOps 45963671 # Number of ops (including micro ops) which were discarded before commit
< system.cpu1.numFetchSuspends 5033 # Number of times Execute suspended instruction fetching
< system.cpu1.quiesceCycles 94121734017 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.cpi 2.048959 # CPI: cycles per instruction
< system.cpu1.ipc 0.488053 # IPC: instructions per cycle
---
> system.cpu1.committedInsts 404507419 # Number of instructions committed
> system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed
> system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit
> system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching
> system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.cpi 2.151581 # CPI: cycles per instruction
> system.cpu1.ipc 0.464774 # IPC: instructions per cycle
1538,1646c1539,1647
< system.cpu1.kern.inst.quiesce 5855 # number of quiesce instructions executed
< system.cpu1.tickCycles 670689322 # Number of cycles that the object actually ticked
< system.cpu1.idleCycles 172923713 # Total number of cycles that the object has spent stopped
< system.cpu1.dcache.tags.replacements 4998697 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 442.736384 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 144280355 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 4999208 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 28.860643 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8387679361000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.736384 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.864720 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.864720 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 306336541 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 306336541 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 73634827 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 73634827 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 66559153 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 66559153 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 217159 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 217159 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 114949 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 114949 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1666179 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1666179 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1632337 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1632337 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 140193980 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 140193980 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 140411139 # number of overall hits
< system.cpu1.dcache.overall_hits::total 140411139 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 3169592 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 3169592 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 2202884 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 2202884 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634590 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 634590 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446274 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 446274 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 155480 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 155480 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187648 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 187648 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 5372476 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 5372476 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 6007066 # number of overall misses
< system.cpu1.dcache.overall_misses::total 6007066 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46997405500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 46997405500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36924614000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 36924614000 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 13123924500 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 13123924500 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2384254000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 2384254000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3955578000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 3955578000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3296000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3296000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 83922019500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 83922019500 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 83922019500 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 83922019500 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 76804419 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 76804419 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 68762037 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 68762037 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 851749 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 851749 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 561223 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 561223 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1821659 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1821659 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1819985 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1819985 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 145566456 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 145566456 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 146418205 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 146418205 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041268 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.041268 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032036 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.032036 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745043 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745043 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.795181 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.795181 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.085351 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.085351 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103104 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103104 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036907 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.036907 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041027 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.041027 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14827.588377 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14827.588377 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16761.942072 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 16761.942072 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 29407.773027 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 29407.773027 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15334.795472 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15334.795472 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21079.777029 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21079.777029 # average StoreCondReq miss latency
---
> system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed
> system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked
> system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped
> system.cpu1.dcache.tags.replacements 4754677 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits
> system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses
> system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41378134500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 143188790 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.707385 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency
1649,1652c1650,1653
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15620.734183 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 15620.734183 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13970.550598 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 13970.550598 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency
1661,1750c1662,1751
< system.cpu1.dcache.writebacks::writebacks 3232302 # number of writebacks
< system.cpu1.dcache.writebacks::total 3232302 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357442 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 357442 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 916671 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 916671 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 62 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 62 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39535 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39535 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 40 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.StoreCondReq_mshr_hits::total 40 # number of StoreCondReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1274113 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1274113 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1274113 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1274113 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2812150 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2812150 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1286213 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1286213 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634154 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 634154 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446212 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 446212 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115945 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115945 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187608 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 187608 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4098363 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4098363 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4732517 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4732517 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5214 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10217 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 37676406000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 37676406000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20748839500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20748839500 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13118141500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13118141500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12673625000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 12673625000 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1579299000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1579299000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3766730000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3766730000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3027000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3027000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58425245500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 58425245500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 71543387000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 71543387000 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 574067000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 574067000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 612660500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 612660500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1186727500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1186727500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036614 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036614 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018705 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018705 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.744532 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.744532 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.795071 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.795071 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063648 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063648 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103082 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103082 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028155 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028155 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032322 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032322 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13397.722739 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13397.722739 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16131.728959 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16131.728959 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20686.050234 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20686.050234 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 28402.698717 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 28402.698717 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13621.104834 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13621.104834 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20077.661933 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20077.661933 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks
> system.cpu1.dcache.writebacks::total 3093987 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1182784 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 3889795 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4459525 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4459525 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38219808000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24026284000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24026284000 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13466616000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13466616000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1560972500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4174804000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62246092000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75712708000 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 75712708000 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4058237000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3938068000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3938068000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7996305000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency
1753,1762c1754,1763
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14255.751748 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14255.751748 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15117.407291 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15117.407291 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110101.074031 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110101.074031 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 122458.624825 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 122458.624825 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116152.246256 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116152.246256 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16002.409381 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16002.409381 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16977.751666 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16977.751666 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172617.481923 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172617.481923 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174466.950204 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174466.950204 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 173523.393082 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 173523.393082 # average overall mshr uncacheable latency
1764,1772c1765,1773
< system.cpu1.icache.tags.replacements 8492244 # number of replacements
< system.cpu1.icache.tags.tagsinuse 506.981743 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 217573051 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 8492756 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 25.618663 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8375822912000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.981743 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990199 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.990199 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 8864427 # number of replacements
> system.cpu1.icache.tags.tagsinuse 506.853262 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 210585390 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 8864939 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 23.754861 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8389731746000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.853262 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989948 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.989948 # Average percentage of cache occupancy
1774,1776c1775,1777
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id
1778,1815c1779,1816
< system.cpu1.icache.tags.tag_accesses 460624372 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 460624372 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 217573051 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 217573051 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 217573051 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 217573051 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 217573051 # number of overall hits
< system.cpu1.icache.overall_hits::total 217573051 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 8492757 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 8492757 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 8492757 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 8492757 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 8492757 # number of overall misses
< system.cpu1.icache.overall_misses::total 8492757 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 83328642500 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 83328642500 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 83328642500 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 83328642500 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 83328642500 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 83328642500 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 226065808 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 226065808 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 226065808 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 226065808 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 226065808 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 226065808 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037568 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.037568 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037568 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.037568 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037568 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.037568 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9811.730455 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 9811.730455 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 9811.730455 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9811.730455 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 9811.730455 # average overall miss latency
---
> system.cpu1.icache.tags.tag_accesses 447765626 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 447765626 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 210585390 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 210585390 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 210585390 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 210585390 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 210585390 # number of overall hits
> system.cpu1.icache.overall_hits::total 210585390 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 8864949 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 8864949 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 8864949 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 8864949 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 8864949 # number of overall misses
> system.cpu1.icache.overall_misses::total 8864949 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93186086500 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 93186086500 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 93186086500 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 93186086500 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 93186086500 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 93186086500 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 219450339 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 219450339 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 219450339 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 219450339 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 219450339 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 219450339 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.040396 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.040396 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.040396 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.040396 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.040396 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.040396 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10511.745358 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10511.745358 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10511.745358 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10511.745358 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10511.745358 # average overall miss latency
1824,1859c1825,1860
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8492757 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 8492757 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 8492757 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 8492757 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 8492757 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 8492757 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
< system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 79082264500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 79082264500 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 79082264500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 79082264500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 79082264500 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 79082264500 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8371000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8371000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8371000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 8371000 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037568 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.037568 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037568 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.037568 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9311.730513 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9311.730513 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 9311.730513 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90010.752688 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90010.752688 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90010.752688 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8864949 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 8864949 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 8864949 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 8864949 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 8864949 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 8864949 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 88753612500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 88753612500 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 88753612500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 88753612500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 88753612500 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 88753612500 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12520000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12520000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12520000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 12520000 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.040396 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.040396 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.040396 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.040396 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10011.745414 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10011.745414 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10011.745414 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 136086.956522 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136086.956522 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency
1861,1863c1862,1864
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 6929819 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 6929951 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 118 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 6449392 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 6450426 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 905 # number of redundant prefetches already in prefetch queue
1866,2027c1867,2026
< system.cpu1.l2cache.prefetcher.pfSpanPage 828225 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2217454 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13495.655652 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 24120573 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2233034 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 10.801704 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 10014360255000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 5089.747096 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 72.528183 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 67.846494 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3761.982865 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3615.755476 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 887.795537 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.310654 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004427 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004141 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.229613 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.220688 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054187 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.823709 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1264 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14232 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 323 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5272 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5785 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2792 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077148 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.868652 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 454838713 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 454838713 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 490664 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168334 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 658998 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 3232300 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 3232300 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70185 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 70185 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33315 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 33315 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 851172 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 851172 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7787132 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 7787132 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2622380 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2622380 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 211432 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 211432 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 490664 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168334 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 7787132 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3473552 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 11919682 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 490664 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168334 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 7787132 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3473552 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 11919682 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11999 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9044 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 21043 # number of ReadReq misses
< system.cpu1.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
< system.cpu1.l2cache.Writeback_misses::total 2 # number of Writeback misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 130491 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 130491 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154287 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 154287 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 236022 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 236022 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 705624 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 705624 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939588 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 939588 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 233719 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 233719 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11999 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9044 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 705624 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1175610 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1902277 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11999 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9044 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 705624 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1175610 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1902277 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 460284000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 375161500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 835445500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2824238500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 2824238500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3183877499 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3183877499 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2927500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2927500 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9419253499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 9419253499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19920417000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19920417000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29851836990 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29851836990 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 10546903000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 10546903000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 460284000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 375161500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19920417000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 39271090489 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 60026952989 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 460284000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 375161500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19920417000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 39271090489 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 60026952989 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 502663 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 177378 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 680041 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 3232302 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 3232302 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 200676 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 200676 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187602 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 187602 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1087194 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1087194 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8492756 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 8492756 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3561968 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3561968 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 445151 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 445151 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 502663 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 177378 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 8492756 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4649162 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 13821959 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 502663 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 177378 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 8492756 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4649162 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 13821959 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050987 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.030944 # miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.650257 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.650257 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.822417 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.822417 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 802102 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2183837 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13560.981052 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 24336260 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2199514 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 11.064381 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9986977778000 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 3995.301083 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.705175 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.813454 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5399.423450 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3183.311357 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 849.426534 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.243854 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004132 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004017 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.329555 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194294 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051845 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.827697 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1064 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14535 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 92 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 248 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 600 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 111 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 33 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 692 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4987 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7639 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1109 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.064941 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887146 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 457590280 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 457590280 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 449487 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151613 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 601100 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 3093985 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 3093985 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 65506 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 65506 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33165 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 33165 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 791344 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 791344 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8112196 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 8112196 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2464747 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2464747 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 204016 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 204016 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 449487 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151613 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 8112196 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3256091 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 11969387 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 449487 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151613 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 8112196 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3256091 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 11969387 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10587 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7678 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 18265 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 126676 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 126676 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 148906 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 148906 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 229716 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 229716 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 752753 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 752753 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 896376 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 896376 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 260955 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 260955 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10587 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7678 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 752753 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1126092 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1897110 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10587 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7678 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 752753 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1126092 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1897110 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 399086500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 314156000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 713242500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3920313500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3920313500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3517664000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3517664000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5390999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5390999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11586003000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 11586003000 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 27103959000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 27103959000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32012190991 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32012190991 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17327350500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 17327350500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 399086500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 314156000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 27103959000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 43598193991 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 71415395491 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 399086500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 314156000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 27103959000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 43598193991 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 71415395491 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 460074 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159291 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 619365 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 3093985 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 3093985 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 192182 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 192182 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 182071 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 182071 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1021060 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1021060 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8864949 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 8864949 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3361123 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3361123 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464971 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 464971 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 460074 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159291 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 8864949 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4382183 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 13866497 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 460074 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159291 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 8864949 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4382183 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 13866497 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048201 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.659146 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.659146 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.817846 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.817846 # miss rate for SCUpgradeReq accesses
2030,2074c2029,2073
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.217093 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.217093 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.083085 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.083085 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.263783 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.263783 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.525033 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.525033 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050987 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.083085 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252865 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.137627 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023871 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050987 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.083085 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252865 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.137627 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41481.811146 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39701.824835 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21643.166962 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21643.166962 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20636.071082 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20636.071082 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 487916.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 487916.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39908.370826 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39908.370826 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28230.923268 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28230.923268 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 31771.198642 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 31771.198642 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 45126.425323 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 45126.425323 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41481.811146 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28230.923268 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33404.862573 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 31555.316596 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38360.196683 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41481.811146 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28230.923268 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33404.862573 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 31555.316596 # average overall miss latency
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224978 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224978 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.084913 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.084913 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.266689 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.266689 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.561229 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.561229 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048201 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.084913 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256971 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.136812 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023012 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048201 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.084913 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256971 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.136812 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40916.384475 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39049.685190 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30947.563074 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30947.563074 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23623.386566 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23623.386566 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 770142.714286 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 770142.714286 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50436.203834 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50436.203834 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36006.444345 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36006.444345 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35712.905066 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35712.905066 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66399.764327 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66399.764327 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 37644.309234 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37695.900633 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40916.384475 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36006.444345 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38716.369525 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 37644.309234 # average overall miss latency
2083,2092c2082,2091
< system.cpu1.l2cache.writebacks::writebacks 960235 # number of writebacks
< system.cpu1.l2cache.writebacks::total 960235 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6240 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 6240 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 370 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 370 # number of ReadSharedReq MSHR hits
---
> system.cpu1.l2cache.writebacks::writebacks 895073 # number of writebacks
> system.cpu1.l2cache.writebacks::total 895073 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4757 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 4757 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 5 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1267 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1267 # number of ReadSharedReq MSHR hits
2095,2187c2094,2182
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6610 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 6614 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6610 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 6614 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11999 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9041 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 21040 # number of ReadReq MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104712 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 104712 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 691959 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 691959 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 130491 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 130491 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 154287 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 154287 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229782 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 229782 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 705623 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 705623 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 939218 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 939218 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 233715 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 233715 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11999 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9041 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 705623 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1169000 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1895663 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11999 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9041 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 705623 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1169000 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 691959 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2587622 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5214 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5307 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5003 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10217 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10310 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 320879500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 709169500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28798715692 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28798715692 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2619056498 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2619056498 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2341678999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2341678999 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2531500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2531500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7275794499 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7275794499 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 15686656500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 15686656500 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24180303490 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24180303490 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 9143886000 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 9143886000 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 320879500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15686656500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 31456097989 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 47851923989 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 388290000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 320879500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15686656500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 31456097989 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28798715692 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 76650639681 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7627000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 532300500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 539927500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 575129000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 575129000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7627000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1107429500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1115056500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030939 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses
< system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses
---
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 6024 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 6030 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 6024 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 6030 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10587 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7677 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 18264 # number of ReadReq MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104448 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 104448 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 626506 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 126676 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 126676 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 148906 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 148906 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224959 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 224959 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 752748 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 752748 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 895109 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 895109 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 260951 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 260951 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10587 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7677 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 752748 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1120068 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1891080 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10587 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7677 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 752748 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1120068 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 626506 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2517586 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23510 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23602 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46082 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46174 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 268081000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 603645500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27110588000 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4296542495 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4296542495 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2791394499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2791394499 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4964999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4964999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9564152000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9564152000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 22587351000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 22587351000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26554233491 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26554233491 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15760443000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15760443000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 268081000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 22587351000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36118385491 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 59309381991 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 335564500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 268081000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 22587351000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36118385491 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27110588000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 86419969991 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11784000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3870100000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3881884000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3768766500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3768766500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 11784000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7638866500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7650650500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.029488 # mshr miss rate for ReadReq accesses
2192,2195c2187,2190
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.650257 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.650257 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.822417 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.822417 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.659146 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.659146 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.817846 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817846 # mshr miss rate for SCUpgradeReq accesses
2198,2214c2193,2209
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211353 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211353 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.083085 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.263680 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.263680 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.525024 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.525024 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251443 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.137149 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023871 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050970 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083085 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251443 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220319 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220319 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084913 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.266312 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266312 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.561220 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.561220 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136378 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023012 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048195 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.084913 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255596 # mshr miss rate for overall accesses
2216,2254c2211,2249
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.187211 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33705.774715 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41619.107045 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20070.782644 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20070.782644 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15177.422589 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.422589 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 421916.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 421916.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31663.900997 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31663.900997 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22230.931390 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 25745.144886 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 25745.144886 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 39124.087029 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 39124.087029 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25242.843263 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32360.196683 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35491.593850 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22230.931390 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26908.552600 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41619.107045 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29622.038954 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102090.621404 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101738.741285 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114956.825904 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 114956.825904 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82010.752688 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 108390.868161 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 108152.909796 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181559 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33051.111476 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43272.670972 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33917.573139 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33917.573139 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18746.017615 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18746.017615 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 709285.571429 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 709285.571429 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 42515.089416 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 42515.089416 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30006.524096 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29665.921682 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency
2256,2288c2251,2289
< system.cpu1.toL2Bus.trans_dist::ReadReq 900589 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 12966269 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 5003 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 6817398 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 13255066 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 909243 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 440871 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344666 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 456246 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1853750 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1095537 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8492756 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6090536 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 551879 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 445151 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25476691 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16156139 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 386266 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1103974 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 43123070 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 543542336 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511133259 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419024 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4021304 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1060115923 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 11712363 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 39696559 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.307834 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.461597 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram
2290,2292c2291,2293
< system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 27476611 69.22% 69.22% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 12219948 30.78% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
2294c2295
< system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2296,2297c2297,2298
< system.cpu1.toL2Bus.snoop_fanout::total 39696559 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 17378215985 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks)
2299c2300
< system.cpu1.toL2Bus.snoopLayer0.occupancy 190636988 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks)
2301c2302
< system.cpu1.toL2Bus.respLayer0.occupancy 12741161217 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks)
2303c2304
< system.cpu1.toL2Bus.respLayer1.occupancy 7401084853 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks)
2305c2306
< system.cpu1.toL2Bus.respLayer2.occupancy 208902970 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks)
2307c2308
< system.cpu1.toL2Bus.respLayer3.occupancy 601334453 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks)
2309,2313c2310,2314
< system.iobus.trans_dist::ReadReq 40366 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40366 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136635 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136635 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47764 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40378 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40378 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136939 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136939 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
2323c2324
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
2328,2330c2329,2331
< system.iobus.pkt_count_system.bridge.master::total 122698 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
2333,2334c2334,2335
< system.iobus.pkt_count::total 354002 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47784 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
2344c2345
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
2349,2351c2350,2352
< system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355480 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7355480 # Cumulative packet size per connected master and slave (bytes)
2354,2355c2355,2356
< system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36259000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7513376 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36227000 # Layer occupancy (ticks)
2375c2376
< system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks)
2383c2384
< system.iobus.reqLayer27.occupancy 569722386 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 567439447 # Layer occupancy (ticks)
2387c2388
< system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92820000 # Layer occupancy (ticks)
2389c2390
< system.iobus.respLayer3.occupancy 147920000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 148222000 # Layer occupancy (ticks)
2393,2394c2394,2395
< system.iocache.tags.replacements 115594 # number of replacements
< system.iocache.tags.tagsinuse 11.293777 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115886 # number of replacements
> system.iocache.tags.tagsinuse 11.252205 # Cycle average of tags in use
2396c2397
< system.iocache.tags.sampled_refs 115610 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115902 # Sample count of references to valid blocks.
2398,2403c2399,2404
< system.iocache.tags.warmup_cycle 9174240356000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.830924 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.462853 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.239433 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.466428 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.705861 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9146784544000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 7.402122 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 3.850083 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.462633 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.240630 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.703263 # Average percentage of cache occupancy
2407,2408c2408,2409
< system.iocache.tags.tag_accesses 1040865 # Number of tag accesses
< system.iocache.tags.data_accesses 1040865 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1043376 # Number of tag accesses
> system.iocache.tags.data_accesses 1043376 # Number of data accesses
2410,2411c2411,2412
< system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8907 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8944 # number of ReadReq misses
2414,2415c2415,2416
< system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
< system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
---
> system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
> system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2417,2418c2418,2419
< system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8924 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8907 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8947 # number of demand (read+write) misses
2420,2421c2421,2422
< system.iocache.overall_misses::realview.ide 8884 # number of overall misses
< system.iocache.overall_misses::total 8924 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8907 # number of overall misses
> system.iocache.overall_misses::total 8947 # number of overall misses
2423,2424c2424,2425
< system.iocache.ReadReq_miss_latency::realview.ide 1643383037 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1648578037 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1688317981 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1693512981 # number of ReadReq miss cycles
2427,2428c2428,2429
< system.iocache.WriteLineReq_miss_latency::realview.ide 12626572349 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12626572349 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13959998466 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13959998466 # number of WriteLineReq miss cycles
2430,2431c2431,2432
< system.iocache.demand_miss_latency::realview.ide 1643383037 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1648947037 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1688317981 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1693881981 # number of demand (read+write) miss cycles
2433,2434c2434,2435
< system.iocache.overall_miss_latency::realview.ide 1643383037 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1648947037 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1688317981 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1693881981 # number of overall miss cycles
2436,2437c2437,2438
< system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8907 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8944 # number of ReadReq accesses(hits+misses)
2440,2441c2441,2442
< system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
< system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
---
> system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
> system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2443,2444c2444,2445
< system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8907 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8947 # number of demand (read+write) accesses
2446,2447c2447,2448
< system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8907 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8947 # number of overall (read+write) accesses
2462,2463c2463,2464
< system.iocache.ReadReq_avg_miss_latency::realview.ide 184982.331945 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 184797.448380 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 189549.565623 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 189346.263529 # average ReadReq miss latency
2466,2467c2467,2468
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118306.089770 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118306.089770 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130486.787426 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130486.787426 # average WriteLineReq miss latency
2469,2470c2470,2471
< system.iocache.demand_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 184776.673801 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 189324.017101 # average overall miss latency
2472,2474c2473,2475
< system.iocache.overall_avg_miss_latency::realview.ide 184982.331945 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 184776.673801 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 32047 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 189549.565623 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 189324.017101 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 34260 # number of cycles access was blocked
2476c2477
< system.iocache.blocked::no_mshrs 3474 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3572 # number of cycles access was blocked
2478c2479
< system.iocache.avg_blocked_cycles::no_mshrs 9.224813 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.591265 # average number of cycles each access was blocked
2482,2483c2483,2484
< system.iocache.writebacks::writebacks 106695 # number of writebacks
< system.iocache.writebacks::total 106695 # number of writebacks
---
> system.iocache.writebacks::writebacks 106949 # number of writebacks
> system.iocache.writebacks::total 106949 # number of writebacks
2485,2486c2486,2487
< system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8907 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8944 # number of ReadReq MSHR misses
2489,2490c2490,2491
< system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
< system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
---
> system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
> system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2492,2493c2493,2494
< system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8907 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8947 # number of demand (read+write) MSHR misses
2495,2496c2496,2497
< system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8907 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8947 # number of overall MSHR misses
2498,2499c2499,2500
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199183037 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1202528037 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1242967981 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1246312981 # number of ReadReq MSHR miss cycles
2502,2503c2503,2504
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7290172349 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7290172349 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8610798466 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8610798466 # number of WriteLineReq MSHR miss cycles
2505,2506c2506,2507
< system.iocache.demand_mshr_miss_latency::realview.ide 1199183037 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1202747037 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1242967981 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1246531981 # number of demand (read+write) MSHR miss cycles
2508,2509c2509,2510
< system.iocache.overall_mshr_miss_latency::realview.ide 1199183037 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1202747037 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1242967981 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1246531981 # number of overall MSHR miss cycles
2524,2525c2525,2526
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134982.331945 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 134797.448380 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139549.565623 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 139346.263529 # average ReadReq mshr miss latency
2528,2529c2529,2530
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68306.089770 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68306.089770 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80486.787426 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80486.787426 # average WriteLineReq mshr miss latency
2531,2532c2532,2533
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency
2534,2535c2535,2536
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 134982.331945 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 134776.673801 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 139549.565623 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 139324.017101 # average overall mshr miss latency
2537,2541c2538,2542
< system.l2c.tags.replacements 1417273 # number of replacements
< system.l2c.tags.tagsinuse 63778.929439 # Cycle average of tags in use
< system.l2c.tags.total_refs 6059487 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1477461 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.101284 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1172651 # number of replacements
> system.l2c.tags.tagsinuse 63896.612844 # Cycle average of tags in use
> system.l2c.tags.total_refs 5899189 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1234288 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 4.779427 # Average number of references to valid blocks.
2543,2840c2544,2844
< system.l2c.tags.occ_blocks::writebacks 17721.105226 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 135.826880 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 142.018903 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 5534.663770 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 7879.546362 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8528.634482 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 234.293349 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 288.797420 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3403.637563 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 8415.757562 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11494.647922 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.270403 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002073 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.002167 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.084452 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.120232 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.130137 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003575 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.004407 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.051935 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.128414 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.175394 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.973189 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 9520 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 195 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 50473 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 311 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 9149 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1751 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5310 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 43220 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.145264 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.002975 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.770157 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 72899096 # Number of tag accesses
< system.l2c.tags.data_accesses 72899096 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 2396145 # number of Writeback hits
< system.l2c.Writeback_hits::total 2396145 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 29304 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 31986 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 61290 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 6099 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 5707 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 11806 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 163881 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 167785 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 331666 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5962 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3875 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 733621 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 590091 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 312280 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6619 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4964 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 660183 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 546610 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 303770 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 3167975 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 5962 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 3875 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 733621 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 753972 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 312280 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6619 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4964 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 660183 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 714395 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 303770 # number of demand (read+write) hits
< system.l2c.demand_hits::total 3499641 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 5962 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 3875 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 733621 # number of overall hits
< system.l2c.overall_hits::cpu0.data 753972 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 312280 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6619 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4964 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 660183 # number of overall hits
< system.l2c.overall_hits::cpu1.data 714395 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 303770 # number of overall hits
< system.l2c.overall_hits::total 3499641 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 45221 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 40936 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 86157 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 9627 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 8295 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 17922 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 527041 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 116613 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 643654 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1386 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1120 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 75246 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 138345 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 230447 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2412 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2147 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 45440 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 109170 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 198349 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 804062 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 1386 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 1120 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 75246 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 665386 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 230447 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 2412 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 2147 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 45440 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 225783 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 198349 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1447716 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 1386 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 1120 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 75246 # number of overall misses
< system.l2c.overall_misses::cpu0.data 665386 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 230447 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 2412 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 2147 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 45440 # number of overall misses
< system.l2c.overall_misses::cpu1.data 225783 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 198349 # number of overall misses
< system.l2c.overall_misses::total 1447716 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 294012000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 222456500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 516468500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 58985000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48576500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 107561500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 49590710499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 9911915500 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 59502625999 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 125671500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 101124000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6225311500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 12482167500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 215227500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192832000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3809523500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 9886876499 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 85291823548 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 125671500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 101124000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 6225311500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 62072877999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 215227500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 192832000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3809523500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 19798791999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 144794449547 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 125671500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 101124000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 6225311500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 62072877999 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 28558623509 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 215227500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 192832000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3809523500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 19798791999 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23694466040 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 144794449547 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 2396145 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 2396145 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 74525 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 72922 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 147447 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 15726 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 14002 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 29728 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 690922 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 284398 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 975320 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7348 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4995 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 808867 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 728436 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 542727 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9031 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7111 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 705623 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 655780 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 502119 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3972037 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 7348 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 4995 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 808867 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1419358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 542727 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 9031 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 7111 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 705623 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 940178 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 502119 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4947357 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 7348 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 4995 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 808867 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1419358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 542727 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 9031 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 7111 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 705623 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 940178 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 502119 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4947357 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.606790 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.561367 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.584325 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.612171 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592415 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.602866 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.762808 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.410035 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.659941 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.188623 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.224224 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.093026 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.189921 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.424609 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.267080 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.301927 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.064397 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166474 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.395024 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.202431 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.188623 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.224224 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.093026 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.468794 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.424609 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.267080 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.301927 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.064397 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.240149 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.395024 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.292624 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.188623 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.224224 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.093026 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.468794 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.424609 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.267080 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.301927 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.064397 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.240149 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.395024 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.292624 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6501.669578 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5434.251026 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5994.504219 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6127.038537 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5856.118143 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 6001.646022 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 94092.699617 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84998.374967 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 92445.049668 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 90672.077922 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90289.285714 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82732.789783 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90224.926813 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 89231.965174 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89814.625058 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83836.344630 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90564.042310 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 106076.177643 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90672.077922 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90289.285714 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 82732.789783 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 93288.524254 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89231.965174 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89814.625058 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 83836.344630 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 87689.471745 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 100015.783169 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90672.077922 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90289.285714 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 82732.789783 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 93288.524254 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 123927.078717 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89231.965174 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89814.625058 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 83836.344630 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 87689.471745 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119458.459786 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 100015.783169 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 1849 # number of cycles access was blocked
---
> system.l2c.tags.occ_blocks::writebacks 19626.342189 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 209.741305 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 250.506537 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 6148.160419 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 12486.088901 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 12942.693356 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 77.886538 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 86.786571 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 4894.205028 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 3546.886464 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3627.315534 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.299474 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003200 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.003822 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.093813 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.190523 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.197490 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001188 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.074680 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.054121 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055348 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.974985 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 12177 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 211 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 49249 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 56 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 1468 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 3502 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 7139 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1696 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 11834 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 35465 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.185806 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.003220 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.751480 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 69068672 # Number of tag accesses
> system.l2c.tags.data_accesses 69068672 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 2213157 # number of Writeback hits
> system.l2c.Writeback_hits::total 2213157 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 26227 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 30963 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 57190 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 5791 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 6000 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 11791 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 170699 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 173368 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 344067 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6059 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4018 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 717194 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 567434 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 309455 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6450 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4624 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 697524 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 530409 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 314319 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 3157486 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 6059 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4018 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 717194 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 738133 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 309455 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 6450 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4624 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 697524 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 703777 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 314319 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3501553 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 6059 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4018 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 717194 # number of overall hits
> system.l2c.overall_hits::cpu0.data 738133 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 309455 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 6450 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4624 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 697524 # number of overall hits
> system.l2c.overall_hits::cpu1.data 703777 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 314319 # number of overall hits
> system.l2c.overall_hits::total 3501553 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 46094 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 42278 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 88372 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 9356 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 8640 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 17996 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 470394 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 130669 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 601063 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1196 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 55388 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 120389 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1070 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 55224 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 85443 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 623362 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 1196 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 55388 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 590783 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1176 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1070 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 55224 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 216112 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1224425 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 1196 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 55388 # number of overall misses
> system.l2c.overall_misses::cpu0.data 590783 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 168332 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1176 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1070 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 55224 # number of overall misses
> system.l2c.overall_misses::cpu1.data 216112 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 133806 # number of overall misses
> system.l2c.overall_misses::total 1224425 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 737888500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 668601000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1406489500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 133423500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 126121000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 259544500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 68021517000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 17893316000 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 85914833000 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 182621000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 165049500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7432164500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 16649727500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 164644500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 152256000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7382488500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 11836491000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 93356372957 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 182621000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 165049500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 7432164500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 84671244500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 164644500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 152256000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 7382488500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 29729807000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 179271205957 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 182621000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 165049500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 7432164500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 84671244500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27728020736 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 164644500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 152256000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 7382488500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 29729807000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 21662909721 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 179271205957 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 2213157 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 2213157 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 72321 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 73241 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 145562 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 15147 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 14640 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 29787 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 641093 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 304037 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 945130 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7397 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5214 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 772582 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 687823 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 477787 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7626 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5694 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 752748 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 615852 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 448125 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3780848 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 7397 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 5214 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 772582 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1328916 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 477787 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 7626 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 5694 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 752748 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 919889 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 448125 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4725978 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 7397 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 5214 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 772582 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1328916 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 477787 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 7626 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 5694 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 752748 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 919889 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 448125 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4725978 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.637353 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.577245 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.607109 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.617680 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590164 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.604156 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.733738 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.429780 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.635958 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.229382 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.071692 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.175029 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.187917 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.073363 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.138740 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.164874 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.229382 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.071692 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.444560 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.187917 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.073363 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.234933 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.259084 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.180884 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.229382 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.071692 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.444560 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.352316 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154209 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.187917 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.073363 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.234933 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.298591 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.259084 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16008.341650 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15814.395194 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 15915.555832 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14260.741770 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14597.337963 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 14422.343854 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144605.409508 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 136936.197568 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 142938.149578 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 138001.254181 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134183.658915 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 138299.408584 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142295.327103 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133682.610821 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138530.845125 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 149762.694802 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 146412.565863 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 136488.041854 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138001.254181 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 134183.658915 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 143320.380749 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164722.219994 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140003.826531 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142295.327103 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 133682.610821 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 137566.664507 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161897.894870 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 146412.565863 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 2168 # number of cycles access was blocked
2842c2846
< system.l2c.blocked::no_mshrs 25 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 31 # number of cycles access was blocked
2844c2848
< system.l2c.avg_blocked_cycles::no_mshrs 73.960000 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 69.935484 # average number of cycles each access was blocked
2848,2976c2852,2983
< system.l2c.writebacks::writebacks 1082222 # number of writebacks
< system.l2c.writebacks::total 1082222 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 107 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 9 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 115 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 19 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 250 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 107 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 9 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 115 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 250 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 107 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 9 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 115 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 250 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 50233 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 50233 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 45221 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 40936 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 86157 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9627 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8295 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 17922 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 527041 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 116613 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 643654 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1386 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1120 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 75139 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 138336 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 230447 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2412 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2147 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45325 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109151 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 198349 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 803812 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 1386 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 1120 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 75139 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 665377 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 230447 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 2412 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 2147 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 45325 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 225764 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 198349 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1447466 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 1386 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 1120 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 75139 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 665377 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 230447 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 2412 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 2147 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 45325 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 225764 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 198349 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1447466 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52292 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32791 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5212 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 90388 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32852 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5003 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 37855 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52292 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65643 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10215 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 128243 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 938962001 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 849367002 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1788329003 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 200436500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 172427000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 372863500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 44320300499 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 8745785500 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 53066085999 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 111811500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 89924000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5466131500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11098053500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26254153509 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 191107500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 171362000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3348487500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 8794010999 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21710976040 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 77236018048 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 111811500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 89924000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 5466131500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 55418353999 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26254153509 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 191107500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 171362000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 3348487500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 17539796499 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21710976040 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 130302104047 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 111811500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 89924000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 5466131500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 55418353999 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26254153509 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 191107500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 171362000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 3348487500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 17539796499 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21710976040 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 130302104047 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5072417000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5669500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 438450000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 8777849000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4909122500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 490071500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5399194000 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3261312500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9981539500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5669500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 928521500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 14177043000 # number of overall MSHR uncacheable cycles
---
> system.l2c.writebacks::writebacks 894068 # number of writebacks
> system.l2c.writebacks::total 894068 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 157 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 29 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 173 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 381 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 157 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 29 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 173 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 381 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 157 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 29 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 173 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 381 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 39667 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 39667 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 46094 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 42278 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 88372 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9356 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8640 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 17996 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 470394 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 130669 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 601063 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1337 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1196 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 55231 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 120360 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1176 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1070 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 55051 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 85422 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 622981 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 1337 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 1196 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 55231 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 590754 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1176 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1070 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 55051 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 216091 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1224044 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 1337 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 1196 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 55231 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 590754 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168332 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1176 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1070 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 55051 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 216091 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 133806 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1224044 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14625 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23508 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 90534 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15482 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38054 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 30107 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 46080 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 128588 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3387465005 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3115331505 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 6502796510 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 715527500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 661381001 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1376908501 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 63317577000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16586626000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 79904203000 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 153089500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6862441500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 15441020000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141556000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6812739500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10979665500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 87082118457 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 153089500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 6862441500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 78758597000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141556000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 6812739500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 27566291500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 166986321457 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 169171500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 153089500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 6862441500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 78758597000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26044700736 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 152884500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141556000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 6812739500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 27566291500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 20324849721 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 166986321457 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2064046000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9850500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3446902500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 11417239000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2154023500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3385027500 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5539051000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5896440000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4218069500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9850500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6831930000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 16956290000 # number of overall MSHR uncacheable cycles
2979,3075c2986,3082
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.606790 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.561367 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.584325 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.612171 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592415 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.602866 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.762808 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.410035 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.659941 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189908 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166445 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202368 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.292574 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.188623 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.224224 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.092894 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.468787 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.424609 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.267080 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.301927 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064234 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.240129 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.395024 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.292574 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20763.848676 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20748.656488 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20756.630372 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20820.245144 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.859554 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20804.792992 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84092.699617 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74998.374967 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 82445.049668 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80225.346258 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80567.388288 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96087.167208 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80672.077922 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80289.285714 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72746.929025 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83288.652898 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 113927.078717 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79231.965174 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79814.625058 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73877.275234 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 77690.847518 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 109458.459786 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 90020.839209 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154689.304992 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84123.177283 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97112.990662 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149431.465360 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 97955.526684 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142628.292167 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62367.331523 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152057.942203 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60962.365591 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 90897.846304 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 110548.279438 # average overall mshr uncacheable latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.637353 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.577245 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.607109 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.617680 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590164 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604156 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733738 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.429780 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.635958 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174987 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.138705 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.164773 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.259003 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180749 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.229382 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.071489 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.444538 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.352316 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154209 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.187917 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073133 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.234910 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.298591 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.259003 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73490.367618 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73686.823052 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73584.353755 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76477.928602 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76548.726968 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76511.919371 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134605.409508 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126936.197568 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 132938.149578 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 128290.295779 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128534.399803 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 139782.944355 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126530.665669 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128001.254181 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124249.814416 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133318.770588 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154722.219994 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency
3077,3092c3084,3099
< system.membus.trans_dist::ReadReq 90388 # Transaction distribution
< system.membus.trans_dist::ReadResp 903121 # Transaction distribution
< system.membus.trans_dist::WriteReq 37855 # Transaction distribution
< system.membus.trans_dist::WriteResp 37855 # Transaction distribution
< system.membus.trans_dist::Writeback 1188917 # Transaction distribution
< system.membus.trans_dist::CleanEvict 251117 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 423385 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 299485 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 111205 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
< system.membus.trans_dist::ReadExReq 657294 # Transaction distribution
< system.membus.trans_dist::ReadExResp 636531 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 812733 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122698 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 90534 # Transaction distribution
> system.membus.trans_dist::ReadResp 722459 # Transaction distribution
> system.membus.trans_dist::WriteReq 38054 # Transaction distribution
> system.membus.trans_dist::WriteResp 38054 # Transaction distribution
> system.membus.trans_dist::Writeback 1001017 # Transaction distribution
> system.membus.trans_dist::CleanEvict 217536 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
> system.membus.trans_dist::ReadExReq 614073 # Transaction distribution
> system.membus.trans_dist::ReadExResp 593351 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes)
3094,3100c3101,3107
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23798 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5171308 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 5317856 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342726 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 342726 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5660582 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes)
3102,3109c3109,3116
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47596 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 164770304 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 164975029 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270144 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7270144 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 172245173 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 635192 # Total snoops (count)
< system.membus.snoop_fanout::samples 3870084 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 620798 # Total snoops (count)
> system.membus.snoop_fanout::samples 3413791 # Request fanout histogram
3114c3121
< system.membus.snoop_fanout::1 3870084 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram
3119,3120c3126,3127
< system.membus.snoop_fanout::total 3870084 # Request fanout histogram
< system.membus.reqLayer0.occupancy 109645497 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3413791 # Request fanout histogram
> system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks)
3124c3131
< system.membus.reqLayer2.occupancy 19606499 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks)
3126c3133
< system.membus.reqLayer5.occupancy 8359681063 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks)
3128c3135
< system.membus.respLayer2.occupancy 8175730132 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks)
3130c3137
< system.membus.respLayer3.occupancy 229316266 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks)
3184,3208c3191,3221
< system.toL2Bus.trans_dist::ReadReq 90390 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4911274 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 37855 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 37855 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 3585089 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1614217 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 477552 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 311291 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 788843 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 110 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 110 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1123188 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1123188 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4828127 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8913245 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6867211 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 15780456 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 273644474 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200023995 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 473668469 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3257042 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 13541412 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.121741 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.326987 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 2987756 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram
3210,3212c3223,3225
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 11892865 87.83% 87.83% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1648547 12.17% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram
3214c3227
< system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3216,3217c3229,3230
< system.toL2Bus.snoop_fanout::total 13541412 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 8755054077 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks)
3219c3232
< system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks)
3221c3234
< system.toL2Bus.respLayer0.occupancy 5258284103 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks)
3223c3236
< system.toL2Bus.respLayer1.occupancy 4190040133 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks)