1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.554910 # Number of seconds simulated
4sim_ticks 47554910274000 # Number of ticks simulated
5final_tick 47554910274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 271941 # Simulator instruction rate (inst/s)
8host_op_rate 319891 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 14743065549 # Simulator tick rate (ticks/s)
10host_mem_usage 772792 # Number of bytes of host memory used
11host_seconds 3225.58 # Real time elapsed on the host
12sim_insts 877166784 # Number of instructions simulated
13sim_ops 1031833041 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 127616 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 113728 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 7300032 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 13854920 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 13786176 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 105536 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.itb.walker 93440 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.inst 3887680 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.data 9545552 # Number of bytes read from this memory
26system.physmem.bytes_read::cpu1.l2cache.prefetcher 11958848 # Number of bytes read from this memory
27system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory
28system.physmem.bytes_read::total 61215640 # Number of bytes read from this memory
29system.physmem.bytes_inst_read::cpu0.inst 7300032 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::cpu1.inst 3887680 # Number of instructions bytes read from this memory
31system.physmem.bytes_inst_read::total 11187712 # Number of instructions bytes read from this memory
32system.physmem.bytes_written::writebacks 74339904 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35system.physmem.bytes_written::total 74360488 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 1994 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 1777 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 114063 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 216496 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 215409 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 1649 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 1460 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 60745 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 149162 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 186857 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 956520 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 1161561 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51system.physmem.num_writes::total 1164135 # Number of write requests responded to by this memory
52system.physmem.bw_read::cpu0.dtb.walker 2684 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.itb.walker 2392 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.data 291346 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.l2cache.prefetcher 289900 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.dtb.walker 2219 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.itb.walker 1965 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.inst 81751 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.data 200727 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.l2cache.prefetcher 251475 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::realview.ide 9297 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::total 1287262 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu1.inst 81751 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::total 235259 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_write::writebacks 1563243 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::total 1563676 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_total::writebacks 1563243 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.dtb.walker 2684 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.itb.walker 2392 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.data 291778 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.l2cache.prefetcher 289900 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.dtb.walker 2219 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.itb.walker 1965 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 81751 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.data 200727 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.l2cache.prefetcher 251475 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::realview.ide 9297 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::total 2850939 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.readReqs 956520 # Number of read requests accepted
85system.physmem.writeReqs 1164135 # Number of write requests accepted
86system.physmem.readBursts 956520 # Number of DRAM read bursts, including those serviced by the write queue
87system.physmem.writeBursts 1164135 # Number of DRAM write bursts, including those merged in the write queue
88system.physmem.bytesReadDRAM 61192448 # Total number of bytes read from DRAM
89system.physmem.bytesReadWrQ 24832 # Total number of bytes read from write queue
90system.physmem.bytesWritten 74357824 # Total number of bytes written to DRAM
91system.physmem.bytesReadSys 61215640 # Total read bytes from the system interface side
92system.physmem.bytesWrittenSys 74360488 # Total written bytes from the system interface side
93system.physmem.servicedByWrQ 388 # Number of DRAM read bursts serviced by the write queue
94system.physmem.mergedWrBursts 2263 # Number of DRAM write bursts merged with an existing one
95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96system.physmem.perBankRdBursts::0 50657 # Per bank write bursts
97system.physmem.perBankRdBursts::1 60930 # Per bank write bursts
98system.physmem.perBankRdBursts::2 49716 # Per bank write bursts
99system.physmem.perBankRdBursts::3 55090 # Per bank write bursts
100system.physmem.perBankRdBursts::4 56536 # Per bank write bursts
101system.physmem.perBankRdBursts::5 68947 # Per bank write bursts
102system.physmem.perBankRdBursts::6 58003 # Per bank write bursts
103system.physmem.perBankRdBursts::7 60908 # Per bank write bursts
104system.physmem.perBankRdBursts::8 53263 # Per bank write bursts
105system.physmem.perBankRdBursts::9 106420 # Per bank write bursts
106system.physmem.perBankRdBursts::10 50504 # Per bank write bursts
107system.physmem.perBankRdBursts::11 59458 # Per bank write bursts
108system.physmem.perBankRdBursts::12 56712 # Per bank write bursts
109system.physmem.perBankRdBursts::13 60494 # Per bank write bursts
110system.physmem.perBankRdBursts::14 55357 # Per bank write bursts
111system.physmem.perBankRdBursts::15 53137 # Per bank write bursts
112system.physmem.perBankWrBursts::0 68064 # Per bank write bursts
113system.physmem.perBankWrBursts::1 74120 # Per bank write bursts
114system.physmem.perBankWrBursts::2 68663 # Per bank write bursts
115system.physmem.perBankWrBursts::3 72095 # Per bank write bursts
116system.physmem.perBankWrBursts::4 73476 # Per bank write bursts
117system.physmem.perBankWrBursts::5 80505 # Per bank write bursts
118system.physmem.perBankWrBursts::6 71958 # Per bank write bursts
119system.physmem.perBankWrBursts::7 74882 # Per bank write bursts
120system.physmem.perBankWrBursts::8 69253 # Per bank write bursts
121system.physmem.perBankWrBursts::9 72875 # Per bank write bursts
122system.physmem.perBankWrBursts::10 68876 # Per bank write bursts
123system.physmem.perBankWrBursts::11 75926 # Per bank write bursts
124system.physmem.perBankWrBursts::12 72095 # Per bank write bursts
125system.physmem.perBankWrBursts::13 75544 # Per bank write bursts
126system.physmem.perBankWrBursts::14 71950 # Per bank write bursts
127system.physmem.perBankWrBursts::15 71559 # Per bank write bursts
128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129system.physmem.numWrRetry 408 # Number of times write queue was full causing retry
130system.physmem.totGap 47554908178500 # Total gap between requests
131system.physmem.readPktSize::0 0 # Read request sizes (log2)
132system.physmem.readPktSize::1 0 # Read request sizes (log2)
133system.physmem.readPktSize::2 0 # Read request sizes (log2)
134system.physmem.readPktSize::3 25 # Read request sizes (log2)
135system.physmem.readPktSize::4 5 # Read request sizes (log2)
136system.physmem.readPktSize::5 0 # Read request sizes (log2)
137system.physmem.readPktSize::6 956490 # Read request sizes (log2)
138system.physmem.writePktSize::0 0 # Write request sizes (log2)
139system.physmem.writePktSize::1 0 # Write request sizes (log2)
140system.physmem.writePktSize::2 2 # Write request sizes (log2)
141system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142system.physmem.writePktSize::4 0 # Write request sizes (log2)
143system.physmem.writePktSize::5 0 # Write request sizes (log2)
144system.physmem.writePktSize::6 1161561 # Write request sizes (log2)
145system.physmem.rdQLenPdf::0 589555 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::1 157739 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::2 46445 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::3 36293 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::4 27945 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::5 25583 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::6 23391 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::7 20914 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::8 18402 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::9 4361 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::10 1587 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::11 1163 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::12 874 # What read queue length does an incoming req see
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184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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193system.physmem.wrQLenPdf::16 31849 # What write queue length does an incoming req see
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195system.physmem.wrQLenPdf::18 55864 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::19 61058 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::20 64206 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::21 66032 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::22 67782 # What write queue length does an incoming req see
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201system.physmem.wrQLenPdf::24 70728 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::25 73352 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::26 74938 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::27 72063 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::28 70410 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::29 71450 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::30 74135 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::31 66609 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::32 62837 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::33 4834 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::34 2922 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::35 2290 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::36 1924 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::37 1530 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::38 1398 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::39 1235 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::40 995 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::41 863 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::42 908 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::43 855 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::44 856 # What write queue length does an incoming req see
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224system.physmem.wrQLenPdf::47 762 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::48 737 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::49 763 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::50 757 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::51 750 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::52 714 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::53 706 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::54 687 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::55 740 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::56 794 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::57 717 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::58 562 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::59 748 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::60 1309 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::61 1089 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::62 448 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::63 933 # What write queue length does an incoming req see
241system.physmem.bytesPerActivate::samples 917155 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::mean 147.793592 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::gmean 99.753334 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::stdev 195.501852 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::0-127 602356 65.68% 65.68% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::128-255 188931 20.60% 86.28% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::256-383 45653 4.98% 91.25% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::384-511 20839 2.27% 93.53% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::512-639 15350 1.67% 95.20% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::640-767 9574 1.04% 96.24% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::768-895 6849 0.75% 96.99% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::896-1023 5486 0.60% 97.59% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::1024-1151 22117 2.41% 100.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::total 917155 # Bytes accessed per row activation
255system.physmem.rdPerTurnAround::samples 56545 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::mean 16.908586 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::stdev 165.794592 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::0-1023 56543 100.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 56545 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 56545 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 20.547193 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 18.712168 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 14.106429 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 48673 86.08% 86.08% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 2227 3.94% 90.02% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 713 1.26% 91.28% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 569 1.01% 92.28% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 930 1.64% 93.93% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 406 0.72% 94.65% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 286 0.51% 95.15% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 280 0.50% 95.65% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 183 0.32% 95.97% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 127 0.22% 96.20% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 115 0.20% 96.40% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 143 0.25% 96.65% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 579 1.02% 97.68% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 140 0.25% 97.92% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 130 0.23% 98.15% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 128 0.23% 98.38% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 106 0.19% 98.57% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 75 0.13% 98.70% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::88-91 85 0.15% 98.85% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::92-95 94 0.17% 99.02% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::96-99 75 0.13% 99.15% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::100-103 62 0.11% 99.26% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::104-107 61 0.11% 99.37% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::108-111 71 0.13% 99.49% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::112-115 39 0.07% 99.56% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::116-119 37 0.07% 99.63% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::120-123 45 0.08% 99.71% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::124-127 34 0.06% 99.77% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::128-131 51 0.09% 99.86% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::132-135 18 0.03% 99.89% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::136-139 12 0.02% 99.91% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::140-143 17 0.03% 99.94% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::148-151 3 0.01% 99.95% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::156-159 3 0.01% 99.96% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::172-175 3 0.01% 99.98% # Writes before turning the bus around for reads
305system.physmem.wrPerTurnAround::176-179 3 0.01% 99.98% # Writes before turning the bus around for reads
306system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads
307system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads
308system.physmem.wrPerTurnAround::196-199 1 0.00% 99.99% # Writes before turning the bus around for reads
309system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads
310system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
311system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads
312system.physmem.wrPerTurnAround::total 56545 # Writes before turning the bus around for reads
313system.physmem.totQLat 49127716705 # Total ticks spent queuing
314system.physmem.totMemAccLat 67055191705 # Total ticks spent from burst creation until serviced by the DRAM
315system.physmem.totBusLat 4780660000 # Total ticks spent in databus transfers
316system.physmem.avgQLat 51381.73 # Average queueing delay per DRAM burst
317system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
318system.physmem.avgMemAccLat 70131.73 # Average memory access latency per DRAM burst
319system.physmem.avgRdBW 1.29 # Average DRAM read bandwidth in MiByte/s
320system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
321system.physmem.avgRdBWSys 1.29 # Average system read bandwidth in MiByte/s
322system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
323system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
324system.physmem.busUtil 0.02 # Data bus utilization in percentage
325system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
326system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
327system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
328system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing
329system.physmem.readRowHits 713884 # Number of row buffer hits during reads
330system.physmem.writeRowHits 486930 # Number of row buffer hits during writes
331system.physmem.readRowHitRate 74.66 # Row buffer hit rate for reads
332system.physmem.writeRowHitRate 41.91 # Row buffer hit rate for writes
333system.physmem.avgGap 22424632.10 # Average gap between requests
334system.physmem.pageHitRate 56.70 # Row buffer hit rate, read and write combined
335system.physmem_0.actEnergy 3312517320 # Energy for activate commands per rank (pJ)
336system.physmem_0.preEnergy 1760633325 # Energy for precharge commands per rank (pJ)
337system.physmem_0.readEnergy 3290019180 # Energy for read commands per rank (pJ)
338system.physmem_0.writeEnergy 3047242860 # Energy for write commands per rank (pJ)
339system.physmem_0.refreshEnergy 39654114240.000008 # Energy for refresh commands per rank (pJ)
340system.physmem_0.actBackEnergy 43514746200 # Energy for active background per rank (pJ)
341system.physmem_0.preBackEnergy 2086179840 # Energy for precharge background per rank (pJ)
342system.physmem_0.actPowerDownEnergy 77547983010 # Energy for active power-down per rank (pJ)
343system.physmem_0.prePowerDownEnergy 55697482080 # Energy for precharge power-down per rank (pJ)
344system.physmem_0.selfRefreshEnergy 11319929946090 # Energy for self refresh per rank (pJ)
345system.physmem_0.totalEnergy 11549857795695 # Total energy per rank (pJ)
346system.physmem_0.averagePower 242.874137 # Core power per rank (mW)
347system.physmem_0.totalIdleTime 47454012976233 # Total Idle time Per DRAM Rank
348system.physmem_0.memoryStateTime::IDLE 3696049077 # Time in different power states
349system.physmem_0.memoryStateTime::REF 16847240000 # Time in different power states
350system.physmem_0.memoryStateTime::SREF 47138905885000 # Time in different power states
351system.physmem_0.memoryStateTime::PRE_PDN 145045339612 # Time in different power states
352system.physmem_0.memoryStateTime::ACT 80353958440 # Time in different power states
353system.physmem_0.memoryStateTime::ACT_PDN 170061801871 # Time in different power states
354system.physmem_1.actEnergy 3235997940 # Energy for activate commands per rank (pJ)
355system.physmem_1.preEnergy 1719969900 # Energy for precharge commands per rank (pJ)
356system.physmem_1.readEnergy 3536763300 # Energy for read commands per rank (pJ)
357system.physmem_1.writeEnergy 3017567160 # Energy for write commands per rank (pJ)
358system.physmem_1.refreshEnergy 38496747120.000008 # Energy for refresh commands per rank (pJ)
359system.physmem_1.actBackEnergy 44079949650 # Energy for active background per rank (pJ)
360system.physmem_1.preBackEnergy 2012350560 # Energy for precharge background per rank (pJ)
361system.physmem_1.actPowerDownEnergy 72751641060 # Energy for active power-down per rank (pJ)
362system.physmem_1.prePowerDownEnergy 54144086400 # Energy for precharge power-down per rank (pJ)
363system.physmem_1.selfRefreshEnergy 11323086477345 # Energy for self refresh per rank (pJ)
364system.physmem_1.totalEnergy 11546099446905 # Total energy per rank (pJ)
365system.physmem_1.averagePower 242.795105 # Core power per rank (mW)
366system.physmem_1.totalIdleTime 47452962329328 # Total Idle time Per DRAM Rank
367system.physmem_1.memoryStateTime::IDLE 3512995347 # Time in different power states
368system.physmem_1.memoryStateTime::REF 16356664000 # Time in different power states
369system.physmem_1.memoryStateTime::SREF 47152420144750 # Time in different power states
370system.physmem_1.memoryStateTime::PRE_PDN 141000345458 # Time in different power states
371system.physmem_1.memoryStateTime::ACT 82076677575 # Time in different power states
372system.physmem_1.memoryStateTime::ACT_PDN 159543446870 # Time in different power states
373system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
374system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
375system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
376system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
377system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
378system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
379system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
380system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
381system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory
382system.realview.nvmem.num_reads::cpu0.inst 11 # Number of read requests responded to by this memory
383system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
384system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
385system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
386system.realview.nvmem.num_reads::total 27 # Number of read requests responded to by this memory
387system.realview.nvmem.bw_read::cpu0.inst 15 # Total read bandwidth from this memory (bytes/s)
388system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
389system.realview.nvmem.bw_read::cpu1.inst 13 # Total read bandwidth from this memory (bytes/s)
390system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
391system.realview.nvmem.bw_read::total 29 # Total read bandwidth from this memory (bytes/s)
392system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
393system.realview.nvmem.bw_inst_read::cpu1.inst 13 # Instruction read bandwidth from this memory (bytes/s)
394system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
395system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
396system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
397system.realview.nvmem.bw_total::cpu1.inst 13 # Total bandwidth to/from this memory (bytes/s)
398system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
399system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
400system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
401system.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
402system.bridge.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
403system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
404system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
405system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
406system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
407system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
408system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
409system.cpu0.branchPred.lookups 137627857 # Number of BP lookups
410system.cpu0.branchPred.condPredicted 96352530 # Number of conditional branches predicted
411system.cpu0.branchPred.condIncorrect 6353129 # Number of conditional branches incorrect
412system.cpu0.branchPred.BTBLookups 102612546 # Number of BTB lookups
413system.cpu0.branchPred.BTBHits 71378761 # Number of BTB hits
414system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
415system.cpu0.branchPred.BTBHitPct 69.561436 # BTB Hit Percentage
416system.cpu0.branchPred.usedRAS 16463463 # Number of times the RAS was used to get a target.
417system.cpu0.branchPred.RASInCorrect 1088270 # Number of incorrect RAS predictions.
418system.cpu0.branchPred.indirectLookups 3669510 # Number of indirect predictor lookups.
419system.cpu0.branchPred.indirectHits 2436336 # Number of indirect target hits.
420system.cpu0.branchPred.indirectMisses 1233174 # Number of indirect misses.
421system.cpu0.branchPredindirectMispredicted 447439 # Number of mispredicted indirect branches.
422system.cpu_clk_domain.clock 500 # Clock period in ticks
423system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
424system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
425system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
426system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
427system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
428system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
429system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
430system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
431system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

445system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
446system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
447system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
448system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
449system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
450system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
451system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
452system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
453system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
454system.cpu0.dtb.walker.walks 282889 # Table walker walks requested
455system.cpu0.dtb.walker.walksLong 282889 # Table walker walks initiated with long descriptors
456system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9418 # Level at which table walker walks with long descriptors terminate
457system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 82700 # Level at which table walker walks with long descriptors terminate
458system.cpu0.dtb.walker.walkWaitTime::samples 282889 # Table walker wait (enqueue to first request) latency
459system.cpu0.dtb.walker.walkWaitTime::0 282889 100.00% 100.00% # Table walker wait (enqueue to first request) latency
460system.cpu0.dtb.walker.walkWaitTime::total 282889 # Table walker wait (enqueue to first request) latency
461system.cpu0.dtb.walker.walkCompletionTime::samples 92118 # Table walker service (enqueue to completion) latency
462system.cpu0.dtb.walker.walkCompletionTime::mean 24516.006644 # Table walker service (enqueue to completion) latency
463system.cpu0.dtb.walker.walkCompletionTime::gmean 22528.646157 # Table walker service (enqueue to completion) latency
464system.cpu0.dtb.walker.walkCompletionTime::stdev 18042.498572 # Table walker service (enqueue to completion) latency
465system.cpu0.dtb.walker.walkCompletionTime::0-65535 90947 98.73% 98.73% # Table walker service (enqueue to completion) latency
466system.cpu0.dtb.walker.walkCompletionTime::65536-131071 867 0.94% 99.67% # Table walker service (enqueue to completion) latency
467system.cpu0.dtb.walker.walkCompletionTime::131072-196607 159 0.17% 99.84% # Table walker service (enqueue to completion) latency
468system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.90% # Table walker service (enqueue to completion) latency
469system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.95% # Table walker service (enqueue to completion) latency
470system.cpu0.dtb.walker.walkCompletionTime::327680-393215 20 0.02% 99.97% # Table walker service (enqueue to completion) latency
471system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
472system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
473system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
474system.cpu0.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
475system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
476system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
477system.cpu0.dtb.walker.walkCompletionTime::total 92118 # Table walker service (enqueue to completion) latency
478system.cpu0.dtb.walker.walksPending::samples 1049600704 # Table walker pending requests distribution
479system.cpu0.dtb.walker.walksPending::0 1049600704 100.00% 100.00% # Table walker pending requests distribution
480system.cpu0.dtb.walker.walksPending::total 1049600704 # Table walker pending requests distribution
481system.cpu0.dtb.walker.walkPageSizes::4K 82700 89.78% 89.78% # Table walker page sizes translated
482system.cpu0.dtb.walker.walkPageSizes::2M 9418 10.22% 100.00% # Table walker page sizes translated
483system.cpu0.dtb.walker.walkPageSizes::total 92118 # Table walker page sizes translated
484system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 282889 # Table walker requests started/completed, data/inst
485system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 282889 # Table walker requests started/completed, data/inst
487system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92118 # Table walker requests started/completed, data/inst
488system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
489system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92118 # Table walker requests started/completed, data/inst
490system.cpu0.dtb.walker.walkRequestOrigin::total 375007 # Table walker requests started/completed, data/inst
491system.cpu0.dtb.inst_hits 0 # ITB inst hits
492system.cpu0.dtb.inst_misses 0 # ITB inst misses
493system.cpu0.dtb.read_hits 87675894 # DTB read hits
494system.cpu0.dtb.read_misses 234519 # DTB read misses
495system.cpu0.dtb.write_hits 78239753 # DTB write hits
496system.cpu0.dtb.write_misses 48370 # DTB write misses
497system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
498system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
499system.cpu0.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID
500system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
501system.cpu0.dtb.flush_entries 38151 # Number of entries that have been flushed from TLB
502system.cpu0.dtb.align_faults 2038 # Number of TLB faults due to alignment restrictions
503system.cpu0.dtb.prefetch_faults 9397 # Number of TLB faults due to prefetch
504system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
505system.cpu0.dtb.perms_faults 11689 # Number of TLB faults due to permissions restrictions
506system.cpu0.dtb.read_accesses 87910413 # DTB read accesses
507system.cpu0.dtb.write_accesses 78288123 # DTB write accesses
508system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
509system.cpu0.dtb.hits 165915647 # DTB hits
510system.cpu0.dtb.misses 282889 # DTB misses
511system.cpu0.dtb.accesses 166198536 # DTB accesses
512system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
513system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
514system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
515system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
516system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
517system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
518system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
519system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
520system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

534system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
535system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
536system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
537system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
538system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
539system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
540system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
541system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
542system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
543system.cpu0.itb.walker.walks 69273 # Table walker walks requested
544system.cpu0.itb.walker.walksLong 69273 # Table walker walks initiated with long descriptors
545system.cpu0.itb.walker.walksLongTerminationLevel::Level2 583 # Level at which table walker walks with long descriptors terminate
546system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61330 # Level at which table walker walks with long descriptors terminate
547system.cpu0.itb.walker.walkWaitTime::samples 69273 # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkWaitTime::0 69273 100.00% 100.00% # Table walker wait (enqueue to first request) latency
549system.cpu0.itb.walker.walkWaitTime::total 69273 # Table walker wait (enqueue to first request) latency
550system.cpu0.itb.walker.walkCompletionTime::samples 61913 # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::mean 26255.972090 # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::gmean 24021.087370 # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::stdev 22669.077424 # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::0-65535 60695 98.03% 98.03% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::65536-131071 852 1.38% 99.41% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::131072-196607 248 0.40% 99.81% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::196608-262143 49 0.08% 99.89% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.91% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.93% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.94% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.94% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::589824-655359 39 0.06% 100.00% # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walkCompletionTime::total 61913 # Table walker service (enqueue to completion) latency
564system.cpu0.itb.walker.walksPending::samples 1048830204 # Table walker pending requests distribution
565system.cpu0.itb.walker.walksPending::0 1048830204 100.00% 100.00% # Table walker pending requests distribution
566system.cpu0.itb.walker.walksPending::total 1048830204 # Table walker pending requests distribution
567system.cpu0.itb.walker.walkPageSizes::4K 61330 99.06% 99.06% # Table walker page sizes translated
568system.cpu0.itb.walker.walkPageSizes::2M 583 0.94% 100.00% # Table walker page sizes translated
569system.cpu0.itb.walker.walkPageSizes::total 61913 # Table walker page sizes translated
570system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
571system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69273 # Table walker requests started/completed, data/inst
572system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69273 # Table walker requests started/completed, data/inst
573system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
574system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61913 # Table walker requests started/completed, data/inst
575system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61913 # Table walker requests started/completed, data/inst
576system.cpu0.itb.walker.walkRequestOrigin::total 131186 # Table walker requests started/completed, data/inst
577system.cpu0.itb.inst_hits 244690597 # ITB inst hits
578system.cpu0.itb.inst_misses 69273 # ITB inst misses
579system.cpu0.itb.read_hits 0 # DTB read hits
580system.cpu0.itb.read_misses 0 # DTB read misses
581system.cpu0.itb.write_hits 0 # DTB write hits
582system.cpu0.itb.write_misses 0 # DTB write misses
583system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
584system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
585system.cpu0.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID
586system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
587system.cpu0.itb.flush_entries 27059 # Number of entries that have been flushed from TLB
588system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
589system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
590system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
591system.cpu0.itb.perms_faults 167788 # Number of TLB faults due to permissions restrictions
592system.cpu0.itb.read_accesses 0 # DTB read accesses
593system.cpu0.itb.write_accesses 0 # DTB write accesses
594system.cpu0.itb.inst_accesses 244759870 # ITB inst accesses
595system.cpu0.itb.hits 244690597 # DTB hits
596system.cpu0.itb.misses 69273 # DTB misses
597system.cpu0.itb.accesses 244759870 # DTB accesses
598system.cpu0.numPwrStateTransitions 27904 # Number of power state transitions
599system.cpu0.pwrStateClkGateDist::samples 13952 # Distribution of time spent in the clock gated state
600system.cpu0.pwrStateClkGateDist::mean 3372797482.084218 # Distribution of time spent in the clock gated state
601system.cpu0.pwrStateClkGateDist::stdev 110921496988.059006 # Distribution of time spent in the clock gated state
602system.cpu0.pwrStateClkGateDist::underflows 3863 27.69% 27.69% # Distribution of time spent in the clock gated state
603system.cpu0.pwrStateClkGateDist::1000-5e+10 10067 72.15% 99.84% # Distribution of time spent in the clock gated state
604system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.08% 99.92% # Distribution of time spent in the clock gated state
605system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state
606system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state
607system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.94% # Distribution of time spent in the clock gated state
608system.cpu0.pwrStateClkGateDist::overflows 8 0.06% 100.00% # Distribution of time spent in the clock gated state
609system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
610system.cpu0.pwrStateClkGateDist::max_value 7351146409252 # Distribution of time spent in the clock gated state
611system.cpu0.pwrStateClkGateDist::total 13952 # Distribution of time spent in the clock gated state
612system.cpu0.pwrStateResidencyTicks::ON 497639803961 # Cumulative time (in ticks) in various power states
613system.cpu0.pwrStateResidencyTicks::CLK_GATED 47057270470039 # Cumulative time (in ticks) in various power states
614system.cpu0.numCycles 995321471 # number of cpu cycles simulated
615system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
616system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
617system.cpu0.committedInsts 452001209 # Number of instructions committed
618system.cpu0.committedOps 531851100 # Number of ops (including micro ops) committed
619system.cpu0.discardedOps 46239027 # Number of ops (including micro ops) which were discarded before commit
620system.cpu0.numFetchSuspends 5092 # Number of times Execute suspended instruction fetching
621system.cpu0.quiesceCycles 94115325169 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
622system.cpu0.cpi 2.202033 # CPI: cycles per instruction
623system.cpu0.ipc 0.454126 # IPC: instructions per cycle
624system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
625system.cpu0.op_class_0::IntAlu 368287155 69.25% 69.25% # Class of committed instruction
626system.cpu0.op_class_0::IntMult 1118982 0.21% 69.46% # Class of committed instruction
627system.cpu0.op_class_0::IntDiv 57276 0.01% 69.47% # Class of committed instruction
628system.cpu0.op_class_0::FloatAdd 8 0.00% 69.47% # Class of committed instruction
629system.cpu0.op_class_0::FloatCmp 13 0.00% 69.47% # Class of committed instruction
630system.cpu0.op_class_0::FloatCvt 21 0.00% 69.47% # Class of committed instruction
631system.cpu0.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction
632system.cpu0.op_class_0::FloatMultAcc 0 0.00% 69.47% # Class of committed instruction
633system.cpu0.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction
634system.cpu0.op_class_0::FloatMisc 85306 0.02% 69.48% # Class of committed instruction
635system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
636system.cpu0.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
637system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
638system.cpu0.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
639system.cpu0.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
640system.cpu0.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
641system.cpu0.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
642system.cpu0.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
643system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
644system.cpu0.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
645system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
646system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
647system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.48% # Class of committed instruction
648system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
649system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.48% # Class of committed instruction
650system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.48% # Class of committed instruction
651system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
652system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 69.48% # Class of committed instruction
653system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction
654system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction
655system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction
656system.cpu0.op_class_0::MemRead 84333617 15.86% 85.34% # Class of committed instruction
657system.cpu0.op_class_0::MemWrite 77481840 14.57% 99.91% # Class of committed instruction
658system.cpu0.op_class_0::FloatMemRead 68467 0.01% 99.92% # Class of committed instruction
659system.cpu0.op_class_0::FloatMemWrite 418414 0.08% 100.00% # Class of committed instruction
660system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
661system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
662system.cpu0.op_class_0::total 531851100 # Class of committed instruction
663system.cpu0.kern.inst.arm 0 # number of arm instructions executed
664system.cpu0.kern.inst.quiesce 13952 # number of quiesce instructions executed
665system.cpu0.tickCycles 729574114 # Number of cycles that the object actually ticked
666system.cpu0.idleCycles 265747357 # Total number of cycles that the object has spent stopped
667system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
668system.cpu0.dcache.tags.replacements 5787900 # number of replacements
669system.cpu0.dcache.tags.tagsinuse 490.209920 # Cycle average of tags in use
670system.cpu0.dcache.tags.total_refs 157471988 # Total number of references to valid blocks.
671system.cpu0.dcache.tags.sampled_refs 5788412 # Sample count of references to valid blocks.
672system.cpu0.dcache.tags.avg_refs 27.204696 # Average number of references to valid blocks.
673system.cpu0.dcache.tags.warmup_cycle 5354308000 # Cycle when the warmup percentage was hit.
674system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.209920 # Average occupied blocks per requestor
675system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957441 # Average percentage of cache occupancy
676system.cpu0.dcache.tags.occ_percent::total 0.957441 # Average percentage of cache occupancy
677system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
678system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
679system.cpu0.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id
680system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
681system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
682system.cpu0.dcache.tags.tag_accesses 334937152 # Number of tag accesses
683system.cpu0.dcache.tags.data_accesses 334937152 # Number of data accesses
684system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
685system.cpu0.dcache.ReadReq_hits::cpu0.data 80549957 # number of ReadReq hits
686system.cpu0.dcache.ReadReq_hits::total 80549957 # number of ReadReq hits
687system.cpu0.dcache.WriteReq_hits::cpu0.data 72496805 # number of WriteReq hits
688system.cpu0.dcache.WriteReq_hits::total 72496805 # number of WriteReq hits
689system.cpu0.dcache.SoftPFReq_hits::cpu0.data 269794 # number of SoftPFReq hits
690system.cpu0.dcache.SoftPFReq_hits::total 269794 # number of SoftPFReq hits
691system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177007 # number of WriteLineReq hits
692system.cpu0.dcache.WriteLineReq_hits::total 177007 # number of WriteLineReq hits
693system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1734640 # number of LoadLockedReq hits
694system.cpu0.dcache.LoadLockedReq_hits::total 1734640 # number of LoadLockedReq hits
695system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1715473 # number of StoreCondReq hits
696system.cpu0.dcache.StoreCondReq_hits::total 1715473 # number of StoreCondReq hits
697system.cpu0.dcache.demand_hits::cpu0.data 153223769 # number of demand (read+write) hits
698system.cpu0.dcache.demand_hits::total 153223769 # number of demand (read+write) hits
699system.cpu0.dcache.overall_hits::cpu0.data 153493563 # number of overall hits
700system.cpu0.dcache.overall_hits::total 153493563 # number of overall hits
701system.cpu0.dcache.ReadReq_misses::cpu0.data 3263198 # number of ReadReq misses
702system.cpu0.dcache.ReadReq_misses::total 3263198 # number of ReadReq misses
703system.cpu0.dcache.WriteReq_misses::cpu0.data 2445366 # number of WriteReq misses
704system.cpu0.dcache.WriteReq_misses::total 2445366 # number of WriteReq misses
705system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673099 # number of SoftPFReq misses
706system.cpu0.dcache.SoftPFReq_misses::total 673099 # number of SoftPFReq misses
707system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844507 # number of WriteLineReq misses
708system.cpu0.dcache.WriteLineReq_misses::total 844507 # number of WriteLineReq misses
709system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 169054 # number of LoadLockedReq misses
710system.cpu0.dcache.LoadLockedReq_misses::total 169054 # number of LoadLockedReq misses
711system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187078 # number of StoreCondReq misses
712system.cpu0.dcache.StoreCondReq_misses::total 187078 # number of StoreCondReq misses
713system.cpu0.dcache.demand_misses::cpu0.data 6553071 # number of demand (read+write) misses
714system.cpu0.dcache.demand_misses::total 6553071 # number of demand (read+write) misses
715system.cpu0.dcache.overall_misses::cpu0.data 7226170 # number of overall misses
716system.cpu0.dcache.overall_misses::total 7226170 # number of overall misses
717system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52395902500 # number of ReadReq miss cycles
718system.cpu0.dcache.ReadReq_miss_latency::total 52395902500 # number of ReadReq miss cycles
719system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52490790500 # number of WriteReq miss cycles
720system.cpu0.dcache.WriteReq_miss_latency::total 52490790500 # number of WriteReq miss cycles
721system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27335813500 # number of WriteLineReq miss cycles
722system.cpu0.dcache.WriteLineReq_miss_latency::total 27335813500 # number of WriteLineReq miss cycles
723system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2555333500 # number of LoadLockedReq miss cycles
724system.cpu0.dcache.LoadLockedReq_miss_latency::total 2555333500 # number of LoadLockedReq miss cycles
725system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4463485500 # number of StoreCondReq miss cycles
726system.cpu0.dcache.StoreCondReq_miss_latency::total 4463485500 # number of StoreCondReq miss cycles
727system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2023000 # number of StoreCondFailReq miss cycles
728system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2023000 # number of StoreCondFailReq miss cycles
729system.cpu0.dcache.demand_miss_latency::cpu0.data 132222506500 # number of demand (read+write) miss cycles
730system.cpu0.dcache.demand_miss_latency::total 132222506500 # number of demand (read+write) miss cycles
731system.cpu0.dcache.overall_miss_latency::cpu0.data 132222506500 # number of overall miss cycles
732system.cpu0.dcache.overall_miss_latency::total 132222506500 # number of overall miss cycles
733system.cpu0.dcache.ReadReq_accesses::cpu0.data 83813155 # number of ReadReq accesses(hits+misses)
734system.cpu0.dcache.ReadReq_accesses::total 83813155 # number of ReadReq accesses(hits+misses)
735system.cpu0.dcache.WriteReq_accesses::cpu0.data 74942171 # number of WriteReq accesses(hits+misses)
736system.cpu0.dcache.WriteReq_accesses::total 74942171 # number of WriteReq accesses(hits+misses)
737system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 942893 # number of SoftPFReq accesses(hits+misses)
738system.cpu0.dcache.SoftPFReq_accesses::total 942893 # number of SoftPFReq accesses(hits+misses)
739system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1021514 # number of WriteLineReq accesses(hits+misses)
740system.cpu0.dcache.WriteLineReq_accesses::total 1021514 # number of WriteLineReq accesses(hits+misses)
741system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1903694 # number of LoadLockedReq accesses(hits+misses)
742system.cpu0.dcache.LoadLockedReq_accesses::total 1903694 # number of LoadLockedReq accesses(hits+misses)
743system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1902551 # number of StoreCondReq accesses(hits+misses)
744system.cpu0.dcache.StoreCondReq_accesses::total 1902551 # number of StoreCondReq accesses(hits+misses)
745system.cpu0.dcache.demand_accesses::cpu0.data 159776840 # number of demand (read+write) accesses
746system.cpu0.dcache.demand_accesses::total 159776840 # number of demand (read+write) accesses
747system.cpu0.dcache.overall_accesses::cpu0.data 160719733 # number of overall (read+write) accesses
748system.cpu0.dcache.overall_accesses::total 160719733 # number of overall (read+write) accesses
749system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038934 # miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_miss_rate::total 0.038934 # miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032630 # miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_miss_rate::total 0.032630 # miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.713866 # miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_miss_rate::total 0.713866 # miss rate for SoftPFReq accesses
755system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.826721 # miss rate for WriteLineReq accesses
756system.cpu0.dcache.WriteLineReq_miss_rate::total 0.826721 # miss rate for WriteLineReq accesses
757system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088803 # miss rate for LoadLockedReq accesses
758system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088803 # miss rate for LoadLockedReq accesses
759system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098330 # miss rate for StoreCondReq accesses
760system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098330 # miss rate for StoreCondReq accesses
761system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041014 # miss rate for demand accesses
762system.cpu0.dcache.demand_miss_rate::total 0.041014 # miss rate for demand accesses
763system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044961 # miss rate for overall accesses
764system.cpu0.dcache.overall_miss_rate::total 0.044961 # miss rate for overall accesses
765system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16056.611490 # average ReadReq miss latency
766system.cpu0.dcache.ReadReq_avg_miss_latency::total 16056.611490 # average ReadReq miss latency
767system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21465.412744 # average WriteReq miss latency
768system.cpu0.dcache.WriteReq_avg_miss_latency::total 21465.412744 # average WriteReq miss latency
769system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32368.960234 # average WriteLineReq miss latency
770system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32368.960234 # average WriteLineReq miss latency
771system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15115.486768 # average LoadLockedReq miss latency
772system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15115.486768 # average LoadLockedReq miss latency
773system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23858.954554 # average StoreCondReq miss latency
774system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23858.954554 # average StoreCondReq miss latency
775system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
776system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
777system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20177.182042 # average overall miss latency
778system.cpu0.dcache.demand_avg_miss_latency::total 20177.182042 # average overall miss latency
779system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18297.729849 # average overall miss latency
780system.cpu0.dcache.overall_avg_miss_latency::total 18297.729849 # average overall miss latency
781system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
784system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
785system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787system.cpu0.dcache.writebacks::writebacks 5787917 # number of writebacks
788system.cpu0.dcache.writebacks::total 5787917 # number of writebacks
789system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 205447 # number of ReadReq MSHR hits
790system.cpu0.dcache.ReadReq_mshr_hits::total 205447 # number of ReadReq MSHR hits
791system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1015907 # number of WriteReq MSHR hits
792system.cpu0.dcache.WriteReq_mshr_hits::total 1015907 # number of WriteReq MSHR hits
793system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 99 # number of WriteLineReq MSHR hits
794system.cpu0.dcache.WriteLineReq_mshr_hits::total 99 # number of WriteLineReq MSHR hits
795system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45884 # number of LoadLockedReq MSHR hits
796system.cpu0.dcache.LoadLockedReq_mshr_hits::total 45884 # number of LoadLockedReq MSHR hits
797system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 37 # number of StoreCondReq MSHR hits
798system.cpu0.dcache.StoreCondReq_mshr_hits::total 37 # number of StoreCondReq MSHR hits
799system.cpu0.dcache.demand_mshr_hits::cpu0.data 1221453 # number of demand (read+write) MSHR hits
800system.cpu0.dcache.demand_mshr_hits::total 1221453 # number of demand (read+write) MSHR hits
801system.cpu0.dcache.overall_mshr_hits::cpu0.data 1221453 # number of overall MSHR hits
802system.cpu0.dcache.overall_mshr_hits::total 1221453 # number of overall MSHR hits
803system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3057751 # number of ReadReq MSHR misses
804system.cpu0.dcache.ReadReq_mshr_misses::total 3057751 # number of ReadReq MSHR misses
805system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1429459 # number of WriteReq MSHR misses
806system.cpu0.dcache.WriteReq_mshr_misses::total 1429459 # number of WriteReq MSHR misses
807system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 670780 # number of SoftPFReq MSHR misses
808system.cpu0.dcache.SoftPFReq_mshr_misses::total 670780 # number of SoftPFReq MSHR misses
809system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 844408 # number of WriteLineReq MSHR misses
810system.cpu0.dcache.WriteLineReq_mshr_misses::total 844408 # number of WriteLineReq MSHR misses
811system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123170 # number of LoadLockedReq MSHR misses
812system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123170 # number of LoadLockedReq MSHR misses
813system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187041 # number of StoreCondReq MSHR misses
814system.cpu0.dcache.StoreCondReq_mshr_misses::total 187041 # number of StoreCondReq MSHR misses
815system.cpu0.dcache.demand_mshr_misses::cpu0.data 5331618 # number of demand (read+write) MSHR misses
816system.cpu0.dcache.demand_mshr_misses::total 5331618 # number of demand (read+write) MSHR misses
817system.cpu0.dcache.overall_mshr_misses::cpu0.data 6002398 # number of overall MSHR misses
818system.cpu0.dcache.overall_mshr_misses::total 6002398 # number of overall MSHR misses
819system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable
820system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31212 # number of ReadReq MSHR uncacheable
821system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable
822system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable
823system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses
824system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61967 # number of overall MSHR uncacheable misses
825system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44254087500 # number of ReadReq MSHR miss cycles
826system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44254087500 # number of ReadReq MSHR miss cycles
827system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29600010500 # number of WriteReq MSHR miss cycles
828system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29600010500 # number of WriteReq MSHR miss cycles
829system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15858321000 # number of SoftPFReq MSHR miss cycles
830system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15858321000 # number of SoftPFReq MSHR miss cycles
831system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26484603000 # number of WriteLineReq MSHR miss cycles
832system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26484603000 # number of WriteLineReq MSHR miss cycles
833system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1676878500 # number of LoadLockedReq MSHR miss cycles
834system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1676878500 # number of LoadLockedReq MSHR miss cycles
835system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4275603000 # number of StoreCondReq MSHR miss cycles
836system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4275603000 # number of StoreCondReq MSHR miss cycles
837system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1773000 # number of StoreCondFailReq MSHR miss cycles
838system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1773000 # number of StoreCondFailReq MSHR miss cycles
839system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 100338701000 # number of demand (read+write) MSHR miss cycles
840system.cpu0.dcache.demand_mshr_miss_latency::total 100338701000 # number of demand (read+write) MSHR miss cycles
841system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116197022000 # number of overall MSHR miss cycles
842system.cpu0.dcache.overall_mshr_miss_latency::total 116197022000 # number of overall MSHR miss cycles
843system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6038825000 # number of ReadReq MSHR uncacheable cycles
844system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6038825000 # number of ReadReq MSHR uncacheable cycles
845system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6038825000 # number of overall MSHR uncacheable cycles
846system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6038825000 # number of overall MSHR uncacheable cycles
847system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036483 # mshr miss rate for ReadReq accesses
848system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036483 # mshr miss rate for ReadReq accesses
849system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019074 # mshr miss rate for WriteReq accesses
850system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019074 # mshr miss rate for WriteReq accesses
851system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.711406 # mshr miss rate for SoftPFReq accesses
852system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.711406 # mshr miss rate for SoftPFReq accesses
853system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.826624 # mshr miss rate for WriteLineReq accesses
854system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.826624 # mshr miss rate for WriteLineReq accesses
855system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses
856system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses
857system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098311 # mshr miss rate for StoreCondReq accesses
858system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098311 # mshr miss rate for StoreCondReq accesses
859system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033369 # mshr miss rate for demand accesses
860system.cpu0.dcache.demand_mshr_miss_rate::total 0.033369 # mshr miss rate for demand accesses
861system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037347 # mshr miss rate for overall accesses
862system.cpu0.dcache.overall_mshr_miss_rate::total 0.037347 # mshr miss rate for overall accesses
863system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14472.757102 # average ReadReq mshr miss latency
864system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14472.757102 # average ReadReq mshr miss latency
865system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20707.142003 # average WriteReq mshr miss latency
866system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20707.142003 # average WriteReq mshr miss latency
867system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23641.612749 # average SoftPFReq mshr miss latency
868system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23641.612749 # average SoftPFReq mshr miss latency
869system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31364.699292 # average WriteLineReq mshr miss latency
870system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31364.699292 # average WriteLineReq mshr miss latency
871system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13614.341966 # average LoadLockedReq mshr miss latency
872system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13614.341966 # average LoadLockedReq mshr miss latency
873system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22859.175261 # average StoreCondReq mshr miss latency
874system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22859.175261 # average StoreCondReq mshr miss latency
875system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
876system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
877system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18819.559278 # average overall mshr miss latency
878system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18819.559278 # average overall mshr miss latency
879system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19358.433413 # average overall mshr miss latency
880system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19358.433413 # average overall mshr miss latency
881system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193477.668845 # average ReadReq mshr uncacheable latency
882system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193477.668845 # average ReadReq mshr uncacheable latency
883system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97452.272984 # average overall mshr uncacheable latency
884system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97452.272984 # average overall mshr uncacheable latency
885system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
886system.cpu0.icache.tags.replacements 9773833 # number of replacements
887system.cpu0.icache.tags.tagsinuse 511.928996 # Cycle average of tags in use
888system.cpu0.icache.tags.total_refs 234741496 # Total number of references to valid blocks.
889system.cpu0.icache.tags.sampled_refs 9774345 # Sample count of references to valid blocks.
890system.cpu0.icache.tags.avg_refs 24.016085 # Average number of references to valid blocks.
891system.cpu0.icache.tags.warmup_cycle 22886662000 # Cycle when the warmup percentage was hit.
892system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.928996 # Average occupied blocks per requestor
893system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999861 # Average percentage of cache occupancy
894system.cpu0.icache.tags.occ_percent::total 0.999861 # Average percentage of cache occupancy
895system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
896system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
897system.cpu0.icache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
898system.cpu0.icache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id
899system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
900system.cpu0.icache.tags.tag_accesses 498806059 # Number of tag accesses
901system.cpu0.icache.tags.data_accesses 498806059 # Number of data accesses
902system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
903system.cpu0.icache.ReadReq_hits::cpu0.inst 234741496 # number of ReadReq hits
904system.cpu0.icache.ReadReq_hits::total 234741496 # number of ReadReq hits
905system.cpu0.icache.demand_hits::cpu0.inst 234741496 # number of demand (read+write) hits
906system.cpu0.icache.demand_hits::total 234741496 # number of demand (read+write) hits
907system.cpu0.icache.overall_hits::cpu0.inst 234741496 # number of overall hits
908system.cpu0.icache.overall_hits::total 234741496 # number of overall hits
909system.cpu0.icache.ReadReq_misses::cpu0.inst 9774356 # number of ReadReq misses
910system.cpu0.icache.ReadReq_misses::total 9774356 # number of ReadReq misses
911system.cpu0.icache.demand_misses::cpu0.inst 9774356 # number of demand (read+write) misses
912system.cpu0.icache.demand_misses::total 9774356 # number of demand (read+write) misses
913system.cpu0.icache.overall_misses::cpu0.inst 9774356 # number of overall misses
914system.cpu0.icache.overall_misses::total 9774356 # number of overall misses
915system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99441985000 # number of ReadReq miss cycles
916system.cpu0.icache.ReadReq_miss_latency::total 99441985000 # number of ReadReq miss cycles
917system.cpu0.icache.demand_miss_latency::cpu0.inst 99441985000 # number of demand (read+write) miss cycles
918system.cpu0.icache.demand_miss_latency::total 99441985000 # number of demand (read+write) miss cycles
919system.cpu0.icache.overall_miss_latency::cpu0.inst 99441985000 # number of overall miss cycles
920system.cpu0.icache.overall_miss_latency::total 99441985000 # number of overall miss cycles
921system.cpu0.icache.ReadReq_accesses::cpu0.inst 244515852 # number of ReadReq accesses(hits+misses)
922system.cpu0.icache.ReadReq_accesses::total 244515852 # number of ReadReq accesses(hits+misses)
923system.cpu0.icache.demand_accesses::cpu0.inst 244515852 # number of demand (read+write) accesses
924system.cpu0.icache.demand_accesses::total 244515852 # number of demand (read+write) accesses
925system.cpu0.icache.overall_accesses::cpu0.inst 244515852 # number of overall (read+write) accesses
926system.cpu0.icache.overall_accesses::total 244515852 # number of overall (read+write) accesses
927system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039974 # miss rate for ReadReq accesses
928system.cpu0.icache.ReadReq_miss_rate::total 0.039974 # miss rate for ReadReq accesses
929system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039974 # miss rate for demand accesses
930system.cpu0.icache.demand_miss_rate::total 0.039974 # miss rate for demand accesses
931system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039974 # miss rate for overall accesses
932system.cpu0.icache.overall_miss_rate::total 0.039974 # miss rate for overall accesses
933system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10173.763366 # average ReadReq miss latency
934system.cpu0.icache.ReadReq_avg_miss_latency::total 10173.763366 # average ReadReq miss latency
935system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency
936system.cpu0.icache.demand_avg_miss_latency::total 10173.763366 # average overall miss latency
937system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10173.763366 # average overall miss latency
938system.cpu0.icache.overall_avg_miss_latency::total 10173.763366 # average overall miss latency
939system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
940system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
941system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
942system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
943system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
944system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
945system.cpu0.icache.writebacks::writebacks 9773833 # number of writebacks
946system.cpu0.icache.writebacks::total 9773833 # number of writebacks
947system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9774356 # number of ReadReq MSHR misses
948system.cpu0.icache.ReadReq_mshr_misses::total 9774356 # number of ReadReq MSHR misses
949system.cpu0.icache.demand_mshr_misses::cpu0.inst 9774356 # number of demand (read+write) MSHR misses
950system.cpu0.icache.demand_mshr_misses::total 9774356 # number of demand (read+write) MSHR misses
951system.cpu0.icache.overall_mshr_misses::cpu0.inst 9774356 # number of overall MSHR misses
952system.cpu0.icache.overall_mshr_misses::total 9774356 # number of overall MSHR misses
953system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable
954system.cpu0.icache.ReadReq_mshr_uncacheable::total 52284 # number of ReadReq MSHR uncacheable
955system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses
956system.cpu0.icache.overall_mshr_uncacheable_misses::total 52284 # number of overall MSHR uncacheable misses
957system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94554807500 # number of ReadReq MSHR miss cycles
958system.cpu0.icache.ReadReq_mshr_miss_latency::total 94554807500 # number of ReadReq MSHR miss cycles
959system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94554807500 # number of demand (read+write) MSHR miss cycles
960system.cpu0.icache.demand_mshr_miss_latency::total 94554807500 # number of demand (read+write) MSHR miss cycles
961system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94554807500 # number of overall MSHR miss cycles
962system.cpu0.icache.overall_mshr_miss_latency::total 94554807500 # number of overall MSHR miss cycles
963system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of ReadReq MSHR uncacheable cycles
964system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5161606000 # number of ReadReq MSHR uncacheable cycles
965system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5161606000 # number of overall MSHR uncacheable cycles
966system.cpu0.icache.overall_mshr_uncacheable_latency::total 5161606000 # number of overall MSHR uncacheable cycles
967system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for ReadReq accesses
968system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039974 # mshr miss rate for ReadReq accesses
969system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for demand accesses
970system.cpu0.icache.demand_mshr_miss_rate::total 0.039974 # mshr miss rate for demand accesses
971system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039974 # mshr miss rate for overall accesses
972system.cpu0.icache.overall_mshr_miss_rate::total 0.039974 # mshr miss rate for overall accesses
973system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average ReadReq mshr miss latency
974system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9673.763417 # average ReadReq mshr miss latency
975system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency
976system.cpu0.icache.demand_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency
977system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9673.763417 # average overall mshr miss latency
978system.cpu0.icache.overall_avg_mshr_miss_latency::total 9673.763417 # average overall mshr miss latency
979system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average ReadReq mshr uncacheable latency
980system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98722.477240 # average ReadReq mshr uncacheable latency
981system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98722.477240 # average overall mshr uncacheable latency
982system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98722.477240 # average overall mshr uncacheable latency
983system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
984system.cpu0.l2cache.prefetcher.num_hwpf_issued 7608993 # number of hwpf issued
985system.cpu0.l2cache.prefetcher.pfIdentified 7610336 # number of prefetch candidates identified
986system.cpu0.l2cache.prefetcher.pfBufferHit 1188 # number of redundant prefetches already in prefetch queue
987system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
988system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
989system.cpu0.l2cache.prefetcher.pfSpanPage 1005416 # number of prefetches not generated due to page crossing
990system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
991system.cpu0.l2cache.tags.replacements 2646552 # number of replacements
992system.cpu0.l2cache.tags.tagsinuse 15691.473570 # Cycle average of tags in use
993system.cpu0.l2cache.tags.total_refs 14028250 # Total number of references to valid blocks.
994system.cpu0.l2cache.tags.sampled_refs 2662377 # Sample count of references to valid blocks.
995system.cpu0.l2cache.tags.avg_refs 5.269070 # Average number of references to valid blocks.
996system.cpu0.l2cache.tags.warmup_cycle 5985886000 # Cycle when the warmup percentage was hit.
997system.cpu0.l2cache.tags.occ_blocks::writebacks 15348.189818 # Average occupied blocks per requestor
998system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.039011 # Average occupied blocks per requestor
999system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 8.868609 # Average occupied blocks per requestor
1000system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 302.376132 # Average occupied blocks per requestor
1001system.cpu0.l2cache.tags.occ_percent::writebacks 0.936779 # Average percentage of cache occupancy
1002system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001956 # Average percentage of cache occupancy
1003system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000541 # Average percentage of cache occupancy
1004system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.018456 # Average percentage of cache occupancy
1005system.cpu0.l2cache.tags.occ_percent::total 0.957732 # Average percentage of cache occupancy
1006system.cpu0.l2cache.tags.occ_task_id_blocks::1022 352 # Occupied blocks per task id
1007system.cpu0.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id
1008system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15410 # Occupied blocks per task id
1009system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id
1010system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
1011system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 65 # Occupied blocks per task id
1012system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 117 # Occupied blocks per task id
1013system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 37 # Occupied blocks per task id
1014system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
1015system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id
1016system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
1017system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1727 # Occupied blocks per task id
1018system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6563 # Occupied blocks per task id
1019system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id
1020system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2911 # Occupied blocks per task id
1021system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021484 # Percentage of cache occupancy per task id
1022system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
1023system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.940552 # Percentage of cache occupancy per task id
1024system.cpu0.l2cache.tags.tag_accesses 534452534 # Number of tag accesses
1025system.cpu0.l2cache.tags.data_accesses 534452534 # Number of data accesses
1026system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1027system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 527649 # number of ReadReq hits
1028system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180298 # number of ReadReq hits
1029system.cpu0.l2cache.ReadReq_hits::total 707947 # number of ReadReq hits
1030system.cpu0.l2cache.WritebackDirty_hits::writebacks 3832122 # number of WritebackDirty hits
1031system.cpu0.l2cache.WritebackDirty_hits::total 3832122 # number of WritebackDirty hits
1032system.cpu0.l2cache.WritebackClean_hits::writebacks 11726658 # number of WritebackClean hits
1033system.cpu0.l2cache.WritebackClean_hits::total 11726658 # number of WritebackClean hits
1034system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits
1035system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
1036system.cpu0.l2cache.ReadExReq_hits::cpu0.data 904488 # number of ReadExReq hits
1037system.cpu0.l2cache.ReadExReq_hits::total 904488 # number of ReadExReq hits
1038system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9076171 # number of ReadCleanReq hits
1039system.cpu0.l2cache.ReadCleanReq_hits::total 9076171 # number of ReadCleanReq hits
1040system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2875219 # number of ReadSharedReq hits
1041system.cpu0.l2cache.ReadSharedReq_hits::total 2875219 # number of ReadSharedReq hits
1042system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 241369 # number of InvalidateReq hits
1043system.cpu0.l2cache.InvalidateReq_hits::total 241369 # number of InvalidateReq hits
1044system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 527649 # number of demand (read+write) hits
1045system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180298 # number of demand (read+write) hits
1046system.cpu0.l2cache.demand_hits::cpu0.inst 9076171 # number of demand (read+write) hits
1047system.cpu0.l2cache.demand_hits::cpu0.data 3779707 # number of demand (read+write) hits
1048system.cpu0.l2cache.demand_hits::total 13563825 # number of demand (read+write) hits
1049system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 527649 # number of overall hits
1050system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180298 # number of overall hits
1051system.cpu0.l2cache.overall_hits::cpu0.inst 9076171 # number of overall hits
1052system.cpu0.l2cache.overall_hits::cpu0.data 3779707 # number of overall hits
1053system.cpu0.l2cache.overall_hits::total 13563825 # number of overall hits
1054system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21665 # number of ReadReq misses
1055system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10120 # number of ReadReq misses
1056system.cpu0.l2cache.ReadReq_misses::total 31785 # number of ReadReq misses
1057system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246294 # number of UpgradeReq misses
1058system.cpu0.l2cache.UpgradeReq_misses::total 246294 # number of UpgradeReq misses
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1070system.cpu0.l2cache.InvalidateReq_misses::total 601118 # number of InvalidateReq misses
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1089system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1705497 # number of SCUpgradeFailReq miss cycles
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1095system.cpu0.l2cache.ReadSharedReq_miss_latency::total 37051733995 # number of ReadSharedReq miss cycles
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1097system.cpu0.l2cache.InvalidateReq_miss_latency::total 336301500 # number of InvalidateReq miss cycles
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1110system.cpu0.l2cache.ReadReq_accesses::total 739732 # number of ReadReq accesses(hits+misses)
1111system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3832122 # number of WritebackDirty accesses(hits+misses)
1112system.cpu0.l2cache.WritebackDirty_accesses::total 3832122 # number of WritebackDirty accesses(hits+misses)
1113system.cpu0.l2cache.WritebackClean_accesses::writebacks 11726658 # number of WritebackClean accesses(hits+misses)
1114system.cpu0.l2cache.WritebackClean_accesses::total 11726658 # number of WritebackClean accesses(hits+misses)
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1116system.cpu0.l2cache.UpgradeReq_accesses::total 246295 # number of UpgradeReq accesses(hits+misses)
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1120system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
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1122system.cpu0.l2cache.ReadExReq_accesses::total 1191277 # number of ReadExReq accesses(hits+misses)
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1124system.cpu0.l2cache.ReadCleanReq_accesses::total 9774355 # number of ReadCleanReq accesses(hits+misses)
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1126system.cpu0.l2cache.ReadSharedReq_accesses::total 3851394 # number of ReadSharedReq accesses(hits+misses)
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1128system.cpu0.l2cache.InvalidateReq_accesses::total 842487 # number of InvalidateReq accesses(hits+misses)
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1135system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 190418 # number of overall (read+write) accesses
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1140system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.053146 # miss rate for ReadReq accesses
1141system.cpu0.l2cache.ReadReq_miss_rate::total 0.042968 # miss rate for ReadReq accesses
1142system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999996 # miss rate for UpgradeReq accesses
1143system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999996 # miss rate for UpgradeReq accesses
1144system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1145system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1146system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1147system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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1149system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240741 # miss rate for ReadExReq accesses
1150system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071430 # miss rate for ReadCleanReq accesses
1151system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071430 # miss rate for ReadCleanReq accesses
1152system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.253460 # miss rate for ReadSharedReq accesses
1153system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.253460 # miss rate for ReadSharedReq accesses
1154system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.713504 # miss rate for InvalidateReq accesses
1155system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.713504 # miss rate for InvalidateReq accesses
1156system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for demand accesses
1157system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.053146 # miss rate for demand accesses
1158system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071430 # miss rate for demand accesses
1159system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250455 # miss rate for demand accesses
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1161system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039440 # miss rate for overall accesses
1162system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.053146 # miss rate for overall accesses
1163system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071430 # miss rate for overall accesses
1164system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250455 # miss rate for overall accesses
1165system.cpu0.l2cache.overall_miss_rate::total 0.128107 # miss rate for overall accesses
1166system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average ReadReq miss latency
1167system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39943.181818 # average ReadReq miss latency
1168system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34625.939909 # average ReadReq miss latency
1169system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3698.541174 # average UpgradeReq miss latency
1170system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3698.541174 # average UpgradeReq miss latency
1171system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1546.731645 # average SCUpgradeReq miss latency
1172system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1546.731645 # average SCUpgradeReq miss latency
1173system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 341099.400000 # average SCUpgradeFailReq miss latency
1174system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 341099.400000 # average SCUpgradeFailReq miss latency
1175system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53797.767690 # average ReadExReq miss latency
1176system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53797.767690 # average ReadExReq miss latency
1177system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35892.103657 # average ReadCleanReq miss latency
1178system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35892.103657 # average ReadCleanReq miss latency
1179system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37956.036566 # average ReadSharedReq miss latency
1180system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37956.036566 # average ReadSharedReq miss latency
1181system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 559.460039 # average InvalidateReq miss latency
1182system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 559.460039 # average InvalidateReq miss latency
1183system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency
1184system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency
1185system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency
1186system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency
1187system.cpu0.l2cache.demand_avg_miss_latency::total 39459.540282 # average overall miss latency
1188system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32142.187861 # average overall miss latency
1189system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39943.181818 # average overall miss latency
1190system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35892.103657 # average overall miss latency
1191system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41553.315845 # average overall miss latency
1192system.cpu0.l2cache.overall_avg_miss_latency::total 39459.540282 # average overall miss latency
1193system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1194system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1195system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1196system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1197system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1198system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1199system.cpu0.l2cache.unused_prefetches 45829 # number of HardPF blocks evicted w/o reference
1200system.cpu0.l2cache.writebacks::writebacks 1629804 # number of writebacks
1201system.cpu0.l2cache.writebacks::total 1629804 # number of writebacks
1202system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 24 # number of ReadReq MSHR hits
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1206system.cpu0.l2cache.ReadExReq_mshr_hits::total 8277 # number of ReadExReq MSHR hits
1207system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 12 # number of ReadCleanReq MSHR hits
1208system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits
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1210system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 866 # number of ReadSharedReq MSHR hits
1211system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
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1215system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 12 # number of demand (read+write) MSHR hits
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1220system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 12 # number of overall MSHR hits
1221system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9143 # number of overall MSHR hits
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1223system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21641 # number of ReadReq MSHR misses
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1225system.cpu0.l2cache.ReadReq_mshr_misses::total 31663 # number of ReadReq MSHR misses
1226system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 782860 # number of HardPFReq MSHR misses
1227system.cpu0.l2cache.HardPFReq_mshr_misses::total 782860 # number of HardPFReq MSHR misses
1228system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246294 # number of UpgradeReq MSHR misses
1229system.cpu0.l2cache.UpgradeReq_mshr_misses::total 246294 # number of UpgradeReq MSHR misses
1230system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187036 # number of SCUpgradeReq MSHR misses
1231system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187036 # number of SCUpgradeReq MSHR misses
1232system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1233system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
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1235system.cpu0.l2cache.ReadExReq_mshr_misses::total 278512 # number of ReadExReq MSHR misses
1236system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 698172 # number of ReadCleanReq MSHR misses
1237system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 698172 # number of ReadCleanReq MSHR misses
1238system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 975309 # number of ReadSharedReq MSHR misses
1239system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 975309 # number of ReadSharedReq MSHR misses
1240system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 601115 # number of InvalidateReq MSHR misses
1241system.cpu0.l2cache.InvalidateReq_mshr_misses::total 601115 # number of InvalidateReq MSHR misses
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1244system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 698172 # number of demand (read+write) MSHR misses
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1248system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10022 # number of overall MSHR misses
1249system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 698172 # number of overall MSHR misses
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1252system.cpu0.l2cache.overall_mshr_misses::total 2766516 # number of overall MSHR misses
1253system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable
1254system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable
1255system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83496 # number of ReadReq MSHR uncacheable
1256system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable
1257system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30755 # number of WriteReq MSHR uncacheable
1258system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses
1259system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses
1260system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114251 # number of overall MSHR uncacheable misses
1261system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of ReadReq MSHR miss cycles
1262system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 342540500 # number of ReadReq MSHR miss cycles
1263system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 908484500 # number of ReadReq MSHR miss cycles
1264system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of HardPFReq MSHR miss cycles
1265system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36299233693 # number of HardPFReq MSHR miss cycles
1266system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4539562995 # number of UpgradeReq MSHR miss cycles
1267system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4539562995 # number of UpgradeReq MSHR miss cycles
1268system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2868254998 # number of SCUpgradeReq MSHR miss cycles
1269system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2868254998 # number of SCUpgradeReq MSHR miss cycles
1270system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1441497 # number of SCUpgradeFailReq MSHR miss cycles
1271system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1441497 # number of SCUpgradeFailReq MSHR miss cycles
1272system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12630779498 # number of ReadExReq MSHR miss cycles
1273system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12630779498 # number of ReadExReq MSHR miss cycles
1274system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20869901000 # number of ReadCleanReq MSHR miss cycles
1275system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20869901000 # number of ReadCleanReq MSHR miss cycles
1276system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 31074032995 # number of ReadSharedReq MSHR miss cycles
1277system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 31074032995 # number of ReadSharedReq MSHR miss cycles
1278system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 19885865000 # number of InvalidateReq MSHR miss cycles
1279system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 19885865000 # number of InvalidateReq MSHR miss cycles
1280system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of demand (read+write) MSHR miss cycles
1281system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 342540500 # number of demand (read+write) MSHR miss cycles
1282system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20869901000 # number of demand (read+write) MSHR miss cycles
1283system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43704812493 # number of demand (read+write) MSHR miss cycles
1284system.cpu0.l2cache.demand_mshr_miss_latency::total 65483197993 # number of demand (read+write) MSHR miss cycles
1285system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 565944000 # number of overall MSHR miss cycles
1286system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 342540500 # number of overall MSHR miss cycles
1287system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20869901000 # number of overall MSHR miss cycles
1288system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43704812493 # number of overall MSHR miss cycles
1289system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36299233693 # number of overall MSHR miss cycles
1290system.cpu0.l2cache.overall_mshr_miss_latency::total 101782431686 # number of overall MSHR miss cycles
1291system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of ReadReq MSHR uncacheable cycles
1292system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788958500 # number of ReadReq MSHR uncacheable cycles
1293system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10532292500 # number of ReadReq MSHR uncacheable cycles
1294system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4743334000 # number of overall MSHR uncacheable cycles
1295system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788958500 # number of overall MSHR uncacheable cycles
1296system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10532292500 # number of overall MSHR uncacheable cycles
1297system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for ReadReq accesses
1298system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for ReadReq accesses
1299system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042803 # mshr miss rate for ReadReq accesses
1300system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1301system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1302system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999996 # mshr miss rate for UpgradeReq accesses
1303system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999996 # mshr miss rate for UpgradeReq accesses
1304system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1305system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1306system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1307system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1308system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.233793 # mshr miss rate for ReadExReq accesses
1309system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.233793 # mshr miss rate for ReadExReq accesses
1310system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for ReadCleanReq accesses
1311system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071429 # mshr miss rate for ReadCleanReq accesses
1312system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.253235 # mshr miss rate for ReadSharedReq accesses
1313system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253235 # mshr miss rate for ReadSharedReq accesses
1314system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.713501 # mshr miss rate for InvalidateReq accesses
1315system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.713501 # mshr miss rate for InvalidateReq accesses
1316system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for demand accesses
1317system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for demand accesses
1318system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for demand accesses
1319system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for demand accesses
1320system.cpu0.l2cache.demand_mshr_miss_rate::total 0.127511 # mshr miss rate for demand accesses
1321system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039396 # mshr miss rate for overall accesses
1322system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052632 # mshr miss rate for overall accesses
1323system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071429 # mshr miss rate for overall accesses
1324system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248642 # mshr miss rate for overall accesses
1325system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1326system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177834 # mshr miss rate for overall accesses
1327system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average ReadReq mshr miss latency
1328system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average ReadReq mshr miss latency
1329system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28692.306478 # average ReadReq mshr miss latency
1330system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average HardPFReq mshr miss latency
1331system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46367.465055 # average HardPFReq mshr miss latency
1332system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18431.480243 # average UpgradeReq mshr miss latency
1333system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18431.480243 # average UpgradeReq mshr miss latency
1334system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15335.309769 # average SCUpgradeReq mshr miss latency
1335system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15335.309769 # average SCUpgradeReq mshr miss latency
1336system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 288299.400000 # average SCUpgradeFailReq mshr miss latency
1337system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 288299.400000 # average SCUpgradeFailReq mshr miss latency
1338system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45350.934602 # average ReadExReq mshr miss latency
1339system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45350.934602 # average ReadExReq mshr miss latency
1340system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average ReadCleanReq mshr miss latency
1341system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29892.205646 # average ReadCleanReq mshr miss latency
1342system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31860.705679 # average ReadSharedReq mshr miss latency
1343system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31860.705679 # average ReadSharedReq mshr miss latency
1344system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33081.631635 # average InvalidateReq mshr miss latency
1345system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33081.631635 # average InvalidateReq mshr miss latency
1346system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency
1347system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency
1348system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency
1349system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency
1350system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33011.367895 # average overall mshr miss latency
1351system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26151.471743 # average overall mshr miss latency
1352system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34178.856516 # average overall mshr miss latency
1353system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29892.205646 # average overall mshr miss latency
1354system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34857.298205 # average overall mshr miss latency
1355system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46367.465055 # average overall mshr miss latency
1356system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36790.834279 # average overall mshr miss latency
1357system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average ReadReq mshr uncacheable latency
1358system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185472.206203 # average ReadReq mshr uncacheable latency
1359system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126141.282217 # average ReadReq mshr uncacheable latency
1360system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90722.477240 # average overall mshr uncacheable latency
1361system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93420.021947 # average overall mshr uncacheable latency
1362system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 92185.560739 # average overall mshr uncacheable latency
1363system.cpu0.toL2Bus.snoop_filter.tot_requests 31945858 # Total number of requests made to the snoop filter.
1364system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16286466 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1365system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2971 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1366system.cpu0.toL2Bus.snoop_filter.tot_snoops 662323 # Total number of snoops made to the snoop filter.
1367system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 662303 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1368system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 20 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1369system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1370system.cpu0.toL2Bus.trans_dist::ReadReq 897088 # Transaction distribution
1371system.cpu0.toL2Bus.trans_dist::ReadResp 14618500 # Transaction distribution
1372system.cpu0.toL2Bus.trans_dist::WriteReq 30756 # Transaction distribution
1373system.cpu0.toL2Bus.trans_dist::WriteResp 30755 # Transaction distribution
1374system.cpu0.toL2Bus.trans_dist::WritebackDirty 5466694 # Transaction distribution
1375system.cpu0.toL2Bus.trans_dist::WritebackClean 11729628 # Transaction distribution
1376system.cpu0.toL2Bus.trans_dist::CleanEvict 1381452 # Transaction distribution
1377system.cpu0.toL2Bus.trans_dist::HardPFReq 1000780 # Transaction distribution
1378system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
1379system.cpu0.toL2Bus.trans_dist::UpgradeReq 445154 # Transaction distribution
1380system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338634 # Transaction distribution
1381system.cpu0.toL2Bus.trans_dist::UpgradeResp 499902 # Transaction distribution
1382system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
1383system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution
1384system.cpu0.toL2Bus.trans_dist::ReadExReq 1222912 # Transaction distribution
1385system.cpu0.toL2Bus.trans_dist::ReadExResp 1199223 # Transaction distribution
1386system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9774356 # Transaction distribution
1387system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4899750 # Transaction distribution
1388system.cpu0.toL2Bus.trans_dist::InvalidateReq 895142 # Transaction distribution
1389system.cpu0.toL2Bus.trans_dist::InvalidateResp 842487 # Transaction distribution
1390system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29427111 # Packet count per connected master and slave (bytes)
1391system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18719100 # Packet count per connected master and slave (bytes)
1392system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 397503 # Packet count per connected master and slave (bytes)
1393system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1155819 # Packet count per connected master and slave (bytes)
1394system.cpu0.toL2Bus.pkt_count::total 49699533 # Packet count per connected master and slave (bytes)
1395system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1254430144 # Cumulative packet size per connected master and slave (bytes)
1396system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 699985190 # Cumulative packet size per connected master and slave (bytes)
1397system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1523344 # Cumulative packet size per connected master and slave (bytes)
1398system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4394512 # Cumulative packet size per connected master and slave (bytes)
1399system.cpu0.toL2Bus.pkt_size::total 1960333190 # Cumulative packet size per connected master and slave (bytes)
1400system.cpu0.toL2Bus.snoops 5744069 # Total snoops (count)
1401system.cpu0.toL2Bus.snoopTraffic 111836388 # Total snoop traffic (bytes)
1402system.cpu0.toL2Bus.snoop_fanout::samples 22520641 # Request fanout histogram
1403system.cpu0.toL2Bus.snoop_fanout::mean 0.042476 # Request fanout histogram
1404system.cpu0.toL2Bus.snoop_fanout::stdev 0.201677 # Request fanout histogram
1405system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1406system.cpu0.toL2Bus.snoop_fanout::0 21564077 95.75% 95.75% # Request fanout histogram
1407system.cpu0.toL2Bus.snoop_fanout::1 956544 4.25% 100.00% # Request fanout histogram
1408system.cpu0.toL2Bus.snoop_fanout::2 20 0.00% 100.00% # Request fanout histogram
1409system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1410system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1411system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1412system.cpu0.toL2Bus.snoop_fanout::total 22520641 # Request fanout histogram
1413system.cpu0.toL2Bus.reqLayer0.occupancy 31868357980 # Layer occupancy (ticks)
1414system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1415system.cpu0.toL2Bus.snoopLayer0.occupancy 188944290 # Layer occupancy (ticks)
1416system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1417system.cpu0.toL2Bus.respLayer0.occupancy 14742648604 # Layer occupancy (ticks)
1418system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1419system.cpu0.toL2Bus.respLayer1.occupancy 8252120363 # Layer occupancy (ticks)
1420system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1421system.cpu0.toL2Bus.respLayer2.occupancy 207185798 # Layer occupancy (ticks)
1422system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1423system.cpu0.toL2Bus.respLayer3.occupancy 606624760 # Layer occupancy (ticks)
1424system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1425system.cpu1.branchPred.lookups 130393488 # Number of BP lookups
1426system.cpu1.branchPred.condPredicted 92735412 # Number of conditional branches predicted
1427system.cpu1.branchPred.condIncorrect 5902942 # Number of conditional branches incorrect
1428system.cpu1.branchPred.BTBLookups 97710710 # Number of BTB lookups
1429system.cpu1.branchPred.BTBHits 68499677 # Number of BTB hits
1430system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1431system.cpu1.branchPred.BTBHitPct 70.104574 # BTB Hit Percentage
1432system.cpu1.branchPred.usedRAS 15029088 # Number of times the RAS was used to get a target.
1433system.cpu1.branchPred.RASInCorrect 982146 # Number of incorrect RAS predictions.
1434system.cpu1.branchPred.indirectLookups 3431599 # Number of indirect predictor lookups.
1435system.cpu1.branchPred.indirectHits 2322480 # Number of indirect target hits.
1436system.cpu1.branchPred.indirectMisses 1109119 # Number of indirect misses.
1437system.cpu1.branchPredindirectMispredicted 398100 # Number of mispredicted indirect branches.
1438system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1439system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1440system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1441system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1442system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1443system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1444system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1445system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1446system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1460system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1461system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1462system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1463system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1464system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1465system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1466system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1467system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1468system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1469system.cpu1.dtb.walker.walks 266586 # Table walker walks requested
1470system.cpu1.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors
1471system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9178 # Level at which table walker walks with long descriptors terminate
1472system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75276 # Level at which table walker walks with long descriptors terminate
1473system.cpu1.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency
1474system.cpu1.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1475system.cpu1.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency
1476system.cpu1.dtb.walker.walkCompletionTime::samples 84454 # Table walker service (enqueue to completion) latency
1477system.cpu1.dtb.walker.walkCompletionTime::mean 23652.319606 # Table walker service (enqueue to completion) latency
1478system.cpu1.dtb.walker.walkCompletionTime::gmean 21901.867132 # Table walker service (enqueue to completion) latency
1479system.cpu1.dtb.walker.walkCompletionTime::stdev 15135.594089 # Table walker service (enqueue to completion) latency
1480system.cpu1.dtb.walker.walkCompletionTime::0-65535 83574 98.96% 98.96% # Table walker service (enqueue to completion) latency
1481system.cpu1.dtb.walker.walkCompletionTime::65536-131071 653 0.77% 99.73% # Table walker service (enqueue to completion) latency
1482system.cpu1.dtb.walker.walkCompletionTime::131072-196607 133 0.16% 99.89% # Table walker service (enqueue to completion) latency
1483system.cpu1.dtb.walker.walkCompletionTime::196608-262143 39 0.05% 99.93% # Table walker service (enqueue to completion) latency
1484system.cpu1.dtb.walker.walkCompletionTime::262144-327679 30 0.04% 99.97% # Table walker service (enqueue to completion) latency
1485system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
1486system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
1487system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1488system.cpu1.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
1489system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1490system.cpu1.dtb.walker.walkCompletionTime::total 84454 # Table walker service (enqueue to completion) latency
1491system.cpu1.dtb.walker.walksPending::samples 112342944 # Table walker pending requests distribution
1492system.cpu1.dtb.walker.walksPending::0 112342944 100.00% 100.00% # Table walker pending requests distribution
1493system.cpu1.dtb.walker.walksPending::total 112342944 # Table walker pending requests distribution
1494system.cpu1.dtb.walker.walkPageSizes::4K 75276 89.13% 89.13% # Table walker page sizes translated
1495system.cpu1.dtb.walker.walkPageSizes::2M 9178 10.87% 100.00% # Table walker page sizes translated
1496system.cpu1.dtb.walker.walkPageSizes::total 84454 # Table walker page sizes translated
1497system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst
1498system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1499system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst
1500system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84454 # Table walker requests started/completed, data/inst
1501system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1502system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84454 # Table walker requests started/completed, data/inst
1503system.cpu1.dtb.walker.walkRequestOrigin::total 351040 # Table walker requests started/completed, data/inst
1504system.cpu1.dtb.inst_hits 0 # ITB inst hits
1505system.cpu1.dtb.inst_misses 0 # ITB inst misses
1506system.cpu1.dtb.read_hits 83602508 # DTB read hits
1507system.cpu1.dtb.read_misses 221634 # DTB read misses
1508system.cpu1.dtb.write_hits 72407946 # DTB write hits
1509system.cpu1.dtb.write_misses 44952 # DTB write misses
1510system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1511system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1512system.cpu1.dtb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID
1513system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1514system.cpu1.dtb.flush_entries 35586 # Number of entries that have been flushed from TLB
1515system.cpu1.dtb.align_faults 1113 # Number of TLB faults due to alignment restrictions
1516system.cpu1.dtb.prefetch_faults 7045 # Number of TLB faults due to prefetch
1517system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1518system.cpu1.dtb.perms_faults 10293 # Number of TLB faults due to permissions restrictions
1519system.cpu1.dtb.read_accesses 83824142 # DTB read accesses
1520system.cpu1.dtb.write_accesses 72452898 # DTB write accesses
1521system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1522system.cpu1.dtb.hits 156010454 # DTB hits
1523system.cpu1.dtb.misses 266586 # DTB misses
1524system.cpu1.dtb.accesses 156277040 # DTB accesses
1525system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1526system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1527system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1528system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1529system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1530system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1531system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1532system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1533system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1547system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1548system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1549system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1550system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1551system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1552system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1553system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1554system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1555system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1556system.cpu1.itb.walker.walks 60007 # Table walker walks requested
1557system.cpu1.itb.walker.walksLong 60007 # Table walker walks initiated with long descriptors
1558system.cpu1.itb.walker.walksLongTerminationLevel::Level2 568 # Level at which table walker walks with long descriptors terminate
1559system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49765 # Level at which table walker walks with long descriptors terminate
1560system.cpu1.itb.walker.walkWaitTime::samples 60007 # Table walker wait (enqueue to first request) latency
1561system.cpu1.itb.walker.walkWaitTime::0 60007 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1562system.cpu1.itb.walker.walkWaitTime::total 60007 # Table walker wait (enqueue to first request) latency
1563system.cpu1.itb.walker.walkCompletionTime::samples 50333 # Table walker service (enqueue to completion) latency
1564system.cpu1.itb.walker.walkCompletionTime::mean 25530.089603 # Table walker service (enqueue to completion) latency
1565system.cpu1.itb.walker.walkCompletionTime::gmean 23478.456634 # Table walker service (enqueue to completion) latency
1566system.cpu1.itb.walker.walkCompletionTime::stdev 19036.287161 # Table walker service (enqueue to completion) latency
1567system.cpu1.itb.walker.walkCompletionTime::0-65535 49435 98.22% 98.22% # Table walker service (enqueue to completion) latency
1568system.cpu1.itb.walker.walkCompletionTime::65536-131071 638 1.27% 99.48% # Table walker service (enqueue to completion) latency
1569system.cpu1.itb.walker.walkCompletionTime::131072-196607 189 0.38% 99.86% # Table walker service (enqueue to completion) latency
1570system.cpu1.itb.walker.walkCompletionTime::196608-262143 38 0.08% 99.93% # Table walker service (enqueue to completion) latency
1571system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.02% 99.95% # Table walker service (enqueue to completion) latency
1572system.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
1573system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
1574system.cpu1.itb.walker.walkCompletionTime::589824-655359 14 0.03% 100.00% # Table walker service (enqueue to completion) latency
1575system.cpu1.itb.walker.walkCompletionTime::total 50333 # Table walker service (enqueue to completion) latency
1576system.cpu1.itb.walker.walksPending::samples 111619444 # Table walker pending requests distribution
1577system.cpu1.itb.walker.walksPending::0 111619444 100.00% 100.00% # Table walker pending requests distribution
1578system.cpu1.itb.walker.walksPending::total 111619444 # Table walker pending requests distribution
1579system.cpu1.itb.walker.walkPageSizes::4K 49765 98.87% 98.87% # Table walker page sizes translated
1580system.cpu1.itb.walker.walkPageSizes::2M 568 1.13% 100.00% # Table walker page sizes translated
1581system.cpu1.itb.walker.walkPageSizes::total 50333 # Table walker page sizes translated
1582system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1583system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60007 # Table walker requests started/completed, data/inst
1584system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60007 # Table walker requests started/completed, data/inst
1585system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1586system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 50333 # Table walker requests started/completed, data/inst
1587system.cpu1.itb.walker.walkRequestOrigin_Completed::total 50333 # Table walker requests started/completed, data/inst
1588system.cpu1.itb.walker.walkRequestOrigin::total 110340 # Table walker requests started/completed, data/inst
1589system.cpu1.itb.inst_hits 231314016 # ITB inst hits
1590system.cpu1.itb.inst_misses 60007 # ITB inst misses
1591system.cpu1.itb.read_hits 0 # DTB read hits
1592system.cpu1.itb.read_misses 0 # DTB read misses
1593system.cpu1.itb.write_hits 0 # DTB write hits
1594system.cpu1.itb.write_misses 0 # DTB write misses
1595system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1596system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1597system.cpu1.itb.flush_tlb_mva_asid 40666 # Number of times TLB was flushed by MVA & ASID
1598system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID
1599system.cpu1.itb.flush_entries 25531 # Number of entries that have been flushed from TLB
1600system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1601system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1602system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1603system.cpu1.itb.perms_faults 167507 # Number of TLB faults due to permissions restrictions
1604system.cpu1.itb.read_accesses 0 # DTB read accesses
1605system.cpu1.itb.write_accesses 0 # DTB write accesses
1606system.cpu1.itb.inst_accesses 231374023 # ITB inst accesses
1607system.cpu1.itb.hits 231314016 # DTB hits
1608system.cpu1.itb.misses 60007 # DTB misses
1609system.cpu1.itb.accesses 231374023 # DTB accesses
1610system.cpu1.numPwrStateTransitions 9626 # Number of power state transitions
1611system.cpu1.pwrStateClkGateDist::samples 4813 # Distribution of time spent in the clock gated state
1612system.cpu1.pwrStateClkGateDist::mean 9788374174.243299 # Distribution of time spent in the clock gated state
1613system.cpu1.pwrStateClkGateDist::stdev 115006828751.685410 # Distribution of time spent in the clock gated state
1614system.cpu1.pwrStateClkGateDist::underflows 3303 68.63% 68.63% # Distribution of time spent in the clock gated state
1615system.cpu1.pwrStateClkGateDist::1000-5e+10 1483 30.81% 99.44% # Distribution of time spent in the clock gated state
1616system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.46% # Distribution of time spent in the clock gated state
1617system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.48% # Distribution of time spent in the clock gated state
1618system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.08% 99.56% # Distribution of time spent in the clock gated state
1619system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.58% # Distribution of time spent in the clock gated state
1620system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state
1621system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state
1622system.cpu1.pwrStateClkGateDist::overflows 18 0.37% 100.00% # Distribution of time spent in the clock gated state
1623system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1624system.cpu1.pwrStateClkGateDist::max_value 1988779353616 # Distribution of time spent in the clock gated state
1625system.cpu1.pwrStateClkGateDist::total 4813 # Distribution of time spent in the clock gated state
1626system.cpu1.pwrStateResidencyTicks::ON 443465373367 # Cumulative time (in ticks) in various power states
1627system.cpu1.pwrStateResidencyTicks::CLK_GATED 47111444900633 # Cumulative time (in ticks) in various power states
1628system.cpu1.numCycles 886937326 # number of cpu cycles simulated
1629system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1630system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1631system.cpu1.committedInsts 425165575 # Number of instructions committed
1632system.cpu1.committedOps 499981941 # Number of ops (including micro ops) committed
1633system.cpu1.discardedOps 45360018 # Number of ops (including micro ops) which were discarded before commit
1634system.cpu1.numFetchSuspends 4813 # Number of times Execute suspended instruction fetching
1635system.cpu1.quiesceCycles 94223530921 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1636system.cpu1.cpi 2.086099 # CPI: cycles per instruction
1637system.cpu1.ipc 0.479364 # IPC: instructions per cycle
1638system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1639system.cpu1.op_class_0::IntAlu 346104827 69.22% 69.22% # Class of committed instruction
1640system.cpu1.op_class_0::IntMult 1095440 0.22% 69.44% # Class of committed instruction
1641system.cpu1.op_class_0::IntDiv 59698 0.01% 69.45% # Class of committed instruction
1642system.cpu1.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
1643system.cpu1.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
1644system.cpu1.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
1645system.cpu1.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
1646system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.45% # Class of committed instruction
1647system.cpu1.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
1648system.cpu1.op_class_0::FloatMisc 26657 0.01% 69.46% # Class of committed instruction
1649system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction
1650system.cpu1.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction
1651system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction
1652system.cpu1.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction
1653system.cpu1.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction
1654system.cpu1.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction
1655system.cpu1.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction
1656system.cpu1.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction
1657system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction
1658system.cpu1.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction
1659system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction
1660system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction
1661system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction
1662system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction
1663system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction
1664system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction
1665system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction
1666system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 69.46% # Class of committed instruction
1667system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
1668system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
1669system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
1670system.cpu1.op_class_0::MemRead 80537576 16.11% 85.57% # Class of committed instruction
1671system.cpu1.op_class_0::MemWrite 71850356 14.37% 99.94% # Class of committed instruction
1672system.cpu1.op_class_0::FloatMemRead 41546 0.01% 99.95% # Class of committed instruction
1673system.cpu1.op_class_0::FloatMemWrite 265841 0.05% 100.00% # Class of committed instruction
1674system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1675system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1676system.cpu1.op_class_0::total 499981941 # Class of committed instruction
1677system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1678system.cpu1.kern.inst.quiesce 4813 # number of quiesce instructions executed
1679system.cpu1.tickCycles 688160387 # Number of cycles that the object actually ticked
1680system.cpu1.idleCycles 198776939 # Total number of cycles that the object has spent stopped
1681system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1682system.cpu1.dcache.tags.replacements 4915770 # number of replacements
1683system.cpu1.dcache.tags.tagsinuse 461.565771 # Cycle average of tags in use
1684system.cpu1.dcache.tags.total_refs 148821179 # Total number of references to valid blocks.
1685system.cpu1.dcache.tags.sampled_refs 4916282 # Sample count of references to valid blocks.
1686system.cpu1.dcache.tags.avg_refs 30.271083 # Average number of references to valid blocks.
1687system.cpu1.dcache.tags.warmup_cycle 8378532705500 # Cycle when the warmup percentage was hit.
1688system.cpu1.dcache.tags.occ_blocks::cpu1.data 461.565771 # Average occupied blocks per requestor
1689system.cpu1.dcache.tags.occ_percent::cpu1.data 0.901496 # Average percentage of cache occupancy
1690system.cpu1.dcache.tags.occ_percent::total 0.901496 # Average percentage of cache occupancy
1691system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1692system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
1693system.cpu1.dcache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
1694system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
1695system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1696system.cpu1.dcache.tags.tag_accesses 314637839 # Number of tag accesses
1697system.cpu1.dcache.tags.data_accesses 314637839 # Number of data accesses
1698system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1699system.cpu1.dcache.ReadReq_hits::cpu1.data 76998524 # number of ReadReq hits
1700system.cpu1.dcache.ReadReq_hits::total 76998524 # number of ReadReq hits
1701system.cpu1.dcache.WriteReq_hits::cpu1.data 67544283 # number of WriteReq hits
1702system.cpu1.dcache.WriteReq_hits::total 67544283 # number of WriteReq hits
1703system.cpu1.dcache.SoftPFReq_hits::cpu1.data 228025 # number of SoftPFReq hits
1704system.cpu1.dcache.SoftPFReq_hits::total 228025 # number of SoftPFReq hits
1705system.cpu1.dcache.WriteLineReq_hits::cpu1.data 143759 # number of WriteLineReq hits
1706system.cpu1.dcache.WriteLineReq_hits::total 143759 # number of WriteLineReq hits
1707system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733263 # number of LoadLockedReq hits
1708system.cpu1.dcache.LoadLockedReq_hits::total 1733263 # number of LoadLockedReq hits
1709system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1698082 # number of StoreCondReq hits
1710system.cpu1.dcache.StoreCondReq_hits::total 1698082 # number of StoreCondReq hits
1711system.cpu1.dcache.demand_hits::cpu1.data 144686566 # number of demand (read+write) hits
1712system.cpu1.dcache.demand_hits::total 144686566 # number of demand (read+write) hits
1713system.cpu1.dcache.overall_hits::cpu1.data 144914591 # number of overall hits
1714system.cpu1.dcache.overall_hits::total 144914591 # number of overall hits
1715system.cpu1.dcache.ReadReq_misses::cpu1.data 2997503 # number of ReadReq misses
1716system.cpu1.dcache.ReadReq_misses::total 2997503 # number of ReadReq misses
1717system.cpu1.dcache.WriteReq_misses::cpu1.data 2132920 # number of WriteReq misses
1718system.cpu1.dcache.WriteReq_misses::total 2132920 # number of WriteReq misses
1719system.cpu1.dcache.SoftPFReq_misses::cpu1.data 598160 # number of SoftPFReq misses
1720system.cpu1.dcache.SoftPFReq_misses::total 598160 # number of SoftPFReq misses
1721system.cpu1.dcache.WriteLineReq_misses::cpu1.data 396373 # number of WriteLineReq misses
1722system.cpu1.dcache.WriteLineReq_misses::total 396373 # number of WriteLineReq misses
1723system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 156072 # number of LoadLockedReq misses
1724system.cpu1.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
1725system.cpu1.dcache.StoreCondReq_misses::cpu1.data 190006 # number of StoreCondReq misses
1726system.cpu1.dcache.StoreCondReq_misses::total 190006 # number of StoreCondReq misses
1727system.cpu1.dcache.demand_misses::cpu1.data 5526796 # number of demand (read+write) misses
1728system.cpu1.dcache.demand_misses::total 5526796 # number of demand (read+write) misses
1729system.cpu1.dcache.overall_misses::cpu1.data 6124956 # number of overall misses
1730system.cpu1.dcache.overall_misses::total 6124956 # number of overall misses
1731system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46710580500 # number of ReadReq miss cycles
1732system.cpu1.dcache.ReadReq_miss_latency::total 46710580500 # number of ReadReq miss cycles
1733system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40169374000 # number of WriteReq miss cycles
1734system.cpu1.dcache.WriteReq_miss_latency::total 40169374000 # number of WriteReq miss cycles
1735system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10226397500 # number of WriteLineReq miss cycles
1736system.cpu1.dcache.WriteLineReq_miss_latency::total 10226397500 # number of WriteLineReq miss cycles
1737system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2373794500 # number of LoadLockedReq miss cycles
1738system.cpu1.dcache.LoadLockedReq_miss_latency::total 2373794500 # number of LoadLockedReq miss cycles
1739system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4526922000 # number of StoreCondReq miss cycles
1740system.cpu1.dcache.StoreCondReq_miss_latency::total 4526922000 # number of StoreCondReq miss cycles
1741system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1761500 # number of StoreCondFailReq miss cycles
1742system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1761500 # number of StoreCondFailReq miss cycles
1743system.cpu1.dcache.demand_miss_latency::cpu1.data 97106352000 # number of demand (read+write) miss cycles
1744system.cpu1.dcache.demand_miss_latency::total 97106352000 # number of demand (read+write) miss cycles
1745system.cpu1.dcache.overall_miss_latency::cpu1.data 97106352000 # number of overall miss cycles
1746system.cpu1.dcache.overall_miss_latency::total 97106352000 # number of overall miss cycles
1747system.cpu1.dcache.ReadReq_accesses::cpu1.data 79996027 # number of ReadReq accesses(hits+misses)
1748system.cpu1.dcache.ReadReq_accesses::total 79996027 # number of ReadReq accesses(hits+misses)
1749system.cpu1.dcache.WriteReq_accesses::cpu1.data 69677203 # number of WriteReq accesses(hits+misses)
1750system.cpu1.dcache.WriteReq_accesses::total 69677203 # number of WriteReq accesses(hits+misses)
1751system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 826185 # number of SoftPFReq accesses(hits+misses)
1752system.cpu1.dcache.SoftPFReq_accesses::total 826185 # number of SoftPFReq accesses(hits+misses)
1753system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 540132 # number of WriteLineReq accesses(hits+misses)
1754system.cpu1.dcache.WriteLineReq_accesses::total 540132 # number of WriteLineReq accesses(hits+misses)
1755system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1889335 # number of LoadLockedReq accesses(hits+misses)
1756system.cpu1.dcache.LoadLockedReq_accesses::total 1889335 # number of LoadLockedReq accesses(hits+misses)
1757system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1888088 # number of StoreCondReq accesses(hits+misses)
1758system.cpu1.dcache.StoreCondReq_accesses::total 1888088 # number of StoreCondReq accesses(hits+misses)
1759system.cpu1.dcache.demand_accesses::cpu1.data 150213362 # number of demand (read+write) accesses
1760system.cpu1.dcache.demand_accesses::total 150213362 # number of demand (read+write) accesses
1761system.cpu1.dcache.overall_accesses::cpu1.data 151039547 # number of overall (read+write) accesses
1762system.cpu1.dcache.overall_accesses::total 151039547 # number of overall (read+write) accesses
1763system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037471 # miss rate for ReadReq accesses
1764system.cpu1.dcache.ReadReq_miss_rate::total 0.037471 # miss rate for ReadReq accesses
1765system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030611 # miss rate for WriteReq accesses
1766system.cpu1.dcache.WriteReq_miss_rate::total 0.030611 # miss rate for WriteReq accesses
1767system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.724002 # miss rate for SoftPFReq accesses
1768system.cpu1.dcache.SoftPFReq_miss_rate::total 0.724002 # miss rate for SoftPFReq accesses
1769system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733845 # miss rate for WriteLineReq accesses
1770system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733845 # miss rate for WriteLineReq accesses
1771system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.082607 # miss rate for LoadLockedReq accesses
1772system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.082607 # miss rate for LoadLockedReq accesses
1773system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100634 # miss rate for StoreCondReq accesses
1774system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100634 # miss rate for StoreCondReq accesses
1775system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036793 # miss rate for demand accesses
1776system.cpu1.dcache.demand_miss_rate::total 0.036793 # miss rate for demand accesses
1777system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040552 # miss rate for overall accesses
1778system.cpu1.dcache.overall_miss_rate::total 0.040552 # miss rate for overall accesses
1779system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15583.163887 # average ReadReq miss latency
1780system.cpu1.dcache.ReadReq_avg_miss_latency::total 15583.163887 # average ReadReq miss latency
1781system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18833.042965 # average WriteReq miss latency
1782system.cpu1.dcache.WriteReq_avg_miss_latency::total 18833.042965 # average WriteReq miss latency
1783system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25799.934658 # average WriteLineReq miss latency
1784system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25799.934658 # average WriteLineReq miss latency
1785system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15209.611590 # average LoadLockedReq miss latency
1786system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15209.611590 # average LoadLockedReq miss latency
1787system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23825.152890 # average StoreCondReq miss latency
1788system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23825.152890 # average StoreCondReq miss latency
1789system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1790system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1791system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17570.098842 # average overall miss latency
1792system.cpu1.dcache.demand_avg_miss_latency::total 17570.098842 # average overall miss latency
1793system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15854.212177 # average overall miss latency
1794system.cpu1.dcache.overall_avg_miss_latency::total 15854.212177 # average overall miss latency
1795system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1796system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1797system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1798system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1799system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1800system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1801system.cpu1.dcache.writebacks::writebacks 4915771 # number of writebacks
1802system.cpu1.dcache.writebacks::total 4915771 # number of writebacks
1803system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 147995 # number of ReadReq MSHR hits
1804system.cpu1.dcache.ReadReq_mshr_hits::total 147995 # number of ReadReq MSHR hits
1805system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 874601 # number of WriteReq MSHR hits
1806system.cpu1.dcache.WriteReq_mshr_hits::total 874601 # number of WriteReq MSHR hits
1807system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits
1808system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits
1809system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 38344 # number of LoadLockedReq MSHR hits
1810system.cpu1.dcache.LoadLockedReq_mshr_hits::total 38344 # number of LoadLockedReq MSHR hits
1811system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 50 # number of StoreCondReq MSHR hits
1812system.cpu1.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits
1813system.cpu1.dcache.demand_mshr_hits::cpu1.data 1022654 # number of demand (read+write) MSHR hits
1814system.cpu1.dcache.demand_mshr_hits::total 1022654 # number of demand (read+write) MSHR hits
1815system.cpu1.dcache.overall_mshr_hits::cpu1.data 1022654 # number of overall MSHR hits
1816system.cpu1.dcache.overall_mshr_hits::total 1022654 # number of overall MSHR hits
1817system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2849508 # number of ReadReq MSHR misses
1818system.cpu1.dcache.ReadReq_mshr_misses::total 2849508 # number of ReadReq MSHR misses
1819system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1258319 # number of WriteReq MSHR misses
1820system.cpu1.dcache.WriteReq_mshr_misses::total 1258319 # number of WriteReq MSHR misses
1821system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 597912 # number of SoftPFReq MSHR misses
1822system.cpu1.dcache.SoftPFReq_mshr_misses::total 597912 # number of SoftPFReq MSHR misses
1823system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 396315 # number of WriteLineReq MSHR misses
1824system.cpu1.dcache.WriteLineReq_mshr_misses::total 396315 # number of WriteLineReq MSHR misses
1825system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117728 # number of LoadLockedReq MSHR misses
1826system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117728 # number of LoadLockedReq MSHR misses
1827system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189956 # number of StoreCondReq MSHR misses
1828system.cpu1.dcache.StoreCondReq_mshr_misses::total 189956 # number of StoreCondReq MSHR misses
1829system.cpu1.dcache.demand_mshr_misses::cpu1.data 4504142 # number of demand (read+write) MSHR misses
1830system.cpu1.dcache.demand_mshr_misses::total 4504142 # number of demand (read+write) MSHR misses
1831system.cpu1.dcache.overall_mshr_misses::cpu1.data 5102054 # number of overall MSHR misses
1832system.cpu1.dcache.overall_mshr_misses::total 5102054 # number of overall MSHR misses
1833system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable
1834system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7183 # number of ReadReq MSHR uncacheable
1835system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable
1836system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable
1837system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses
1838system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14692 # number of overall MSHR uncacheable misses
1839system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40476665500 # number of ReadReq MSHR miss cycles
1840system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40476665500 # number of ReadReq MSHR miss cycles
1841system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23125073000 # number of WriteReq MSHR miss cycles
1842system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23125073000 # number of WriteReq MSHR miss cycles
1843system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13939684500 # number of SoftPFReq MSHR miss cycles
1844system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13939684500 # number of SoftPFReq MSHR miss cycles
1845system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9826633500 # number of WriteLineReq MSHR miss cycles
1846system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9826633500 # number of WriteLineReq MSHR miss cycles
1847system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1586206000 # number of LoadLockedReq MSHR miss cycles
1848system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1586206000 # number of LoadLockedReq MSHR miss cycles
1849system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4335749000 # number of StoreCondReq MSHR miss cycles
1850system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4335749000 # number of StoreCondReq MSHR miss cycles
1851system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1584500 # number of StoreCondFailReq MSHR miss cycles
1852system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1584500 # number of StoreCondFailReq MSHR miss cycles
1853system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73428372000 # number of demand (read+write) MSHR miss cycles
1854system.cpu1.dcache.demand_mshr_miss_latency::total 73428372000 # number of demand (read+write) MSHR miss cycles
1855system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87368056500 # number of overall MSHR miss cycles
1856system.cpu1.dcache.overall_mshr_miss_latency::total 87368056500 # number of overall MSHR miss cycles
1857system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 918087500 # number of ReadReq MSHR uncacheable cycles
1858system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 918087500 # number of ReadReq MSHR uncacheable cycles
1859system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 918087500 # number of overall MSHR uncacheable cycles
1860system.cpu1.dcache.overall_mshr_uncacheable_latency::total 918087500 # number of overall MSHR uncacheable cycles
1861system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035621 # mshr miss rate for ReadReq accesses
1862system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035621 # mshr miss rate for ReadReq accesses
1863system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018059 # mshr miss rate for WriteReq accesses
1864system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018059 # mshr miss rate for WriteReq accesses
1865system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.723702 # mshr miss rate for SoftPFReq accesses
1866system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.723702 # mshr miss rate for SoftPFReq accesses
1867system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.733737 # mshr miss rate for WriteLineReq accesses
1868system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.733737 # mshr miss rate for WriteLineReq accesses
1869system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062312 # mshr miss rate for LoadLockedReq accesses
1870system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062312 # mshr miss rate for LoadLockedReq accesses
1871system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100608 # mshr miss rate for StoreCondReq accesses
1872system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100608 # mshr miss rate for StoreCondReq accesses
1873system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029985 # mshr miss rate for demand accesses
1874system.cpu1.dcache.demand_mshr_miss_rate::total 0.029985 # mshr miss rate for demand accesses
1875system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033780 # mshr miss rate for overall accesses
1876system.cpu1.dcache.overall_mshr_miss_rate::total 0.033780 # mshr miss rate for overall accesses
1877system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14204.790967 # average ReadReq mshr miss latency
1878system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14204.790967 # average ReadReq mshr miss latency
1879system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18377.750793 # average WriteReq mshr miss latency
1880system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18377.750793 # average WriteReq mshr miss latency
1881system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23313.940011 # average SoftPFReq mshr miss latency
1882system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23313.940011 # average SoftPFReq mshr miss latency
1883system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24795.007759 # average WriteLineReq mshr miss latency
1884system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 24795.007759 # average WriteLineReq mshr miss latency
1885system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13473.481245 # average LoadLockedReq mshr miss latency
1886system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13473.481245 # average LoadLockedReq mshr miss latency
1887system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22825.017372 # average StoreCondReq mshr miss latency
1888system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22825.017372 # average StoreCondReq mshr miss latency
1889system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1890system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1891system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16302.410537 # average overall mshr miss latency
1892system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16302.410537 # average overall mshr miss latency
1893system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17124.094825 # average overall mshr miss latency
1894system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17124.094825 # average overall mshr miss latency
1895system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127813.935681 # average ReadReq mshr uncacheable latency
1896system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 127813.935681 # average ReadReq mshr uncacheable latency
1897system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 62488.939559 # average overall mshr uncacheable latency
1898system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 62488.939559 # average overall mshr uncacheable latency
1899system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1900system.cpu1.icache.tags.replacements 8832346 # number of replacements
1901system.cpu1.icache.tags.tagsinuse 507.234959 # Cycle average of tags in use
1902system.cpu1.icache.tags.total_refs 222308626 # Total number of references to valid blocks.
1903system.cpu1.icache.tags.sampled_refs 8832858 # Sample count of references to valid blocks.
1904system.cpu1.icache.tags.avg_refs 25.168369 # Average number of references to valid blocks.
1905system.cpu1.icache.tags.warmup_cycle 8368864848000 # Cycle when the warmup percentage was hit.
1906system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.234959 # Average occupied blocks per requestor
1907system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990693 # Average percentage of cache occupancy
1908system.cpu1.icache.tags.occ_percent::total 0.990693 # Average percentage of cache occupancy
1909system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1910system.cpu1.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
1911system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
1912system.cpu1.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
1913system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1914system.cpu1.icache.tags.tag_accesses 471115826 # Number of tag accesses
1915system.cpu1.icache.tags.data_accesses 471115826 # Number of data accesses
1916system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1917system.cpu1.icache.ReadReq_hits::cpu1.inst 222308626 # number of ReadReq hits
1918system.cpu1.icache.ReadReq_hits::total 222308626 # number of ReadReq hits
1919system.cpu1.icache.demand_hits::cpu1.inst 222308626 # number of demand (read+write) hits
1920system.cpu1.icache.demand_hits::total 222308626 # number of demand (read+write) hits
1921system.cpu1.icache.overall_hits::cpu1.inst 222308626 # number of overall hits
1922system.cpu1.icache.overall_hits::total 222308626 # number of overall hits
1923system.cpu1.icache.ReadReq_misses::cpu1.inst 8832858 # number of ReadReq misses
1924system.cpu1.icache.ReadReq_misses::total 8832858 # number of ReadReq misses
1925system.cpu1.icache.demand_misses::cpu1.inst 8832858 # number of demand (read+write) misses
1926system.cpu1.icache.demand_misses::total 8832858 # number of demand (read+write) misses
1927system.cpu1.icache.overall_misses::cpu1.inst 8832858 # number of overall misses
1928system.cpu1.icache.overall_misses::total 8832858 # number of overall misses
1929system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91672034000 # number of ReadReq miss cycles
1930system.cpu1.icache.ReadReq_miss_latency::total 91672034000 # number of ReadReq miss cycles
1931system.cpu1.icache.demand_miss_latency::cpu1.inst 91672034000 # number of demand (read+write) miss cycles
1932system.cpu1.icache.demand_miss_latency::total 91672034000 # number of demand (read+write) miss cycles
1933system.cpu1.icache.overall_miss_latency::cpu1.inst 91672034000 # number of overall miss cycles
1934system.cpu1.icache.overall_miss_latency::total 91672034000 # number of overall miss cycles
1935system.cpu1.icache.ReadReq_accesses::cpu1.inst 231141484 # number of ReadReq accesses(hits+misses)
1936system.cpu1.icache.ReadReq_accesses::total 231141484 # number of ReadReq accesses(hits+misses)
1937system.cpu1.icache.demand_accesses::cpu1.inst 231141484 # number of demand (read+write) accesses
1938system.cpu1.icache.demand_accesses::total 231141484 # number of demand (read+write) accesses
1939system.cpu1.icache.overall_accesses::cpu1.inst 231141484 # number of overall (read+write) accesses
1940system.cpu1.icache.overall_accesses::total 231141484 # number of overall (read+write) accesses
1941system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038214 # miss rate for ReadReq accesses
1942system.cpu1.icache.ReadReq_miss_rate::total 0.038214 # miss rate for ReadReq accesses
1943system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038214 # miss rate for demand accesses
1944system.cpu1.icache.demand_miss_rate::total 0.038214 # miss rate for demand accesses
1945system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038214 # miss rate for overall accesses
1946system.cpu1.icache.overall_miss_rate::total 0.038214 # miss rate for overall accesses
1947system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10378.524595 # average ReadReq miss latency
1948system.cpu1.icache.ReadReq_avg_miss_latency::total 10378.524595 # average ReadReq miss latency
1949system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency
1950system.cpu1.icache.demand_avg_miss_latency::total 10378.524595 # average overall miss latency
1951system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10378.524595 # average overall miss latency
1952system.cpu1.icache.overall_avg_miss_latency::total 10378.524595 # average overall miss latency
1953system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1954system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1955system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1956system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1957system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1958system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1959system.cpu1.icache.writebacks::writebacks 8832346 # number of writebacks
1960system.cpu1.icache.writebacks::total 8832346 # number of writebacks
1961system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8832858 # number of ReadReq MSHR misses
1962system.cpu1.icache.ReadReq_mshr_misses::total 8832858 # number of ReadReq MSHR misses
1963system.cpu1.icache.demand_mshr_misses::cpu1.inst 8832858 # number of demand (read+write) MSHR misses
1964system.cpu1.icache.demand_mshr_misses::total 8832858 # number of demand (read+write) MSHR misses
1965system.cpu1.icache.overall_mshr_misses::cpu1.inst 8832858 # number of overall MSHR misses
1966system.cpu1.icache.overall_mshr_misses::total 8832858 # number of overall MSHR misses
1967system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
1968system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
1969system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
1970system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
1971system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 87255605000 # number of ReadReq MSHR miss cycles
1972system.cpu1.icache.ReadReq_mshr_miss_latency::total 87255605000 # number of ReadReq MSHR miss cycles
1973system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 87255605000 # number of demand (read+write) MSHR miss cycles
1974system.cpu1.icache.demand_mshr_miss_latency::total 87255605000 # number of demand (read+write) MSHR miss cycles
1975system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 87255605000 # number of overall MSHR miss cycles
1976system.cpu1.icache.overall_mshr_miss_latency::total 87255605000 # number of overall MSHR miss cycles
1977system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9824500 # number of ReadReq MSHR uncacheable cycles
1978system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9824500 # number of ReadReq MSHR uncacheable cycles
1979system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9824500 # number of overall MSHR uncacheable cycles
1980system.cpu1.icache.overall_mshr_uncacheable_latency::total 9824500 # number of overall MSHR uncacheable cycles
1981system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for ReadReq accesses
1982system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038214 # mshr miss rate for ReadReq accesses
1983system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for demand accesses
1984system.cpu1.icache.demand_mshr_miss_rate::total 0.038214 # mshr miss rate for demand accesses
1985system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038214 # mshr miss rate for overall accesses
1986system.cpu1.icache.overall_mshr_miss_rate::total 0.038214 # mshr miss rate for overall accesses
1987system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average ReadReq mshr miss latency
1988system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9878.524595 # average ReadReq mshr miss latency
1989system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency
1990system.cpu1.icache.demand_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency
1991system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9878.524595 # average overall mshr miss latency
1992system.cpu1.icache.overall_avg_mshr_miss_latency::total 9878.524595 # average overall mshr miss latency
1993system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average ReadReq mshr uncacheable latency
1994system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 103415.789474 # average ReadReq mshr uncacheable latency
1995system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 103415.789474 # average overall mshr uncacheable latency
1996system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 103415.789474 # average overall mshr uncacheable latency
1997system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
1998system.cpu1.l2cache.prefetcher.num_hwpf_issued 6928823 # number of hwpf issued
1999system.cpu1.l2cache.prefetcher.pfIdentified 6928917 # number of prefetch candidates identified
2000system.cpu1.l2cache.prefetcher.pfBufferHit 84 # number of redundant prefetches already in prefetch queue
2001system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2002system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2003system.cpu1.l2cache.prefetcher.pfSpanPage 861587 # number of prefetches not generated due to page crossing
2004system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2005system.cpu1.l2cache.tags.replacements 2157597 # number of replacements
2006system.cpu1.l2cache.tags.tagsinuse 13047.513497 # Cycle average of tags in use
2007system.cpu1.l2cache.tags.total_refs 12560684 # Total number of references to valid blocks.
2008system.cpu1.l2cache.tags.sampled_refs 2173028 # Sample count of references to valid blocks.
2009system.cpu1.l2cache.tags.avg_refs 5.780268 # Average number of references to valid blocks.
2010system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2011system.cpu1.l2cache.tags.occ_blocks::writebacks 12721.719403 # Average occupied blocks per requestor
2012system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 48.343114 # Average occupied blocks per requestor
2013system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 32.192156 # Average occupied blocks per requestor
2014system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.258823 # Average occupied blocks per requestor
2015system.cpu1.l2cache.tags.occ_percent::writebacks 0.776472 # Average percentage of cache occupancy
2016system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002951 # Average percentage of cache occupancy
2017system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001965 # Average percentage of cache occupancy
2018system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014969 # Average percentage of cache occupancy
2019system.cpu1.l2cache.tags.occ_percent::total 0.796357 # Average percentage of cache occupancy
2020system.cpu1.l2cache.tags.occ_task_id_blocks::1022 270 # Occupied blocks per task id
2021system.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id
2022system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15088 # Occupied blocks per task id
2023system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 102 # Occupied blocks per task id
2024system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id
2025system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 61 # Occupied blocks per task id
2026system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
2027system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
2028system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id
2029system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
2030system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id
2031system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 832 # Occupied blocks per task id
2032system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6150 # Occupied blocks per task id
2033system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6722 # Occupied blocks per task id
2034system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1111 # Occupied blocks per task id
2035system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.016479 # Percentage of cache occupancy per task id
2036system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id
2037system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.920898 # Percentage of cache occupancy per task id
2038system.cpu1.l2cache.tags.tag_accesses 472979438 # Number of tag accesses
2039system.cpu1.l2cache.tags.data_accesses 472979438 # Number of data accesses
2040system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2041system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 496781 # number of ReadReq hits
2042system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 150336 # number of ReadReq hits
2043system.cpu1.l2cache.ReadReq_hits::total 647117 # number of ReadReq hits
2044system.cpu1.l2cache.WritebackDirty_hits::writebacks 3051311 # number of WritebackDirty hits
2045system.cpu1.l2cache.WritebackDirty_hits::total 3051311 # number of WritebackDirty hits
2046system.cpu1.l2cache.WritebackClean_hits::writebacks 10695223 # number of WritebackClean hits
2047system.cpu1.l2cache.WritebackClean_hits::total 10695223 # number of WritebackClean hits
2048system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2 # number of UpgradeReq hits
2049system.cpu1.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits
2050system.cpu1.l2cache.ReadExReq_hits::cpu1.data 813214 # number of ReadExReq hits
2051system.cpu1.l2cache.ReadExReq_hits::total 813214 # number of ReadExReq hits
2052system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8132856 # number of ReadCleanReq hits
2053system.cpu1.l2cache.ReadCleanReq_hits::total 8132856 # number of ReadCleanReq hits
2054system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2632220 # number of ReadSharedReq hits
2055system.cpu1.l2cache.ReadSharedReq_hits::total 2632220 # number of ReadSharedReq hits
2056system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 143613 # number of InvalidateReq hits
2057system.cpu1.l2cache.InvalidateReq_hits::total 143613 # number of InvalidateReq hits
2058system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 496781 # number of demand (read+write) hits
2059system.cpu1.l2cache.demand_hits::cpu1.itb.walker 150336 # number of demand (read+write) hits
2060system.cpu1.l2cache.demand_hits::cpu1.inst 8132856 # number of demand (read+write) hits
2061system.cpu1.l2cache.demand_hits::cpu1.data 3445434 # number of demand (read+write) hits
2062system.cpu1.l2cache.demand_hits::total 12225407 # number of demand (read+write) hits
2063system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 496781 # number of overall hits
2064system.cpu1.l2cache.overall_hits::cpu1.itb.walker 150336 # number of overall hits
2065system.cpu1.l2cache.overall_hits::cpu1.inst 8132856 # number of overall hits
2066system.cpu1.l2cache.overall_hits::cpu1.data 3445434 # number of overall hits
2067system.cpu1.l2cache.overall_hits::total 12225407 # number of overall hits
2068system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 19778 # number of ReadReq misses
2069system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9507 # number of ReadReq misses
2070system.cpu1.l2cache.ReadReq_misses::total 29285 # number of ReadReq misses
2071system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 216104 # number of UpgradeReq misses
2072system.cpu1.l2cache.UpgradeReq_misses::total 216104 # number of UpgradeReq misses
2073system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 189953 # number of SCUpgradeReq misses
2074system.cpu1.l2cache.SCUpgradeReq_misses::total 189953 # number of SCUpgradeReq misses
2075system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2076system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2077system.cpu1.l2cache.ReadExReq_misses::cpu1.data 231177 # number of ReadExReq misses
2078system.cpu1.l2cache.ReadExReq_misses::total 231177 # number of ReadExReq misses
2079system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 700002 # number of ReadCleanReq misses
2080system.cpu1.l2cache.ReadCleanReq_misses::total 700002 # number of ReadCleanReq misses
2081system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 932644 # number of ReadSharedReq misses
2082system.cpu1.l2cache.ReadSharedReq_misses::total 932644 # number of ReadSharedReq misses
2083system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250983 # number of InvalidateReq misses
2084system.cpu1.l2cache.InvalidateReq_misses::total 250983 # number of InvalidateReq misses
2085system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 19778 # number of demand (read+write) misses
2086system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9507 # number of demand (read+write) misses
2087system.cpu1.l2cache.demand_misses::cpu1.inst 700002 # number of demand (read+write) misses
2088system.cpu1.l2cache.demand_misses::cpu1.data 1163821 # number of demand (read+write) misses
2089system.cpu1.l2cache.demand_misses::total 1893108 # number of demand (read+write) misses
2090system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 19778 # number of overall misses
2091system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9507 # number of overall misses
2092system.cpu1.l2cache.overall_misses::cpu1.inst 700002 # number of overall misses
2093system.cpu1.l2cache.overall_misses::cpu1.data 1163821 # number of overall misses
2094system.cpu1.l2cache.overall_misses::total 1893108 # number of overall misses
2095system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 605384500 # number of ReadReq miss cycles
2096system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 346513000 # number of ReadReq miss cycles
2097system.cpu1.l2cache.ReadReq_miss_latency::total 951897500 # number of ReadReq miss cycles
2098system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 912243000 # number of UpgradeReq miss cycles
2099system.cpu1.l2cache.UpgradeReq_miss_latency::total 912243000 # number of UpgradeReq miss cycles
2100system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 268121000 # number of SCUpgradeReq miss cycles
2101system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 268121000 # number of SCUpgradeReq miss cycles
2102system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1526000 # number of SCUpgradeFailReq miss cycles
2103system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1526000 # number of SCUpgradeFailReq miss cycles
2104system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10578569498 # number of ReadExReq miss cycles
2105system.cpu1.l2cache.ReadExReq_miss_latency::total 10578569498 # number of ReadExReq miss cycles
2106system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24914386500 # number of ReadCleanReq miss cycles
2107system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24914386500 # number of ReadCleanReq miss cycles
2108system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33296141988 # number of ReadSharedReq miss cycles
2109system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33296141988 # number of ReadSharedReq miss cycles
2110system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 300579500 # number of InvalidateReq miss cycles
2111system.cpu1.l2cache.InvalidateReq_miss_latency::total 300579500 # number of InvalidateReq miss cycles
2112system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 605384500 # number of demand (read+write) miss cycles
2113system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 346513000 # number of demand (read+write) miss cycles
2114system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24914386500 # number of demand (read+write) miss cycles
2115system.cpu1.l2cache.demand_miss_latency::cpu1.data 43874711486 # number of demand (read+write) miss cycles
2116system.cpu1.l2cache.demand_miss_latency::total 69740995486 # number of demand (read+write) miss cycles
2117system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 605384500 # number of overall miss cycles
2118system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 346513000 # number of overall miss cycles
2119system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24914386500 # number of overall miss cycles
2120system.cpu1.l2cache.overall_miss_latency::cpu1.data 43874711486 # number of overall miss cycles
2121system.cpu1.l2cache.overall_miss_latency::total 69740995486 # number of overall miss cycles
2122system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 516559 # number of ReadReq accesses(hits+misses)
2123system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 159843 # number of ReadReq accesses(hits+misses)
2124system.cpu1.l2cache.ReadReq_accesses::total 676402 # number of ReadReq accesses(hits+misses)
2125system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3051311 # number of WritebackDirty accesses(hits+misses)
2126system.cpu1.l2cache.WritebackDirty_accesses::total 3051311 # number of WritebackDirty accesses(hits+misses)
2127system.cpu1.l2cache.WritebackClean_accesses::writebacks 10695223 # number of WritebackClean accesses(hits+misses)
2128system.cpu1.l2cache.WritebackClean_accesses::total 10695223 # number of WritebackClean accesses(hits+misses)
2129system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 216106 # number of UpgradeReq accesses(hits+misses)
2130system.cpu1.l2cache.UpgradeReq_accesses::total 216106 # number of UpgradeReq accesses(hits+misses)
2131system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189953 # number of SCUpgradeReq accesses(hits+misses)
2132system.cpu1.l2cache.SCUpgradeReq_accesses::total 189953 # number of SCUpgradeReq accesses(hits+misses)
2133system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2134system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2135system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1044391 # number of ReadExReq accesses(hits+misses)
2136system.cpu1.l2cache.ReadExReq_accesses::total 1044391 # number of ReadExReq accesses(hits+misses)
2137system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8832858 # number of ReadCleanReq accesses(hits+misses)
2138system.cpu1.l2cache.ReadCleanReq_accesses::total 8832858 # number of ReadCleanReq accesses(hits+misses)
2139system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3564864 # number of ReadSharedReq accesses(hits+misses)
2140system.cpu1.l2cache.ReadSharedReq_accesses::total 3564864 # number of ReadSharedReq accesses(hits+misses)
2141system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 394596 # number of InvalidateReq accesses(hits+misses)
2142system.cpu1.l2cache.InvalidateReq_accesses::total 394596 # number of InvalidateReq accesses(hits+misses)
2143system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 516559 # number of demand (read+write) accesses
2144system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 159843 # number of demand (read+write) accesses
2145system.cpu1.l2cache.demand_accesses::cpu1.inst 8832858 # number of demand (read+write) accesses
2146system.cpu1.l2cache.demand_accesses::cpu1.data 4609255 # number of demand (read+write) accesses
2147system.cpu1.l2cache.demand_accesses::total 14118515 # number of demand (read+write) accesses
2148system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 516559 # number of overall (read+write) accesses
2149system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 159843 # number of overall (read+write) accesses
2150system.cpu1.l2cache.overall_accesses::cpu1.inst 8832858 # number of overall (read+write) accesses
2151system.cpu1.l2cache.overall_accesses::cpu1.data 4609255 # number of overall (read+write) accesses
2152system.cpu1.l2cache.overall_accesses::total 14118515 # number of overall (read+write) accesses
2153system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for ReadReq accesses
2154system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059477 # miss rate for ReadReq accesses
2155system.cpu1.l2cache.ReadReq_miss_rate::total 0.043295 # miss rate for ReadReq accesses
2156system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999991 # miss rate for UpgradeReq accesses
2157system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999991 # miss rate for UpgradeReq accesses
2158system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2159system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2160system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2161system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2162system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221351 # miss rate for ReadExReq accesses
2163system.cpu1.l2cache.ReadExReq_miss_rate::total 0.221351 # miss rate for ReadExReq accesses
2164system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.079250 # miss rate for ReadCleanReq accesses
2165system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.079250 # miss rate for ReadCleanReq accesses
2166system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.261621 # miss rate for ReadSharedReq accesses
2167system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.261621 # miss rate for ReadSharedReq accesses
2168system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.636051 # miss rate for InvalidateReq accesses
2169system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.636051 # miss rate for InvalidateReq accesses
2170system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for demand accesses
2171system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059477 # miss rate for demand accesses
2172system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079250 # miss rate for demand accesses
2173system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252497 # miss rate for demand accesses
2174system.cpu1.l2cache.demand_miss_rate::total 0.134087 # miss rate for demand accesses
2175system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038288 # miss rate for overall accesses
2176system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059477 # miss rate for overall accesses
2177system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079250 # miss rate for overall accesses
2178system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252497 # miss rate for overall accesses
2179system.cpu1.l2cache.overall_miss_rate::total 0.134087 # miss rate for overall accesses
2180system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average ReadReq miss latency
2181system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36448.196066 # average ReadReq miss latency
2182system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32504.609869 # average ReadReq miss latency
2183system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4221.314737 # average UpgradeReq miss latency
2184system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4221.314737 # average UpgradeReq miss latency
2185system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1411.512321 # average SCUpgradeReq miss latency
2186system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1411.512321 # average SCUpgradeReq miss latency
2187system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 508666.666667 # average SCUpgradeFailReq miss latency
2188system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 508666.666667 # average SCUpgradeFailReq miss latency
2189system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45759.610593 # average ReadExReq miss latency
2190system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45759.610593 # average ReadExReq miss latency
2191system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35591.879023 # average ReadCleanReq miss latency
2192system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35591.879023 # average ReadCleanReq miss latency
2193system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35700.805439 # average ReadSharedReq miss latency
2194system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35700.805439 # average ReadSharedReq miss latency
2195system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1197.609001 # average InvalidateReq miss latency
2196system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1197.609001 # average InvalidateReq miss latency
2197system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency
2198system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency
2199system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency
2200system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency
2201system.cpu1.l2cache.demand_avg_miss_latency::total 36839.417237 # average overall miss latency
2202system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30608.984731 # average overall miss latency
2203system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36448.196066 # average overall miss latency
2204system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35591.879023 # average overall miss latency
2205system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37698.848436 # average overall miss latency
2206system.cpu1.l2cache.overall_avg_miss_latency::total 36839.417237 # average overall miss latency
2207system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2208system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2209system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2210system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2211system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2212system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2213system.cpu1.l2cache.unused_prefetches 43184 # number of HardPF blocks evicted w/o reference
2214system.cpu1.l2cache.writebacks::writebacks 1062517 # number of writebacks
2215system.cpu1.l2cache.writebacks::total 1062517 # number of writebacks
2216system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 15 # number of ReadReq MSHR hits
2217system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 83 # number of ReadReq MSHR hits
2218system.cpu1.l2cache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits
2219system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6377 # number of ReadExReq MSHR hits
2220system.cpu1.l2cache.ReadExReq_mshr_hits::total 6377 # number of ReadExReq MSHR hits
2221system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits
2222system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
2223system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 790 # number of ReadSharedReq MSHR hits
2224system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 790 # number of ReadSharedReq MSHR hits
2225system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits
2226system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits
2227system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 15 # number of demand (read+write) MSHR hits
2228system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 83 # number of demand (read+write) MSHR hits
2229system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
2230system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7167 # number of demand (read+write) MSHR hits
2231system.cpu1.l2cache.demand_mshr_hits::total 7267 # number of demand (read+write) MSHR hits
2232system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 15 # number of overall MSHR hits
2233system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 83 # number of overall MSHR hits
2234system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
2235system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7167 # number of overall MSHR hits
2236system.cpu1.l2cache.overall_mshr_hits::total 7267 # number of overall MSHR hits
2237system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 19763 # number of ReadReq MSHR misses
2238system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9424 # number of ReadReq MSHR misses
2239system.cpu1.l2cache.ReadReq_mshr_misses::total 29187 # number of ReadReq MSHR misses
2240system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of HardPFReq MSHR misses
2241system.cpu1.l2cache.HardPFReq_mshr_misses::total 714287 # number of HardPFReq MSHR misses
2242system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 216104 # number of UpgradeReq MSHR misses
2243system.cpu1.l2cache.UpgradeReq_mshr_misses::total 216104 # number of UpgradeReq MSHR misses
2244system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 189953 # number of SCUpgradeReq MSHR misses
2245system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 189953 # number of SCUpgradeReq MSHR misses
2246system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2247system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2248system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 224800 # number of ReadExReq MSHR misses
2249system.cpu1.l2cache.ReadExReq_mshr_misses::total 224800 # number of ReadExReq MSHR misses
2250system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 700000 # number of ReadCleanReq MSHR misses
2251system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 700000 # number of ReadCleanReq MSHR misses
2252system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 931854 # number of ReadSharedReq MSHR misses
2253system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 931854 # number of ReadSharedReq MSHR misses
2254system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250982 # number of InvalidateReq MSHR misses
2255system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250982 # number of InvalidateReq MSHR misses
2256system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 19763 # number of demand (read+write) MSHR misses
2257system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9424 # number of demand (read+write) MSHR misses
2258system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 700000 # number of demand (read+write) MSHR misses
2259system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1156654 # number of demand (read+write) MSHR misses
2260system.cpu1.l2cache.demand_mshr_misses::total 1885841 # number of demand (read+write) MSHR misses
2261system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 19763 # number of overall MSHR misses
2262system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9424 # number of overall MSHR misses
2263system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 700000 # number of overall MSHR misses
2264system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1156654 # number of overall MSHR misses
2265system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 714287 # number of overall MSHR misses
2266system.cpu1.l2cache.overall_mshr_misses::total 2600128 # number of overall MSHR misses
2267system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
2268system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7183 # number of ReadReq MSHR uncacheable
2269system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7278 # number of ReadReq MSHR uncacheable
2270system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable
2271system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7509 # number of WriteReq MSHR uncacheable
2272system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
2273system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14692 # number of overall MSHR uncacheable misses
2274system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14787 # number of overall MSHR uncacheable misses
2275system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of ReadReq MSHR miss cycles
2276system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 288576500 # number of ReadReq MSHR miss cycles
2277system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 775021000 # number of ReadReq MSHR miss cycles
2278system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of HardPFReq MSHR miss cycles
2279system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 30894742332 # number of HardPFReq MSHR miss cycles
2280system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4083186496 # number of UpgradeReq MSHR miss cycles
2281system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4083186496 # number of UpgradeReq MSHR miss cycles
2282system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2906568497 # number of SCUpgradeReq MSHR miss cycles
2283system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2906568497 # number of SCUpgradeReq MSHR miss cycles
2284system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1292000 # number of SCUpgradeFailReq MSHR miss cycles
2285system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1292000 # number of SCUpgradeFailReq MSHR miss cycles
2286system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8335690998 # number of ReadExReq MSHR miss cycles
2287system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8335690998 # number of ReadExReq MSHR miss cycles
2288system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20714350500 # number of ReadCleanReq MSHR miss cycles
2289system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20714350500 # number of ReadCleanReq MSHR miss cycles
2290system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27592853988 # number of ReadSharedReq MSHR miss cycles
2291system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27592853988 # number of ReadSharedReq MSHR miss cycles
2292system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6684154500 # number of InvalidateReq MSHR miss cycles
2293system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6684154500 # number of InvalidateReq MSHR miss cycles
2294system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of demand (read+write) MSHR miss cycles
2295system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 288576500 # number of demand (read+write) MSHR miss cycles
2296system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20714350500 # number of demand (read+write) MSHR miss cycles
2297system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35928544986 # number of demand (read+write) MSHR miss cycles
2298system.cpu1.l2cache.demand_mshr_miss_latency::total 57417916486 # number of demand (read+write) MSHR miss cycles
2299system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 486444500 # number of overall MSHR miss cycles
2300system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 288576500 # number of overall MSHR miss cycles
2301system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20714350500 # number of overall MSHR miss cycles
2302system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35928544986 # number of overall MSHR miss cycles
2303system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30894742332 # number of overall MSHR miss cycles
2304system.cpu1.l2cache.overall_mshr_miss_latency::total 88312658818 # number of overall MSHR miss cycles
2305system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9064500 # number of ReadReq MSHR uncacheable cycles
2306system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860524000 # number of ReadReq MSHR uncacheable cycles
2307system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 869588500 # number of ReadReq MSHR uncacheable cycles
2308system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9064500 # number of overall MSHR uncacheable cycles
2309system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860524000 # number of overall MSHR uncacheable cycles
2310system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 869588500 # number of overall MSHR uncacheable cycles
2311system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for ReadReq accesses
2312system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for ReadReq accesses
2313system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.043150 # mshr miss rate for ReadReq accesses
2314system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2315system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2316system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999991 # mshr miss rate for UpgradeReq accesses
2317system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999991 # mshr miss rate for UpgradeReq accesses
2318system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2319system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2320system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2321system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2322system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215245 # mshr miss rate for ReadExReq accesses
2323system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215245 # mshr miss rate for ReadExReq accesses
2324system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for ReadCleanReq accesses
2325system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079250 # mshr miss rate for ReadCleanReq accesses
2326system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261400 # mshr miss rate for ReadSharedReq accesses
2327system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261400 # mshr miss rate for ReadSharedReq accesses
2328system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.636048 # mshr miss rate for InvalidateReq accesses
2329system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.636048 # mshr miss rate for InvalidateReq accesses
2330system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for demand accesses
2331system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for demand accesses
2332system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for demand accesses
2333system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for demand accesses
2334system.cpu1.l2cache.demand_mshr_miss_rate::total 0.133572 # mshr miss rate for demand accesses
2335system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038259 # mshr miss rate for overall accesses
2336system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.058958 # mshr miss rate for overall accesses
2337system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079250 # mshr miss rate for overall accesses
2338system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250942 # mshr miss rate for overall accesses
2339system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2340system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184164 # mshr miss rate for overall accesses
2341system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average ReadReq mshr miss latency
2342system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average ReadReq mshr miss latency
2343system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26553.636893 # average ReadReq mshr miss latency
2344system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average HardPFReq mshr miss latency
2345system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43252.561410 # average HardPFReq mshr miss latency
2346system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18894.543812 # average UpgradeReq mshr miss latency
2347system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18894.543812 # average UpgradeReq mshr miss latency
2348system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15301.514043 # average SCUpgradeReq mshr miss latency
2349system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15301.514043 # average SCUpgradeReq mshr miss latency
2350system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 430666.666667 # average SCUpgradeFailReq mshr miss latency
2351system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 430666.666667 # average SCUpgradeFailReq mshr miss latency
2352system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37080.475970 # average ReadExReq mshr miss latency
2353system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37080.475970 # average ReadExReq mshr miss latency
2354system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average ReadCleanReq mshr miss latency
2355system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29591.929286 # average ReadCleanReq mshr miss latency
2356system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29610.705098 # average ReadSharedReq mshr miss latency
2357system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29610.705098 # average ReadSharedReq mshr miss latency
2358system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26632.007475 # average InvalidateReq mshr miss latency
2359system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26632.007475 # average InvalidateReq mshr miss latency
2360system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency
2361system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency
2362system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency
2363system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency
2364system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30446.849170 # average overall mshr miss latency
2365system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24613.899712 # average overall mshr miss latency
2366system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30621.445246 # average overall mshr miss latency
2367system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29591.929286 # average overall mshr miss latency
2368system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31062.482805 # average overall mshr miss latency
2369system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43252.561410 # average overall mshr miss latency
2370system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33964.735128 # average overall mshr miss latency
2371system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average ReadReq mshr uncacheable latency
2372system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119800.083531 # average ReadReq mshr uncacheable latency
2373system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119481.794449 # average ReadReq mshr uncacheable latency
2374system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95415.789474 # average overall mshr uncacheable latency
2375system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 58570.922951 # average overall mshr uncacheable latency
2376system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 58807.635085 # average overall mshr uncacheable latency
2377system.cpu1.toL2Bus.snoop_filter.tot_requests 28307892 # Total number of requests made to the snoop filter.
2378system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14471357 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2379system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1579 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2380system.cpu1.toL2Bus.snoop_filter.tot_snoops 577788 # Total number of snoops made to the snoop filter.
2381system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 577774 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2382system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2383system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2384system.cpu1.toL2Bus.trans_dist::ReadReq 765944 # Transaction distribution
2385system.cpu1.toL2Bus.trans_dist::ReadResp 13251577 # Transaction distribution
2386system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
2387system.cpu1.toL2Bus.trans_dist::WriteReq 7509 # Transaction distribution
2388system.cpu1.toL2Bus.trans_dist::WriteResp 7509 # Transaction distribution
2389system.cpu1.toL2Bus.trans_dist::WritebackDirty 4119049 # Transaction distribution
2390system.cpu1.toL2Bus.trans_dist::WritebackClean 10696803 # Transaction distribution
2391system.cpu1.toL2Bus.trans_dist::CleanEvict 1405207 # Transaction distribution
2392system.cpu1.toL2Bus.trans_dist::HardPFReq 907922 # Transaction distribution
2393system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
2394system.cpu1.toL2Bus.trans_dist::UpgradeReq 426575 # Transaction distribution
2395system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 338167 # Transaction distribution
2396system.cpu1.toL2Bus.trans_dist::UpgradeResp 466317 # Transaction distribution
2397system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution
2398system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution
2399system.cpu1.toL2Bus.trans_dist::ReadExReq 1072889 # Transaction distribution
2400system.cpu1.toL2Bus.trans_dist::ReadExResp 1050772 # Transaction distribution
2401system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8832858 # Transaction distribution
2402system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4591457 # Transaction distribution
2403system.cpu1.toL2Bus.trans_dist::InvalidateReq 449471 # Transaction distribution
2404system.cpu1.toL2Bus.trans_dist::InvalidateResp 394596 # Transaction distribution
2405system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26498252 # Packet count per connected master and slave (bytes)
2406system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15919614 # Packet count per connected master and slave (bytes)
2407system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339109 # Packet count per connected master and slave (bytes)
2408system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1095958 # Packet count per connected master and slave (bytes)
2409system.cpu1.toL2Bus.pkt_count::total 43852933 # Packet count per connected master and slave (bytes)
2410system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1130579136 # Cumulative packet size per connected master and slave (bytes)
2411system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615678398 # Cumulative packet size per connected master and slave (bytes)
2412system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1278736 # Cumulative packet size per connected master and slave (bytes)
2413system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4132472 # Cumulative packet size per connected master and slave (bytes)
2414system.cpu1.toL2Bus.pkt_size::total 1751668742 # Cumulative packet size per connected master and slave (bytes)
2415system.cpu1.toL2Bus.snoops 5086460 # Total snoops (count)
2416system.cpu1.toL2Bus.snoopTraffic 75030592 # Total snoop traffic (bytes)
2417system.cpu1.toL2Bus.snoop_fanout::samples 19865784 # Request fanout histogram
2418system.cpu1.toL2Bus.snoop_fanout::mean 0.045122 # Request fanout histogram
2419system.cpu1.toL2Bus.snoop_fanout::stdev 0.207576 # Request fanout histogram
2420system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2421system.cpu1.toL2Bus.snoop_fanout::0 18969410 95.49% 95.49% # Request fanout histogram
2422system.cpu1.toL2Bus.snoop_fanout::1 896360 4.51% 100.00% # Request fanout histogram
2423system.cpu1.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram
2424system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2425system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2426system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2427system.cpu1.toL2Bus.snoop_fanout::total 19865784 # Request fanout histogram
2428system.cpu1.toL2Bus.reqLayer0.occupancy 28134048478 # Layer occupancy (ticks)
2429system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2430system.cpu1.toL2Bus.snoopLayer0.occupancy 171886209 # Layer occupancy (ticks)
2431system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2432system.cpu1.toL2Bus.respLayer0.occupancy 13252138560 # Layer occupancy (ticks)
2433system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2434system.cpu1.toL2Bus.respLayer1.occupancy 7328947477 # Layer occupancy (ticks)
2435system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2436system.cpu1.toL2Bus.respLayer2.occupancy 179350830 # Layer occupancy (ticks)
2437system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2438system.cpu1.toL2Bus.respLayer3.occupancy 579510776 # Layer occupancy (ticks)
2439system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2440system.iobus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2441system.iobus.trans_dist::ReadReq 40272 # Transaction distribution
2442system.iobus.trans_dist::ReadResp 40272 # Transaction distribution
2443system.iobus.trans_dist::WriteReq 136595 # Transaction distribution
2444system.iobus.trans_dist::WriteResp 136595 # Transaction distribution
2445system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes)
2446system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2447system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2448system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2449system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2450system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2451system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2452system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2453system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2454system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2455system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2456system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2457system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2458system.iobus.pkt_count_system.bridge.master::total 122510 # Packet count per connected master and slave (bytes)
2459system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231144 # Packet count per connected master and slave (bytes)
2460system.iobus.pkt_count_system.realview.ide.dma::total 231144 # Packet count per connected master and slave (bytes)
2461system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2462system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2463system.iobus.pkt_count::total 353734 # Packet count per connected master and slave (bytes)
2464system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes)
2465system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2466system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2467system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2468system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2469system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2470system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2471system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2472system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2473system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2474system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2475system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2476system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2477system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes)
2478system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338592 # Cumulative packet size per connected master and slave (bytes)
2479system.iobus.pkt_size_system.realview.ide.dma::total 7338592 # Cumulative packet size per connected master and slave (bytes)
2480system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2481system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2482system.iobus.pkt_size::total 7496318 # Cumulative packet size per connected master and slave (bytes)
2483system.iobus.reqLayer0.occupancy 42593000 # Layer occupancy (ticks)
2484system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2485system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2486system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2487system.iobus.reqLayer2.occupancy 316000 # Layer occupancy (ticks)
2488system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2489system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
2490system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2491system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
2492system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2493system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
2494system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2495system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2496system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2497system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
2498system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2499system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2500system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2501system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks)
2502system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2503system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
2504system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2505system.iobus.reqLayer23.occupancy 25879501 # Layer occupancy (ticks)
2506system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2507system.iobus.reqLayer24.occupancy 34434000 # Layer occupancy (ticks)
2508system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2509system.iobus.reqLayer25.occupancy 569469195 # Layer occupancy (ticks)
2510system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2511system.iobus.respLayer0.occupancy 92646000 # Layer occupancy (ticks)
2512system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2513system.iobus.respLayer3.occupancy 147840000 # Layer occupancy (ticks)
2514system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2515system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2516system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2517system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2518system.iocache.tags.replacements 115567 # number of replacements
2519system.iocache.tags.tagsinuse 11.304352 # Cycle average of tags in use
2520system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2521system.iocache.tags.sampled_refs 115583 # Sample count of references to valid blocks.
2522system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2523system.iocache.tags.warmup_cycle 9167343261000 # Cycle when the warmup percentage was hit.
2524system.iocache.tags.occ_blocks::realview.ethernet 7.387949 # Average occupied blocks per requestor
2525system.iocache.tags.occ_blocks::realview.ide 3.916404 # Average occupied blocks per requestor
2526system.iocache.tags.occ_percent::realview.ethernet 0.461747 # Average percentage of cache occupancy
2527system.iocache.tags.occ_percent::realview.ide 0.244775 # Average percentage of cache occupancy
2528system.iocache.tags.occ_percent::total 0.706522 # Average percentage of cache occupancy
2529system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2530system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2531system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2532system.iocache.tags.tag_accesses 1040505 # Number of tag accesses
2533system.iocache.tags.data_accesses 1040505 # Number of data accesses
2534system.iocache.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2535system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2536system.iocache.ReadReq_misses::realview.ide 8844 # number of ReadReq misses
2537system.iocache.ReadReq_misses::total 8881 # number of ReadReq misses
2538system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2539system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2540system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2541system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2542system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2543system.iocache.demand_misses::realview.ide 115572 # number of demand (read+write) misses
2544system.iocache.demand_misses::total 115612 # number of demand (read+write) misses
2545system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2546system.iocache.overall_misses::realview.ide 115572 # number of overall misses
2547system.iocache.overall_misses::total 115612 # number of overall misses
2548system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
2549system.iocache.ReadReq_miss_latency::realview.ide 1979797452 # number of ReadReq miss cycles
2550system.iocache.ReadReq_miss_latency::total 1984993952 # number of ReadReq miss cycles
2551system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2552system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2553system.iocache.WriteLineReq_miss_latency::realview.ide 13211000243 # number of WriteLineReq miss cycles
2554system.iocache.WriteLineReq_miss_latency::total 13211000243 # number of WriteLineReq miss cycles
2555system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
2556system.iocache.demand_miss_latency::realview.ide 15190797695 # number of demand (read+write) miss cycles
2557system.iocache.demand_miss_latency::total 15196363195 # number of demand (read+write) miss cycles
2558system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
2559system.iocache.overall_miss_latency::realview.ide 15190797695 # number of overall miss cycles
2560system.iocache.overall_miss_latency::total 15196363195 # number of overall miss cycles
2561system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2562system.iocache.ReadReq_accesses::realview.ide 8844 # number of ReadReq accesses(hits+misses)
2563system.iocache.ReadReq_accesses::total 8881 # number of ReadReq accesses(hits+misses)
2564system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2565system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2566system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2567system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2568system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2569system.iocache.demand_accesses::realview.ide 115572 # number of demand (read+write) accesses
2570system.iocache.demand_accesses::total 115612 # number of demand (read+write) accesses
2571system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2572system.iocache.overall_accesses::realview.ide 115572 # number of overall (read+write) accesses
2573system.iocache.overall_accesses::total 115612 # number of overall (read+write) accesses
2574system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2575system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2576system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2577system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2578system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2579system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2580system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2581system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2582system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2583system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2584system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2585system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2586system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2587system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
2588system.iocache.ReadReq_avg_miss_latency::realview.ide 223857.694708 # average ReadReq miss latency
2589system.iocache.ReadReq_avg_miss_latency::total 223510.184889 # average ReadReq miss latency
2590system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2591system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2592system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123781.952655 # average WriteLineReq miss latency
2593system.iocache.WriteLineReq_avg_miss_latency::total 123781.952655 # average WriteLineReq miss latency
2594system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2595system.iocache.demand_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency
2596system.iocache.demand_avg_miss_latency::total 131442.784443 # average overall miss latency
2597system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2598system.iocache.overall_avg_miss_latency::realview.ide 131440.121266 # average overall miss latency
2599system.iocache.overall_avg_miss_latency::total 131442.784443 # average overall miss latency
2600system.iocache.blocked_cycles::no_mshrs 49739 # number of cycles access was blocked
2601system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2602system.iocache.blocked::no_mshrs 3574 # number of cycles access was blocked
2603system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2604system.iocache.avg_blocked_cycles::no_mshrs 13.916900 # average number of cycles each access was blocked
2605system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2606system.iocache.writebacks::writebacks 106693 # number of writebacks
2607system.iocache.writebacks::total 106693 # number of writebacks
2608system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2609system.iocache.ReadReq_mshr_misses::realview.ide 8844 # number of ReadReq MSHR misses
2610system.iocache.ReadReq_mshr_misses::total 8881 # number of ReadReq MSHR misses
2611system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2612system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2613system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2614system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2615system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2616system.iocache.demand_mshr_misses::realview.ide 115572 # number of demand (read+write) MSHR misses
2617system.iocache.demand_mshr_misses::total 115612 # number of demand (read+write) MSHR misses
2618system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2619system.iocache.overall_mshr_misses::realview.ide 115572 # number of overall MSHR misses
2620system.iocache.overall_mshr_misses::total 115612 # number of overall MSHR misses
2621system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles
2622system.iocache.ReadReq_mshr_miss_latency::realview.ide 1537597452 # number of ReadReq MSHR miss cycles
2623system.iocache.ReadReq_mshr_miss_latency::total 1540943952 # number of ReadReq MSHR miss cycles
2624system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2625system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2626system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7865666947 # number of WriteLineReq MSHR miss cycles
2627system.iocache.WriteLineReq_mshr_miss_latency::total 7865666947 # number of WriteLineReq MSHR miss cycles
2628system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles
2629system.iocache.demand_mshr_miss_latency::realview.ide 9403264399 # number of demand (read+write) MSHR miss cycles
2630system.iocache.demand_mshr_miss_latency::total 9406829899 # number of demand (read+write) MSHR miss cycles
2631system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles
2632system.iocache.overall_mshr_miss_latency::realview.ide 9403264399 # number of overall MSHR miss cycles
2633system.iocache.overall_mshr_miss_latency::total 9406829899 # number of overall MSHR miss cycles
2634system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2635system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2636system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2637system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2638system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2639system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2640system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2641system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2642system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2643system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2644system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2645system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2646system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2647system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency
2648system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 173857.694708 # average ReadReq mshr miss latency
2649system.iocache.ReadReq_avg_mshr_miss_latency::total 173510.184889 # average ReadReq mshr miss latency
2650system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2651system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2652system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73698.251134 # average WriteLineReq mshr miss latency
2653system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73698.251134 # average WriteLineReq mshr miss latency
2654system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2655system.iocache.demand_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency
2656system.iocache.demand_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency
2657system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2658system.iocache.overall_avg_mshr_miss_latency::realview.ide 81362.824897 # average overall mshr miss latency
2659system.iocache.overall_avg_mshr_miss_latency::total 81365.514817 # average overall mshr miss latency
2660system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2661system.l2c.tags.replacements 1396284 # number of replacements
2662system.l2c.tags.tagsinuse 65138.751942 # Cycle average of tags in use
2663system.l2c.tags.total_refs 7016729 # Total number of references to valid blocks.
2664system.l2c.tags.sampled_refs 1457215 # Sample count of references to valid blocks.
2665system.l2c.tags.avg_refs 4.815164 # Average number of references to valid blocks.
2666system.l2c.tags.warmup_cycle 8133240500 # Cycle when the warmup percentage was hit.
2667system.l2c.tags.occ_blocks::writebacks 10857.852094 # Average occupied blocks per requestor
2668system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.720367 # Average occupied blocks per requestor
2669system.l2c.tags.occ_blocks::cpu0.itb.walker 194.423316 # Average occupied blocks per requestor
2670system.l2c.tags.occ_blocks::cpu0.inst 4494.530949 # Average occupied blocks per requestor
2671system.l2c.tags.occ_blocks::cpu0.data 16342.707209 # Average occupied blocks per requestor
2672system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9582.831884 # Average occupied blocks per requestor
2673system.l2c.tags.occ_blocks::cpu1.dtb.walker 263.988799 # Average occupied blocks per requestor
2674system.l2c.tags.occ_blocks::cpu1.itb.walker 269.731759 # Average occupied blocks per requestor
2675system.l2c.tags.occ_blocks::cpu1.inst 4576.542600 # Average occupied blocks per requestor
2676system.l2c.tags.occ_blocks::cpu1.data 8162.860696 # Average occupied blocks per requestor
2677system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10199.562268 # Average occupied blocks per requestor
2678system.l2c.tags.occ_percent::writebacks 0.165678 # Average percentage of cache occupancy
2679system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002956 # Average percentage of cache occupancy
2680system.l2c.tags.occ_percent::cpu0.itb.walker 0.002967 # Average percentage of cache occupancy
2681system.l2c.tags.occ_percent::cpu0.inst 0.068581 # Average percentage of cache occupancy
2682system.l2c.tags.occ_percent::cpu0.data 0.249370 # Average percentage of cache occupancy
2683system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146222 # Average percentage of cache occupancy
2684system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004028 # Average percentage of cache occupancy
2685system.l2c.tags.occ_percent::cpu1.itb.walker 0.004116 # Average percentage of cache occupancy
2686system.l2c.tags.occ_percent::cpu1.inst 0.069832 # Average percentage of cache occupancy
2687system.l2c.tags.occ_percent::cpu1.data 0.124555 # Average percentage of cache occupancy
2688system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.155633 # Average percentage of cache occupancy
2689system.l2c.tags.occ_percent::total 0.993938 # Average percentage of cache occupancy
2690system.l2c.tags.occ_task_id_blocks::1022 9763 # Occupied blocks per task id
2691system.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id
2692system.l2c.tags.occ_task_id_blocks::1024 50927 # Occupied blocks per task id
2693system.l2c.tags.age_task_id_blocks_1022::2 80 # Occupied blocks per task id
2694system.l2c.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id
2695system.l2c.tags.age_task_id_blocks_1022::4 9269 # Occupied blocks per task id
2696system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id
2697system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
2698system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
2699system.l2c.tags.age_task_id_blocks_1024::2 1371 # Occupied blocks per task id
2700system.l2c.tags.age_task_id_blocks_1024::3 4645 # Occupied blocks per task id
2701system.l2c.tags.age_task_id_blocks_1024::4 44789 # Occupied blocks per task id
2702system.l2c.tags.occ_task_id_percent::1022 0.148972 # Percentage of cache occupancy per task id
2703system.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id
2704system.l2c.tags.occ_task_id_percent::1024 0.777084 # Percentage of cache occupancy per task id
2705system.l2c.tags.tag_accesses 77350226 # Number of tag accesses
2706system.l2c.tags.data_accesses 77350226 # Number of data accesses
2707system.l2c.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
2708system.l2c.WritebackDirty_hits::writebacks 2692321 # number of WritebackDirty hits
2709system.l2c.WritebackDirty_hits::total 2692321 # number of WritebackDirty hits
2710system.l2c.UpgradeReq_hits::cpu0.data 204225 # number of UpgradeReq hits
2711system.l2c.UpgradeReq_hits::cpu1.data 155483 # number of UpgradeReq hits
2712system.l2c.UpgradeReq_hits::total 359708 # number of UpgradeReq hits
2713system.l2c.SCUpgradeReq_hits::cpu0.data 52320 # number of SCUpgradeReq hits
2714system.l2c.SCUpgradeReq_hits::cpu1.data 51074 # number of SCUpgradeReq hits
2715system.l2c.SCUpgradeReq_hits::total 103394 # number of SCUpgradeReq hits
2716system.l2c.ReadExReq_hits::cpu0.data 55531 # number of ReadExReq hits
2717system.l2c.ReadExReq_hits::cpu1.data 51791 # number of ReadExReq hits
2718system.l2c.ReadExReq_hits::total 107322 # number of ReadExReq hits
2719system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13410 # number of ReadSharedReq hits
2720system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5332 # number of ReadSharedReq hits
2721system.l2c.ReadSharedReq_hits::cpu0.inst 636242 # number of ReadSharedReq hits
2722system.l2c.ReadSharedReq_hits::cpu0.data 595342 # number of ReadSharedReq hits
2723system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315678 # number of ReadSharedReq hits
2724system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10946 # number of ReadSharedReq hits
2725system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4404 # number of ReadSharedReq hits
2726system.l2c.ReadSharedReq_hits::cpu1.inst 639193 # number of ReadSharedReq hits
2727system.l2c.ReadSharedReq_hits::cpu1.data 560416 # number of ReadSharedReq hits
2728system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 301207 # number of ReadSharedReq hits
2729system.l2c.ReadSharedReq_hits::total 3082170 # number of ReadSharedReq hits
2730system.l2c.InvalidateReq_hits::cpu0.data 138800 # number of InvalidateReq hits
2731system.l2c.InvalidateReq_hits::cpu1.data 132737 # number of InvalidateReq hits
2732system.l2c.InvalidateReq_hits::total 271537 # number of InvalidateReq hits
2733system.l2c.demand_hits::cpu0.dtb.walker 13410 # number of demand (read+write) hits
2734system.l2c.demand_hits::cpu0.itb.walker 5332 # number of demand (read+write) hits
2735system.l2c.demand_hits::cpu0.inst 636242 # number of demand (read+write) hits
2736system.l2c.demand_hits::cpu0.data 650873 # number of demand (read+write) hits
2737system.l2c.demand_hits::cpu0.l2cache.prefetcher 315678 # number of demand (read+write) hits
2738system.l2c.demand_hits::cpu1.dtb.walker 10946 # number of demand (read+write) hits
2739system.l2c.demand_hits::cpu1.itb.walker 4404 # number of demand (read+write) hits
2740system.l2c.demand_hits::cpu1.inst 639193 # number of demand (read+write) hits
2741system.l2c.demand_hits::cpu1.data 612207 # number of demand (read+write) hits
2742system.l2c.demand_hits::cpu1.l2cache.prefetcher 301207 # number of demand (read+write) hits
2743system.l2c.demand_hits::total 3189492 # number of demand (read+write) hits
2744system.l2c.overall_hits::cpu0.dtb.walker 13410 # number of overall hits
2745system.l2c.overall_hits::cpu0.itb.walker 5332 # number of overall hits
2746system.l2c.overall_hits::cpu0.inst 636242 # number of overall hits
2747system.l2c.overall_hits::cpu0.data 650873 # number of overall hits
2748system.l2c.overall_hits::cpu0.l2cache.prefetcher 315678 # number of overall hits
2749system.l2c.overall_hits::cpu1.dtb.walker 10946 # number of overall hits
2750system.l2c.overall_hits::cpu1.itb.walker 4404 # number of overall hits
2751system.l2c.overall_hits::cpu1.inst 639193 # number of overall hits
2752system.l2c.overall_hits::cpu1.data 612207 # number of overall hits
2753system.l2c.overall_hits::cpu1.l2cache.prefetcher 301207 # number of overall hits
2754system.l2c.overall_hits::total 3189492 # number of overall hits
2755system.l2c.UpgradeReq_misses::cpu0.data 22618 # number of UpgradeReq misses
2756system.l2c.UpgradeReq_misses::cpu1.data 28127 # number of UpgradeReq misses
2757system.l2c.UpgradeReq_misses::total 50745 # number of UpgradeReq misses
2758system.l2c.SCUpgradeReq_misses::cpu0.data 499 # number of SCUpgradeReq misses
2759system.l2c.SCUpgradeReq_misses::cpu1.data 689 # number of SCUpgradeReq misses
2760system.l2c.SCUpgradeReq_misses::total 1188 # number of SCUpgradeReq misses
2761system.l2c.ReadExReq_misses::cpu0.data 80171 # number of ReadExReq misses
2762system.l2c.ReadExReq_misses::cpu1.data 45173 # number of ReadExReq misses
2763system.l2c.ReadExReq_misses::total 125344 # number of ReadExReq misses
2764system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq misses
2765system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1777 # number of ReadSharedReq misses
2766system.l2c.ReadSharedReq_misses::cpu0.inst 61929 # number of ReadSharedReq misses
2767system.l2c.ReadSharedReq_misses::cpu0.data 136966 # number of ReadSharedReq misses
2768system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 215441 # number of ReadSharedReq misses
2769system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq misses
2770system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1460 # number of ReadSharedReq misses
2771system.l2c.ReadSharedReq_misses::cpu1.inst 60807 # number of ReadSharedReq misses
2772system.l2c.ReadSharedReq_misses::cpu1.data 104797 # number of ReadSharedReq misses
2773system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq misses
2774system.l2c.ReadSharedReq_misses::total 773882 # number of ReadSharedReq misses
2775system.l2c.InvalidateReq_misses::cpu0.data 449504 # number of InvalidateReq misses
2776system.l2c.InvalidateReq_misses::cpu1.data 106576 # number of InvalidateReq misses
2777system.l2c.InvalidateReq_misses::total 556080 # number of InvalidateReq misses
2778system.l2c.demand_misses::cpu0.dtb.walker 1994 # number of demand (read+write) misses
2779system.l2c.demand_misses::cpu0.itb.walker 1777 # number of demand (read+write) misses
2780system.l2c.demand_misses::cpu0.inst 61929 # number of demand (read+write) misses
2781system.l2c.demand_misses::cpu0.data 217137 # number of demand (read+write) misses
2782system.l2c.demand_misses::cpu0.l2cache.prefetcher 215441 # number of demand (read+write) misses
2783system.l2c.demand_misses::cpu1.dtb.walker 1649 # number of demand (read+write) misses
2784system.l2c.demand_misses::cpu1.itb.walker 1460 # number of demand (read+write) misses
2785system.l2c.demand_misses::cpu1.inst 60807 # number of demand (read+write) misses
2786system.l2c.demand_misses::cpu1.data 149970 # number of demand (read+write) misses
2787system.l2c.demand_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) misses
2788system.l2c.demand_misses::total 899226 # number of demand (read+write) misses
2789system.l2c.overall_misses::cpu0.dtb.walker 1994 # number of overall misses
2790system.l2c.overall_misses::cpu0.itb.walker 1777 # number of overall misses
2791system.l2c.overall_misses::cpu0.inst 61929 # number of overall misses
2792system.l2c.overall_misses::cpu0.data 217137 # number of overall misses
2793system.l2c.overall_misses::cpu0.l2cache.prefetcher 215441 # number of overall misses
2794system.l2c.overall_misses::cpu1.dtb.walker 1649 # number of overall misses
2795system.l2c.overall_misses::cpu1.itb.walker 1460 # number of overall misses
2796system.l2c.overall_misses::cpu1.inst 60807 # number of overall misses
2797system.l2c.overall_misses::cpu1.data 149970 # number of overall misses
2798system.l2c.overall_misses::cpu1.l2cache.prefetcher 187062 # number of overall misses
2799system.l2c.overall_misses::total 899226 # number of overall misses
2800system.l2c.UpgradeReq_miss_latency::cpu0.data 166509500 # number of UpgradeReq miss cycles
2801system.l2c.UpgradeReq_miss_latency::cpu1.data 180855500 # number of UpgradeReq miss cycles
2802system.l2c.UpgradeReq_miss_latency::total 347365000 # number of UpgradeReq miss cycles
2803system.l2c.SCUpgradeReq_miss_latency::cpu0.data 6105500 # number of SCUpgradeReq miss cycles
2804system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8200500 # number of SCUpgradeReq miss cycles
2805system.l2c.SCUpgradeReq_miss_latency::total 14306000 # number of SCUpgradeReq miss cycles
2806system.l2c.ReadExReq_miss_latency::cpu0.data 8647457500 # number of ReadExReq miss cycles
2807system.l2c.ReadExReq_miss_latency::cpu1.data 4904092500 # number of ReadExReq miss cycles
2808system.l2c.ReadExReq_miss_latency::total 13551550000 # number of ReadExReq miss cycles
2809system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 211493000 # number of ReadSharedReq miss cycles
2810system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 194819500 # number of ReadSharedReq miss cycles
2811system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6896332000 # number of ReadSharedReq miss cycles
2812system.l2c.ReadSharedReq_miss_latency::cpu0.data 15165548000 # number of ReadSharedReq miss cycles
2813system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of ReadSharedReq miss cycles
2814system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 166890000 # number of ReadSharedReq miss cycles
2815system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 150626500 # number of ReadSharedReq miss cycles
2816system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6689940000 # number of ReadSharedReq miss cycles
2817system.l2c.ReadSharedReq_miss_latency::cpu1.data 12141260000 # number of ReadSharedReq miss cycles
2818system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of ReadSharedReq miss cycles
2819system.l2c.ReadSharedReq_miss_latency::total 97864036626 # number of ReadSharedReq miss cycles
2820system.l2c.InvalidateReq_miss_latency::cpu0.data 46615500 # number of InvalidateReq miss cycles
2821system.l2c.InvalidateReq_miss_latency::cpu1.data 36764000 # number of InvalidateReq miss cycles
2822system.l2c.InvalidateReq_miss_latency::total 83379500 # number of InvalidateReq miss cycles
2823system.l2c.demand_miss_latency::cpu0.dtb.walker 211493000 # number of demand (read+write) miss cycles
2824system.l2c.demand_miss_latency::cpu0.itb.walker 194819500 # number of demand (read+write) miss cycles
2825system.l2c.demand_miss_latency::cpu0.inst 6896332000 # number of demand (read+write) miss cycles
2826system.l2c.demand_miss_latency::cpu0.data 23813005500 # number of demand (read+write) miss cycles
2827system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of demand (read+write) miss cycles
2828system.l2c.demand_miss_latency::cpu1.dtb.walker 166890000 # number of demand (read+write) miss cycles
2829system.l2c.demand_miss_latency::cpu1.itb.walker 150626500 # number of demand (read+write) miss cycles
2830system.l2c.demand_miss_latency::cpu1.inst 6689940000 # number of demand (read+write) miss cycles
2831system.l2c.demand_miss_latency::cpu1.data 17045352500 # number of demand (read+write) miss cycles
2832system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of demand (read+write) miss cycles
2833system.l2c.demand_miss_latency::total 111415586626 # number of demand (read+write) miss cycles
2834system.l2c.overall_miss_latency::cpu0.dtb.walker 211493000 # number of overall miss cycles
2835system.l2c.overall_miss_latency::cpu0.itb.walker 194819500 # number of overall miss cycles
2836system.l2c.overall_miss_latency::cpu0.inst 6896332000 # number of overall miss cycles
2837system.l2c.overall_miss_latency::cpu0.data 23813005500 # number of overall miss cycles
2838system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30671403248 # number of overall miss cycles
2839system.l2c.overall_miss_latency::cpu1.dtb.walker 166890000 # number of overall miss cycles
2840system.l2c.overall_miss_latency::cpu1.itb.walker 150626500 # number of overall miss cycles
2841system.l2c.overall_miss_latency::cpu1.inst 6689940000 # number of overall miss cycles
2842system.l2c.overall_miss_latency::cpu1.data 17045352500 # number of overall miss cycles
2843system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 25575724378 # number of overall miss cycles
2844system.l2c.overall_miss_latency::total 111415586626 # number of overall miss cycles
2845system.l2c.WritebackDirty_accesses::writebacks 2692321 # number of WritebackDirty accesses(hits+misses)
2846system.l2c.WritebackDirty_accesses::total 2692321 # number of WritebackDirty accesses(hits+misses)
2847system.l2c.UpgradeReq_accesses::cpu0.data 226843 # number of UpgradeReq accesses(hits+misses)
2848system.l2c.UpgradeReq_accesses::cpu1.data 183610 # number of UpgradeReq accesses(hits+misses)
2849system.l2c.UpgradeReq_accesses::total 410453 # number of UpgradeReq accesses(hits+misses)
2850system.l2c.SCUpgradeReq_accesses::cpu0.data 52819 # number of SCUpgradeReq accesses(hits+misses)
2851system.l2c.SCUpgradeReq_accesses::cpu1.data 51763 # number of SCUpgradeReq accesses(hits+misses)
2852system.l2c.SCUpgradeReq_accesses::total 104582 # number of SCUpgradeReq accesses(hits+misses)
2853system.l2c.ReadExReq_accesses::cpu0.data 135702 # number of ReadExReq accesses(hits+misses)
2854system.l2c.ReadExReq_accesses::cpu1.data 96964 # number of ReadExReq accesses(hits+misses)
2855system.l2c.ReadExReq_accesses::total 232666 # number of ReadExReq accesses(hits+misses)
2856system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15404 # number of ReadSharedReq accesses(hits+misses)
2857system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7109 # number of ReadSharedReq accesses(hits+misses)
2858system.l2c.ReadSharedReq_accesses::cpu0.inst 698171 # number of ReadSharedReq accesses(hits+misses)
2859system.l2c.ReadSharedReq_accesses::cpu0.data 732308 # number of ReadSharedReq accesses(hits+misses)
2860system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 531119 # number of ReadSharedReq accesses(hits+misses)
2861system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12595 # number of ReadSharedReq accesses(hits+misses)
2862system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5864 # number of ReadSharedReq accesses(hits+misses)
2863system.l2c.ReadSharedReq_accesses::cpu1.inst 700000 # number of ReadSharedReq accesses(hits+misses)
2864system.l2c.ReadSharedReq_accesses::cpu1.data 665213 # number of ReadSharedReq accesses(hits+misses)
2865system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 488269 # number of ReadSharedReq accesses(hits+misses)
2866system.l2c.ReadSharedReq_accesses::total 3856052 # number of ReadSharedReq accesses(hits+misses)
2867system.l2c.InvalidateReq_accesses::cpu0.data 588304 # number of InvalidateReq accesses(hits+misses)
2868system.l2c.InvalidateReq_accesses::cpu1.data 239313 # number of InvalidateReq accesses(hits+misses)
2869system.l2c.InvalidateReq_accesses::total 827617 # number of InvalidateReq accesses(hits+misses)
2870system.l2c.demand_accesses::cpu0.dtb.walker 15404 # number of demand (read+write) accesses
2871system.l2c.demand_accesses::cpu0.itb.walker 7109 # number of demand (read+write) accesses
2872system.l2c.demand_accesses::cpu0.inst 698171 # number of demand (read+write) accesses
2873system.l2c.demand_accesses::cpu0.data 868010 # number of demand (read+write) accesses
2874system.l2c.demand_accesses::cpu0.l2cache.prefetcher 531119 # number of demand (read+write) accesses
2875system.l2c.demand_accesses::cpu1.dtb.walker 12595 # number of demand (read+write) accesses
2876system.l2c.demand_accesses::cpu1.itb.walker 5864 # number of demand (read+write) accesses
2877system.l2c.demand_accesses::cpu1.inst 700000 # number of demand (read+write) accesses
2878system.l2c.demand_accesses::cpu1.data 762177 # number of demand (read+write) accesses
2879system.l2c.demand_accesses::cpu1.l2cache.prefetcher 488269 # number of demand (read+write) accesses
2880system.l2c.demand_accesses::total 4088718 # number of demand (read+write) accesses
2881system.l2c.overall_accesses::cpu0.dtb.walker 15404 # number of overall (read+write) accesses
2882system.l2c.overall_accesses::cpu0.itb.walker 7109 # number of overall (read+write) accesses
2883system.l2c.overall_accesses::cpu0.inst 698171 # number of overall (read+write) accesses
2884system.l2c.overall_accesses::cpu0.data 868010 # number of overall (read+write) accesses
2885system.l2c.overall_accesses::cpu0.l2cache.prefetcher 531119 # number of overall (read+write) accesses
2886system.l2c.overall_accesses::cpu1.dtb.walker 12595 # number of overall (read+write) accesses
2887system.l2c.overall_accesses::cpu1.itb.walker 5864 # number of overall (read+write) accesses
2888system.l2c.overall_accesses::cpu1.inst 700000 # number of overall (read+write) accesses
2889system.l2c.overall_accesses::cpu1.data 762177 # number of overall (read+write) accesses
2890system.l2c.overall_accesses::cpu1.l2cache.prefetcher 488269 # number of overall (read+write) accesses
2891system.l2c.overall_accesses::total 4088718 # number of overall (read+write) accesses
2892system.l2c.UpgradeReq_miss_rate::cpu0.data 0.099708 # miss rate for UpgradeReq accesses
2893system.l2c.UpgradeReq_miss_rate::cpu1.data 0.153189 # miss rate for UpgradeReq accesses
2894system.l2c.UpgradeReq_miss_rate::total 0.123632 # miss rate for UpgradeReq accesses
2895system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.009447 # miss rate for SCUpgradeReq accesses
2896system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.013311 # miss rate for SCUpgradeReq accesses
2897system.l2c.SCUpgradeReq_miss_rate::total 0.011360 # miss rate for SCUpgradeReq accesses
2898system.l2c.ReadExReq_miss_rate::cpu0.data 0.590787 # miss rate for ReadExReq accesses
2899system.l2c.ReadExReq_miss_rate::cpu1.data 0.465874 # miss rate for ReadExReq accesses
2900system.l2c.ReadExReq_miss_rate::total 0.538729 # miss rate for ReadExReq accesses
2901system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for ReadSharedReq accesses
2902system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.249965 # miss rate for ReadSharedReq accesses
2903system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.088702 # miss rate for ReadSharedReq accesses
2904system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187033 # miss rate for ReadSharedReq accesses
2905system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for ReadSharedReq accesses
2906system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for ReadSharedReq accesses
2907system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.248977 # miss rate for ReadSharedReq accesses
2908system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086867 # miss rate for ReadSharedReq accesses
2909system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.157539 # miss rate for ReadSharedReq accesses
2910system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for ReadSharedReq accesses
2911system.l2c.ReadSharedReq_miss_rate::total 0.200693 # miss rate for ReadSharedReq accesses
2912system.l2c.InvalidateReq_miss_rate::cpu0.data 0.764068 # miss rate for InvalidateReq accesses
2913system.l2c.InvalidateReq_miss_rate::cpu1.data 0.445341 # miss rate for InvalidateReq accesses
2914system.l2c.InvalidateReq_miss_rate::total 0.671905 # miss rate for InvalidateReq accesses
2915system.l2c.demand_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for demand accesses
2916system.l2c.demand_miss_rate::cpu0.itb.walker 0.249965 # miss rate for demand accesses
2917system.l2c.demand_miss_rate::cpu0.inst 0.088702 # miss rate for demand accesses
2918system.l2c.demand_miss_rate::cpu0.data 0.250155 # miss rate for demand accesses
2919system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for demand accesses
2920system.l2c.demand_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for demand accesses
2921system.l2c.demand_miss_rate::cpu1.itb.walker 0.248977 # miss rate for demand accesses
2922system.l2c.demand_miss_rate::cpu1.inst 0.086867 # miss rate for demand accesses
2923system.l2c.demand_miss_rate::cpu1.data 0.196765 # miss rate for demand accesses
2924system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for demand accesses
2925system.l2c.demand_miss_rate::total 0.219929 # miss rate for demand accesses
2926system.l2c.overall_miss_rate::cpu0.dtb.walker 0.129447 # miss rate for overall accesses
2927system.l2c.overall_miss_rate::cpu0.itb.walker 0.249965 # miss rate for overall accesses
2928system.l2c.overall_miss_rate::cpu0.inst 0.088702 # miss rate for overall accesses
2929system.l2c.overall_miss_rate::cpu0.data 0.250155 # miss rate for overall accesses
2930system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.405636 # miss rate for overall accesses
2931system.l2c.overall_miss_rate::cpu1.dtb.walker 0.130925 # miss rate for overall accesses
2932system.l2c.overall_miss_rate::cpu1.itb.walker 0.248977 # miss rate for overall accesses
2933system.l2c.overall_miss_rate::cpu1.inst 0.086867 # miss rate for overall accesses
2934system.l2c.overall_miss_rate::cpu1.data 0.196765 # miss rate for overall accesses
2935system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383113 # miss rate for overall accesses
2936system.l2c.overall_miss_rate::total 0.219929 # miss rate for overall accesses
2937system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7361.813600 # average UpgradeReq miss latency
2938system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6429.960536 # average UpgradeReq miss latency
2939system.l2c.UpgradeReq_avg_miss_latency::total 6845.304956 # average UpgradeReq miss latency
2940system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12235.470942 # average SCUpgradeReq miss latency
2941system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11902.031930 # average SCUpgradeReq miss latency
2942system.l2c.SCUpgradeReq_avg_miss_latency::total 12042.087542 # average SCUpgradeReq miss latency
2943system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107862.662309 # average ReadExReq miss latency
2944system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108562.470945 # average ReadExReq miss latency
2945system.l2c.ReadExReq_avg_miss_latency::total 108114.867884 # average ReadExReq miss latency
2946system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average ReadSharedReq miss latency
2947system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 109633.933596 # average ReadSharedReq miss latency
2948system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 111358.684946 # average ReadSharedReq miss latency
2949system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 110724.909832 # average ReadSharedReq miss latency
2950system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average ReadSharedReq miss latency
2951system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average ReadSharedReq miss latency
2952system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103168.835616 # average ReadSharedReq miss latency
2953system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 110019.241206 # average ReadSharedReq miss latency
2954system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115855.034018 # average ReadSharedReq miss latency
2955system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average ReadSharedReq miss latency
2956system.l2c.ReadSharedReq_avg_miss_latency::total 126458.603025 # average ReadSharedReq miss latency
2957system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 103.704305 # average InvalidateReq miss latency
2958system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 344.955712 # average InvalidateReq miss latency
2959system.l2c.InvalidateReq_avg_miss_latency::total 149.941555 # average InvalidateReq miss latency
2960system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency
2961system.l2c.demand_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency
2962system.l2c.demand_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency
2963system.l2c.demand_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency
2964system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency
2965system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency
2966system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency
2967system.l2c.demand_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency
2968system.l2c.demand_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency
2969system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency
2970system.l2c.demand_avg_miss_latency::total 123901.651672 # average overall miss latency
2971system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 106064.694082 # average overall miss latency
2972system.l2c.overall_avg_miss_latency::cpu0.itb.walker 109633.933596 # average overall miss latency
2973system.l2c.overall_avg_miss_latency::cpu0.inst 111358.684946 # average overall miss latency
2974system.l2c.overall_avg_miss_latency::cpu0.data 109668.115061 # average overall miss latency
2975system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 142365.674352 # average overall miss latency
2976system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101206.791995 # average overall miss latency
2977system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103168.835616 # average overall miss latency
2978system.l2c.overall_avg_miss_latency::cpu1.inst 110019.241206 # average overall miss latency
2979system.l2c.overall_avg_miss_latency::cpu1.data 113658.415016 # average overall miss latency
2980system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136723.248859 # average overall miss latency
2981system.l2c.overall_avg_miss_latency::total 123901.651672 # average overall miss latency
2982system.l2c.blocked_cycles::no_mshrs 622 # number of cycles access was blocked
2983system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2984system.l2c.blocked::no_mshrs 12 # number of cycles access was blocked
2985system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2986system.l2c.avg_blocked_cycles::no_mshrs 51.833333 # average number of cycles each access was blocked
2987system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2988system.l2c.writebacks::writebacks 1054868 # number of writebacks
2989system.l2c.writebacks::total 1054868 # number of writebacks
2990system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits
2991system.l2c.ReadSharedReq_mshr_hits::cpu0.data 25 # number of ReadSharedReq MSHR hits
2992system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
2993system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 132 # number of ReadSharedReq MSHR hits
2994system.l2c.ReadSharedReq_mshr_hits::cpu1.data 14 # number of ReadSharedReq MSHR hits
2995system.l2c.ReadSharedReq_mshr_hits::total 311 # number of ReadSharedReq MSHR hits
2996system.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits
2997system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits
2998system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
2999system.l2c.demand_mshr_hits::cpu1.inst 132 # number of demand (read+write) MSHR hits
3000system.l2c.demand_mshr_hits::cpu1.data 14 # number of demand (read+write) MSHR hits
3001system.l2c.demand_mshr_hits::total 311 # number of demand (read+write) MSHR hits
3002system.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits
3003system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits
3004system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits
3005system.l2c.overall_mshr_hits::cpu1.inst 132 # number of overall MSHR hits
3006system.l2c.overall_mshr_hits::cpu1.data 14 # number of overall MSHR hits
3007system.l2c.overall_mshr_hits::total 311 # number of overall MSHR hits
3008system.l2c.CleanEvict_mshr_misses::writebacks 56418 # number of CleanEvict MSHR misses
3009system.l2c.CleanEvict_mshr_misses::total 56418 # number of CleanEvict MSHR misses
3010system.l2c.UpgradeReq_mshr_misses::cpu0.data 22618 # number of UpgradeReq MSHR misses
3011system.l2c.UpgradeReq_mshr_misses::cpu1.data 28127 # number of UpgradeReq MSHR misses
3012system.l2c.UpgradeReq_mshr_misses::total 50745 # number of UpgradeReq MSHR misses
3013system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 499 # number of SCUpgradeReq MSHR misses
3014system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 689 # number of SCUpgradeReq MSHR misses
3015system.l2c.SCUpgradeReq_mshr_misses::total 1188 # number of SCUpgradeReq MSHR misses
3016system.l2c.ReadExReq_mshr_misses::cpu0.data 80171 # number of ReadExReq MSHR misses
3017system.l2c.ReadExReq_mshr_misses::cpu1.data 45173 # number of ReadExReq MSHR misses
3018system.l2c.ReadExReq_mshr_misses::total 125344 # number of ReadExReq MSHR misses
3019system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1994 # number of ReadSharedReq MSHR misses
3020system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1777 # number of ReadSharedReq MSHR misses
3021system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 61790 # number of ReadSharedReq MSHR misses
3022system.l2c.ReadSharedReq_mshr_misses::cpu0.data 136941 # number of ReadSharedReq MSHR misses
3023system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of ReadSharedReq MSHR misses
3024system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1649 # number of ReadSharedReq MSHR misses
3025system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1460 # number of ReadSharedReq MSHR misses
3026system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 60675 # number of ReadSharedReq MSHR misses
3027system.l2c.ReadSharedReq_mshr_misses::cpu1.data 104783 # number of ReadSharedReq MSHR misses
3028system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of ReadSharedReq MSHR misses
3029system.l2c.ReadSharedReq_mshr_misses::total 773571 # number of ReadSharedReq MSHR misses
3030system.l2c.InvalidateReq_mshr_misses::cpu0.data 449504 # number of InvalidateReq MSHR misses
3031system.l2c.InvalidateReq_mshr_misses::cpu1.data 106576 # number of InvalidateReq MSHR misses
3032system.l2c.InvalidateReq_mshr_misses::total 556080 # number of InvalidateReq MSHR misses
3033system.l2c.demand_mshr_misses::cpu0.dtb.walker 1994 # number of demand (read+write) MSHR misses
3034system.l2c.demand_mshr_misses::cpu0.itb.walker 1777 # number of demand (read+write) MSHR misses
3035system.l2c.demand_mshr_misses::cpu0.inst 61790 # number of demand (read+write) MSHR misses
3036system.l2c.demand_mshr_misses::cpu0.data 217112 # number of demand (read+write) MSHR misses
3037system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 215440 # number of demand (read+write) MSHR misses
3038system.l2c.demand_mshr_misses::cpu1.dtb.walker 1649 # number of demand (read+write) MSHR misses
3039system.l2c.demand_mshr_misses::cpu1.itb.walker 1460 # number of demand (read+write) MSHR misses
3040system.l2c.demand_mshr_misses::cpu1.inst 60675 # number of demand (read+write) MSHR misses
3041system.l2c.demand_mshr_misses::cpu1.data 149956 # number of demand (read+write) MSHR misses
3042system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of demand (read+write) MSHR misses
3043system.l2c.demand_mshr_misses::total 898915 # number of demand (read+write) MSHR misses
3044system.l2c.overall_mshr_misses::cpu0.dtb.walker 1994 # number of overall MSHR misses
3045system.l2c.overall_mshr_misses::cpu0.itb.walker 1777 # number of overall MSHR misses
3046system.l2c.overall_mshr_misses::cpu0.inst 61790 # number of overall MSHR misses
3047system.l2c.overall_mshr_misses::cpu0.data 217112 # number of overall MSHR misses
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3049system.l2c.overall_mshr_misses::cpu1.dtb.walker 1649 # number of overall MSHR misses
3050system.l2c.overall_mshr_misses::cpu1.itb.walker 1460 # number of overall MSHR misses
3051system.l2c.overall_mshr_misses::cpu1.inst 60675 # number of overall MSHR misses
3052system.l2c.overall_mshr_misses::cpu1.data 149956 # number of overall MSHR misses
3053system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 187062 # number of overall MSHR misses
3054system.l2c.overall_mshr_misses::total 898915 # number of overall MSHR misses
3055system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52284 # number of ReadReq MSHR uncacheable
3056system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31212 # number of ReadReq MSHR uncacheable
3057system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
3058system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7181 # number of ReadReq MSHR uncacheable
3059system.l2c.ReadReq_mshr_uncacheable::total 90772 # number of ReadReq MSHR uncacheable
3060system.l2c.WriteReq_mshr_uncacheable::cpu0.data 30755 # number of WriteReq MSHR uncacheable
3061system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7509 # number of WriteReq MSHR uncacheable
3062system.l2c.WriteReq_mshr_uncacheable::total 38264 # number of WriteReq MSHR uncacheable
3063system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52284 # number of overall MSHR uncacheable misses
3064system.l2c.overall_mshr_uncacheable_misses::cpu0.data 61967 # number of overall MSHR uncacheable misses
3065system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
3066system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14690 # number of overall MSHR uncacheable misses
3067system.l2c.overall_mshr_uncacheable_misses::total 129036 # number of overall MSHR uncacheable misses
3068system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 461841000 # number of UpgradeReq MSHR miss cycles
3069system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 578903500 # number of UpgradeReq MSHR miss cycles
3070system.l2c.UpgradeReq_mshr_miss_latency::total 1040744500 # number of UpgradeReq MSHR miss cycles
3071system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 11863000 # number of SCUpgradeReq MSHR miss cycles
3072system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 16565000 # number of SCUpgradeReq MSHR miss cycles
3073system.l2c.SCUpgradeReq_mshr_miss_latency::total 28428000 # number of SCUpgradeReq MSHR miss cycles
3074system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7845723550 # number of ReadExReq MSHR miss cycles
3075system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4452337552 # number of ReadExReq MSHR miss cycles
3076system.l2c.ReadExReq_mshr_miss_latency::total 12298061102 # number of ReadExReq MSHR miss cycles
3077system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of ReadSharedReq MSHR miss cycles
3078system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 177048502 # number of ReadSharedReq MSHR miss cycles
3079system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6267361033 # number of ReadSharedReq MSHR miss cycles
3080system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 13793559696 # number of ReadSharedReq MSHR miss cycles
3081system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of ReadSharedReq MSHR miss cycles
3082system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of ReadSharedReq MSHR miss cycles
3083system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 136026500 # number of ReadSharedReq MSHR miss cycles
3084system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6069566554 # number of ReadSharedReq MSHR miss cycles
3085system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11092033207 # number of ReadSharedReq MSHR miss cycles
3086system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of ReadSharedReq MSHR miss cycles
3087system.l2c.ReadSharedReq_mshr_miss_latency::total 90099351689 # number of ReadSharedReq MSHR miss cycles
3088system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 9394175000 # number of InvalidateReq MSHR miss cycles
3089system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2170818500 # number of InvalidateReq MSHR miss cycles
3090system.l2c.InvalidateReq_mshr_miss_latency::total 11564993500 # number of InvalidateReq MSHR miss cycles
3091system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of demand (read+write) MSHR miss cycles
3092system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 177048502 # number of demand (read+write) MSHR miss cycles
3093system.l2c.demand_mshr_miss_latency::cpu0.inst 6267361033 # number of demand (read+write) MSHR miss cycles
3094system.l2c.demand_mshr_miss_latency::cpu0.data 21639283246 # number of demand (read+write) MSHR miss cycles
3095system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of demand (read+write) MSHR miss cycles
3096system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of demand (read+write) MSHR miss cycles
3097system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 136026500 # number of demand (read+write) MSHR miss cycles
3098system.l2c.demand_mshr_miss_latency::cpu1.inst 6069566554 # number of demand (read+write) MSHR miss cycles
3099system.l2c.demand_mshr_miss_latency::cpu1.data 15544370759 # number of demand (read+write) MSHR miss cycles
3100system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of demand (read+write) MSHR miss cycles
3101system.l2c.demand_mshr_miss_latency::total 102397412791 # number of demand (read+write) MSHR miss cycles
3102system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 191553000 # number of overall MSHR miss cycles
3103system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 177048502 # number of overall MSHR miss cycles
3104system.l2c.overall_mshr_miss_latency::cpu0.inst 6267361033 # number of overall MSHR miss cycles
3105system.l2c.overall_mshr_miss_latency::cpu0.data 21639283246 # number of overall MSHR miss cycles
3106system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28516814074 # number of overall MSHR miss cycles
3107system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 150400000 # number of overall MSHR miss cycles
3108system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 136026500 # number of overall MSHR miss cycles
3109system.l2c.overall_mshr_miss_latency::cpu1.inst 6069566554 # number of overall MSHR miss cycles
3110system.l2c.overall_mshr_miss_latency::cpu1.data 15544370759 # number of overall MSHR miss cycles
3111system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23704989123 # number of overall MSHR miss cycles
3112system.l2c.overall_mshr_miss_latency::total 102397412791 # number of overall MSHR miss cycles
3113system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of ReadReq MSHR uncacheable cycles
3114system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5226952503 # number of ReadReq MSHR uncacheable cycles
3115system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7066500 # number of ReadReq MSHR uncacheable cycles
3116system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 731143001 # number of ReadReq MSHR uncacheable cycles
3117system.l2c.ReadReq_mshr_uncacheable_latency::total 9610531504 # number of ReadReq MSHR uncacheable cycles
3118system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3645369500 # number of overall MSHR uncacheable cycles
3119system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5226952503 # number of overall MSHR uncacheable cycles
3120system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7066500 # number of overall MSHR uncacheable cycles
3121system.l2c.overall_mshr_uncacheable_latency::cpu1.data 731143001 # number of overall MSHR uncacheable cycles
3122system.l2c.overall_mshr_uncacheable_latency::total 9610531504 # number of overall MSHR uncacheable cycles
3123system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3124system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3125system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.099708 # mshr miss rate for UpgradeReq accesses
3126system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.153189 # mshr miss rate for UpgradeReq accesses
3127system.l2c.UpgradeReq_mshr_miss_rate::total 0.123632 # mshr miss rate for UpgradeReq accesses
3128system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.009447 # mshr miss rate for SCUpgradeReq accesses
3129system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.013311 # mshr miss rate for SCUpgradeReq accesses
3130system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.011360 # mshr miss rate for SCUpgradeReq accesses
3131system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590787 # mshr miss rate for ReadExReq accesses
3132system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465874 # mshr miss rate for ReadExReq accesses
3133system.l2c.ReadExReq_mshr_miss_rate::total 0.538729 # mshr miss rate for ReadExReq accesses
3134system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for ReadSharedReq accesses
3135system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for ReadSharedReq accesses
3136system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for ReadSharedReq accesses
3137system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186999 # mshr miss rate for ReadSharedReq accesses
3138system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for ReadSharedReq accesses
3139system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for ReadSharedReq accesses
3140system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for ReadSharedReq accesses
3141system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for ReadSharedReq accesses
3142system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.157518 # mshr miss rate for ReadSharedReq accesses
3143system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for ReadSharedReq accesses
3144system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200612 # mshr miss rate for ReadSharedReq accesses
3145system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.764068 # mshr miss rate for InvalidateReq accesses
3146system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.445341 # mshr miss rate for InvalidateReq accesses
3147system.l2c.InvalidateReq_mshr_miss_rate::total 0.671905 # mshr miss rate for InvalidateReq accesses
3148system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for demand accesses
3149system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for demand accesses
3150system.l2c.demand_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for demand accesses
3151system.l2c.demand_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for demand accesses
3152system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for demand accesses
3153system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for demand accesses
3154system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for demand accesses
3155system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for demand accesses
3156system.l2c.demand_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for demand accesses
3157system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for demand accesses
3158system.l2c.demand_mshr_miss_rate::total 0.219853 # mshr miss rate for demand accesses
3159system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.129447 # mshr miss rate for overall accesses
3160system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.249965 # mshr miss rate for overall accesses
3161system.l2c.overall_mshr_miss_rate::cpu0.inst 0.088503 # mshr miss rate for overall accesses
3162system.l2c.overall_mshr_miss_rate::cpu0.data 0.250126 # mshr miss rate for overall accesses
3163system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.405634 # mshr miss rate for overall accesses
3164system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.130925 # mshr miss rate for overall accesses
3165system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.248977 # mshr miss rate for overall accesses
3166system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086679 # mshr miss rate for overall accesses
3167system.l2c.overall_mshr_miss_rate::cpu1.data 0.196747 # mshr miss rate for overall accesses
3168system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383113 # mshr miss rate for overall accesses
3169system.l2c.overall_mshr_miss_rate::total 0.219853 # mshr miss rate for overall accesses
3170system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20419.179415 # average UpgradeReq mshr miss latency
3171system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20581.771963 # average UpgradeReq mshr miss latency
3172system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20509.301409 # average UpgradeReq mshr miss latency
3173system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23773.547094 # average SCUpgradeReq mshr miss latency
3174system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24042.089985 # average SCUpgradeReq mshr miss latency
3175system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 23929.292929 # average SCUpgradeReq mshr miss latency
3176system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97862.363573 # average ReadExReq mshr miss latency
3177system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98561.918668 # average ReadExReq mshr miss latency
3178system.l2c.ReadExReq_avg_mshr_miss_latency::total 98114.477773 # average ReadExReq mshr miss latency
3179system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average ReadSharedReq mshr miss latency
3180system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average ReadSharedReq mshr miss latency
3181system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average ReadSharedReq mshr miss latency
3182system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 100726.295967 # average ReadSharedReq mshr miss latency
3183system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average ReadSharedReq mshr miss latency
3184system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average ReadSharedReq mshr miss latency
3185system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average ReadSharedReq mshr miss latency
3186system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average ReadSharedReq mshr miss latency
3187system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105857.183007 # average ReadSharedReq mshr miss latency
3188system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average ReadSharedReq mshr miss latency
3189system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116471.987302 # average ReadSharedReq mshr miss latency
3190system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20898.979764 # average InvalidateReq mshr miss latency
3191system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20368.736864 # average InvalidateReq mshr miss latency
3192system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20797.355596 # average InvalidateReq mshr miss latency
3193system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency
3194system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency
3195system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency
3196system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency
3197system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency
3198system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency
3199system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency
3200system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency
3201system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency
3202system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency
3203system.l2c.demand_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency
3204system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 96064.694082 # average overall mshr miss latency
3205system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 99633.371975 # average overall mshr miss latency
3206system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 101430.021573 # average overall mshr miss latency
3207system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99668.757351 # average overall mshr miss latency
3208system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 132365.457083 # average overall mshr miss latency
3209system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91206.791995 # average overall mshr miss latency
3210system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93168.835616 # average overall mshr miss latency
3211system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 100034.059398 # average overall mshr miss latency
3212system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103659.545193 # average overall mshr miss latency
3213system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126722.632726 # average overall mshr miss latency
3214system.l2c.overall_avg_mshr_miss_latency::total 113912.230624 # average overall mshr miss latency
3215system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average ReadReq mshr uncacheable latency
3216system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167466.118897 # average ReadReq mshr uncacheable latency
3217system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average ReadReq mshr uncacheable latency
3218system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101816.320986 # average ReadReq mshr uncacheable latency
3219system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 105875.506808 # average ReadReq mshr uncacheable latency
3220system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69722.467677 # average overall mshr uncacheable latency
3221system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84350.581810 # average overall mshr uncacheable latency
3222system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 74384.210526 # average overall mshr uncacheable latency
3223system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 49771.477263 # average overall mshr uncacheable latency
3224system.l2c.overall_avg_mshr_uncacheable_latency::total 74479.459252 # average overall mshr uncacheable latency
3225system.membus.snoop_filter.tot_requests 3616665 # Total number of requests made to the snoop filter.
3226system.membus.snoop_filter.hit_single_requests 2148581 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3227system.membus.snoop_filter.hit_multi_requests 2925 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3228system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3229system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3230system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3231system.membus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3232system.membus.trans_dist::ReadReq 90772 # Transaction distribution
3233system.membus.trans_dist::ReadResp 873224 # Transaction distribution
3234system.membus.trans_dist::WriteReq 38264 # Transaction distribution
3235system.membus.trans_dist::WriteResp 38264 # Transaction distribution
3236system.membus.trans_dist::WritebackDirty 1161561 # Transaction distribution
3237system.membus.trans_dist::CleanEvict 250705 # Transaction distribution
3238system.membus.trans_dist::UpgradeReq 347946 # Transaction distribution
3239system.membus.trans_dist::SCUpgradeReq 273520 # Transaction distribution
3240system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
3241system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
3242system.membus.trans_dist::ReadExReq 139972 # Transaction distribution
3243system.membus.trans_dist::ReadExResp 124377 # Transaction distribution
3244system.membus.trans_dist::ReadSharedReq 782452 # Transaction distribution
3245system.membus.trans_dist::InvalidateReq 660097 # Transaction distribution
3246system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122510 # Packet count per connected master and slave (bytes)
3247system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
3248system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25584 # Packet count per connected master and slave (bytes)
3249system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4392225 # Packet count per connected master and slave (bytes)
3250system.membus.pkt_count_system.l2c.mem_side::total 4540373 # Packet count per connected master and slave (bytes)
3251system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238087 # Packet count per connected master and slave (bytes)
3252system.membus.pkt_count_system.iocache.mem_side::total 238087 # Packet count per connected master and slave (bytes)
3253system.membus.pkt_count::total 4778460 # Packet count per connected master and slave (bytes)
3254system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes)
3255system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
3256system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51168 # Cumulative packet size per connected master and slave (bytes)
3257system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128305664 # Cumulative packet size per connected master and slave (bytes)
3258system.membus.pkt_size_system.l2c.mem_side::total 128513860 # Cumulative packet size per connected master and slave (bytes)
3259system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7270464 # Cumulative packet size per connected master and slave (bytes)
3260system.membus.pkt_size_system.iocache.mem_side::total 7270464 # Cumulative packet size per connected master and slave (bytes)
3261system.membus.pkt_size::total 135784324 # Cumulative packet size per connected master and slave (bytes)
3262system.membus.snoops 584171 # Total snoops (count)
3263system.membus.snoopTraffic 172608 # Total snoop traffic (bytes)
3264system.membus.snoop_fanout::samples 2333030 # Request fanout histogram
3265system.membus.snoop_fanout::mean 0.013166 # Request fanout histogram
3266system.membus.snoop_fanout::stdev 0.113984 # Request fanout histogram
3267system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3268system.membus.snoop_fanout::0 2302314 98.68% 98.68% # Request fanout histogram
3269system.membus.snoop_fanout::1 30716 1.32% 100.00% # Request fanout histogram
3270system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3271system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3272system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3273system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3274system.membus.snoop_fanout::total 2333030 # Request fanout histogram
3275system.membus.reqLayer0.occupancy 103320999 # Layer occupancy (ticks)
3276system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3277system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
3278system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3279system.membus.reqLayer2.occupancy 21353996 # Layer occupancy (ticks)
3280system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3281system.membus.reqLayer5.occupancy 8035790677 # Layer occupancy (ticks)
3282system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3283system.membus.respLayer2.occupancy 5121349382 # Layer occupancy (ticks)
3284system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3285system.membus.respLayer3.occupancy 45284261 # Layer occupancy (ticks)
3286system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3287system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3288system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3289system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3290system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3291system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3292system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3293system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3294system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3295system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3296system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3297system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3298system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3299system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3300system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3301system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3302system.realview.ethernet.txBytes 966 # Bytes Transmitted
3303system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3304system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3305system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3306system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3307system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3308system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3309system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

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3336system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3337system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3338system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3339system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3340system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3341system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3342system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3343system.realview.ethernet.droppedPackets 0 # number of packets dropped
3344system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3345system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3346system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3347system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3348system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3349system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3350system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3351system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3352system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3353system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3354system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3355system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3356system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3357system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3358system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3359system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3360system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3361system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3362system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3363system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3364system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3365system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3366system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3367system.toL2Bus.snoop_filter.tot_requests 12127091 # Total number of requests made to the snoop filter.
3368system.toL2Bus.snoop_filter.hit_single_requests 6563266 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3369system.toL2Bus.snoop_filter.hit_multi_requests 2068389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3370system.toL2Bus.snoop_filter.tot_snoops 180040 # Total number of snoops made to the snoop filter.
3371system.toL2Bus.snoop_filter.hit_single_snoops 163507 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3372system.toL2Bus.snoop_filter.hit_multi_snoops 16533 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3373system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47554910274000 # Cumulative time (in ticks) in various power states
3374system.toL2Bus.trans_dist::ReadReq 90774 # Transaction distribution
3375system.toL2Bus.trans_dist::ReadResp 4717359 # Transaction distribution
3376system.toL2Bus.trans_dist::WriteReq 38264 # Transaction distribution
3377system.toL2Bus.trans_dist::WriteResp 38264 # Transaction distribution
3378system.toL2Bus.trans_dist::WritebackDirty 3747189 # Transaction distribution
3379system.toL2Bus.trans_dist::CleanEvict 2956256 # Transaction distribution
3380system.toL2Bus.trans_dist::UpgradeReq 703976 # Transaction distribution
3381system.toL2Bus.trans_dist::SCUpgradeReq 376914 # Transaction distribution
3382system.toL2Bus.trans_dist::UpgradeResp 1080890 # Transaction distribution
3383system.toL2Bus.trans_dist::SCUpgradeFailReq 83 # Transaction distribution
3384system.toL2Bus.trans_dist::UpgradeFailResp 83 # Transaction distribution
3385system.toL2Bus.trans_dist::ReadExReq 286236 # Transaction distribution
3386system.toL2Bus.trans_dist::ReadExResp 286236 # Transaction distribution
3387system.toL2Bus.trans_dist::ReadSharedReq 4627139 # Transaction distribution
3388system.toL2Bus.trans_dist::InvalidateReq 855379 # Transaction distribution
3389system.toL2Bus.trans_dist::InvalidateResp 827617 # Transaction distribution
3390system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9817286 # Packet count per connected master and slave (bytes)
3391system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8000729 # Packet count per connected master and slave (bytes)
3392system.toL2Bus.pkt_count::total 17818015 # Packet count per connected master and slave (bytes)
3393system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243574806 # Cumulative packet size per connected master and slave (bytes)
3394system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194096942 # Cumulative packet size per connected master and slave (bytes)
3395system.toL2Bus.pkt_size::total 437671748 # Cumulative packet size per connected master and slave (bytes)
3396system.toL2Bus.snoops 2816292 # Total snoops (count)
3397system.toL2Bus.snoopTraffic 120259472 # Total snoop traffic (bytes)
3398system.toL2Bus.snoop_fanout::samples 8375094 # Request fanout histogram
3399system.toL2Bus.snoop_fanout::mean 0.374182 # Request fanout histogram
3400system.toL2Bus.snoop_fanout::stdev 0.487973 # Request fanout histogram
3401system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3402system.toL2Bus.snoop_fanout::0 5257818 62.78% 62.78% # Request fanout histogram
3403system.toL2Bus.snoop_fanout::1 3100743 37.02% 99.80% # Request fanout histogram
3404system.toL2Bus.snoop_fanout::2 16533 0.20% 100.00% # Request fanout histogram
3405system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3406system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3407system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3408system.toL2Bus.snoop_fanout::total 8375094 # Request fanout histogram
3409system.toL2Bus.reqLayer0.occupancy 9230074402 # Layer occupancy (ticks)
3410system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3411system.toL2Bus.snoopLayer0.occupancy 2547405 # Layer occupancy (ticks)
3412system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3413system.toL2Bus.respLayer0.occupancy 4495965489 # Layer occupancy (ticks)
3414system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3415system.toL2Bus.respLayer1.occupancy 3978820805 # Layer occupancy (ticks)
3416system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3417
3418---------- End Simulation Statistics ----------