1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.381683 # Number of seconds simulated
4sim_ticks 47381683294000 # Number of ticks simulated
5final_tick 47381683294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 169119 # Simulator instruction rate (inst/s)
8host_op_rate 198983 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9178439782 # Simulator tick rate (ticks/s)
10host_mem_usage 757568 # Number of bytes of host memory used
11host_seconds 5162.28 # Real time elapsed on the host
12sim_insts 873041938 # Number of instructions simulated
13sim_ops 1027205539 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 75648 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 7273408 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 37833736 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 11654720 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 106816 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 96448 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3691584 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 15254352 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 10772160 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 424448 # Number of bytes read from this memory
27system.physmem.bytes_read::total 87268888 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 7273408 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3691584 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 10964992 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 68656704 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 68677288 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1182 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 113647 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 591165 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 182105 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 1669 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1507 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 57681 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 238362 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 168315 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6632 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1363602 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1072761 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1075335 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 1806 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 1597 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 798489 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 245975 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 2254 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 2036 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 77912 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 321946 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 227349 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 8958 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1841828 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 77912 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 231418 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1449014 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1449448 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1449014 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 1597 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 798923 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 245975 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 2254 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 2036 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 77912 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 321946 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 227349 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 8958 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3291276 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1363603 # Number of read requests accepted
84system.physmem.writeReqs 1075335 # Number of write requests accepted
85system.physmem.readBursts 1363603 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1075335 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 87237120 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue
89system.physmem.bytesWritten 68675712 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 87268952 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 68677288 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 497625 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 80650 # Per bank write bursts
96system.physmem.perBankRdBursts::1 88729 # Per bank write bursts
97system.physmem.perBankRdBursts::2 73569 # Per bank write bursts
98system.physmem.perBankRdBursts::3 80330 # Per bank write bursts
99system.physmem.perBankRdBursts::4 79168 # Per bank write bursts
100system.physmem.perBankRdBursts::5 89219 # Per bank write bursts
101system.physmem.perBankRdBursts::6 76757 # Per bank write bursts
102system.physmem.perBankRdBursts::7 80146 # Per bank write bursts
103system.physmem.perBankRdBursts::8 80110 # Per bank write bursts
104system.physmem.perBankRdBursts::9 145487 # Per bank write bursts
105system.physmem.perBankRdBursts::10 85462 # Per bank write bursts
106system.physmem.perBankRdBursts::11 91495 # Per bank write bursts
107system.physmem.perBankRdBursts::12 74671 # Per bank write bursts
108system.physmem.perBankRdBursts::13 80575 # Per bank write bursts
109system.physmem.perBankRdBursts::14 75276 # Per bank write bursts
110system.physmem.perBankRdBursts::15 81436 # Per bank write bursts
111system.physmem.perBankWrBursts::0 65415 # Per bank write bursts
112system.physmem.perBankWrBursts::1 72062 # Per bank write bursts
113system.physmem.perBankWrBursts::2 62920 # Per bank write bursts
114system.physmem.perBankWrBursts::3 67234 # Per bank write bursts
115system.physmem.perBankWrBursts::4 65543 # Per bank write bursts
116system.physmem.perBankWrBursts::5 71204 # Per bank write bursts
117system.physmem.perBankWrBursts::6 63108 # Per bank write bursts
118system.physmem.perBankWrBursts::7 65618 # Per bank write bursts
119system.physmem.perBankWrBursts::8 64627 # Per bank write bursts
120system.physmem.perBankWrBursts::9 73983 # Per bank write bursts
121system.physmem.perBankWrBursts::10 67070 # Per bank write bursts
122system.physmem.perBankWrBursts::11 71654 # Per bank write bursts
123system.physmem.perBankWrBursts::12 63584 # Per bank write bursts
124system.physmem.perBankWrBursts::13 67795 # Per bank write bursts
125system.physmem.perBankWrBursts::14 63419 # Per bank write bursts
126system.physmem.perBankWrBursts::15 67822 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 20 # Number of times write queue was full causing retry
129system.physmem.totGap 47381681282500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1363573 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1072761 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 866656 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 332331 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 37458 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 26767 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 22591 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 20794 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 18575 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 16649 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 13953 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 2927 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 1423 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 882 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 650 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 423 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 256 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 225 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 182 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 162 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 96 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see

--- 6 unchanged lines hidden (view full) ---

183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 18197 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 20578 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 39692 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 50721 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 56749 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 59564 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 63294 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 64512 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 67826 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 69607 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 74517 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 70375 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 69942 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 75013 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 68273 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 64139 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 61949 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 1753 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 1150 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 769 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 679 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 540 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 363 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 392 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 316 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 401 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 286 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 290 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 277 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 272 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 198 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 149 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 141 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 133 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 845070 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 184.496716 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 112.937858 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 245.074486 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 518646 61.37% 61.37% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 158346 18.74% 80.11% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 53030 6.28% 86.39% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 28124 3.33% 89.71% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 18210 2.15% 91.87% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11789 1.40% 93.26% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 8638 1.02% 94.29% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 8488 1.00% 95.29% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 39799 4.71% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 845070 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 60101 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 22.679190 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 352.199560 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 60098 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 60101 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 60101 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.854245 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.273539 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 7.223401 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 56328 93.72% 93.72% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 1584 2.64% 96.36% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 235 0.39% 96.75% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 339 0.56% 97.31% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 81 0.13% 97.45% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 304 0.51% 97.95% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 166 0.28% 98.23% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 108 0.18% 98.41% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 84 0.14% 98.55% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 101 0.17% 98.72% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 39 0.06% 98.78% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 59 0.10% 98.88% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 433 0.72% 99.60% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 41 0.07% 99.67% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 33 0.05% 99.72% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 91 0.15% 99.88% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 21 0.03% 99.91% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::120-123 4 0.01% 99.93% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::total 60101 # Writes before turning the bus around for reads
300system.physmem.totQLat 33864601554 # Total ticks spent queuing
301system.physmem.totMemAccLat 59422351554 # Total ticks spent from burst creation until serviced by the DRAM
302system.physmem.totBusLat 6815400000 # Total ticks spent in databus transfers
303system.physmem.avgQLat 24844.18 # Average queueing delay per DRAM burst
304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
305system.physmem.avgMemAccLat 43594.18 # Average memory access latency per DRAM burst
306system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s
307system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s
308system.physmem.avgRdBWSys 1.84 # Average system read bandwidth in MiByte/s
309system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s
310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
311system.physmem.busUtil 0.03 # Data bus utilization in percentage
312system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
313system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
314system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
315system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
316system.physmem.readRowHits 1093420 # Number of row buffer hits during reads
317system.physmem.writeRowHits 497646 # Number of row buffer hits during writes
318system.physmem.readRowHitRate 80.22 # Row buffer hit rate for reads
319system.physmem.writeRowHitRate 46.38 # Row buffer hit rate for writes
320system.physmem.avgGap 19427177.44 # Average gap between requests
321system.physmem.pageHitRate 65.31 # Row buffer hit rate, read and write combined
322system.physmem_0.actEnergy 3178488600 # Energy for activate commands per rank (pJ)
323system.physmem_0.preEnergy 1734294375 # Energy for precharge commands per rank (pJ)
324system.physmem_0.readEnergy 5058697800 # Energy for read commands per rank (pJ)
325system.physmem_0.writeEnergy 3454513920 # Energy for write commands per rank (pJ)
326system.physmem_0.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
327system.physmem_0.actBackEnergy 1187868500820 # Energy for active background per rank (pJ)
328system.physmem_0.preBackEnergy 27387019861500 # Energy for precharge background per rank (pJ)
329system.physmem_0.totalEnergy 31683055542135 # Total energy per rank (pJ)
330system.physmem_0.averagePower 668.677294 # Core power per rank (mW)
331system.physmem_0.memoryStateTime::IDLE 45560417443643 # Time in different power states
332system.physmem_0.memoryStateTime::REF 1582178520000 # Time in different power states
333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
334system.physmem_0.memoryStateTime::ACT 239087007607 # Time in different power states
335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
336system.physmem_1.actEnergy 3210233040 # Energy for activate commands per rank (pJ)
337system.physmem_1.preEnergy 1751615250 # Energy for precharge commands per rank (pJ)
338system.physmem_1.readEnergy 5573178000 # Energy for read commands per rank (pJ)
339system.physmem_1.writeEnergy 3498901920 # Energy for write commands per rank (pJ)
340system.physmem_1.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ)
341system.physmem_1.actBackEnergy 1203743481615 # Energy for active background per rank (pJ)
342system.physmem_1.preBackEnergy 27373094439750 # Energy for precharge background per rank (pJ)
343system.physmem_1.totalEnergy 31685613034695 # Total energy per rank (pJ)
344system.physmem_1.averagePower 668.731270 # Core power per rank (mW)
345system.physmem_1.memoryStateTime::IDLE 45537111526279 # Time in different power states
346system.physmem_1.memoryStateTime::REF 1582178520000 # Time in different power states
347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
348system.physmem_1.memoryStateTime::ACT 262392956221 # Time in different power states
349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
350system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
351system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
352system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
353system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
354system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
355system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
356system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

374system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
375system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
376system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
377system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
378system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
379system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
380system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
381system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
382system.cpu0.branchPred.lookups 132357688 # Number of BP lookups
383system.cpu0.branchPred.condPredicted 93633614 # Number of conditional branches predicted
384system.cpu0.branchPred.condIncorrect 5912907 # Number of conditional branches incorrect
385system.cpu0.branchPred.BTBLookups 98988393 # Number of BTB lookups
386system.cpu0.branchPred.BTBHits 72530253 # Number of BTB hits
387system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
388system.cpu0.branchPred.BTBHitPct 73.271472 # BTB Hit Percentage
389system.cpu0.branchPred.usedRAS 15763072 # Number of times the RAS was used to get a target.
390system.cpu0.branchPred.RASInCorrect 1049472 # Number of incorrect RAS predictions.
391system.cpu_clk_domain.clock 500 # Clock period in ticks
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

413system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
414system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
415system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
416system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
417system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
418system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
419system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
420system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
421system.cpu0.dtb.walker.walks 265700 # Table walker walks requested
422system.cpu0.dtb.walker.walksLong 265700 # Table walker walks initiated with long descriptors
423system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9033 # Level at which table walker walks with long descriptors terminate
424system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73083 # Level at which table walker walks with long descriptors terminate
425system.cpu0.dtb.walker.walkWaitTime::samples 265700 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::0 265700 100.00% 100.00% # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::total 265700 # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkCompletionTime::samples 82116 # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471 # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602 # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::0-65535 81335 99.05% 99.05% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::65536-131071 195 0.24% 99.29% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::131072-196607 500 0.61% 99.90% # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.92% # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.03% 99.95% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::total 82116 # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walkPageSizes::4K 73083 89.00% 89.00% # Table walker page sizes translated
449system.cpu0.dtb.walker.walkPageSizes::2M 9033 11.00% 100.00% # Table walker page sizes translated
450system.cpu0.dtb.walker.walkPageSizes::total 82116 # Table walker page sizes translated
451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 265700 # Table walker requests started/completed, data/inst
452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 265700 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 82116 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 82116 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin::total 347816 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.inst_hits 0 # ITB inst hits
459system.cpu0.dtb.inst_misses 0 # ITB inst misses
460system.cpu0.dtb.read_hits 86394812 # DTB read hits
461system.cpu0.dtb.read_misses 220998 # DTB read misses
462system.cpu0.dtb.write_hits 74903999 # DTB write hits
463system.cpu0.dtb.write_misses 44702 # DTB write misses
464system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
465system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
466system.cpu0.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
467system.cpu0.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
468system.cpu0.dtb.flush_entries 37665 # Number of entries that have been flushed from TLB
469system.cpu0.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions
470system.cpu0.dtb.prefetch_faults 8673 # Number of TLB faults due to prefetch
471system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
472system.cpu0.dtb.perms_faults 10301 # Number of TLB faults due to permissions restrictions
473system.cpu0.dtb.read_accesses 86615810 # DTB read accesses
474system.cpu0.dtb.write_accesses 74948701 # DTB write accesses
475system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
476system.cpu0.dtb.hits 161298811 # DTB hits
477system.cpu0.dtb.misses 265700 # DTB misses
478system.cpu0.dtb.accesses 161564511 # DTB accesses
479system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

500system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
501system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
502system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
503system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
504system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
505system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
506system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
507system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
508system.cpu0.itb.walker.walks 59769 # Table walker walks requested
509system.cpu0.itb.walker.walksLong 59769 # Table walker walks initiated with long descriptors
510system.cpu0.itb.walker.walksLongTerminationLevel::Level2 498 # Level at which table walker walks with long descriptors terminate
511system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49758 # Level at which table walker walks with long descriptors terminate
512system.cpu0.itb.walker.walkWaitTime::samples 59769 # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::0 59769 100.00% 100.00% # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::total 59769 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkCompletionTime::samples 50256 # Table walker service (enqueue to completion) latency
516system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267 # Table walker service (enqueue to completion) latency
517system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::0-32767 46691 92.91% 92.91% # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::32768-65535 2859 5.69% 98.60% # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::65536-98303 7 0.01% 98.61% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::131072-163839 383 0.76% 99.37% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::163840-196607 254 0.51% 99.88% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::196608-229375 9 0.02% 99.89% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.90% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.91% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::294912-327679 25 0.05% 99.96% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.98% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::total 50256 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
534system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
535system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
536system.cpu0.itb.walker.walkPageSizes::4K 49758 99.01% 99.01% # Table walker page sizes translated
537system.cpu0.itb.walker.walkPageSizes::2M 498 0.99% 100.00% # Table walker page sizes translated
538system.cpu0.itb.walker.walkPageSizes::total 50256 # Table walker page sizes translated
539system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59769 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59769 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50256 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50256 # Table walker requests started/completed, data/inst
545system.cpu0.itb.walker.walkRequestOrigin::total 110025 # Table walker requests started/completed, data/inst
546system.cpu0.itb.inst_hits 238646690 # ITB inst hits
547system.cpu0.itb.inst_misses 59769 # ITB inst misses
548system.cpu0.itb.read_hits 0 # DTB read hits
549system.cpu0.itb.read_misses 0 # DTB read misses
550system.cpu0.itb.write_hits 0 # DTB write hits
551system.cpu0.itb.write_misses 0 # DTB write misses
552system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
553system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
554system.cpu0.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
555system.cpu0.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
556system.cpu0.itb.flush_entries 27225 # Number of entries that have been flushed from TLB
557system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
558system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
559system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
560system.cpu0.itb.perms_faults 203945 # Number of TLB faults due to permissions restrictions
561system.cpu0.itb.read_accesses 0 # DTB read accesses
562system.cpu0.itb.write_accesses 0 # DTB write accesses
563system.cpu0.itb.inst_accesses 238706459 # ITB inst accesses
564system.cpu0.itb.hits 238646690 # DTB hits
565system.cpu0.itb.misses 59769 # DTB misses
566system.cpu0.itb.accesses 238706459 # DTB accesses
567system.cpu0.numCycles 1007854766 # number of cpu cycles simulated
568system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
569system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
570system.cpu0.committedInsts 441362500 # Number of instructions committed
571system.cpu0.committedOps 518398273 # Number of ops (including micro ops) committed
572system.cpu0.discardedOps 43962057 # Number of ops (including micro ops) which were discarded before commit
573system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
574system.cpu0.quiesceCycles 93756283149 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
575system.cpu0.cpi 2.283508 # CPI: cycles per instruction
576system.cpu0.ipc 0.437923 # IPC: instructions per cycle
577system.cpu0.kern.inst.arm 0 # number of arm instructions executed
578system.cpu0.kern.inst.quiesce 5202 # number of quiesce instructions executed
579system.cpu0.tickCycles 710760418 # Number of cycles that the object actually ticked
580system.cpu0.idleCycles 297094348 # Total number of cycles that the object has spent stopped
581system.cpu0.dcache.tags.replacements 5529190 # number of replacements
582system.cpu0.dcache.tags.tagsinuse 480.574807 # Cycle average of tags in use
583system.cpu0.dcache.tags.total_refs 153025870 # Total number of references to valid blocks.
584system.cpu0.dcache.tags.sampled_refs 5529699 # Sample count of references to valid blocks.
585system.cpu0.dcache.tags.avg_refs 27.673454 # Average number of references to valid blocks.
586system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
587system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.574807 # Average occupied blocks per requestor
588system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938623 # Average percentage of cache occupancy
589system.cpu0.dcache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy
590system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
591system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
592system.cpu0.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id
593system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id
594system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
595system.cpu0.dcache.tags.tag_accesses 325514940 # Number of tag accesses
596system.cpu0.dcache.tags.data_accesses 325514940 # Number of data accesses
597system.cpu0.dcache.ReadReq_hits::cpu0.data 79084139 # number of ReadReq hits
598system.cpu0.dcache.ReadReq_hits::total 79084139 # number of ReadReq hits
599system.cpu0.dcache.WriteReq_hits::cpu0.data 69445340 # number of WriteReq hits
600system.cpu0.dcache.WriteReq_hits::total 69445340 # number of WriteReq hits
601system.cpu0.dcache.SoftPFReq_hits::cpu0.data 251787 # number of SoftPFReq hits
602system.cpu0.dcache.SoftPFReq_hits::total 251787 # number of SoftPFReq hits
603system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143392 # number of WriteLineReq hits
604system.cpu0.dcache.WriteLineReq_hits::total 143392 # number of WriteLineReq hits
605system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1790882 # number of LoadLockedReq hits
606system.cpu0.dcache.LoadLockedReq_hits::total 1790882 # number of LoadLockedReq hits
607system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1762255 # number of StoreCondReq hits
608system.cpu0.dcache.StoreCondReq_hits::total 1762255 # number of StoreCondReq hits
609system.cpu0.dcache.demand_hits::cpu0.data 148529479 # number of demand (read+write) hits
610system.cpu0.dcache.demand_hits::total 148529479 # number of demand (read+write) hits
611system.cpu0.dcache.overall_hits::cpu0.data 148781266 # number of overall hits
612system.cpu0.dcache.overall_hits::total 148781266 # number of overall hits
613system.cpu0.dcache.ReadReq_misses::cpu0.data 3438422 # number of ReadReq misses
614system.cpu0.dcache.ReadReq_misses::total 3438422 # number of ReadReq misses
615system.cpu0.dcache.WriteReq_misses::cpu0.data 2286291 # number of WriteReq misses
616system.cpu0.dcache.WriteReq_misses::total 2286291 # number of WriteReq misses
617system.cpu0.dcache.SoftPFReq_misses::cpu0.data 632969 # number of SoftPFReq misses
618system.cpu0.dcache.SoftPFReq_misses::total 632969 # number of SoftPFReq misses
619system.cpu0.dcache.WriteLineReq_misses::cpu0.data 749661 # number of WriteLineReq misses
620system.cpu0.dcache.WriteLineReq_misses::total 749661 # number of WriteLineReq misses
621system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167888 # number of LoadLockedReq misses
622system.cpu0.dcache.LoadLockedReq_misses::total 167888 # number of LoadLockedReq misses
623system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194810 # number of StoreCondReq misses
624system.cpu0.dcache.StoreCondReq_misses::total 194810 # number of StoreCondReq misses
625system.cpu0.dcache.demand_misses::cpu0.data 5724713 # number of demand (read+write) misses
626system.cpu0.dcache.demand_misses::total 5724713 # number of demand (read+write) misses
627system.cpu0.dcache.overall_misses::cpu0.data 6357682 # number of overall misses
628system.cpu0.dcache.overall_misses::total 6357682 # number of overall misses
629system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57301041000 # number of ReadReq miss cycles
630system.cpu0.dcache.ReadReq_miss_latency::total 57301041000 # number of ReadReq miss cycles
631system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 58503452500 # number of WriteReq miss cycles
632system.cpu0.dcache.WriteReq_miss_latency::total 58503452500 # number of WriteReq miss cycles
633system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 69078584500 # number of WriteLineReq miss cycles
634system.cpu0.dcache.WriteLineReq_miss_latency::total 69078584500 # number of WriteLineReq miss cycles
635system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2562226000 # number of LoadLockedReq miss cycles
636system.cpu0.dcache.LoadLockedReq_miss_latency::total 2562226000 # number of LoadLockedReq miss cycles
637system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5482087500 # number of StoreCondReq miss cycles
638system.cpu0.dcache.StoreCondReq_miss_latency::total 5482087500 # number of StoreCondReq miss cycles
639system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5099500 # number of StoreCondFailReq miss cycles
640system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5099500 # number of StoreCondFailReq miss cycles
641system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500 # number of demand (read+write) miss cycles
642system.cpu0.dcache.demand_miss_latency::total 115804493500 # number of demand (read+write) miss cycles
643system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500 # number of overall miss cycles
644system.cpu0.dcache.overall_miss_latency::total 115804493500 # number of overall miss cycles
645system.cpu0.dcache.ReadReq_accesses::cpu0.data 82522561 # number of ReadReq accesses(hits+misses)
646system.cpu0.dcache.ReadReq_accesses::total 82522561 # number of ReadReq accesses(hits+misses)
647system.cpu0.dcache.WriteReq_accesses::cpu0.data 71731631 # number of WriteReq accesses(hits+misses)
648system.cpu0.dcache.WriteReq_accesses::total 71731631 # number of WriteReq accesses(hits+misses)
649system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 884756 # number of SoftPFReq accesses(hits+misses)
650system.cpu0.dcache.SoftPFReq_accesses::total 884756 # number of SoftPFReq accesses(hits+misses)
651system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 893053 # number of WriteLineReq accesses(hits+misses)
652system.cpu0.dcache.WriteLineReq_accesses::total 893053 # number of WriteLineReq accesses(hits+misses)
653system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1958770 # number of LoadLockedReq accesses(hits+misses)
654system.cpu0.dcache.LoadLockedReq_accesses::total 1958770 # number of LoadLockedReq accesses(hits+misses)
655system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1957065 # number of StoreCondReq accesses(hits+misses)
656system.cpu0.dcache.StoreCondReq_accesses::total 1957065 # number of StoreCondReq accesses(hits+misses)
657system.cpu0.dcache.demand_accesses::cpu0.data 154254192 # number of demand (read+write) accesses
658system.cpu0.dcache.demand_accesses::total 154254192 # number of demand (read+write) accesses
659system.cpu0.dcache.overall_accesses::cpu0.data 155138948 # number of overall (read+write) accesses
660system.cpu0.dcache.overall_accesses::total 155138948 # number of overall (read+write) accesses
661system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041666 # miss rate for ReadReq accesses
662system.cpu0.dcache.ReadReq_miss_rate::total 0.041666 # miss rate for ReadReq accesses
663system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031873 # miss rate for WriteReq accesses
664system.cpu0.dcache.WriteReq_miss_rate::total 0.031873 # miss rate for WriteReq accesses
665system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715416 # miss rate for SoftPFReq accesses
666system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715416 # miss rate for SoftPFReq accesses
667system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839436 # miss rate for WriteLineReq accesses
668system.cpu0.dcache.WriteLineReq_miss_rate::total 0.839436 # miss rate for WriteLineReq accesses
669system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085711 # miss rate for LoadLockedReq accesses
670system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085711 # miss rate for LoadLockedReq accesses
671system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses
672system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses
673system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037112 # miss rate for demand accesses
674system.cpu0.dcache.demand_miss_rate::total 0.037112 # miss rate for demand accesses
675system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040981 # miss rate for overall accesses
676system.cpu0.dcache.overall_miss_rate::total 0.040981 # miss rate for overall accesses
677system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16664.923910 # average ReadReq miss latency
678system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910 # average ReadReq miss latency
679system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094 # average WriteReq miss latency
680system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094 # average WriteReq miss latency
681system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519 # average WriteLineReq miss latency
682system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519 # average WriteLineReq miss latency
683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584 # average LoadLockedReq miss latency
684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584 # average LoadLockedReq miss latency
685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363 # average StoreCondReq miss latency
686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363 # average StoreCondReq miss latency
687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220 # average overall miss latency
690system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220 # average overall miss latency
691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393 # average overall miss latency
692system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393 # average overall miss latency
693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
699system.cpu0.dcache.fast_writes 0 # number of fast writes performed
700system.cpu0.dcache.cache_copies 0 # number of cache copies performed
701system.cpu0.dcache.writebacks::writebacks 5529208 # number of writebacks
702system.cpu0.dcache.writebacks::total 5529208 # number of writebacks
703system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 425438 # number of ReadReq MSHR hits
704system.cpu0.dcache.ReadReq_mshr_hits::total 425438 # number of ReadReq MSHR hits
705system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 937459 # number of WriteReq MSHR hits
706system.cpu0.dcache.WriteReq_mshr_hits::total 937459 # number of WriteReq MSHR hits
707system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 53 # number of WriteLineReq MSHR hits
708system.cpu0.dcache.WriteLineReq_mshr_hits::total 53 # number of WriteLineReq MSHR hits
709system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41154 # number of LoadLockedReq MSHR hits
710system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41154 # number of LoadLockedReq MSHR hits
711system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 15 # number of StoreCondReq MSHR hits
712system.cpu0.dcache.StoreCondReq_mshr_hits::total 15 # number of StoreCondReq MSHR hits
713system.cpu0.dcache.demand_mshr_hits::cpu0.data 1362897 # number of demand (read+write) MSHR hits
714system.cpu0.dcache.demand_mshr_hits::total 1362897 # number of demand (read+write) MSHR hits
715system.cpu0.dcache.overall_mshr_hits::cpu0.data 1362897 # number of overall MSHR hits
716system.cpu0.dcache.overall_mshr_hits::total 1362897 # number of overall MSHR hits
717system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3012984 # number of ReadReq MSHR misses
718system.cpu0.dcache.ReadReq_mshr_misses::total 3012984 # number of ReadReq MSHR misses
719system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1348832 # number of WriteReq MSHR misses
720system.cpu0.dcache.WriteReq_mshr_misses::total 1348832 # number of WriteReq MSHR misses
721system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631309 # number of SoftPFReq MSHR misses
722system.cpu0.dcache.SoftPFReq_mshr_misses::total 631309 # number of SoftPFReq MSHR misses
723system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 749608 # number of WriteLineReq MSHR misses
724system.cpu0.dcache.WriteLineReq_mshr_misses::total 749608 # number of WriteLineReq MSHR misses
725system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126734 # number of LoadLockedReq MSHR misses
726system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126734 # number of LoadLockedReq MSHR misses
727system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194795 # number of StoreCondReq MSHR misses
728system.cpu0.dcache.StoreCondReq_mshr_misses::total 194795 # number of StoreCondReq MSHR misses
729system.cpu0.dcache.demand_mshr_misses::cpu0.data 4361816 # number of demand (read+write) MSHR misses
730system.cpu0.dcache.demand_mshr_misses::total 4361816 # number of demand (read+write) MSHR misses
731system.cpu0.dcache.overall_mshr_misses::cpu0.data 4993125 # number of overall MSHR misses
732system.cpu0.dcache.overall_mshr_misses::total 4993125 # number of overall MSHR misses
733system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
734system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15485 # number of ReadReq MSHR uncacheable
735system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
736system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable
737system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
738system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31915 # number of overall MSHR uncacheable misses
739system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44936822000 # number of ReadReq MSHR miss cycles
740system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44936822000 # number of ReadReq MSHR miss cycles
741system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34248227000 # number of WriteReq MSHR miss cycles
742system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34248227000 # number of WriteReq MSHR miss cycles
743system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15688131000 # number of SoftPFReq MSHR miss cycles
744system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15688131000 # number of SoftPFReq MSHR miss cycles
745system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 68324152500 # number of WriteLineReq MSHR miss cycles
746system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 68324152500 # number of WriteLineReq MSHR miss cycles
747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1728085500 # number of LoadLockedReq MSHR miss cycles
748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1728085500 # number of LoadLockedReq MSHR miss cycles
749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5286161500 # number of StoreCondReq MSHR miss cycles
750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5286161500 # number of StoreCondReq MSHR miss cycles
751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5009500 # number of StoreCondFailReq MSHR miss cycles
752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5009500 # number of StoreCondFailReq MSHR miss cycles
753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79185049000 # number of demand (read+write) MSHR miss cycles
754system.cpu0.dcache.demand_mshr_miss_latency::total 79185049000 # number of demand (read+write) MSHR miss cycles
755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94873180000 # number of overall MSHR miss cycles
756system.cpu0.dcache.overall_mshr_miss_latency::total 94873180000 # number of overall MSHR miss cycles
757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2777500000 # number of ReadReq MSHR uncacheable cycles
758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2777500000 # number of ReadReq MSHR uncacheable cycles
759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2891122000 # number of WriteReq MSHR uncacheable cycles
760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2891122000 # number of WriteReq MSHR uncacheable cycles
761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5668622000 # number of overall MSHR uncacheable cycles
762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5668622000 # number of overall MSHR uncacheable cycles
763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036511 # mshr miss rate for ReadReq accesses
764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadReq accesses
765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses
766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses
767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.713540 # mshr miss rate for SoftPFReq accesses
768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.713540 # mshr miss rate for SoftPFReq accesses
769system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.839377 # mshr miss rate for WriteLineReq accesses
770system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.839377 # mshr miss rate for WriteLineReq accesses
771system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses
772system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses
773system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099534 # mshr miss rate for StoreCondReq accesses
774system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099534 # mshr miss rate for StoreCondReq accesses
775system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028277 # mshr miss rate for demand accesses
776system.cpu0.dcache.demand_mshr_miss_rate::total 0.028277 # mshr miss rate for demand accesses
777system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032185 # mshr miss rate for overall accesses
778system.cpu0.dcache.overall_mshr_miss_rate::total 0.032185 # mshr miss rate for overall accesses
779system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182 # average ReadReq mshr miss latency
780system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182 # average ReadReq mshr miss latency
781system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976 # average WriteReq mshr miss latency
782system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976 # average WriteReq mshr miss latency
783system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123 # average SoftPFReq mshr miss latency
784system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123 # average SoftPFReq mshr miss latency
785system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242 # average WriteLineReq mshr miss latency
786system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242 # average WriteLineReq mshr miss latency
787system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901 # average LoadLockedReq mshr miss latency
788system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901 # average LoadLockedReq mshr miss latency
789system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206 # average StoreCondReq mshr miss latency
790system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206 # average StoreCondReq mshr miss latency
791system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
792system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
793system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034 # average overall mshr miss latency
794system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034 # average overall mshr miss latency
795system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048 # average overall mshr miss latency
796system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048 # average overall mshr miss latency
797system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480 # average ReadReq mshr uncacheable latency
798system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480 # average ReadReq mshr uncacheable latency
799system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736 # average WriteReq mshr uncacheable latency
800system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736 # average WriteReq mshr uncacheable latency
801system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613 # average overall mshr uncacheable latency
802system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613 # average overall mshr uncacheable latency
803system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
804system.cpu0.icache.tags.replacements 8961850 # number of replacements
805system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use
806system.cpu0.icache.tags.total_refs 229474819 # Total number of references to valid blocks.
807system.cpu0.icache.tags.sampled_refs 8962362 # Sample count of references to valid blocks.
808system.cpu0.icache.tags.avg_refs 25.604279 # Average number of references to valid blocks.
809system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit.
810system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor
811system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy
812system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy
813system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
814system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
815system.cpu0.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
816system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id
817system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
818system.cpu0.icache.tags.tag_accesses 485836753 # Number of tag accesses
819system.cpu0.icache.tags.data_accesses 485836753 # Number of data accesses
820system.cpu0.icache.ReadReq_hits::cpu0.inst 229474819 # number of ReadReq hits
821system.cpu0.icache.ReadReq_hits::total 229474819 # number of ReadReq hits
822system.cpu0.icache.demand_hits::cpu0.inst 229474819 # number of demand (read+write) hits
823system.cpu0.icache.demand_hits::total 229474819 # number of demand (read+write) hits
824system.cpu0.icache.overall_hits::cpu0.inst 229474819 # number of overall hits
825system.cpu0.icache.overall_hits::total 229474819 # number of overall hits
826system.cpu0.icache.ReadReq_misses::cpu0.inst 8962372 # number of ReadReq misses
827system.cpu0.icache.ReadReq_misses::total 8962372 # number of ReadReq misses
828system.cpu0.icache.demand_misses::cpu0.inst 8962372 # number of demand (read+write) misses
829system.cpu0.icache.demand_misses::total 8962372 # number of demand (read+write) misses
830system.cpu0.icache.overall_misses::cpu0.inst 8962372 # number of overall misses
831system.cpu0.icache.overall_misses::total 8962372 # number of overall misses
832system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94471116000 # number of ReadReq miss cycles
833system.cpu0.icache.ReadReq_miss_latency::total 94471116000 # number of ReadReq miss cycles
834system.cpu0.icache.demand_miss_latency::cpu0.inst 94471116000 # number of demand (read+write) miss cycles
835system.cpu0.icache.demand_miss_latency::total 94471116000 # number of demand (read+write) miss cycles
836system.cpu0.icache.overall_miss_latency::cpu0.inst 94471116000 # number of overall miss cycles
837system.cpu0.icache.overall_miss_latency::total 94471116000 # number of overall miss cycles
838system.cpu0.icache.ReadReq_accesses::cpu0.inst 238437191 # number of ReadReq accesses(hits+misses)
839system.cpu0.icache.ReadReq_accesses::total 238437191 # number of ReadReq accesses(hits+misses)
840system.cpu0.icache.demand_accesses::cpu0.inst 238437191 # number of demand (read+write) accesses
841system.cpu0.icache.demand_accesses::total 238437191 # number of demand (read+write) accesses
842system.cpu0.icache.overall_accesses::cpu0.inst 238437191 # number of overall (read+write) accesses
843system.cpu0.icache.overall_accesses::total 238437191 # number of overall (read+write) accesses
844system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037588 # miss rate for ReadReq accesses
845system.cpu0.icache.ReadReq_miss_rate::total 0.037588 # miss rate for ReadReq accesses
846system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037588 # miss rate for demand accesses
847system.cpu0.icache.demand_miss_rate::total 0.037588 # miss rate for demand accesses
848system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037588 # miss rate for overall accesses
849system.cpu0.icache.overall_miss_rate::total 0.037588 # miss rate for overall accesses
850system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835 # average ReadReq miss latency
851system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835 # average ReadReq miss latency
852system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
853system.cpu0.icache.demand_avg_miss_latency::total 10540.860835 # average overall miss latency
854system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency
855system.cpu0.icache.overall_avg_miss_latency::total 10540.860835 # average overall miss latency
856system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
857system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
858system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
859system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
860system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
861system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
862system.cpu0.icache.fast_writes 0 # number of fast writes performed
863system.cpu0.icache.cache_copies 0 # number of cache copies performed
864system.cpu0.icache.writebacks::writebacks 8961850 # number of writebacks
865system.cpu0.icache.writebacks::total 8961850 # number of writebacks
866system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8962372 # number of ReadReq MSHR misses
867system.cpu0.icache.ReadReq_mshr_misses::total 8962372 # number of ReadReq MSHR misses
868system.cpu0.icache.demand_mshr_misses::cpu0.inst 8962372 # number of demand (read+write) MSHR misses
869system.cpu0.icache.demand_mshr_misses::total 8962372 # number of demand (read+write) MSHR misses
870system.cpu0.icache.overall_mshr_misses::cpu0.inst 8962372 # number of overall MSHR misses
871system.cpu0.icache.overall_mshr_misses::total 8962372 # number of overall MSHR misses
872system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
873system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
874system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
875system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
876system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 89989930500 # number of ReadReq MSHR miss cycles
877system.cpu0.icache.ReadReq_mshr_miss_latency::total 89989930500 # number of ReadReq MSHR miss cycles
878system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89989930500 # number of demand (read+write) MSHR miss cycles
879system.cpu0.icache.demand_mshr_miss_latency::total 89989930500 # number of demand (read+write) MSHR miss cycles
880system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89989930500 # number of overall MSHR miss cycles
881system.cpu0.icache.overall_mshr_miss_latency::total 89989930500 # number of overall MSHR miss cycles
882system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles
883system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles
884system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles
885system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles
886system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for ReadReq accesses
887system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037588 # mshr miss rate for ReadReq accesses
888system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for demand accesses
889system.cpu0.icache.demand_mshr_miss_rate::total 0.037588 # mshr miss rate for demand accesses
890system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037588 # mshr miss rate for overall accesses
891system.cpu0.icache.overall_mshr_miss_rate::total 0.037588 # mshr miss rate for overall accesses
892system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average ReadReq mshr miss latency
893system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10040.860890 # average ReadReq mshr miss latency
894system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
895system.cpu0.icache.demand_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
896system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10040.860890 # average overall mshr miss latency
897system.cpu0.icache.overall_avg_mshr_miss_latency::total 10040.860890 # average overall mshr miss latency
898system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency
899system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
900system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
901system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
902system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
903system.cpu0.l2cache.prefetcher.num_hwpf_issued 7773827 # number of hwpf issued
904system.cpu0.l2cache.prefetcher.pfIdentified 7774021 # number of prefetch candidates identified
905system.cpu0.l2cache.prefetcher.pfBufferHit 173 # number of redundant prefetches already in prefetch queue
906system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
907system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
908system.cpu0.l2cache.prefetcher.pfSpanPage 1015459 # number of prefetches not generated due to page crossing
909system.cpu0.l2cache.tags.replacements 2700718 # number of replacements
910system.cpu0.l2cache.tags.tagsinuse 16213.055668 # Cycle average of tags in use
911system.cpu0.l2cache.tags.total_refs 22438549 # Total number of references to valid blocks.
912system.cpu0.l2cache.tags.sampled_refs 2716794 # Sample count of references to valid blocks.
913system.cpu0.l2cache.tags.avg_refs 8.259201 # Average number of references to valid blocks.
914system.cpu0.l2cache.tags.warmup_cycle 9049945000 # Cycle when the warmup percentage was hit.
915system.cpu0.l2cache.tags.occ_blocks::writebacks 15223.315465 # Average occupied blocks per requestor
916system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 55.903430 # Average occupied blocks per requestor
917system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.295505 # Average occupied blocks per requestor
918system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 879.541268 # Average occupied blocks per requestor
919system.cpu0.l2cache.tags.occ_percent::writebacks 0.929157 # Average percentage of cache occupancy
920system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003412 # Average percentage of cache occupancy
921system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003314 # Average percentage of cache occupancy
922system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053683 # Average percentage of cache occupancy
923system.cpu0.l2cache.tags.occ_percent::total 0.989566 # Average percentage of cache occupancy
924system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1224 # Occupied blocks per task id
925system.cpu0.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id
926system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14798 # Occupied blocks per task id
927system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id
928system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 814 # Occupied blocks per task id
929system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id
930system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 215 # Occupied blocks per task id
931system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
932system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id
933system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
934system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
935system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 997 # Occupied blocks per task id
936system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
937system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6189 # Occupied blocks per task id
938system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2013 # Occupied blocks per task id
939system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074707 # Percentage of cache occupancy per task id
940system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id
941system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903198 # Percentage of cache occupancy per task id
942system.cpu0.l2cache.tags.tag_accesses 488653498 # Number of tag accesses
943system.cpu0.l2cache.tags.data_accesses 488653498 # Number of data accesses
944system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 497387 # number of ReadReq hits
945system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 151168 # number of ReadReq hits
946system.cpu0.l2cache.ReadReq_hits::total 648555 # number of ReadReq hits
947system.cpu0.l2cache.WritebackDirty_hits::writebacks 3589798 # number of WritebackDirty hits
948system.cpu0.l2cache.WritebackDirty_hits::total 3589798 # number of WritebackDirty hits
949system.cpu0.l2cache.WritebackClean_hits::writebacks 10898588 # number of WritebackClean hits
950system.cpu0.l2cache.WritebackClean_hits::total 10898588 # number of WritebackClean hits
951system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 348 # number of UpgradeReq hits
952system.cpu0.l2cache.UpgradeReq_hits::total 348 # number of UpgradeReq hits
953system.cpu0.l2cache.ReadExReq_hits::cpu0.data 828045 # number of ReadExReq hits
954system.cpu0.l2cache.ReadExReq_hits::total 828045 # number of ReadExReq hits
955system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8251361 # number of ReadCleanReq hits
956system.cpu0.l2cache.ReadCleanReq_hits::total 8251361 # number of ReadCleanReq hits
957system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2786170 # number of ReadSharedReq hits
958system.cpu0.l2cache.ReadSharedReq_hits::total 2786170 # number of ReadSharedReq hits
959system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 167822 # number of InvalidateReq hits
960system.cpu0.l2cache.InvalidateReq_hits::total 167822 # number of InvalidateReq hits
961system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 497387 # number of demand (read+write) hits
962system.cpu0.l2cache.demand_hits::cpu0.itb.walker 151168 # number of demand (read+write) hits
963system.cpu0.l2cache.demand_hits::cpu0.inst 8251361 # number of demand (read+write) hits
964system.cpu0.l2cache.demand_hits::cpu0.data 3614215 # number of demand (read+write) hits
965system.cpu0.l2cache.demand_hits::total 12514131 # number of demand (read+write) hits
966system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 497387 # number of overall hits
967system.cpu0.l2cache.overall_hits::cpu0.itb.walker 151168 # number of overall hits
968system.cpu0.l2cache.overall_hits::cpu0.inst 8251361 # number of overall hits
969system.cpu0.l2cache.overall_hits::cpu0.data 3614215 # number of overall hits
970system.cpu0.l2cache.overall_hits::total 12514131 # number of overall hits
971system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11281 # number of ReadReq misses
972system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7561 # number of ReadReq misses
973system.cpu0.l2cache.ReadReq_misses::total 18842 # number of ReadReq misses
974system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256026 # number of UpgradeReq misses
975system.cpu0.l2cache.UpgradeReq_misses::total 256026 # number of UpgradeReq misses
976system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 194786 # number of SCUpgradeReq misses
977system.cpu0.l2cache.SCUpgradeReq_misses::total 194786 # number of SCUpgradeReq misses
978system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses
979system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
980system.cpu0.l2cache.ReadExReq_misses::cpu0.data 272487 # number of ReadExReq misses
981system.cpu0.l2cache.ReadExReq_misses::total 272487 # number of ReadExReq misses
982system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 711010 # number of ReadCleanReq misses
983system.cpu0.l2cache.ReadCleanReq_misses::total 711010 # number of ReadCleanReq misses
984system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 984601 # number of ReadSharedReq misses
985system.cpu0.l2cache.ReadSharedReq_misses::total 984601 # number of ReadSharedReq misses
986system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 580093 # number of InvalidateReq misses
987system.cpu0.l2cache.InvalidateReq_misses::total 580093 # number of InvalidateReq misses
988system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11281 # number of demand (read+write) misses
989system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7561 # number of demand (read+write) misses
990system.cpu0.l2cache.demand_misses::cpu0.inst 711010 # number of demand (read+write) misses
991system.cpu0.l2cache.demand_misses::cpu0.data 1257088 # number of demand (read+write) misses
992system.cpu0.l2cache.demand_misses::total 1986940 # number of demand (read+write) misses
993system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11281 # number of overall misses
994system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7561 # number of overall misses
995system.cpu0.l2cache.overall_misses::cpu0.inst 711010 # number of overall misses
996system.cpu0.l2cache.overall_misses::cpu0.data 1257088 # number of overall misses
997system.cpu0.l2cache.overall_misses::total 1986940 # number of overall misses
998system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 432507500 # number of ReadReq miss cycles
999system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 322890000 # number of ReadReq miss cycles
1000system.cpu0.l2cache.ReadReq_miss_latency::total 755397500 # number of ReadReq miss cycles
1001system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3595898500 # number of UpgradeReq miss cycles
1002system.cpu0.l2cache.UpgradeReq_miss_latency::total 3595898500 # number of UpgradeReq miss cycles
1003system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1942602000 # number of SCUpgradeReq miss cycles
1004system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1942602000 # number of SCUpgradeReq miss cycles
1005system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4921998 # number of SCUpgradeFailReq miss cycles
1006system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4921998 # number of SCUpgradeFailReq miss cycles
1007system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 17184690000 # number of ReadExReq miss cycles
1008system.cpu0.l2cache.ReadExReq_miss_latency::total 17184690000 # number of ReadExReq miss cycles
1009system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 26717037500 # number of ReadCleanReq miss cycles
1010system.cpu0.l2cache.ReadCleanReq_miss_latency::total 26717037500 # number of ReadCleanReq miss cycles
1011system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 38302477992 # number of ReadSharedReq miss cycles
1012system.cpu0.l2cache.ReadSharedReq_miss_latency::total 38302477992 # number of ReadSharedReq miss cycles
1013system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 65953326000 # number of InvalidateReq miss cycles
1014system.cpu0.l2cache.InvalidateReq_miss_latency::total 65953326000 # number of InvalidateReq miss cycles
1015system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 432507500 # number of demand (read+write) miss cycles
1016system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 322890000 # number of demand (read+write) miss cycles
1017system.cpu0.l2cache.demand_miss_latency::cpu0.inst 26717037500 # number of demand (read+write) miss cycles
1018system.cpu0.l2cache.demand_miss_latency::cpu0.data 55487167992 # number of demand (read+write) miss cycles
1019system.cpu0.l2cache.demand_miss_latency::total 82959602992 # number of demand (read+write) miss cycles
1020system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 432507500 # number of overall miss cycles
1021system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 322890000 # number of overall miss cycles
1022system.cpu0.l2cache.overall_miss_latency::cpu0.inst 26717037500 # number of overall miss cycles
1023system.cpu0.l2cache.overall_miss_latency::cpu0.data 55487167992 # number of overall miss cycles
1024system.cpu0.l2cache.overall_miss_latency::total 82959602992 # number of overall miss cycles
1025system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 508668 # number of ReadReq accesses(hits+misses)
1026system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158729 # number of ReadReq accesses(hits+misses)
1027system.cpu0.l2cache.ReadReq_accesses::total 667397 # number of ReadReq accesses(hits+misses)
1028system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3589798 # number of WritebackDirty accesses(hits+misses)
1029system.cpu0.l2cache.WritebackDirty_accesses::total 3589798 # number of WritebackDirty accesses(hits+misses)
1030system.cpu0.l2cache.WritebackClean_accesses::writebacks 10898588 # number of WritebackClean accesses(hits+misses)
1031system.cpu0.l2cache.WritebackClean_accesses::total 10898588 # number of WritebackClean accesses(hits+misses)
1032system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256374 # number of UpgradeReq accesses(hits+misses)
1033system.cpu0.l2cache.UpgradeReq_accesses::total 256374 # number of UpgradeReq accesses(hits+misses)
1034system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194786 # number of SCUpgradeReq accesses(hits+misses)
1035system.cpu0.l2cache.SCUpgradeReq_accesses::total 194786 # number of SCUpgradeReq accesses(hits+misses)
1036system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
1037system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
1038system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1100532 # number of ReadExReq accesses(hits+misses)
1039system.cpu0.l2cache.ReadExReq_accesses::total 1100532 # number of ReadExReq accesses(hits+misses)
1040system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 8962371 # number of ReadCleanReq accesses(hits+misses)
1041system.cpu0.l2cache.ReadCleanReq_accesses::total 8962371 # number of ReadCleanReq accesses(hits+misses)
1042system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3770771 # number of ReadSharedReq accesses(hits+misses)
1043system.cpu0.l2cache.ReadSharedReq_accesses::total 3770771 # number of ReadSharedReq accesses(hits+misses)
1044system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 747915 # number of InvalidateReq accesses(hits+misses)
1045system.cpu0.l2cache.InvalidateReq_accesses::total 747915 # number of InvalidateReq accesses(hits+misses)
1046system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 508668 # number of demand (read+write) accesses
1047system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 158729 # number of demand (read+write) accesses
1048system.cpu0.l2cache.demand_accesses::cpu0.inst 8962371 # number of demand (read+write) accesses
1049system.cpu0.l2cache.demand_accesses::cpu0.data 4871303 # number of demand (read+write) accesses
1050system.cpu0.l2cache.demand_accesses::total 14501071 # number of demand (read+write) accesses
1051system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 508668 # number of overall (read+write) accesses
1052system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 158729 # number of overall (read+write) accesses
1053system.cpu0.l2cache.overall_accesses::cpu0.inst 8962371 # number of overall (read+write) accesses
1054system.cpu0.l2cache.overall_accesses::cpu0.data 4871303 # number of overall (read+write) accesses
1055system.cpu0.l2cache.overall_accesses::total 14501071 # number of overall (read+write) accesses
1056system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for ReadReq accesses
1057system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047635 # miss rate for ReadReq accesses
1058system.cpu0.l2cache.ReadReq_miss_rate::total 0.028232 # miss rate for ReadReq accesses
1059system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998643 # miss rate for UpgradeReq accesses
1060system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998643 # miss rate for UpgradeReq accesses
1061system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1062system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1063system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1064system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1065system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.247596 # miss rate for ReadExReq accesses
1066system.cpu0.l2cache.ReadExReq_miss_rate::total 0.247596 # miss rate for ReadExReq accesses
1067system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.079333 # miss rate for ReadCleanReq accesses
1068system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.079333 # miss rate for ReadCleanReq accesses
1069system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.261114 # miss rate for ReadSharedReq accesses
1070system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.261114 # miss rate for ReadSharedReq accesses
1071system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.775614 # miss rate for InvalidateReq accesses
1072system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.775614 # miss rate for InvalidateReq accesses
1073system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for demand accesses
1074system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047635 # miss rate for demand accesses
1075system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079333 # miss rate for demand accesses
1076system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258060 # miss rate for demand accesses
1077system.cpu0.l2cache.demand_miss_rate::total 0.137020 # miss rate for demand accesses
1078system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022178 # miss rate for overall accesses
1079system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047635 # miss rate for overall accesses
1080system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079333 # miss rate for overall accesses
1081system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258060 # miss rate for overall accesses
1082system.cpu0.l2cache.overall_miss_rate::total 0.137020 # miss rate for overall accesses
1083system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average ReadReq miss latency
1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 42704.668695 # average ReadReq miss latency
1085system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40091.152744 # average ReadReq miss latency
1086system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14045.052065 # average UpgradeReq miss latency
1087system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14045.052065 # average UpgradeReq miss latency
1088system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9973.006274 # average SCUpgradeReq miss latency
1089system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9973.006274 # average SCUpgradeReq miss latency
1090system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 546888.666667 # average SCUpgradeFailReq miss latency
1091system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 546888.666667 # average SCUpgradeFailReq miss latency
1092system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63066.091226 # average ReadExReq miss latency
1093system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63066.091226 # average ReadExReq miss latency
1094system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37576.176847 # average ReadCleanReq miss latency
1095system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37576.176847 # average ReadCleanReq miss latency
1096system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38901.522538 # average ReadSharedReq miss latency
1097system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38901.522538 # average ReadSharedReq miss latency
1098system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 113694.400725 # average InvalidateReq miss latency
1099system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 113694.400725 # average InvalidateReq miss latency
1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average overall miss latency
1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 42704.668695 # average overall miss latency
1102system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37576.176847 # average overall miss latency
1103system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 44139.446079 # average overall miss latency
1104system.cpu0.l2cache.demand_avg_miss_latency::total 41752.444962 # average overall miss latency
1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38339.464586 # average overall miss latency
1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 42704.668695 # average overall miss latency
1107system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37576.176847 # average overall miss latency
1108system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 44139.446079 # average overall miss latency
1109system.cpu0.l2cache.overall_avg_miss_latency::total 41752.444962 # average overall miss latency
1110system.cpu0.l2cache.blocked_cycles::no_mshrs 34 # number of cycles access was blocked
1111system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1112system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1113system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1114system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked
1115system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1116system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1117system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1118system.cpu0.l2cache.writebacks::writebacks 1535075 # number of writebacks
1119system.cpu0.l2cache.writebacks::total 1535075 # number of writebacks
1120system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
1121system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1122system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5686 # number of ReadExReq MSHR hits
1123system.cpu0.l2cache.ReadExReq_mshr_hits::total 5686 # number of ReadExReq MSHR hits
1124system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits
1125system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
1126system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1129 # number of ReadSharedReq MSHR hits
1127system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1129 # number of ReadSharedReq MSHR hits
1128system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
1129system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
1130system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6815 # number of demand (read+write) MSHR hits
1131system.cpu0.l2cache.demand_mshr_hits::total 6824 # number of demand (read+write) MSHR hits
1132system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
1133system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
1134system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6815 # number of overall MSHR hits
1135system.cpu0.l2cache.overall_mshr_hits::total 6824 # number of overall MSHR hits
1136system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11281 # number of ReadReq MSHR misses
1137system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7559 # number of ReadReq MSHR misses
1138system.cpu0.l2cache.ReadReq_mshr_misses::total 18840 # number of ReadReq MSHR misses
1139system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 764184 # number of HardPFReq MSHR misses
1140system.cpu0.l2cache.HardPFReq_mshr_misses::total 764184 # number of HardPFReq MSHR misses
1141system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256026 # number of UpgradeReq MSHR misses
1142system.cpu0.l2cache.UpgradeReq_mshr_misses::total 256026 # number of UpgradeReq MSHR misses
1143system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 194786 # number of SCUpgradeReq MSHR misses
1144system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 194786 # number of SCUpgradeReq MSHR misses
1145system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses
1146system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
1147system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 266801 # number of ReadExReq MSHR misses
1148system.cpu0.l2cache.ReadExReq_mshr_misses::total 266801 # number of ReadExReq MSHR misses
1149system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 711003 # number of ReadCleanReq MSHR misses
1150system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 711003 # number of ReadCleanReq MSHR misses
1151system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 983472 # number of ReadSharedReq MSHR misses
1152system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 983472 # number of ReadSharedReq MSHR misses
1153system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 580093 # number of InvalidateReq MSHR misses
1154system.cpu0.l2cache.InvalidateReq_mshr_misses::total 580093 # number of InvalidateReq MSHR misses
1155system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11281 # number of demand (read+write) MSHR misses
1156system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7559 # number of demand (read+write) MSHR misses
1157system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 711003 # number of demand (read+write) MSHR misses
1158system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1250273 # number of demand (read+write) MSHR misses
1159system.cpu0.l2cache.demand_mshr_misses::total 1980116 # number of demand (read+write) MSHR misses
1160system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11281 # number of overall MSHR misses
1161system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7559 # number of overall MSHR misses
1162system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 711003 # number of overall MSHR misses
1163system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1250273 # number of overall MSHR misses
1164system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 764184 # number of overall MSHR misses
1165system.cpu0.l2cache.overall_mshr_misses::total 2744300 # number of overall MSHR misses
1166system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
1167system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
1168system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 67794 # number of ReadReq MSHR uncacheable
1169system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
1170system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable
1171system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
1172system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
1173system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84224 # number of overall MSHR uncacheable misses
1174system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of ReadReq MSHR miss cycles
1175system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 277497500 # number of ReadReq MSHR miss cycles
1176system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 642319000 # number of ReadReq MSHR miss cycles
1177system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of HardPFReq MSHR miss cycles
1178system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 35765340066 # number of HardPFReq MSHR miss cycles
1179system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7977745499 # number of UpgradeReq MSHR miss cycles
1180system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7977745499 # number of UpgradeReq MSHR miss cycles
1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3820823499 # number of SCUpgradeReq MSHR miss cycles
1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3820823499 # number of SCUpgradeReq MSHR miss cycles
1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4591998 # number of SCUpgradeFailReq MSHR miss cycles
1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4591998 # number of SCUpgradeFailReq MSHR miss cycles
1185system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14771566500 # number of ReadExReq MSHR miss cycles
1186system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14771566500 # number of ReadExReq MSHR miss cycles
1187system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 22450783500 # number of ReadCleanReq MSHR miss cycles
1188system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22450783500 # number of ReadCleanReq MSHR miss cycles
1189system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32316263992 # number of ReadSharedReq MSHR miss cycles
1190system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32316263992 # number of ReadSharedReq MSHR miss cycles
1191system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 62472768000 # number of InvalidateReq MSHR miss cycles
1192system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 62472768000 # number of InvalidateReq MSHR miss cycles
1193system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of demand (read+write) MSHR miss cycles
1194system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 277497500 # number of demand (read+write) MSHR miss cycles
1195system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22450783500 # number of demand (read+write) MSHR miss cycles
1196system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 47087830492 # number of demand (read+write) MSHR miss cycles
1197system.cpu0.l2cache.demand_mshr_miss_latency::total 70180932992 # number of demand (read+write) MSHR miss cycles
1198system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364821500 # number of overall MSHR miss cycles
1199system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 277497500 # number of overall MSHR miss cycles
1200system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22450783500 # number of overall MSHR miss cycles
1201system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 47087830492 # number of overall MSHR miss cycles
1202system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 35765340066 # number of overall MSHR miss cycles
1203system.cpu0.l2cache.overall_mshr_miss_latency::total 105946273058 # number of overall MSHR miss cycles
1204system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles
1205system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2653464500 # number of ReadReq MSHR uncacheable cycles
1206system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9649619500 # number of ReadReq MSHR uncacheable cycles
1207system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2767850000 # number of WriteReq MSHR uncacheable cycles
1208system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2767850000 # number of WriteReq MSHR uncacheable cycles
1209system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles
1210system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5421314500 # number of overall MSHR uncacheable cycles
1211system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12417469500 # number of overall MSHR uncacheable cycles
1212system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for ReadReq accesses
1213system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for ReadReq accesses
1214system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028229 # mshr miss rate for ReadReq accesses
1215system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1216system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1217system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998643 # mshr miss rate for UpgradeReq accesses
1218system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998643 # mshr miss rate for UpgradeReq accesses
1219system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1223system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.242429 # mshr miss rate for ReadExReq accesses
1224system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.242429 # mshr miss rate for ReadExReq accesses
1225system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for ReadCleanReq accesses
1226system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079332 # mshr miss rate for ReadCleanReq accesses
1227system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260815 # mshr miss rate for ReadSharedReq accesses
1228system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260815 # mshr miss rate for ReadSharedReq accesses
1229system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.775614 # mshr miss rate for InvalidateReq accesses
1230system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.775614 # mshr miss rate for InvalidateReq accesses
1231system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for demand accesses
1232system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for demand accesses
1233system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for demand accesses
1234system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for demand accesses
1235system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136550 # mshr miss rate for demand accesses
1236system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for overall accesses
1237system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for overall accesses
1238system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for overall accesses
1239system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for overall accesses
1240system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1241system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189248 # mshr miss rate for overall accesses
1242system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average ReadReq mshr miss latency
1243system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average ReadReq mshr miss latency
1244system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180 # average ReadReq mshr miss latency
1245system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average HardPFReq mshr miss latency
1246system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652 # average HardPFReq mshr miss latency
1247system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678 # average UpgradeReq mshr miss latency
1248system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678 # average UpgradeReq mshr miss latency
1249system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408 # average SCUpgradeReq mshr miss latency
1250system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408 # average SCUpgradeReq mshr miss latency
1251system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 510222 # average SCUpgradeFailReq mshr miss latency
1252system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 510222 # average SCUpgradeFailReq mshr miss latency
1253system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012 # average ReadExReq mshr miss latency
1254system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012 # average ReadExReq mshr miss latency
1255system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average ReadCleanReq mshr miss latency
1256system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868 # average ReadCleanReq mshr miss latency
1257system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553 # average ReadSharedReq mshr miss latency
1258system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553 # average ReadSharedReq mshr miss latency
1259system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725 # average InvalidateReq mshr miss latency
1260system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725 # average InvalidateReq mshr miss latency
1261system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
1262system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
1263system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
1264system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
1265system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203 # average overall mshr miss latency
1266system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency
1267system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency
1268system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency
1269system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency
1270system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average overall mshr miss latency
1271system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054 # average overall mshr miss latency
1272system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
1273system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504 # average ReadReq mshr uncacheable latency
1274system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614 # average ReadReq mshr uncacheable latency
1275system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115 # average WriteReq mshr uncacheable latency
1276system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115 # average WriteReq mshr uncacheable latency
1277system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
1278system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109 # average overall mshr uncacheable latency
1279system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895 # average overall mshr uncacheable latency
1280system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1281system.cpu0.toL2Bus.snoop_filter.tot_requests 29837081 # Total number of requests made to the snoop filter.
1282system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15255646 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1283system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2671 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1284system.cpu0.toL2Bus.snoop_filter.tot_snoops 2145858 # Total number of snoops made to the snoop filter.
1285system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2145409 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1286system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 449 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1287system.cpu0.toL2Bus.trans_dist::ReadReq 816702 # Transaction distribution
1288system.cpu0.toL2Bus.trans_dist::ReadResp 13639128 # Transaction distribution
1289system.cpu0.toL2Bus.trans_dist::WriteReq 16430 # Transaction distribution
1290system.cpu0.toL2Bus.trans_dist::WriteResp 16430 # Transaction distribution
1291system.cpu0.toL2Bus.trans_dist::WritebackDirty 5128977 # Transaction distribution
1292system.cpu0.toL2Bus.trans_dist::WritebackClean 10898588 # Transaction distribution
1293system.cpu0.toL2Bus.trans_dist::CleanEvict 2922524 # Transaction distribution
1294system.cpu0.toL2Bus.trans_dist::HardPFReq 983530 # Transaction distribution
1295system.cpu0.toL2Bus.trans_dist::UpgradeReq 456186 # Transaction distribution
1296system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 346923 # Transaction distribution
1297system.cpu0.toL2Bus.trans_dist::UpgradeResp 512261 # Transaction distribution
1298system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution
1299system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
1300system.cpu0.toL2Bus.trans_dist::ReadExReq 1174017 # Transaction distribution
1301system.cpu0.toL2Bus.trans_dist::ReadExResp 1108975 # Transaction distribution
1302system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8962372 # Transaction distribution
1303system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4744543 # Transaction distribution
1304system.cpu0.toL2Bus.trans_dist::InvalidateReq 755832 # Transaction distribution
1305system.cpu0.toL2Bus.trans_dist::InvalidateResp 747915 # Transaction distribution
1306system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26989618 # Packet count per connected master and slave (bytes)
1307system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17891664 # Packet count per connected master and slave (bytes)
1308system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 337201 # Packet count per connected master and slave (bytes)
1309system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1079102 # Packet count per connected master and slave (bytes)
1310system.cpu0.toL2Bus.pkt_count::total 46297585 # Packet count per connected master and slave (bytes)
1311system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1150395968 # Cumulative packet size per connected master and slave (bytes)
1312system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671911459 # Cumulative packet size per connected master and slave (bytes)
1313system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1269832 # Cumulative packet size per connected master and slave (bytes)
1314system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4069344 # Cumulative packet size per connected master and slave (bytes)
1315system.cpu0.toL2Bus.pkt_size::total 1827646603 # Cumulative packet size per connected master and slave (bytes)
1316system.cpu0.toL2Bus.snoops 7092856 # Total snoops (count)
1317system.cpu0.toL2Bus.snoop_fanout::samples 22718303 # Request fanout histogram
1318system.cpu0.toL2Bus.snoop_fanout::mean 0.108382 # Request fanout histogram
1319system.cpu0.toL2Bus.snoop_fanout::stdev 0.310926 # Request fanout histogram
1320system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1321system.cpu0.toL2Bus.snoop_fanout::0 20256496 89.16% 89.16% # Request fanout histogram
1322system.cpu0.toL2Bus.snoop_fanout::1 2461358 10.83% 100.00% # Request fanout histogram
1323system.cpu0.toL2Bus.snoop_fanout::2 449 0.00% 100.00% # Request fanout histogram
1324system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1325system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1326system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1327system.cpu0.toL2Bus.snoop_fanout::total 22718303 # Request fanout histogram
1328system.cpu0.toL2Bus.reqLayer0.occupancy 29677749987 # Layer occupancy (ticks)
1329system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1330system.cpu0.toL2Bus.snoopLayer0.occupancy 177431926 # Layer occupancy (ticks)
1331system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1332system.cpu0.toL2Bus.respLayer0.occupancy 13525621280 # Layer occupancy (ticks)
1333system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1334system.cpu0.toL2Bus.respLayer1.occupancy 7933800899 # Layer occupancy (ticks)
1335system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1336system.cpu0.toL2Bus.respLayer2.occupancy 178529385 # Layer occupancy (ticks)
1337system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1338system.cpu0.toL2Bus.respLayer3.occupancy 570584194 # Layer occupancy (ticks)
1339system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1340system.cpu1.branchPred.lookups 131141392 # Number of BP lookups
1341system.cpu1.branchPred.condPredicted 92458444 # Number of conditional branches predicted
1342system.cpu1.branchPred.condIncorrect 6313157 # Number of conditional branches incorrect
1343system.cpu1.branchPred.BTBLookups 97645974 # Number of BTB lookups
1344system.cpu1.branchPred.BTBHits 70218111 # Number of BTB hits
1345system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1346system.cpu1.branchPred.BTBHitPct 71.910913 # BTB Hit Percentage
1347system.cpu1.branchPred.usedRAS 15567912 # Number of times the RAS was used to get a target.
1348system.cpu1.branchPred.RASInCorrect 1046402 # Number of incorrect RAS predictions.
1349system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1350system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1351system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1352system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1353system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1354system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1355system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1356system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1370system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1371system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1372system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1373system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1374system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1375system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1376system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1377system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1378system.cpu1.dtb.walker.walks 286101 # Table walker walks requested
1379system.cpu1.dtb.walker.walksLong 286101 # Table walker walks initiated with long descriptors
1380system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9457 # Level at which table walker walks with long descriptors terminate
1381system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80855 # Level at which table walker walks with long descriptors terminate
1382system.cpu1.dtb.walker.walkWaitTime::samples 286101 # Table walker wait (enqueue to first request) latency
1383system.cpu1.dtb.walker.walkWaitTime::0 286101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1384system.cpu1.dtb.walker.walkWaitTime::total 286101 # Table walker wait (enqueue to first request) latency
1385system.cpu1.dtb.walker.walkCompletionTime::samples 90312 # Table walker service (enqueue to completion) latency
1386system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486 # Table walker service (enqueue to completion) latency
1387system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691 # Table walker service (enqueue to completion) latency
1388system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334 # Table walker service (enqueue to completion) latency
1389system.cpu1.dtb.walker.walkCompletionTime::0-65535 89271 98.85% 98.85% # Table walker service (enqueue to completion) latency
1390system.cpu1.dtb.walker.walkCompletionTime::65536-131071 163 0.18% 99.03% # Table walker service (enqueue to completion) latency
1391system.cpu1.dtb.walker.walkCompletionTime::131072-196607 728 0.81% 99.83% # Table walker service (enqueue to completion) latency
1392system.cpu1.dtb.walker.walkCompletionTime::196608-262143 35 0.04% 99.87% # Table walker service (enqueue to completion) latency
1393system.cpu1.dtb.walker.walkCompletionTime::262144-327679 43 0.05% 99.92% # Table walker service (enqueue to completion) latency
1394system.cpu1.dtb.walker.walkCompletionTime::327680-393215 28 0.03% 99.95% # Table walker service (enqueue to completion) latency
1395system.cpu1.dtb.walker.walkCompletionTime::393216-458751 30 0.03% 99.98% # Table walker service (enqueue to completion) latency
1396system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1397system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
1398system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1399system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1400system.cpu1.dtb.walker.walkCompletionTime::total 90312 # Table walker service (enqueue to completion) latency
1401system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution
1402system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution
1403system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution
1404system.cpu1.dtb.walker.walkPageSizes::4K 80855 89.53% 89.53% # Table walker page sizes translated
1405system.cpu1.dtb.walker.walkPageSizes::2M 9457 10.47% 100.00% # Table walker page sizes translated
1406system.cpu1.dtb.walker.walkPageSizes::total 90312 # Table walker page sizes translated
1407system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 286101 # Table walker requests started/completed, data/inst
1408system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1409system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 286101 # Table walker requests started/completed, data/inst
1410system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90312 # Table walker requests started/completed, data/inst
1411system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1412system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90312 # Table walker requests started/completed, data/inst
1413system.cpu1.dtb.walker.walkRequestOrigin::total 376413 # Table walker requests started/completed, data/inst
1414system.cpu1.dtb.inst_hits 0 # ITB inst hits
1415system.cpu1.dtb.inst_misses 0 # ITB inst misses
1416system.cpu1.dtb.read_hits 84597106 # DTB read hits
1417system.cpu1.dtb.read_misses 236435 # DTB read misses
1418system.cpu1.dtb.write_hits 75395592 # DTB write hits
1419system.cpu1.dtb.write_misses 49666 # DTB write misses
1420system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1421system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1422system.cpu1.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
1423system.cpu1.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
1424system.cpu1.dtb.flush_entries 35920 # Number of entries that have been flushed from TLB
1425system.cpu1.dtb.align_faults 1878 # Number of TLB faults due to alignment restrictions
1426system.cpu1.dtb.prefetch_faults 8819 # Number of TLB faults due to prefetch
1427system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1428system.cpu1.dtb.perms_faults 11434 # Number of TLB faults due to permissions restrictions
1429system.cpu1.dtb.read_accesses 84833541 # DTB read accesses
1430system.cpu1.dtb.write_accesses 75445258 # DTB write accesses
1431system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1432system.cpu1.dtb.hits 159992698 # DTB hits
1433system.cpu1.dtb.misses 286101 # DTB misses
1434system.cpu1.dtb.accesses 160278799 # DTB accesses
1435system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1436system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1437system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1441system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1442system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1456system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1457system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1458system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1459system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1460system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1461system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1462system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1463system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1464system.cpu1.itb.walker.walks 70499 # Table walker walks requested
1465system.cpu1.itb.walker.walksLong 70499 # Table walker walks initiated with long descriptors
1466system.cpu1.itb.walker.walksLongTerminationLevel::Level2 664 # Level at which table walker walks with long descriptors terminate
1467system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63113 # Level at which table walker walks with long descriptors terminate
1468system.cpu1.itb.walker.walkWaitTime::samples 70499 # Table walker wait (enqueue to first request) latency
1469system.cpu1.itb.walker.walkWaitTime::0 70499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1470system.cpu1.itb.walker.walkWaitTime::total 70499 # Table walker wait (enqueue to first request) latency
1471system.cpu1.itb.walker.walkCompletionTime::samples 63777 # Table walker service (enqueue to completion) latency
1472system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917 # Table walker service (enqueue to completion) latency
1473system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979 # Table walker service (enqueue to completion) latency
1474system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290 # Table walker service (enqueue to completion) latency
1475system.cpu1.itb.walker.walkCompletionTime::0-65535 62694 98.30% 98.30% # Table walker service (enqueue to completion) latency
1476system.cpu1.itb.walker.walkCompletionTime::65536-131071 8 0.01% 98.31% # Table walker service (enqueue to completion) latency
1477system.cpu1.itb.walker.walkCompletionTime::131072-196607 977 1.53% 99.85% # Table walker service (enqueue to completion) latency
1478system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.03% 99.88% # Table walker service (enqueue to completion) latency
1479system.cpu1.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
1480system.cpu1.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.99% # Table walker service (enqueue to completion) latency
1481system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
1482system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1483system.cpu1.itb.walker.walkCompletionTime::total 63777 # Table walker service (enqueue to completion) latency
1484system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution
1485system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution
1486system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution
1487system.cpu1.itb.walker.walkPageSizes::4K 63113 98.96% 98.96% # Table walker page sizes translated
1488system.cpu1.itb.walker.walkPageSizes::2M 664 1.04% 100.00% # Table walker page sizes translated
1489system.cpu1.itb.walker.walkPageSizes::total 63777 # Table walker page sizes translated
1490system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1491system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 70499 # Table walker requests started/completed, data/inst
1492system.cpu1.itb.walker.walkRequestOrigin_Requested::total 70499 # Table walker requests started/completed, data/inst
1493system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1494system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63777 # Table walker requests started/completed, data/inst
1495system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63777 # Table walker requests started/completed, data/inst
1496system.cpu1.itb.walker.walkRequestOrigin::total 134276 # Table walker requests started/completed, data/inst
1497system.cpu1.itb.inst_hits 232338774 # ITB inst hits
1498system.cpu1.itb.inst_misses 70499 # ITB inst misses
1499system.cpu1.itb.read_hits 0 # DTB read hits
1500system.cpu1.itb.read_misses 0 # DTB read misses
1501system.cpu1.itb.write_hits 0 # DTB write hits
1502system.cpu1.itb.write_misses 0 # DTB write misses
1503system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1504system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1505system.cpu1.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID
1506system.cpu1.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID
1507system.cpu1.itb.flush_entries 25488 # Number of entries that have been flushed from TLB
1508system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1509system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1510system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1511system.cpu1.itb.perms_faults 208774 # Number of TLB faults due to permissions restrictions
1512system.cpu1.itb.read_accesses 0 # DTB read accesses
1513system.cpu1.itb.write_accesses 0 # DTB write accesses
1514system.cpu1.itb.inst_accesses 232409273 # ITB inst accesses
1515system.cpu1.itb.hits 232338774 # DTB hits
1516system.cpu1.itb.misses 70499 # DTB misses
1517system.cpu1.itb.accesses 232409273 # DTB accesses
1518system.cpu1.numCycles 934140798 # number of cpu cycles simulated
1519system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1520system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1521system.cpu1.committedInsts 431679438 # Number of instructions committed
1522system.cpu1.committedOps 508807266 # Number of ops (including micro ops) committed
1523system.cpu1.discardedOps 44929639 # Number of ops (including micro ops) which were discarded before commit
1524system.cpu1.numFetchSuspends 4564 # Number of times Execute suspended instruction fetching
1525system.cpu1.quiesceCycles 93829974504 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1526system.cpu1.cpi 2.163969 # CPI: cycles per instruction
1527system.cpu1.ipc 0.462114 # IPC: instructions per cycle
1528system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1529system.cpu1.kern.inst.quiesce 13472 # number of quiesce instructions executed
1530system.cpu1.tickCycles 702823433 # Number of cycles that the object actually ticked
1531system.cpu1.idleCycles 231317365 # Total number of cycles that the object has spent stopped
1532system.cpu1.dcache.tags.replacements 5070717 # number of replacements
1533system.cpu1.dcache.tags.tagsinuse 459.449189 # Cycle average of tags in use
1534system.cpu1.dcache.tags.total_refs 152180192 # Total number of references to valid blocks.
1535system.cpu1.dcache.tags.sampled_refs 5071229 # Sample count of references to valid blocks.
1536system.cpu1.dcache.tags.avg_refs 30.008543 # Average number of references to valid blocks.
1537system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit.
1538system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.449189 # Average occupied blocks per requestor
1539system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897362 # Average percentage of cache occupancy
1540system.cpu1.dcache.tags.occ_percent::total 0.897362 # Average percentage of cache occupancy
1541system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1542system.cpu1.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
1543system.cpu1.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
1544system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
1545system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1546system.cpu1.dcache.tags.tag_accesses 322309894 # Number of tag accesses
1547system.cpu1.dcache.tags.data_accesses 322309894 # Number of data accesses
1548system.cpu1.dcache.ReadReq_hits::cpu1.data 77705355 # number of ReadReq hits
1549system.cpu1.dcache.ReadReq_hits::total 77705355 # number of ReadReq hits
1550system.cpu1.dcache.WriteReq_hits::cpu1.data 70371137 # number of WriteReq hits
1551system.cpu1.dcache.WriteReq_hits::total 70371137 # number of WriteReq hits
1552system.cpu1.dcache.SoftPFReq_hits::cpu1.data 247594 # number of SoftPFReq hits
1553system.cpu1.dcache.SoftPFReq_hits::total 247594 # number of SoftPFReq hits
1554system.cpu1.dcache.WriteLineReq_hits::cpu1.data 180643 # number of WriteLineReq hits
1555system.cpu1.dcache.WriteLineReq_hits::total 180643 # number of WriteLineReq hits
1556system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624088 # number of LoadLockedReq hits
1557system.cpu1.dcache.LoadLockedReq_hits::total 1624088 # number of LoadLockedReq hits
1558system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1588942 # number of StoreCondReq hits
1559system.cpu1.dcache.StoreCondReq_hits::total 1588942 # number of StoreCondReq hits
1560system.cpu1.dcache.demand_hits::cpu1.data 148076492 # number of demand (read+write) hits
1561system.cpu1.dcache.demand_hits::total 148076492 # number of demand (read+write) hits
1562system.cpu1.dcache.overall_hits::cpu1.data 148324086 # number of overall hits
1563system.cpu1.dcache.overall_hits::total 148324086 # number of overall hits
1564system.cpu1.dcache.ReadReq_misses::cpu1.data 3222913 # number of ReadReq misses
1565system.cpu1.dcache.ReadReq_misses::total 3222913 # number of ReadReq misses
1566system.cpu1.dcache.WriteReq_misses::cpu1.data 2183254 # number of WriteReq misses
1567system.cpu1.dcache.WriteReq_misses::total 2183254 # number of WriteReq misses
1568system.cpu1.dcache.SoftPFReq_misses::cpu1.data 592382 # number of SoftPFReq misses
1569system.cpu1.dcache.SoftPFReq_misses::total 592382 # number of SoftPFReq misses
1570system.cpu1.dcache.WriteLineReq_misses::cpu1.data 513289 # number of WriteLineReq misses
1571system.cpu1.dcache.WriteLineReq_misses::total 513289 # number of WriteLineReq misses
1572system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 153645 # number of LoadLockedReq misses
1573system.cpu1.dcache.LoadLockedReq_misses::total 153645 # number of LoadLockedReq misses
1574system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187516 # number of StoreCondReq misses
1575system.cpu1.dcache.StoreCondReq_misses::total 187516 # number of StoreCondReq misses
1576system.cpu1.dcache.demand_misses::cpu1.data 5406167 # number of demand (read+write) misses
1577system.cpu1.dcache.demand_misses::total 5406167 # number of demand (read+write) misses
1578system.cpu1.dcache.overall_misses::cpu1.data 5998549 # number of overall misses
1579system.cpu1.dcache.overall_misses::total 5998549 # number of overall misses
1580system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52049628500 # number of ReadReq miss cycles
1581system.cpu1.dcache.ReadReq_miss_latency::total 52049628500 # number of ReadReq miss cycles
1582system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 47596189000 # number of WriteReq miss cycles
1583system.cpu1.dcache.WriteReq_miss_latency::total 47596189000 # number of WriteReq miss cycles
1584system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20614887000 # number of WriteLineReq miss cycles
1585system.cpu1.dcache.WriteLineReq_miss_latency::total 20614887000 # number of WriteLineReq miss cycles
1586system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2521232500 # number of LoadLockedReq miss cycles
1587system.cpu1.dcache.LoadLockedReq_miss_latency::total 2521232500 # number of LoadLockedReq miss cycles
1588system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5224495500 # number of StoreCondReq miss cycles
1589system.cpu1.dcache.StoreCondReq_miss_latency::total 5224495500 # number of StoreCondReq miss cycles
1590system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4869500 # number of StoreCondFailReq miss cycles
1591system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4869500 # number of StoreCondFailReq miss cycles
1592system.cpu1.dcache.demand_miss_latency::cpu1.data 99645817500 # number of demand (read+write) miss cycles
1593system.cpu1.dcache.demand_miss_latency::total 99645817500 # number of demand (read+write) miss cycles
1594system.cpu1.dcache.overall_miss_latency::cpu1.data 99645817500 # number of overall miss cycles
1595system.cpu1.dcache.overall_miss_latency::total 99645817500 # number of overall miss cycles
1596system.cpu1.dcache.ReadReq_accesses::cpu1.data 80928268 # number of ReadReq accesses(hits+misses)
1597system.cpu1.dcache.ReadReq_accesses::total 80928268 # number of ReadReq accesses(hits+misses)
1598system.cpu1.dcache.WriteReq_accesses::cpu1.data 72554391 # number of WriteReq accesses(hits+misses)
1599system.cpu1.dcache.WriteReq_accesses::total 72554391 # number of WriteReq accesses(hits+misses)
1600system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 839976 # number of SoftPFReq accesses(hits+misses)
1601system.cpu1.dcache.SoftPFReq_accesses::total 839976 # number of SoftPFReq accesses(hits+misses)
1602system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 693932 # number of WriteLineReq accesses(hits+misses)
1603system.cpu1.dcache.WriteLineReq_accesses::total 693932 # number of WriteLineReq accesses(hits+misses)
1604system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1777733 # number of LoadLockedReq accesses(hits+misses)
1605system.cpu1.dcache.LoadLockedReq_accesses::total 1777733 # number of LoadLockedReq accesses(hits+misses)
1606system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1776458 # number of StoreCondReq accesses(hits+misses)
1607system.cpu1.dcache.StoreCondReq_accesses::total 1776458 # number of StoreCondReq accesses(hits+misses)
1608system.cpu1.dcache.demand_accesses::cpu1.data 153482659 # number of demand (read+write) accesses
1609system.cpu1.dcache.demand_accesses::total 153482659 # number of demand (read+write) accesses
1610system.cpu1.dcache.overall_accesses::cpu1.data 154322635 # number of overall (read+write) accesses
1611system.cpu1.dcache.overall_accesses::total 154322635 # number of overall (read+write) accesses
1612system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039824 # miss rate for ReadReq accesses
1613system.cpu1.dcache.ReadReq_miss_rate::total 0.039824 # miss rate for ReadReq accesses
1614system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030091 # miss rate for WriteReq accesses
1615system.cpu1.dcache.WriteReq_miss_rate::total 0.030091 # miss rate for WriteReq accesses
1616system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.705237 # miss rate for SoftPFReq accesses
1617system.cpu1.dcache.SoftPFReq_miss_rate::total 0.705237 # miss rate for SoftPFReq accesses
1618system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739682 # miss rate for WriteLineReq accesses
1619system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739682 # miss rate for WriteLineReq accesses
1620system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086427 # miss rate for LoadLockedReq accesses
1621system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086427 # miss rate for LoadLockedReq accesses
1622system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105556 # miss rate for StoreCondReq accesses
1623system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105556 # miss rate for StoreCondReq accesses
1624system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035223 # miss rate for demand accesses
1625system.cpu1.dcache.demand_miss_rate::total 0.035223 # miss rate for demand accesses
1626system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038870 # miss rate for overall accesses
1627system.cpu1.dcache.overall_miss_rate::total 0.038870 # miss rate for overall accesses
1628system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16149.870785 # average ReadReq miss latency
1629system.cpu1.dcache.ReadReq_avg_miss_latency::total 16149.870785 # average ReadReq miss latency
1630system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21800.573364 # average WriteReq miss latency
1631system.cpu1.dcache.WriteReq_avg_miss_latency::total 21800.573364 # average WriteReq miss latency
1632system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40162.339345 # average WriteLineReq miss latency
1633system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 40162.339345 # average WriteLineReq miss latency
1634system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16409.466628 # average LoadLockedReq miss latency
1635system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16409.466628 # average LoadLockedReq miss latency
1636system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27861.598477 # average StoreCondReq miss latency
1637system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27861.598477 # average StoreCondReq miss latency
1638system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1639system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1640system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18431.879278 # average overall miss latency
1641system.cpu1.dcache.demand_avg_miss_latency::total 18431.879278 # average overall miss latency
1642system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16611.653502 # average overall miss latency
1643system.cpu1.dcache.overall_avg_miss_latency::total 16611.653502 # average overall miss latency
1644system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1645system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1646system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1647system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1648system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1649system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1650system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1651system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1652system.cpu1.dcache.writebacks::writebacks 5070732 # number of writebacks
1653system.cpu1.dcache.writebacks::total 5070732 # number of writebacks
1654system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 348629 # number of ReadReq MSHR hits
1655system.cpu1.dcache.ReadReq_mshr_hits::total 348629 # number of ReadReq MSHR hits
1656system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 899898 # number of WriteReq MSHR hits
1657system.cpu1.dcache.WriteReq_mshr_hits::total 899898 # number of WriteReq MSHR hits
1658system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 110 # number of WriteLineReq MSHR hits
1659system.cpu1.dcache.WriteLineReq_mshr_hits::total 110 # number of WriteLineReq MSHR hits
1660system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43396 # number of LoadLockedReq MSHR hits
1661system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43396 # number of LoadLockedReq MSHR hits
1662system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 20 # number of StoreCondReq MSHR hits
1663system.cpu1.dcache.StoreCondReq_mshr_hits::total 20 # number of StoreCondReq MSHR hits
1664system.cpu1.dcache.demand_mshr_hits::cpu1.data 1248527 # number of demand (read+write) MSHR hits
1665system.cpu1.dcache.demand_mshr_hits::total 1248527 # number of demand (read+write) MSHR hits
1666system.cpu1.dcache.overall_mshr_hits::cpu1.data 1248527 # number of overall MSHR hits
1667system.cpu1.dcache.overall_mshr_hits::total 1248527 # number of overall MSHR hits
1668system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2874284 # number of ReadReq MSHR misses
1669system.cpu1.dcache.ReadReq_mshr_misses::total 2874284 # number of ReadReq MSHR misses
1670system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1283356 # number of WriteReq MSHR misses
1671system.cpu1.dcache.WriteReq_mshr_misses::total 1283356 # number of WriteReq MSHR misses
1672system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 591957 # number of SoftPFReq MSHR misses
1673system.cpu1.dcache.SoftPFReq_mshr_misses::total 591957 # number of SoftPFReq MSHR misses
1674system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 513179 # number of WriteLineReq MSHR misses
1675system.cpu1.dcache.WriteLineReq_mshr_misses::total 513179 # number of WriteLineReq MSHR misses
1676system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 110249 # number of LoadLockedReq MSHR misses
1677system.cpu1.dcache.LoadLockedReq_mshr_misses::total 110249 # number of LoadLockedReq MSHR misses
1678system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187496 # number of StoreCondReq MSHR misses
1679system.cpu1.dcache.StoreCondReq_mshr_misses::total 187496 # number of StoreCondReq MSHR misses
1680system.cpu1.dcache.demand_mshr_misses::cpu1.data 4157640 # number of demand (read+write) MSHR misses
1681system.cpu1.dcache.demand_mshr_misses::total 4157640 # number of demand (read+write) MSHR misses
1682system.cpu1.dcache.overall_mshr_misses::cpu1.data 4749597 # number of overall MSHR misses
1683system.cpu1.dcache.overall_mshr_misses::total 4749597 # number of overall MSHR misses
1684system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
1685system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22695 # number of ReadReq MSHR uncacheable
1686system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
1687system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable
1688system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
1689system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44342 # number of overall MSHR uncacheable misses
1690system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41633767000 # number of ReadReq MSHR miss cycles
1691system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41633767000 # number of ReadReq MSHR miss cycles
1692system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 28169318500 # number of WriteReq MSHR miss cycles
1693system.cpu1.dcache.WriteReq_mshr_miss_latency::total 28169318500 # number of WriteReq MSHR miss cycles
1694system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14402198000 # number of SoftPFReq MSHR miss cycles
1695system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14402198000 # number of SoftPFReq MSHR miss cycles
1696system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20089556500 # number of WriteLineReq MSHR miss cycles
1697system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20089556500 # number of WriteLineReq MSHR miss cycles
1698system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1594381500 # number of LoadLockedReq MSHR miss cycles
1699system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1594381500 # number of LoadLockedReq MSHR miss cycles
1700system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035777500 # number of StoreCondReq MSHR miss cycles
1701system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035777500 # number of StoreCondReq MSHR miss cycles
1702system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4638000 # number of StoreCondFailReq MSHR miss cycles
1703system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4638000 # number of StoreCondFailReq MSHR miss cycles
1704system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69803085500 # number of demand (read+write) MSHR miss cycles
1705system.cpu1.dcache.demand_mshr_miss_latency::total 69803085500 # number of demand (read+write) MSHR miss cycles
1706system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 84205283500 # number of overall MSHR miss cycles
1707system.cpu1.dcache.overall_mshr_miss_latency::total 84205283500 # number of overall MSHR miss cycles
1708system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4145895000 # number of ReadReq MSHR uncacheable cycles
1709system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4145895000 # number of ReadReq MSHR uncacheable cycles
1710system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4016889500 # number of WriteReq MSHR uncacheable cycles
1711system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4016889500 # number of WriteReq MSHR uncacheable cycles
1712system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8162784500 # number of overall MSHR uncacheable cycles
1713system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8162784500 # number of overall MSHR uncacheable cycles
1714system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035516 # mshr miss rate for ReadReq accesses
1715system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035516 # mshr miss rate for ReadReq accesses
1716system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017688 # mshr miss rate for WriteReq accesses
1717system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017688 # mshr miss rate for WriteReq accesses
1718system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.704731 # mshr miss rate for SoftPFReq accesses
1719system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.704731 # mshr miss rate for SoftPFReq accesses
1720system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.739523 # mshr miss rate for WriteLineReq accesses
1721system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739523 # mshr miss rate for WriteLineReq accesses
1722system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062017 # mshr miss rate for LoadLockedReq accesses
1723system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062017 # mshr miss rate for LoadLockedReq accesses
1724system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105545 # mshr miss rate for StoreCondReq accesses
1725system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105545 # mshr miss rate for StoreCondReq accesses
1726system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027089 # mshr miss rate for demand accesses
1727system.cpu1.dcache.demand_mshr_miss_rate::total 0.027089 # mshr miss rate for demand accesses
1728system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030777 # mshr miss rate for overall accesses
1729system.cpu1.dcache.overall_mshr_miss_rate::total 0.030777 # mshr miss rate for overall accesses
1730system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635 # average ReadReq mshr miss latency
1731system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635 # average ReadReq mshr miss latency
1732system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628 # average WriteReq mshr miss latency
1733system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628 # average WriteReq mshr miss latency
1734system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361 # average SoftPFReq mshr miss latency
1735system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361 # average SoftPFReq mshr miss latency
1736system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276 # average WriteLineReq mshr miss latency
1737system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276 # average WriteLineReq mshr miss latency
1738system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375 # average LoadLockedReq mshr miss latency
1739system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375 # average LoadLockedReq mshr miss latency
1740system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972 # average StoreCondReq mshr miss latency
1741system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972 # average StoreCondReq mshr miss latency
1742system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1743system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1744system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16789.112453 # average overall mshr miss latency
1745system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16789.112453 # average overall mshr miss latency
1746system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17728.932265 # average overall mshr miss latency
1747system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17728.932265 # average overall mshr miss latency
1748system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182678.783873 # average ReadReq mshr uncacheable latency
1749system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182678.783873 # average ReadReq mshr uncacheable latency
1750system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185563.334411 # average WriteReq mshr uncacheable latency
1751system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185563.334411 # average WriteReq mshr uncacheable latency
1752system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184086.971720 # average overall mshr uncacheable latency
1753system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720 # average overall mshr uncacheable latency
1754system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1755system.cpu1.icache.tags.replacements 9965841 # number of replacements
1756system.cpu1.icache.tags.tagsinuse 506.684865 # Cycle average of tags in use
1757system.cpu1.icache.tags.total_refs 222156193 # Total number of references to valid blocks.
1758system.cpu1.icache.tags.sampled_refs 9966353 # Sample count of references to valid blocks.
1759system.cpu1.icache.tags.avg_refs 22.290621 # Average number of references to valid blocks.
1760system.cpu1.icache.tags.warmup_cycle 8388652871500 # Cycle when the warmup percentage was hit.
1761system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.684865 # Average occupied blocks per requestor
1762system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989619 # Average percentage of cache occupancy
1763system.cpu1.icache.tags.occ_percent::total 0.989619 # Average percentage of cache occupancy
1764system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1765system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
1766system.cpu1.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
1767system.cpu1.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id
1768system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1769system.cpu1.icache.tags.tag_accesses 474211445 # Number of tag accesses
1770system.cpu1.icache.tags.data_accesses 474211445 # Number of data accesses
1771system.cpu1.icache.ReadReq_hits::cpu1.inst 222156193 # number of ReadReq hits
1772system.cpu1.icache.ReadReq_hits::total 222156193 # number of ReadReq hits
1773system.cpu1.icache.demand_hits::cpu1.inst 222156193 # number of demand (read+write) hits
1774system.cpu1.icache.demand_hits::total 222156193 # number of demand (read+write) hits
1775system.cpu1.icache.overall_hits::cpu1.inst 222156193 # number of overall hits
1776system.cpu1.icache.overall_hits::total 222156193 # number of overall hits
1777system.cpu1.icache.ReadReq_misses::cpu1.inst 9966353 # number of ReadReq misses
1778system.cpu1.icache.ReadReq_misses::total 9966353 # number of ReadReq misses
1779system.cpu1.icache.demand_misses::cpu1.inst 9966353 # number of demand (read+write) misses
1780system.cpu1.icache.demand_misses::total 9966353 # number of demand (read+write) misses
1781system.cpu1.icache.overall_misses::cpu1.inst 9966353 # number of overall misses
1782system.cpu1.icache.overall_misses::total 9966353 # number of overall misses
1783system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 101175482500 # number of ReadReq miss cycles
1784system.cpu1.icache.ReadReq_miss_latency::total 101175482500 # number of ReadReq miss cycles
1785system.cpu1.icache.demand_miss_latency::cpu1.inst 101175482500 # number of demand (read+write) miss cycles
1786system.cpu1.icache.demand_miss_latency::total 101175482500 # number of demand (read+write) miss cycles
1787system.cpu1.icache.overall_miss_latency::cpu1.inst 101175482500 # number of overall miss cycles
1788system.cpu1.icache.overall_miss_latency::total 101175482500 # number of overall miss cycles
1789system.cpu1.icache.ReadReq_accesses::cpu1.inst 232122546 # number of ReadReq accesses(hits+misses)
1790system.cpu1.icache.ReadReq_accesses::total 232122546 # number of ReadReq accesses(hits+misses)
1791system.cpu1.icache.demand_accesses::cpu1.inst 232122546 # number of demand (read+write) accesses
1792system.cpu1.icache.demand_accesses::total 232122546 # number of demand (read+write) accesses
1793system.cpu1.icache.overall_accesses::cpu1.inst 232122546 # number of overall (read+write) accesses
1794system.cpu1.icache.overall_accesses::total 232122546 # number of overall (read+write) accesses
1795system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.042936 # miss rate for ReadReq accesses
1796system.cpu1.icache.ReadReq_miss_rate::total 0.042936 # miss rate for ReadReq accesses
1797system.cpu1.icache.demand_miss_rate::cpu1.inst 0.042936 # miss rate for demand accesses
1798system.cpu1.icache.demand_miss_rate::total 0.042936 # miss rate for demand accesses
1799system.cpu1.icache.overall_miss_rate::cpu1.inst 0.042936 # miss rate for overall accesses
1800system.cpu1.icache.overall_miss_rate::total 0.042936 # miss rate for overall accesses
1801system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10151.705694 # average ReadReq miss latency
1802system.cpu1.icache.ReadReq_avg_miss_latency::total 10151.705694 # average ReadReq miss latency
1803system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
1804system.cpu1.icache.demand_avg_miss_latency::total 10151.705694 # average overall miss latency
1805system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10151.705694 # average overall miss latency
1806system.cpu1.icache.overall_avg_miss_latency::total 10151.705694 # average overall miss latency
1807system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1808system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1809system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1810system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1811system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1812system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1813system.cpu1.icache.fast_writes 0 # number of fast writes performed
1814system.cpu1.icache.cache_copies 0 # number of cache copies performed
1815system.cpu1.icache.writebacks::writebacks 9965841 # number of writebacks
1816system.cpu1.icache.writebacks::total 9965841 # number of writebacks
1817system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9966353 # number of ReadReq MSHR misses
1818system.cpu1.icache.ReadReq_mshr_misses::total 9966353 # number of ReadReq MSHR misses
1819system.cpu1.icache.demand_mshr_misses::cpu1.inst 9966353 # number of demand (read+write) MSHR misses
1820system.cpu1.icache.demand_mshr_misses::total 9966353 # number of demand (read+write) MSHR misses
1821system.cpu1.icache.overall_mshr_misses::cpu1.inst 9966353 # number of overall MSHR misses
1822system.cpu1.icache.overall_mshr_misses::total 9966353 # number of overall MSHR misses
1823system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
1824system.cpu1.icache.ReadReq_mshr_uncacheable::total 92 # number of ReadReq MSHR uncacheable
1825system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
1826system.cpu1.icache.overall_mshr_uncacheable_misses::total 92 # number of overall MSHR uncacheable misses
1827system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 96192306000 # number of ReadReq MSHR miss cycles
1828system.cpu1.icache.ReadReq_mshr_miss_latency::total 96192306000 # number of ReadReq MSHR miss cycles
1829system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 96192306000 # number of demand (read+write) MSHR miss cycles
1830system.cpu1.icache.demand_mshr_miss_latency::total 96192306000 # number of demand (read+write) MSHR miss cycles
1831system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 96192306000 # number of overall MSHR miss cycles
1832system.cpu1.icache.overall_mshr_miss_latency::total 96192306000 # number of overall MSHR miss cycles
1833system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12950500 # number of ReadReq MSHR uncacheable cycles
1834system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 12950500 # number of ReadReq MSHR uncacheable cycles
1835system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 12950500 # number of overall MSHR uncacheable cycles
1836system.cpu1.icache.overall_mshr_uncacheable_latency::total 12950500 # number of overall MSHR uncacheable cycles
1837system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for ReadReq accesses
1838system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.042936 # mshr miss rate for ReadReq accesses
1839system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for demand accesses
1840system.cpu1.icache.demand_mshr_miss_rate::total 0.042936 # mshr miss rate for demand accesses
1841system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.042936 # mshr miss rate for overall accesses
1842system.cpu1.icache.overall_mshr_miss_rate::total 0.042936 # mshr miss rate for overall accesses
1843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average ReadReq mshr miss latency
1844system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9651.705694 # average ReadReq mshr miss latency
1845system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
1846system.cpu1.icache.demand_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
1847system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9651.705694 # average overall mshr miss latency
1848system.cpu1.icache.overall_avg_mshr_miss_latency::total 9651.705694 # average overall mshr miss latency
1849system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency
1850system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency
1851system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency
1852system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency
1853system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1854system.cpu1.l2cache.prefetcher.num_hwpf_issued 6510084 # number of hwpf issued
1855system.cpu1.l2cache.prefetcher.pfIdentified 6511152 # number of prefetch candidates identified
1856system.cpu1.l2cache.prefetcher.pfBufferHit 939 # number of redundant prefetches already in prefetch queue
1857system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1858system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1859system.cpu1.l2cache.prefetcher.pfSpanPage 783896 # number of prefetches not generated due to page crossing
1860system.cpu1.l2cache.tags.replacements 2135895 # number of replacements
1861system.cpu1.l2cache.tags.tagsinuse 13423.461637 # Cycle average of tags in use
1862system.cpu1.l2cache.tags.total_refs 24573645 # Total number of references to valid blocks.
1863system.cpu1.l2cache.tags.sampled_refs 2151628 # Sample count of references to valid blocks.
1864system.cpu1.l2cache.tags.avg_refs 11.420954 # Average number of references to valid blocks.
1865system.cpu1.l2cache.tags.warmup_cycle 9991507442000 # Cycle when the warmup percentage was hit.
1866system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999 # Average occupied blocks per requestor
1867system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.598025 # Average occupied blocks per requestor
1868system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.072993 # Average occupied blocks per requestor
1869system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 692.984620 # Average occupied blocks per requestor
1870system.cpu1.l2cache.tags.occ_percent::writebacks 0.768421 # Average percentage of cache occupancy
1871system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy
1872system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004460 # Average percentage of cache occupancy
1873system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.042296 # Average percentage of cache occupancy
1874system.cpu1.l2cache.tags.occ_percent::total 0.819303 # Average percentage of cache occupancy
1875system.cpu1.l2cache.tags.occ_task_id_blocks::1022 945 # Occupied blocks per task id
1876system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id
1877system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14692 # Occupied blocks per task id
1878system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
1879system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id
1880system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id
1881system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
1882system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
1883system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
1884system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 44 # Occupied blocks per task id
1885system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
1886system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1194 # Occupied blocks per task id
1887system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
1888system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8241 # Occupied blocks per task id
1889system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 388 # Occupied blocks per task id
1890system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.057678 # Percentage of cache occupancy per task id
1891system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id
1892system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896729 # Percentage of cache occupancy per task id
1893system.cpu1.l2cache.tags.tag_accesses 506241329 # Number of tag accesses
1894system.cpu1.l2cache.tags.data_accesses 506241329 # Number of data accesses
1895system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551867 # number of ReadReq hits
1896system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186859 # number of ReadReq hits
1897system.cpu1.l2cache.ReadReq_hits::total 738726 # number of ReadReq hits
1898system.cpu1.l2cache.WritebackDirty_hits::writebacks 3212995 # number of WritebackDirty hits
1899system.cpu1.l2cache.WritebackDirty_hits::total 3212995 # number of WritebackDirty hits
1900system.cpu1.l2cache.WritebackClean_hits::writebacks 11821046 # number of WritebackClean hits
1901system.cpu1.l2cache.WritebackClean_hits::total 11821046 # number of WritebackClean hits
1902system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 371 # number of UpgradeReq hits
1903system.cpu1.l2cache.UpgradeReq_hits::total 371 # number of UpgradeReq hits
1904system.cpu1.l2cache.ReadExReq_hits::cpu1.data 838525 # number of ReadExReq hits
1905system.cpu1.l2cache.ReadExReq_hits::total 838525 # number of ReadExReq hits
1906system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 9300099 # number of ReadCleanReq hits
1907system.cpu1.l2cache.ReadCleanReq_hits::total 9300099 # number of ReadCleanReq hits
1908system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698124 # number of ReadSharedReq hits
1909system.cpu1.l2cache.ReadSharedReq_hits::total 2698124 # number of ReadSharedReq hits
1910system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 249185 # number of InvalidateReq hits
1911system.cpu1.l2cache.InvalidateReq_hits::total 249185 # number of InvalidateReq hits
1912system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 551867 # number of demand (read+write) hits
1913system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186859 # number of demand (read+write) hits
1914system.cpu1.l2cache.demand_hits::cpu1.inst 9300099 # number of demand (read+write) hits
1915system.cpu1.l2cache.demand_hits::cpu1.data 3536649 # number of demand (read+write) hits
1916system.cpu1.l2cache.demand_hits::total 13575474 # number of demand (read+write) hits
1917system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 551867 # number of overall hits
1918system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186859 # number of overall hits
1919system.cpu1.l2cache.overall_hits::cpu1.inst 9300099 # number of overall hits
1920system.cpu1.l2cache.overall_hits::cpu1.data 3536649 # number of overall hits
1921system.cpu1.l2cache.overall_hits::total 13575474 # number of overall hits
1922system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10809 # number of ReadReq misses
1923system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8103 # number of ReadReq misses
1924system.cpu1.l2cache.ReadReq_misses::total 18912 # number of ReadReq misses
1925system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
1926system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
1927system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204693 # number of UpgradeReq misses
1928system.cpu1.l2cache.UpgradeReq_misses::total 204693 # number of UpgradeReq misses
1929system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 187493 # number of SCUpgradeReq misses
1930system.cpu1.l2cache.SCUpgradeReq_misses::total 187493 # number of SCUpgradeReq misses
1931system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
1932system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
1933system.cpu1.l2cache.ReadExReq_misses::cpu1.data 242458 # number of ReadExReq misses
1934system.cpu1.l2cache.ReadExReq_misses::total 242458 # number of ReadExReq misses
1935system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 666254 # number of ReadCleanReq misses
1936system.cpu1.l2cache.ReadCleanReq_misses::total 666254 # number of ReadCleanReq misses
1937system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 877979 # number of ReadSharedReq misses
1938system.cpu1.l2cache.ReadSharedReq_misses::total 877979 # number of ReadSharedReq misses
1939system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 262039 # number of InvalidateReq misses
1940system.cpu1.l2cache.InvalidateReq_misses::total 262039 # number of InvalidateReq misses
1941system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10809 # number of demand (read+write) misses
1942system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8103 # number of demand (read+write) misses
1943system.cpu1.l2cache.demand_misses::cpu1.inst 666254 # number of demand (read+write) misses
1944system.cpu1.l2cache.demand_misses::cpu1.data 1120437 # number of demand (read+write) misses
1945system.cpu1.l2cache.demand_misses::total 1805603 # number of demand (read+write) misses
1946system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10809 # number of overall misses
1947system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8103 # number of overall misses
1948system.cpu1.l2cache.overall_misses::cpu1.inst 666254 # number of overall misses
1949system.cpu1.l2cache.overall_misses::cpu1.data 1120437 # number of overall misses
1950system.cpu1.l2cache.overall_misses::total 1805603 # number of overall misses
1951system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 470190500 # number of ReadReq miss cycles
1952system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 378267000 # number of ReadReq miss cycles
1953system.cpu1.l2cache.ReadReq_miss_latency::total 848457500 # number of ReadReq miss cycles
1954system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3269531500 # number of UpgradeReq miss cycles
1955system.cpu1.l2cache.UpgradeReq_miss_latency::total 3269531500 # number of UpgradeReq miss cycles
1956system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1816771500 # number of SCUpgradeReq miss cycles
1957system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1816771500 # number of SCUpgradeReq miss cycles
1958system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4553499 # number of SCUpgradeFailReq miss cycles
1959system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4553499 # number of SCUpgradeFailReq miss cycles
1960system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12943476999 # number of ReadExReq miss cycles
1961system.cpu1.l2cache.ReadExReq_miss_latency::total 12943476999 # number of ReadExReq miss cycles
1962system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 25012449000 # number of ReadCleanReq miss cycles
1963system.cpu1.l2cache.ReadCleanReq_miss_latency::total 25012449000 # number of ReadCleanReq miss cycles
1964system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34434512490 # number of ReadSharedReq miss cycles
1965system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34434512490 # number of ReadSharedReq miss cycles
1966system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17540729000 # number of InvalidateReq miss cycles
1967system.cpu1.l2cache.InvalidateReq_miss_latency::total 17540729000 # number of InvalidateReq miss cycles
1968system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 470190500 # number of demand (read+write) miss cycles
1969system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 378267000 # number of demand (read+write) miss cycles
1970system.cpu1.l2cache.demand_miss_latency::cpu1.inst 25012449000 # number of demand (read+write) miss cycles
1971system.cpu1.l2cache.demand_miss_latency::cpu1.data 47377989489 # number of demand (read+write) miss cycles
1972system.cpu1.l2cache.demand_miss_latency::total 73238895989 # number of demand (read+write) miss cycles
1973system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 470190500 # number of overall miss cycles
1974system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 378267000 # number of overall miss cycles
1975system.cpu1.l2cache.overall_miss_latency::cpu1.inst 25012449000 # number of overall miss cycles
1976system.cpu1.l2cache.overall_miss_latency::cpu1.data 47377989489 # number of overall miss cycles
1977system.cpu1.l2cache.overall_miss_latency::total 73238895989 # number of overall miss cycles
1978system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 562676 # number of ReadReq accesses(hits+misses)
1979system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 194962 # number of ReadReq accesses(hits+misses)
1980system.cpu1.l2cache.ReadReq_accesses::total 757638 # number of ReadReq accesses(hits+misses)
1981system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3212997 # number of WritebackDirty accesses(hits+misses)
1982system.cpu1.l2cache.WritebackDirty_accesses::total 3212997 # number of WritebackDirty accesses(hits+misses)
1983system.cpu1.l2cache.WritebackClean_accesses::writebacks 11821046 # number of WritebackClean accesses(hits+misses)
1984system.cpu1.l2cache.WritebackClean_accesses::total 11821046 # number of WritebackClean accesses(hits+misses)
1985system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205064 # number of UpgradeReq accesses(hits+misses)
1986system.cpu1.l2cache.UpgradeReq_accesses::total 205064 # number of UpgradeReq accesses(hits+misses)
1987system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187493 # number of SCUpgradeReq accesses(hits+misses)
1988system.cpu1.l2cache.SCUpgradeReq_accesses::total 187493 # number of SCUpgradeReq accesses(hits+misses)
1989system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
1990system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
1991system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1080983 # number of ReadExReq accesses(hits+misses)
1992system.cpu1.l2cache.ReadExReq_accesses::total 1080983 # number of ReadExReq accesses(hits+misses)
1993system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9966353 # number of ReadCleanReq accesses(hits+misses)
1994system.cpu1.l2cache.ReadCleanReq_accesses::total 9966353 # number of ReadCleanReq accesses(hits+misses)
1995system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3576103 # number of ReadSharedReq accesses(hits+misses)
1996system.cpu1.l2cache.ReadSharedReq_accesses::total 3576103 # number of ReadSharedReq accesses(hits+misses)
1997system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 511224 # number of InvalidateReq accesses(hits+misses)
1998system.cpu1.l2cache.InvalidateReq_accesses::total 511224 # number of InvalidateReq accesses(hits+misses)
1999system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 562676 # number of demand (read+write) accesses
2000system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 194962 # number of demand (read+write) accesses
2001system.cpu1.l2cache.demand_accesses::cpu1.inst 9966353 # number of demand (read+write) accesses
2002system.cpu1.l2cache.demand_accesses::cpu1.data 4657086 # number of demand (read+write) accesses
2003system.cpu1.l2cache.demand_accesses::total 15381077 # number of demand (read+write) accesses
2004system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 562676 # number of overall (read+write) accesses
2005system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 194962 # number of overall (read+write) accesses
2006system.cpu1.l2cache.overall_accesses::cpu1.inst 9966353 # number of overall (read+write) accesses
2007system.cpu1.l2cache.overall_accesses::cpu1.data 4657086 # number of overall (read+write) accesses
2008system.cpu1.l2cache.overall_accesses::total 15381077 # number of overall (read+write) accesses
2009system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for ReadReq accesses
2010system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041562 # miss rate for ReadReq accesses
2011system.cpu1.l2cache.ReadReq_miss_rate::total 0.024962 # miss rate for ReadReq accesses
2012system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
2013system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2014system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998191 # miss rate for UpgradeReq accesses
2015system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998191 # miss rate for UpgradeReq accesses
2016system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2017system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2018system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2019system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2020system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224294 # miss rate for ReadExReq accesses
2021system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224294 # miss rate for ReadExReq accesses
2022system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.066850 # miss rate for ReadCleanReq accesses
2023system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.066850 # miss rate for ReadCleanReq accesses
2024system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245513 # miss rate for ReadSharedReq accesses
2025system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245513 # miss rate for ReadSharedReq accesses
2026system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.512572 # miss rate for InvalidateReq accesses
2027system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.512572 # miss rate for InvalidateReq accesses
2028system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for demand accesses
2029system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.041562 # miss rate for demand accesses
2030system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.066850 # miss rate for demand accesses
2031system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240588 # miss rate for demand accesses
2032system.cpu1.l2cache.demand_miss_rate::total 0.117391 # miss rate for demand accesses
2033system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for overall accesses
2034system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.041562 # miss rate for overall accesses
2035system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.066850 # miss rate for overall accesses
2036system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240588 # miss rate for overall accesses
2037system.cpu1.l2cache.overall_miss_rate::total 0.117391 # miss rate for overall accesses
2038system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average ReadReq miss latency
2039system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46682.339874 # average ReadReq miss latency
2040system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44863.446489 # average ReadReq miss latency
2041system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15972.854470 # average UpgradeReq miss latency
2042system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15972.854470 # average UpgradeReq miss latency
2043system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9689.809753 # average SCUpgradeReq miss latency
2044system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9689.809753 # average SCUpgradeReq miss latency
2045system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1517833 # average SCUpgradeFailReq miss latency
2046system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1517833 # average SCUpgradeFailReq miss latency
2047system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53384.408842 # average ReadExReq miss latency
2048system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53384.408842 # average ReadExReq miss latency
2049system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37541.911943 # average ReadCleanReq miss latency
2050system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37541.911943 # average ReadCleanReq miss latency
2051system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39220.200586 # average ReadSharedReq miss latency
2052system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39220.200586 # average ReadSharedReq miss latency
2053system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 66939.383069 # average InvalidateReq miss latency
2054system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 66939.383069 # average InvalidateReq miss latency
2055system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
2056system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
2057system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
2058system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
2059system.cpu1.l2cache.demand_avg_miss_latency::total 40562.015010 # average overall miss latency
2060system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43499.907485 # average overall miss latency
2061system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46682.339874 # average overall miss latency
2062system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37541.911943 # average overall miss latency
2063system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42285.277520 # average overall miss latency
2064system.cpu1.l2cache.overall_avg_miss_latency::total 40562.015010 # average overall miss latency
2065system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2066system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2067system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2068system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2069system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2070system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2071system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2072system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2073system.cpu1.l2cache.writebacks::writebacks 1050489 # number of writebacks
2074system.cpu1.l2cache.writebacks::total 1050489 # number of writebacks
2075system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
2076system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
2077system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5853 # number of ReadExReq MSHR hits
2078system.cpu1.l2cache.ReadExReq_mshr_hits::total 5853 # number of ReadExReq MSHR hits
2079system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 8 # number of ReadCleanReq MSHR hits
2080system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
2081system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 1181 # number of ReadSharedReq MSHR hits
2082system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 1181 # number of ReadSharedReq MSHR hits
2083system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
2084system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
2085system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7034 # number of demand (read+write) MSHR hits
2086system.cpu1.l2cache.demand_mshr_hits::total 7045 # number of demand (read+write) MSHR hits
2087system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
2088system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
2089system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7034 # number of overall MSHR hits
2090system.cpu1.l2cache.overall_mshr_hits::total 7045 # number of overall MSHR hits
2091system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10809 # number of ReadReq MSHR misses
2092system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8100 # number of ReadReq MSHR misses
2093system.cpu1.l2cache.ReadReq_mshr_misses::total 18909 # number of ReadReq MSHR misses
2094system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
2095system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
2096system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 706258 # number of HardPFReq MSHR misses
2097system.cpu1.l2cache.HardPFReq_mshr_misses::total 706258 # number of HardPFReq MSHR misses
2098system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204693 # number of UpgradeReq MSHR misses
2099system.cpu1.l2cache.UpgradeReq_mshr_misses::total 204693 # number of UpgradeReq MSHR misses
2100system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 187493 # number of SCUpgradeReq MSHR misses
2101system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 187493 # number of SCUpgradeReq MSHR misses
2102system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2103system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2104system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 236605 # number of ReadExReq MSHR misses
2105system.cpu1.l2cache.ReadExReq_mshr_misses::total 236605 # number of ReadExReq MSHR misses
2106system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 666246 # number of ReadCleanReq MSHR misses
2107system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 666246 # number of ReadCleanReq MSHR misses
2108system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 876798 # number of ReadSharedReq MSHR misses
2109system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 876798 # number of ReadSharedReq MSHR misses
2110system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 262039 # number of InvalidateReq MSHR misses
2111system.cpu1.l2cache.InvalidateReq_mshr_misses::total 262039 # number of InvalidateReq MSHR misses
2112system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10809 # number of demand (read+write) MSHR misses
2113system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8100 # number of demand (read+write) MSHR misses
2114system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 666246 # number of demand (read+write) MSHR misses
2115system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1113403 # number of demand (read+write) MSHR misses
2116system.cpu1.l2cache.demand_mshr_misses::total 1798558 # number of demand (read+write) MSHR misses
2117system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10809 # number of overall MSHR misses
2118system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8100 # number of overall MSHR misses
2119system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 666246 # number of overall MSHR misses
2120system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1113403 # number of overall MSHR misses
2121system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 706258 # number of overall MSHR misses
2122system.cpu1.l2cache.overall_mshr_misses::total 2504816 # number of overall MSHR misses
2123system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
2124system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22695 # number of ReadReq MSHR uncacheable
2125system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22787 # number of ReadReq MSHR uncacheable
2126system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
2127system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21647 # number of WriteReq MSHR uncacheable
2128system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
2129system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44342 # number of overall MSHR uncacheable misses
2130system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44434 # number of overall MSHR uncacheable misses
2131system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of ReadReq MSHR miss cycles
2132system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 329621500 # number of ReadReq MSHR miss cycles
2133system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 734958000 # number of ReadReq MSHR miss cycles
2134system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of HardPFReq MSHR miss cycles
2135system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32803670450 # number of HardPFReq MSHR miss cycles
2136system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6637113997 # number of UpgradeReq MSHR miss cycles
2137system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6637113997 # number of UpgradeReq MSHR miss cycles
2138system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3625235500 # number of SCUpgradeReq MSHR miss cycles
2139system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3625235500 # number of SCUpgradeReq MSHR miss cycles
2140system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4217499 # number of SCUpgradeFailReq MSHR miss cycles
2141system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4217499 # number of SCUpgradeFailReq MSHR miss cycles
2142system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10699007999 # number of ReadExReq MSHR miss cycles
2143system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10699007999 # number of ReadExReq MSHR miss cycles
2144system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 21014773500 # number of ReadCleanReq MSHR miss cycles
2145system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 21014773500 # number of ReadCleanReq MSHR miss cycles
2146system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29089304990 # number of ReadSharedReq MSHR miss cycles
2147system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29089304990 # number of ReadSharedReq MSHR miss cycles
2148system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15968495000 # number of InvalidateReq MSHR miss cycles
2149system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15968495000 # number of InvalidateReq MSHR miss cycles
2150system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of demand (read+write) MSHR miss cycles
2151system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 329621500 # number of demand (read+write) MSHR miss cycles
2152system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 21014773500 # number of demand (read+write) MSHR miss cycles
2153system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39788312989 # number of demand (read+write) MSHR miss cycles
2154system.cpu1.l2cache.demand_mshr_miss_latency::total 61538044489 # number of demand (read+write) MSHR miss cycles
2155system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405336500 # number of overall MSHR miss cycles
2156system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 329621500 # number of overall MSHR miss cycles
2157system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 21014773500 # number of overall MSHR miss cycles
2158system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39788312989 # number of overall MSHR miss cycles
2159system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803670450 # number of overall MSHR miss cycles
2160system.cpu1.l2cache.overall_mshr_miss_latency::total 94341714939 # number of overall MSHR miss cycles
2161system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12214500 # number of ReadReq MSHR uncacheable cycles
2162system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3964210500 # number of ReadReq MSHR uncacheable cycles
2163system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3976425000 # number of ReadReq MSHR uncacheable cycles
2164system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3854486000 # number of WriteReq MSHR uncacheable cycles
2165system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3854486000 # number of WriteReq MSHR uncacheable cycles
2166system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12214500 # number of overall MSHR uncacheable cycles
2167system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7818696500 # number of overall MSHR uncacheable cycles
2168system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7830911000 # number of overall MSHR uncacheable cycles
2169system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for ReadReq accesses
2170system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for ReadReq accesses
2171system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024958 # mshr miss rate for ReadReq accesses
2172system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
2173system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2174system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2175system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2176system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998191 # mshr miss rate for UpgradeReq accesses
2177system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998191 # mshr miss rate for UpgradeReq accesses
2178system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2179system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2180system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2181system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2182system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218879 # mshr miss rate for ReadExReq accesses
2183system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218879 # mshr miss rate for ReadExReq accesses
2184system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for ReadCleanReq accesses
2185system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.066850 # mshr miss rate for ReadCleanReq accesses
2186system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245183 # mshr miss rate for ReadSharedReq accesses
2187system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245183 # mshr miss rate for ReadSharedReq accesses
2188system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.512572 # mshr miss rate for InvalidateReq accesses
2189system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.512572 # mshr miss rate for InvalidateReq accesses
2190system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for demand accesses
2191system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for demand accesses
2192system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for demand accesses
2193system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for demand accesses
2194system.cpu1.l2cache.demand_mshr_miss_rate::total 0.116933 # mshr miss rate for demand accesses
2195system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for overall accesses
2196system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for overall accesses
2197system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for overall accesses
2198system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for overall accesses
2199system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2200system.cpu1.l2cache.overall_mshr_miss_rate::total 0.162850 # mshr miss rate for overall accesses
2201system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average ReadReq mshr miss latency
2202system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average ReadReq mshr miss latency
2203system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020 # average ReadReq mshr miss latency
2204system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average HardPFReq mshr miss latency
2205system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846 # average HardPFReq mshr miss latency
2206system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840 # average UpgradeReq mshr miss latency
2207system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840 # average UpgradeReq mshr miss latency
2208system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185 # average SCUpgradeReq mshr miss latency
2209system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185 # average SCUpgradeReq mshr miss latency
2210system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1405833 # average SCUpgradeFailReq mshr miss latency
2211system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1405833 # average SCUpgradeFailReq mshr miss latency
2212system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431 # average ReadExReq mshr miss latency
2213system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431 # average ReadExReq mshr miss latency
2214system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average ReadCleanReq mshr miss latency
2215system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292 # average ReadCleanReq mshr miss latency
2216system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514 # average ReadSharedReq mshr miss latency
2217system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514 # average ReadSharedReq mshr miss latency
2218system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069 # average InvalidateReq mshr miss latency
2219system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069 # average InvalidateReq mshr miss latency
2220system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
2221system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
2222system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
2223system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
2224system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681 # average overall mshr miss latency
2225system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency
2226system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency
2227system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency
2228system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency
2229system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average overall mshr miss latency
2230system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796 # average overall mshr miss latency
2231system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency
2232system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083 # average ReadReq mshr uncacheable latency
2233system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217 # average ReadReq mshr uncacheable latency
2234system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427 # average WriteReq mshr uncacheable latency
2235system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427 # average WriteReq mshr uncacheable latency
2236system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency
2237system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228 # average overall mshr uncacheable latency
2238system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175 # average overall mshr uncacheable latency
2239system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2240system.cpu1.toL2Bus.snoop_filter.tot_requests 30858357 # Total number of requests made to the snoop filter.
2241system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15723821 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2242system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2243system.cpu1.toL2Bus.snoop_filter.tot_snoops 1980391 # Total number of snoops made to the snoop filter.
2244system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1980008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2245system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 383 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2246system.cpu1.toL2Bus.trans_dist::ReadReq 850137 # Transaction distribution
2247system.cpu1.toL2Bus.trans_dist::ReadResp 14487242 # Transaction distribution
2248system.cpu1.toL2Bus.trans_dist::WriteReq 21647 # Transaction distribution
2249system.cpu1.toL2Bus.trans_dist::WriteResp 21647 # Transaction distribution
2250system.cpu1.toL2Bus.trans_dist::WritebackDirty 4268815 # Transaction distribution
2251system.cpu1.toL2Bus.trans_dist::WritebackClean 11821046 # Transaction distribution
2252system.cpu1.toL2Bus.trans_dist::CleanEvict 2688015 # Transaction distribution
2253system.cpu1.toL2Bus.trans_dist::HardPFReq 913599 # Transaction distribution
2254system.cpu1.toL2Bus.trans_dist::UpgradeReq 423664 # Transaction distribution
2255system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342986 # Transaction distribution
2256system.cpu1.toL2Bus.trans_dist::UpgradeResp 458900 # Transaction distribution
2257system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
2258system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
2259system.cpu1.toL2Bus.trans_dist::ReadExReq 1168045 # Transaction distribution
2260system.cpu1.toL2Bus.trans_dist::ReadExResp 1089891 # Transaction distribution
2261system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9966353 # Transaction distribution
2262system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4640105 # Transaction distribution
2263system.cpu1.toL2Bus.trans_dist::InvalidateReq 517058 # Transaction distribution
2264system.cpu1.toL2Bus.trans_dist::InvalidateResp 511224 # Transaction distribution
2265system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 29897221 # Packet count per connected master and slave (bytes)
2266system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16450144 # Packet count per connected master and slave (bytes)
2267system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405579 # Packet count per connected master and slave (bytes)
2268system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179409 # Packet count per connected master and slave (bytes)
2269system.cpu1.toL2Bus.pkt_count::total 47932353 # Packet count per connected master and slave (bytes)
2270system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1275569664 # Cumulative packet size per connected master and slave (bytes)
2271system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 629289128 # Cumulative packet size per connected master and slave (bytes)
2272system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1559696 # Cumulative packet size per connected master and slave (bytes)
2273system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4501408 # Cumulative packet size per connected master and slave (bytes)
2274system.cpu1.toL2Bus.pkt_size::total 1910919896 # Cumulative packet size per connected master and slave (bytes)
2275system.cpu1.toL2Bus.snoops 6428198 # Total snoops (count)
2276system.cpu1.toL2Bus.snoop_fanout::samples 22587485 # Request fanout histogram
2277system.cpu1.toL2Bus.snoop_fanout::mean 0.100846 # Request fanout histogram
2278system.cpu1.toL2Bus.snoop_fanout::stdev 0.301181 # Request fanout histogram
2279system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2280system.cpu1.toL2Bus.snoop_fanout::0 20310003 89.92% 89.92% # Request fanout histogram
2281system.cpu1.toL2Bus.snoop_fanout::1 2277099 10.08% 100.00% # Request fanout histogram
2282system.cpu1.toL2Bus.snoop_fanout::2 383 0.00% 100.00% # Request fanout histogram
2283system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2284system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2285system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2286system.cpu1.toL2Bus.snoop_fanout::total 22587485 # Request fanout histogram
2287system.cpu1.toL2Bus.reqLayer0.occupancy 30765191484 # Layer occupancy (ticks)
2288system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2289system.cpu1.toL2Bus.snoopLayer0.occupancy 188815582 # Layer occupancy (ticks)
2290system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2291system.cpu1.toL2Bus.respLayer0.occupancy 14953353610 # Layer occupancy (ticks)
2292system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2293system.cpu1.toL2Bus.respLayer1.occupancy 7474900412 # Layer occupancy (ticks)
2294system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2295system.cpu1.toL2Bus.respLayer2.occupancy 210684864 # Layer occupancy (ticks)
2296system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2297system.cpu1.toL2Bus.respLayer3.occupancy 616864733 # Layer occupancy (ticks)
2298system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2299system.iobus.trans_dist::ReadReq 40414 # Transaction distribution
2300system.iobus.trans_dist::ReadResp 40414 # Transaction distribution
2301system.iobus.trans_dist::WriteReq 136987 # Transaction distribution
2302system.iobus.trans_dist::WriteResp 136987 # Transaction distribution
2303system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47846 # Packet count per connected master and slave (bytes)
2304system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2305system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2306system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2307system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2308system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2309system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2310system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2311system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2312system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2313system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2314system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
2315system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2316system.iobus.pkt_count_system.bridge.master::total 122988 # Packet count per connected master and slave (bytes)
2317system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231734 # Packet count per connected master and slave (bytes)
2318system.iobus.pkt_count_system.realview.ide.dma::total 231734 # Packet count per connected master and slave (bytes)
2319system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2320system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2321system.iobus.pkt_count::total 354802 # Packet count per connected master and slave (bytes)
2322system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47866 # Cumulative packet size per connected master and slave (bytes)
2323system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2324system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2325system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2326system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2327system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2328system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2329system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2330system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2331system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2332system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2333system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes)
2334system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2335system.iobus.pkt_size_system.bridge.master::total 156003 # Cumulative packet size per connected master and slave (bytes)
2336system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355288 # Cumulative packet size per connected master and slave (bytes)
2337system.iobus.pkt_size_system.realview.ide.dma::total 7355288 # Cumulative packet size per connected master and slave (bytes)
2338system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2339system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2340system.iobus.pkt_size::total 7513377 # Cumulative packet size per connected master and slave (bytes)
2341system.iobus.reqLayer0.occupancy 47239500 # Layer occupancy (ticks)
2342system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2343system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
2344system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2345system.iobus.reqLayer2.occupancy 315000 # Layer occupancy (ticks)
2346system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2347system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2348system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2349system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks)
2350system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2351system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks)
2352system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2353system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
2354system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2355system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks)
2356system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2357system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks)
2358system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2359system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks)
2360system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2361system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
2362system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2363system.iobus.reqLayer23.occupancy 26112500 # Layer occupancy (ticks)
2364system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2365system.iobus.reqLayer24.occupancy 36405000 # Layer occupancy (ticks)
2366system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2367system.iobus.reqLayer25.occupancy 566670204 # Layer occupancy (ticks)
2368system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2369system.iobus.respLayer0.occupancy 92988000 # Layer occupancy (ticks)
2370system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2371system.iobus.respLayer3.occupancy 148174000 # Layer occupancy (ticks)
2372system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2373system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2374system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2375system.iocache.tags.replacements 115848 # number of replacements
2376system.iocache.tags.tagsinuse 11.264479 # Cycle average of tags in use
2377system.iocache.tags.total_refs 11 # Total number of references to valid blocks.
2378system.iocache.tags.sampled_refs 115864 # Sample count of references to valid blocks.
2379system.iocache.tags.avg_refs 0.000095 # Average number of references to valid blocks.
2380system.iocache.tags.warmup_cycle 9145999585000 # Cycle when the warmup percentage was hit.
2381system.iocache.tags.occ_blocks::realview.ethernet 7.415083 # Average occupied blocks per requestor
2382system.iocache.tags.occ_blocks::realview.ide 3.849396 # Average occupied blocks per requestor
2383system.iocache.tags.occ_percent::realview.ethernet 0.463443 # Average percentage of cache occupancy
2384system.iocache.tags.occ_percent::realview.ide 0.240587 # Average percentage of cache occupancy
2385system.iocache.tags.occ_percent::total 0.704030 # Average percentage of cache occupancy
2386system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2387system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2388system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2389system.iocache.tags.tag_accesses 1043144 # Number of tag accesses
2390system.iocache.tags.data_accesses 1043144 # Number of data accesses
2391system.iocache.WriteLineReq_hits::realview.ide 6 # number of WriteLineReq hits
2392system.iocache.WriteLineReq_hits::total 6 # number of WriteLineReq hits
2393system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2394system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
2395system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
2396system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2397system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2398system.iocache.WriteLineReq_misses::realview.ide 106978 # number of WriteLineReq misses
2399system.iocache.WriteLineReq_misses::total 106978 # number of WriteLineReq misses
2400system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2401system.iocache.demand_misses::realview.ide 8883 # number of demand (read+write) misses
2402system.iocache.demand_misses::total 8923 # number of demand (read+write) misses
2403system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2404system.iocache.overall_misses::realview.ide 8883 # number of overall misses
2405system.iocache.overall_misses::total 8923 # number of overall misses
2406system.iocache.ReadReq_miss_latency::realview.ethernet 5243500 # number of ReadReq miss cycles
2407system.iocache.ReadReq_miss_latency::realview.ide 1665415552 # number of ReadReq miss cycles
2408system.iocache.ReadReq_miss_latency::total 1670659052 # number of ReadReq miss cycles
2409system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2410system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2411system.iocache.WriteLineReq_miss_latency::realview.ide 14002624152 # number of WriteLineReq miss cycles
2412system.iocache.WriteLineReq_miss_latency::total 14002624152 # number of WriteLineReq miss cycles
2413system.iocache.demand_miss_latency::realview.ethernet 5612500 # number of demand (read+write) miss cycles
2414system.iocache.demand_miss_latency::realview.ide 1665415552 # number of demand (read+write) miss cycles
2415system.iocache.demand_miss_latency::total 1671028052 # number of demand (read+write) miss cycles
2416system.iocache.overall_miss_latency::realview.ethernet 5612500 # number of overall miss cycles
2417system.iocache.overall_miss_latency::realview.ide 1665415552 # number of overall miss cycles
2418system.iocache.overall_miss_latency::total 1671028052 # number of overall miss cycles
2419system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2420system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses)
2421system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses)
2422system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2423system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2424system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2425system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2426system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2427system.iocache.demand_accesses::realview.ide 8883 # number of demand (read+write) accesses
2428system.iocache.demand_accesses::total 8923 # number of demand (read+write) accesses
2429system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2430system.iocache.overall_accesses::realview.ide 8883 # number of overall (read+write) accesses
2431system.iocache.overall_accesses::total 8923 # number of overall (read+write) accesses
2432system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2433system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2434system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2435system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2436system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2437system.iocache.WriteLineReq_miss_rate::realview.ide 0.999944 # miss rate for WriteLineReq accesses
2438system.iocache.WriteLineReq_miss_rate::total 0.999944 # miss rate for WriteLineReq accesses
2439system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2440system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2441system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2442system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2443system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2444system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2445system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216 # average ReadReq miss latency
2446system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391 # average ReadReq miss latency
2447system.iocache.ReadReq_avg_miss_latency::total 187293.615695 # average ReadReq miss latency
2448system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2449system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2450system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769 # average WriteLineReq miss latency
2451system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769 # average WriteLineReq miss latency
2452system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
2453system.iocache.demand_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
2454system.iocache.demand_avg_miss_latency::total 187271.999552 # average overall miss latency
2455system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency
2456system.iocache.overall_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency
2457system.iocache.overall_avg_miss_latency::total 187271.999552 # average overall miss latency
2458system.iocache.blocked_cycles::no_mshrs 35141 # number of cycles access was blocked
2459system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2460system.iocache.blocked::no_mshrs 3655 # number of cycles access was blocked
2461system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2462system.iocache.avg_blocked_cycles::no_mshrs 9.614501 # average number of cycles each access was blocked
2463system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2464system.iocache.fast_writes 0 # number of fast writes performed
2465system.iocache.cache_copies 0 # number of cache copies performed
2466system.iocache.writebacks::writebacks 106943 # number of writebacks
2467system.iocache.writebacks::total 106943 # number of writebacks
2468system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2469system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses
2470system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses
2471system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2472system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2473system.iocache.WriteLineReq_mshr_misses::realview.ide 106978 # number of WriteLineReq MSHR misses
2474system.iocache.WriteLineReq_mshr_misses::total 106978 # number of WriteLineReq MSHR misses
2475system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2476system.iocache.demand_mshr_misses::realview.ide 8883 # number of demand (read+write) MSHR misses
2477system.iocache.demand_mshr_misses::total 8923 # number of demand (read+write) MSHR misses
2478system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2479system.iocache.overall_mshr_misses::realview.ide 8883 # number of overall MSHR misses
2480system.iocache.overall_mshr_misses::total 8923 # number of overall MSHR misses
2481system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3393500 # number of ReadReq MSHR miss cycles
2482system.iocache.ReadReq_mshr_miss_latency::realview.ide 1221265552 # number of ReadReq MSHR miss cycles
2483system.iocache.ReadReq_mshr_miss_latency::total 1224659052 # number of ReadReq MSHR miss cycles
2484system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2485system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2486system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8653724152 # number of WriteLineReq MSHR miss cycles
2487system.iocache.WriteLineReq_mshr_miss_latency::total 8653724152 # number of WriteLineReq MSHR miss cycles
2488system.iocache.demand_mshr_miss_latency::realview.ethernet 3612500 # number of demand (read+write) MSHR miss cycles
2489system.iocache.demand_mshr_miss_latency::realview.ide 1221265552 # number of demand (read+write) MSHR miss cycles
2490system.iocache.demand_mshr_miss_latency::total 1224878052 # number of demand (read+write) MSHR miss cycles
2491system.iocache.overall_mshr_miss_latency::realview.ethernet 3612500 # number of overall MSHR miss cycles
2492system.iocache.overall_mshr_miss_latency::realview.ide 1221265552 # number of overall MSHR miss cycles
2493system.iocache.overall_mshr_miss_latency::total 1224878052 # number of overall MSHR miss cycles
2494system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2495system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2496system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2497system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2498system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2499system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999944 # mshr miss rate for WriteLineReq accesses
2500system.iocache.WriteLineReq_mshr_miss_rate::total 0.999944 # mshr miss rate for WriteLineReq accesses
2501system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2502system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2503system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2504system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2505system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2506system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2507system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216 # average ReadReq mshr miss latency
2508system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391 # average ReadReq mshr miss latency
2509system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695 # average ReadReq mshr miss latency
2510system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2511system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2512system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769 # average WriteLineReq mshr miss latency
2513system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769 # average WriteLineReq mshr miss latency
2514system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
2515system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
2516system.iocache.demand_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
2517system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency
2518system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency
2519system.iocache.overall_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency
2520system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2521system.l2c.tags.replacements 1253630 # number of replacements
2522system.l2c.tags.tagsinuse 63075.564404 # Cycle average of tags in use
2523system.l2c.tags.total_refs 6221998 # Total number of references to valid blocks.
2524system.l2c.tags.sampled_refs 1313632 # Sample count of references to valid blocks.
2525system.l2c.tags.avg_refs 4.736485 # Average number of references to valid blocks.
2526system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2527system.l2c.tags.occ_blocks::writebacks 23067.685004 # Average occupied blocks per requestor
2528system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.868876 # Average occupied blocks per requestor
2529system.l2c.tags.occ_blocks::cpu0.itb.walker 206.473413 # Average occupied blocks per requestor
2530system.l2c.tags.occ_blocks::cpu0.inst 5441.439609 # Average occupied blocks per requestor
2531system.l2c.tags.occ_blocks::cpu0.data 6307.681817 # Average occupied blocks per requestor
2532system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8428.958067 # Average occupied blocks per requestor
2533system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.047033 # Average occupied blocks per requestor
2534system.l2c.tags.occ_blocks::cpu1.itb.walker 198.225362 # Average occupied blocks per requestor
2535system.l2c.tags.occ_blocks::cpu1.inst 4720.872050 # Average occupied blocks per requestor
2536system.l2c.tags.occ_blocks::cpu1.data 6856.377655 # Average occupied blocks per requestor
2537system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7560.935517 # Average occupied blocks per requestor
2538system.l2c.tags.occ_percent::writebacks 0.351985 # Average percentage of cache occupancy
2539system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002241 # Average percentage of cache occupancy
2540system.l2c.tags.occ_percent::cpu0.itb.walker 0.003151 # Average percentage of cache occupancy
2541system.l2c.tags.occ_percent::cpu0.inst 0.083030 # Average percentage of cache occupancy
2542system.l2c.tags.occ_percent::cpu0.data 0.096248 # Average percentage of cache occupancy
2543system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.128616 # Average percentage of cache occupancy
2544system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002137 # Average percentage of cache occupancy
2545system.l2c.tags.occ_percent::cpu1.itb.walker 0.003025 # Average percentage of cache occupancy
2546system.l2c.tags.occ_percent::cpu1.inst 0.072035 # Average percentage of cache occupancy
2547system.l2c.tags.occ_percent::cpu1.data 0.104620 # Average percentage of cache occupancy
2548system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.115371 # Average percentage of cache occupancy
2549system.l2c.tags.occ_percent::total 0.962457 # Average percentage of cache occupancy
2550system.l2c.tags.occ_task_id_blocks::1022 9537 # Occupied blocks per task id
2551system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
2552system.l2c.tags.occ_task_id_blocks::1024 50225 # Occupied blocks per task id
2553system.l2c.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id
2554system.l2c.tags.age_task_id_blocks_1022::1 233 # Occupied blocks per task id
2555system.l2c.tags.age_task_id_blocks_1022::2 325 # Occupied blocks per task id
2556system.l2c.tags.age_task_id_blocks_1022::3 1551 # Occupied blocks per task id
2557system.l2c.tags.age_task_id_blocks_1022::4 7383 # Occupied blocks per task id
2558system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
2559system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
2560system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
2561system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
2562system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id
2563system.l2c.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id
2564system.l2c.tags.age_task_id_blocks_1024::3 11674 # Occupied blocks per task id
2565system.l2c.tags.age_task_id_blocks_1024::4 35545 # Occupied blocks per task id
2566system.l2c.tags.occ_task_id_percent::1022 0.145523 # Percentage of cache occupancy per task id
2567system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
2568system.l2c.tags.occ_task_id_percent::1024 0.766373 # Percentage of cache occupancy per task id
2569system.l2c.tags.tag_accesses 75571866 # Number of tag accesses
2570system.l2c.tags.data_accesses 75571866 # Number of data accesses
2571system.l2c.WritebackDirty_hits::writebacks 2585563 # number of WritebackDirty hits
2572system.l2c.WritebackDirty_hits::total 2585563 # number of WritebackDirty hits
2573system.l2c.UpgradeReq_hits::cpu0.data 160084 # number of UpgradeReq hits
2574system.l2c.UpgradeReq_hits::cpu1.data 122219 # number of UpgradeReq hits
2575system.l2c.UpgradeReq_hits::total 282303 # number of UpgradeReq hits
2576system.l2c.SCUpgradeReq_hits::cpu0.data 41093 # number of SCUpgradeReq hits
2577system.l2c.SCUpgradeReq_hits::cpu1.data 37320 # number of SCUpgradeReq hits
2578system.l2c.SCUpgradeReq_hits::total 78413 # number of SCUpgradeReq hits
2579system.l2c.ReadExReq_hits::cpu0.data 164973 # number of ReadExReq hits
2580system.l2c.ReadExReq_hits::cpu1.data 176191 # number of ReadExReq hits
2581system.l2c.ReadExReq_hits::total 341164 # number of ReadExReq hits
2582system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5942 # number of ReadSharedReq hits
2583system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3808 # number of ReadSharedReq hits
2584system.l2c.ReadSharedReq_hits::cpu0.inst 649495 # number of ReadSharedReq hits
2585system.l2c.ReadSharedReq_hits::cpu0.data 595249 # number of ReadSharedReq hits
2586system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 326607 # number of ReadSharedReq hits
2587system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6405 # number of ReadSharedReq hits
2588system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4811 # number of ReadSharedReq hits
2589system.l2c.ReadSharedReq_hits::cpu1.inst 608519 # number of ReadSharedReq hits
2590system.l2c.ReadSharedReq_hits::cpu1.data 523825 # number of ReadSharedReq hits
2591system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 313790 # number of ReadSharedReq hits
2592system.l2c.ReadSharedReq_hits::total 3038451 # number of ReadSharedReq hits
2593system.l2c.demand_hits::cpu0.dtb.walker 5942 # number of demand (read+write) hits
2594system.l2c.demand_hits::cpu0.itb.walker 3808 # number of demand (read+write) hits
2595system.l2c.demand_hits::cpu0.inst 649495 # number of demand (read+write) hits
2596system.l2c.demand_hits::cpu0.data 760222 # number of demand (read+write) hits
2597system.l2c.demand_hits::cpu0.l2cache.prefetcher 326607 # number of demand (read+write) hits
2598system.l2c.demand_hits::cpu1.dtb.walker 6405 # number of demand (read+write) hits
2599system.l2c.demand_hits::cpu1.itb.walker 4811 # number of demand (read+write) hits
2600system.l2c.demand_hits::cpu1.inst 608519 # number of demand (read+write) hits
2601system.l2c.demand_hits::cpu1.data 700016 # number of demand (read+write) hits
2602system.l2c.demand_hits::cpu1.l2cache.prefetcher 313790 # number of demand (read+write) hits
2603system.l2c.demand_hits::total 3379615 # number of demand (read+write) hits
2604system.l2c.overall_hits::cpu0.dtb.walker 5942 # number of overall hits
2605system.l2c.overall_hits::cpu0.itb.walker 3808 # number of overall hits
2606system.l2c.overall_hits::cpu0.inst 649495 # number of overall hits
2607system.l2c.overall_hits::cpu0.data 760222 # number of overall hits
2608system.l2c.overall_hits::cpu0.l2cache.prefetcher 326607 # number of overall hits
2609system.l2c.overall_hits::cpu1.dtb.walker 6405 # number of overall hits
2610system.l2c.overall_hits::cpu1.itb.walker 4811 # number of overall hits
2611system.l2c.overall_hits::cpu1.inst 608519 # number of overall hits
2612system.l2c.overall_hits::cpu1.data 700016 # number of overall hits
2613system.l2c.overall_hits::cpu1.l2cache.prefetcher 313790 # number of overall hits
2614system.l2c.overall_hits::total 3379615 # number of overall hits
2615system.l2c.UpgradeReq_misses::cpu0.data 64947 # number of UpgradeReq misses
2616system.l2c.UpgradeReq_misses::cpu1.data 58762 # number of UpgradeReq misses
2617system.l2c.UpgradeReq_misses::total 123709 # number of UpgradeReq misses
2618system.l2c.SCUpgradeReq_misses::cpu0.data 12100 # number of SCUpgradeReq misses
2619system.l2c.SCUpgradeReq_misses::cpu1.data 11098 # number of SCUpgradeReq misses
2620system.l2c.SCUpgradeReq_misses::total 23198 # number of SCUpgradeReq misses
2621system.l2c.ReadExReq_misses::cpu0.data 478835 # number of ReadExReq misses
2622system.l2c.ReadExReq_misses::cpu1.data 137880 # number of ReadExReq misses
2623system.l2c.ReadExReq_misses::total 616715 # number of ReadExReq misses
2624system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1338 # number of ReadSharedReq misses
2625system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1182 # number of ReadSharedReq misses
2626system.l2c.ReadSharedReq_misses::cpu0.inst 61507 # number of ReadSharedReq misses
2627system.l2c.ReadSharedReq_misses::cpu0.data 116953 # number of ReadSharedReq misses
2628system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 182171 # number of ReadSharedReq misses
2629system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1669 # number of ReadSharedReq misses
2630system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1507 # number of ReadSharedReq misses
2631system.l2c.ReadSharedReq_misses::cpu1.inst 57727 # number of ReadSharedReq misses
2632system.l2c.ReadSharedReq_misses::cpu1.data 105504 # number of ReadSharedReq misses
2633system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 168487 # number of ReadSharedReq misses
2634system.l2c.ReadSharedReq_misses::total 698045 # number of ReadSharedReq misses
2635system.l2c.demand_misses::cpu0.dtb.walker 1338 # number of demand (read+write) misses
2636system.l2c.demand_misses::cpu0.itb.walker 1182 # number of demand (read+write) misses
2637system.l2c.demand_misses::cpu0.inst 61507 # number of demand (read+write) misses
2638system.l2c.demand_misses::cpu0.data 595788 # number of demand (read+write) misses
2639system.l2c.demand_misses::cpu0.l2cache.prefetcher 182171 # number of demand (read+write) misses
2640system.l2c.demand_misses::cpu1.dtb.walker 1669 # number of demand (read+write) misses
2641system.l2c.demand_misses::cpu1.itb.walker 1507 # number of demand (read+write) misses
2642system.l2c.demand_misses::cpu1.inst 57727 # number of demand (read+write) misses
2643system.l2c.demand_misses::cpu1.data 243384 # number of demand (read+write) misses
2644system.l2c.demand_misses::cpu1.l2cache.prefetcher 168487 # number of demand (read+write) misses
2645system.l2c.demand_misses::total 1314760 # number of demand (read+write) misses
2646system.l2c.overall_misses::cpu0.dtb.walker 1338 # number of overall misses
2647system.l2c.overall_misses::cpu0.itb.walker 1182 # number of overall misses
2648system.l2c.overall_misses::cpu0.inst 61507 # number of overall misses
2649system.l2c.overall_misses::cpu0.data 595788 # number of overall misses
2650system.l2c.overall_misses::cpu0.l2cache.prefetcher 182171 # number of overall misses
2651system.l2c.overall_misses::cpu1.dtb.walker 1669 # number of overall misses
2652system.l2c.overall_misses::cpu1.itb.walker 1507 # number of overall misses
2653system.l2c.overall_misses::cpu1.inst 57727 # number of overall misses
2654system.l2c.overall_misses::cpu1.data 243384 # number of overall misses
2655system.l2c.overall_misses::cpu1.l2cache.prefetcher 168487 # number of overall misses
2656system.l2c.overall_misses::total 1314760 # number of overall misses
2657system.l2c.UpgradeReq_miss_latency::cpu0.data 1164704000 # number of UpgradeReq miss cycles
2658system.l2c.UpgradeReq_miss_latency::cpu1.data 1071145000 # number of UpgradeReq miss cycles
2659system.l2c.UpgradeReq_miss_latency::total 2235849000 # number of UpgradeReq miss cycles
2660system.l2c.SCUpgradeReq_miss_latency::cpu0.data 211169000 # number of SCUpgradeReq miss cycles
2661system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187264500 # number of SCUpgradeReq miss cycles
2662system.l2c.SCUpgradeReq_miss_latency::total 398433500 # number of SCUpgradeReq miss cycles
2663system.l2c.ReadExReq_miss_latency::cpu0.data 66775651499 # number of ReadExReq miss cycles
2664system.l2c.ReadExReq_miss_latency::cpu1.data 18645271000 # number of ReadExReq miss cycles
2665system.l2c.ReadExReq_miss_latency::total 85420922499 # number of ReadExReq miss cycles
2666system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 186837000 # number of ReadSharedReq miss cycles
2667system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 167036500 # number of ReadSharedReq miss cycles
2668system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8232186000 # number of ReadSharedReq miss cycles
2669system.l2c.ReadSharedReq_miss_latency::cpu0.data 16101034000 # number of ReadSharedReq miss cycles
2670system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of ReadSharedReq miss cycles
2671system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 234710500 # number of ReadSharedReq miss cycles
2672system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 209918500 # number of ReadSharedReq miss cycles
2673system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7713073500 # number of ReadSharedReq miss cycles
2674system.l2c.ReadSharedReq_miss_latency::cpu1.data 14641394000 # number of ReadSharedReq miss cycles
2675system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of ReadSharedReq miss cycles
2676system.l2c.ReadSharedReq_miss_latency::total 104705937820 # number of ReadSharedReq miss cycles
2677system.l2c.demand_miss_latency::cpu0.dtb.walker 186837000 # number of demand (read+write) miss cycles
2678system.l2c.demand_miss_latency::cpu0.itb.walker 167036500 # number of demand (read+write) miss cycles
2679system.l2c.demand_miss_latency::cpu0.inst 8232186000 # number of demand (read+write) miss cycles
2680system.l2c.demand_miss_latency::cpu0.data 82876685499 # number of demand (read+write) miss cycles
2681system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of demand (read+write) miss cycles
2682system.l2c.demand_miss_latency::cpu1.dtb.walker 234710500 # number of demand (read+write) miss cycles
2683system.l2c.demand_miss_latency::cpu1.itb.walker 209918500 # number of demand (read+write) miss cycles
2684system.l2c.demand_miss_latency::cpu1.inst 7713073500 # number of demand (read+write) miss cycles
2685system.l2c.demand_miss_latency::cpu1.data 33286665000 # number of demand (read+write) miss cycles
2686system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of demand (read+write) miss cycles
2687system.l2c.demand_miss_latency::total 190126860319 # number of demand (read+write) miss cycles
2688system.l2c.overall_miss_latency::cpu0.dtb.walker 186837000 # number of overall miss cycles
2689system.l2c.overall_miss_latency::cpu0.itb.walker 167036500 # number of overall miss cycles
2690system.l2c.overall_miss_latency::cpu0.inst 8232186000 # number of overall miss cycles
2691system.l2c.overall_miss_latency::cpu0.data 82876685499 # number of overall miss cycles
2692system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29946000398 # number of overall miss cycles
2693system.l2c.overall_miss_latency::cpu1.dtb.walker 234710500 # number of overall miss cycles
2694system.l2c.overall_miss_latency::cpu1.itb.walker 209918500 # number of overall miss cycles
2695system.l2c.overall_miss_latency::cpu1.inst 7713073500 # number of overall miss cycles
2696system.l2c.overall_miss_latency::cpu1.data 33286665000 # number of overall miss cycles
2697system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27273747422 # number of overall miss cycles
2698system.l2c.overall_miss_latency::total 190126860319 # number of overall miss cycles
2699system.l2c.WritebackDirty_accesses::writebacks 2585563 # number of WritebackDirty accesses(hits+misses)
2700system.l2c.WritebackDirty_accesses::total 2585563 # number of WritebackDirty accesses(hits+misses)
2701system.l2c.UpgradeReq_accesses::cpu0.data 225031 # number of UpgradeReq accesses(hits+misses)
2702system.l2c.UpgradeReq_accesses::cpu1.data 180981 # number of UpgradeReq accesses(hits+misses)
2703system.l2c.UpgradeReq_accesses::total 406012 # number of UpgradeReq accesses(hits+misses)
2704system.l2c.SCUpgradeReq_accesses::cpu0.data 53193 # number of SCUpgradeReq accesses(hits+misses)
2705system.l2c.SCUpgradeReq_accesses::cpu1.data 48418 # number of SCUpgradeReq accesses(hits+misses)
2706system.l2c.SCUpgradeReq_accesses::total 101611 # number of SCUpgradeReq accesses(hits+misses)
2707system.l2c.ReadExReq_accesses::cpu0.data 643808 # number of ReadExReq accesses(hits+misses)
2708system.l2c.ReadExReq_accesses::cpu1.data 314071 # number of ReadExReq accesses(hits+misses)
2709system.l2c.ReadExReq_accesses::total 957879 # number of ReadExReq accesses(hits+misses)
2710system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7280 # number of ReadSharedReq accesses(hits+misses)
2711system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4990 # number of ReadSharedReq accesses(hits+misses)
2712system.l2c.ReadSharedReq_accesses::cpu0.inst 711002 # number of ReadSharedReq accesses(hits+misses)
2713system.l2c.ReadSharedReq_accesses::cpu0.data 712202 # number of ReadSharedReq accesses(hits+misses)
2714system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 508778 # number of ReadSharedReq accesses(hits+misses)
2715system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8074 # number of ReadSharedReq accesses(hits+misses)
2716system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6318 # number of ReadSharedReq accesses(hits+misses)
2717system.l2c.ReadSharedReq_accesses::cpu1.inst 666246 # number of ReadSharedReq accesses(hits+misses)
2718system.l2c.ReadSharedReq_accesses::cpu1.data 629329 # number of ReadSharedReq accesses(hits+misses)
2719system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 482277 # number of ReadSharedReq accesses(hits+misses)
2720system.l2c.ReadSharedReq_accesses::total 3736496 # number of ReadSharedReq accesses(hits+misses)
2721system.l2c.demand_accesses::cpu0.dtb.walker 7280 # number of demand (read+write) accesses
2722system.l2c.demand_accesses::cpu0.itb.walker 4990 # number of demand (read+write) accesses
2723system.l2c.demand_accesses::cpu0.inst 711002 # number of demand (read+write) accesses
2724system.l2c.demand_accesses::cpu0.data 1356010 # number of demand (read+write) accesses
2725system.l2c.demand_accesses::cpu0.l2cache.prefetcher 508778 # number of demand (read+write) accesses
2726system.l2c.demand_accesses::cpu1.dtb.walker 8074 # number of demand (read+write) accesses
2727system.l2c.demand_accesses::cpu1.itb.walker 6318 # number of demand (read+write) accesses
2728system.l2c.demand_accesses::cpu1.inst 666246 # number of demand (read+write) accesses
2729system.l2c.demand_accesses::cpu1.data 943400 # number of demand (read+write) accesses
2730system.l2c.demand_accesses::cpu1.l2cache.prefetcher 482277 # number of demand (read+write) accesses
2731system.l2c.demand_accesses::total 4694375 # number of demand (read+write) accesses
2732system.l2c.overall_accesses::cpu0.dtb.walker 7280 # number of overall (read+write) accesses
2733system.l2c.overall_accesses::cpu0.itb.walker 4990 # number of overall (read+write) accesses
2734system.l2c.overall_accesses::cpu0.inst 711002 # number of overall (read+write) accesses
2735system.l2c.overall_accesses::cpu0.data 1356010 # number of overall (read+write) accesses
2736system.l2c.overall_accesses::cpu0.l2cache.prefetcher 508778 # number of overall (read+write) accesses
2737system.l2c.overall_accesses::cpu1.dtb.walker 8074 # number of overall (read+write) accesses
2738system.l2c.overall_accesses::cpu1.itb.walker 6318 # number of overall (read+write) accesses
2739system.l2c.overall_accesses::cpu1.inst 666246 # number of overall (read+write) accesses
2740system.l2c.overall_accesses::cpu1.data 943400 # number of overall (read+write) accesses
2741system.l2c.overall_accesses::cpu1.l2cache.prefetcher 482277 # number of overall (read+write) accesses
2742system.l2c.overall_accesses::total 4694375 # number of overall (read+write) accesses
2743system.l2c.UpgradeReq_miss_rate::cpu0.data 0.288614 # miss rate for UpgradeReq accesses
2744system.l2c.UpgradeReq_miss_rate::cpu1.data 0.324686 # miss rate for UpgradeReq accesses
2745system.l2c.UpgradeReq_miss_rate::total 0.304693 # miss rate for UpgradeReq accesses
2746system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.227474 # miss rate for SCUpgradeReq accesses
2747system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.229212 # miss rate for SCUpgradeReq accesses
2748system.l2c.SCUpgradeReq_miss_rate::total 0.228302 # miss rate for SCUpgradeReq accesses
2749system.l2c.ReadExReq_miss_rate::cpu0.data 0.743754 # miss rate for ReadExReq accesses
2750system.l2c.ReadExReq_miss_rate::cpu1.data 0.439009 # miss rate for ReadExReq accesses
2751system.l2c.ReadExReq_miss_rate::total 0.643834 # miss rate for ReadExReq accesses
2752system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for ReadSharedReq accesses
2753system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.236874 # miss rate for ReadSharedReq accesses
2754system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.086507 # miss rate for ReadSharedReq accesses
2755system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.164213 # miss rate for ReadSharedReq accesses
2756system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for ReadSharedReq accesses
2757system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for ReadSharedReq accesses
2758system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.238525 # miss rate for ReadSharedReq accesses
2759system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.086645 # miss rate for ReadSharedReq accesses
2760system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167645 # miss rate for ReadSharedReq accesses
2761system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for ReadSharedReq accesses
2762system.l2c.ReadSharedReq_miss_rate::total 0.186818 # miss rate for ReadSharedReq accesses
2763system.l2c.demand_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for demand accesses
2764system.l2c.demand_miss_rate::cpu0.itb.walker 0.236874 # miss rate for demand accesses
2765system.l2c.demand_miss_rate::cpu0.inst 0.086507 # miss rate for demand accesses
2766system.l2c.demand_miss_rate::cpu0.data 0.439368 # miss rate for demand accesses
2767system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for demand accesses
2768system.l2c.demand_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for demand accesses
2769system.l2c.demand_miss_rate::cpu1.itb.walker 0.238525 # miss rate for demand accesses
2770system.l2c.demand_miss_rate::cpu1.inst 0.086645 # miss rate for demand accesses
2771system.l2c.demand_miss_rate::cpu1.data 0.257986 # miss rate for demand accesses
2772system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for demand accesses
2773system.l2c.demand_miss_rate::total 0.280071 # miss rate for demand accesses
2774system.l2c.overall_miss_rate::cpu0.dtb.walker 0.183791 # miss rate for overall accesses
2775system.l2c.overall_miss_rate::cpu0.itb.walker 0.236874 # miss rate for overall accesses
2776system.l2c.overall_miss_rate::cpu0.inst 0.086507 # miss rate for overall accesses
2777system.l2c.overall_miss_rate::cpu0.data 0.439368 # miss rate for overall accesses
2778system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.358056 # miss rate for overall accesses
2779system.l2c.overall_miss_rate::cpu1.dtb.walker 0.206713 # miss rate for overall accesses
2780system.l2c.overall_miss_rate::cpu1.itb.walker 0.238525 # miss rate for overall accesses
2781system.l2c.overall_miss_rate::cpu1.inst 0.086645 # miss rate for overall accesses
2782system.l2c.overall_miss_rate::cpu1.data 0.257986 # miss rate for overall accesses
2783system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.349357 # miss rate for overall accesses
2784system.l2c.overall_miss_rate::total 0.280071 # miss rate for overall accesses
2785system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17933.145488 # average UpgradeReq miss latency
2786system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18228.532045 # average UpgradeReq miss latency
2787system.l2c.UpgradeReq_avg_miss_latency::total 18073.454640 # average UpgradeReq miss latency
2788system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17451.983471 # average SCUpgradeReq miss latency
2789system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16873.715985 # average SCUpgradeReq miss latency
2790system.l2c.SCUpgradeReq_avg_miss_latency::total 17175.338391 # average SCUpgradeReq miss latency
2791system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139454.408093 # average ReadExReq miss latency
2792system.l2c.ReadExReq_avg_miss_latency::cpu1.data 135228.249202 # average ReadExReq miss latency
2793system.l2c.ReadExReq_avg_miss_latency::total 138509.558709 # average ReadExReq miss latency
2794system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average ReadSharedReq miss latency
2795system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141316.835871 # average ReadSharedReq miss latency
2796system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 133841.448941 # average ReadSharedReq miss latency
2797system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137670.978940 # average ReadSharedReq miss latency
2798system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average ReadSharedReq miss latency
2799system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average ReadSharedReq miss latency
2800system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 139295.620438 # average ReadSharedReq miss latency
2801system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 133612.928093 # average ReadSharedReq miss latency
2802system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138775.724143 # average ReadSharedReq miss latency
2803system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average ReadSharedReq miss latency
2804system.l2c.ReadSharedReq_avg_miss_latency::total 149998.836493 # average ReadSharedReq miss latency
2805system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average overall miss latency
2806system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141316.835871 # average overall miss latency
2807system.l2c.demand_avg_miss_latency::cpu0.inst 133841.448941 # average overall miss latency
2808system.l2c.demand_avg_miss_latency::cpu0.data 139104.321502 # average overall miss latency
2809system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average overall miss latency
2810system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average overall miss latency
2811system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139295.620438 # average overall miss latency
2812system.l2c.demand_avg_miss_latency::cpu1.inst 133612.928093 # average overall miss latency
2813system.l2c.demand_avg_miss_latency::cpu1.data 136766.036387 # average overall miss latency
2814system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average overall miss latency
2815system.l2c.demand_avg_miss_latency::total 144609.556359 # average overall miss latency
2816system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 139639.013453 # average overall miss latency
2817system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141316.835871 # average overall miss latency
2818system.l2c.overall_avg_miss_latency::cpu0.inst 133841.448941 # average overall miss latency
2819system.l2c.overall_avg_miss_latency::cpu0.data 139104.321502 # average overall miss latency
2820system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 164384.015008 # average overall miss latency
2821system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 140629.418814 # average overall miss latency
2822system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139295.620438 # average overall miss latency
2823system.l2c.overall_avg_miss_latency::cpu1.inst 133612.928093 # average overall miss latency
2824system.l2c.overall_avg_miss_latency::cpu1.data 136766.036387 # average overall miss latency
2825system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161874.491338 # average overall miss latency
2826system.l2c.overall_avg_miss_latency::total 144609.556359 # average overall miss latency
2827system.l2c.blocked_cycles::no_mshrs 2084 # number of cycles access was blocked
2828system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2829system.l2c.blocked::no_mshrs 32 # number of cycles access was blocked
2830system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2831system.l2c.avg_blocked_cycles::no_mshrs 65.125000 # average number of cycles each access was blocked
2832system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2833system.l2c.fast_writes 0 # number of fast writes performed
2834system.l2c.cache_copies 0 # number of cache copies performed
2835system.l2c.writebacks::writebacks 965818 # number of writebacks
2836system.l2c.writebacks::total 965818 # number of writebacks
2837system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadSharedReq MSHR hits
2838system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 143 # number of ReadSharedReq MSHR hits
2839system.l2c.ReadSharedReq_mshr_hits::cpu0.data 157 # number of ReadSharedReq MSHR hits
2840system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 129 # number of ReadSharedReq MSHR hits
2841system.l2c.ReadSharedReq_mshr_hits::cpu1.data 82 # number of ReadSharedReq MSHR hits
2842system.l2c.ReadSharedReq_mshr_hits::total 512 # number of ReadSharedReq MSHR hits
2843system.l2c.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
2844system.l2c.demand_mshr_hits::cpu0.inst 143 # number of demand (read+write) MSHR hits
2845system.l2c.demand_mshr_hits::cpu0.data 157 # number of demand (read+write) MSHR hits
2846system.l2c.demand_mshr_hits::cpu1.inst 129 # number of demand (read+write) MSHR hits
2847system.l2c.demand_mshr_hits::cpu1.data 82 # number of demand (read+write) MSHR hits
2848system.l2c.demand_mshr_hits::total 512 # number of demand (read+write) MSHR hits
2849system.l2c.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
2850system.l2c.overall_mshr_hits::cpu0.inst 143 # number of overall MSHR hits
2851system.l2c.overall_mshr_hits::cpu0.data 157 # number of overall MSHR hits
2852system.l2c.overall_mshr_hits::cpu1.inst 129 # number of overall MSHR hits
2853system.l2c.overall_mshr_hits::cpu1.data 82 # number of overall MSHR hits
2854system.l2c.overall_mshr_hits::total 512 # number of overall MSHR hits
2855system.l2c.CleanEvict_mshr_misses::writebacks 48026 # number of CleanEvict MSHR misses
2856system.l2c.CleanEvict_mshr_misses::total 48026 # number of CleanEvict MSHR misses
2857system.l2c.UpgradeReq_mshr_misses::cpu0.data 64947 # number of UpgradeReq MSHR misses
2858system.l2c.UpgradeReq_mshr_misses::cpu1.data 58762 # number of UpgradeReq MSHR misses
2859system.l2c.UpgradeReq_mshr_misses::total 123709 # number of UpgradeReq MSHR misses
2860system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12100 # number of SCUpgradeReq MSHR misses
2861system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11098 # number of SCUpgradeReq MSHR misses
2862system.l2c.SCUpgradeReq_mshr_misses::total 23198 # number of SCUpgradeReq MSHR misses
2863system.l2c.ReadExReq_mshr_misses::cpu0.data 478835 # number of ReadExReq MSHR misses
2864system.l2c.ReadExReq_mshr_misses::cpu1.data 137880 # number of ReadExReq MSHR misses
2865system.l2c.ReadExReq_mshr_misses::total 616715 # number of ReadExReq MSHR misses
2866system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1337 # number of ReadSharedReq MSHR misses
2867system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1182 # number of ReadSharedReq MSHR misses
2868system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 61364 # number of ReadSharedReq MSHR misses
2869system.l2c.ReadSharedReq_mshr_misses::cpu0.data 116796 # number of ReadSharedReq MSHR misses
2870system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of ReadSharedReq MSHR misses
2871system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1669 # number of ReadSharedReq MSHR misses
2872system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1507 # number of ReadSharedReq MSHR misses
2873system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57598 # number of ReadSharedReq MSHR misses
2874system.l2c.ReadSharedReq_mshr_misses::cpu1.data 105422 # number of ReadSharedReq MSHR misses
2875system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of ReadSharedReq MSHR misses
2876system.l2c.ReadSharedReq_mshr_misses::total 697533 # number of ReadSharedReq MSHR misses
2877system.l2c.demand_mshr_misses::cpu0.dtb.walker 1337 # number of demand (read+write) MSHR misses
2878system.l2c.demand_mshr_misses::cpu0.itb.walker 1182 # number of demand (read+write) MSHR misses
2879system.l2c.demand_mshr_misses::cpu0.inst 61364 # number of demand (read+write) MSHR misses
2880system.l2c.demand_mshr_misses::cpu0.data 595631 # number of demand (read+write) MSHR misses
2881system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of demand (read+write) MSHR misses
2882system.l2c.demand_mshr_misses::cpu1.dtb.walker 1669 # number of demand (read+write) MSHR misses
2883system.l2c.demand_mshr_misses::cpu1.itb.walker 1507 # number of demand (read+write) MSHR misses
2884system.l2c.demand_mshr_misses::cpu1.inst 57598 # number of demand (read+write) MSHR misses
2885system.l2c.demand_mshr_misses::cpu1.data 243302 # number of demand (read+write) MSHR misses
2886system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of demand (read+write) MSHR misses
2887system.l2c.demand_mshr_misses::total 1314248 # number of demand (read+write) MSHR misses
2888system.l2c.overall_mshr_misses::cpu0.dtb.walker 1337 # number of overall MSHR misses
2889system.l2c.overall_mshr_misses::cpu0.itb.walker 1182 # number of overall MSHR misses
2890system.l2c.overall_mshr_misses::cpu0.inst 61364 # number of overall MSHR misses
2891system.l2c.overall_mshr_misses::cpu0.data 595631 # number of overall MSHR misses
2892system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 182171 # number of overall MSHR misses
2893system.l2c.overall_mshr_misses::cpu1.dtb.walker 1669 # number of overall MSHR misses
2894system.l2c.overall_mshr_misses::cpu1.itb.walker 1507 # number of overall MSHR misses
2895system.l2c.overall_mshr_misses::cpu1.inst 57598 # number of overall MSHR misses
2896system.l2c.overall_mshr_misses::cpu1.data 243302 # number of overall MSHR misses
2897system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 168487 # number of overall MSHR misses
2898system.l2c.overall_mshr_misses::total 1314248 # number of overall MSHR misses
2899system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
2900system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15485 # number of ReadReq MSHR uncacheable
2901system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 92 # number of ReadReq MSHR uncacheable
2902system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22693 # number of ReadReq MSHR uncacheable
2903system.l2c.ReadReq_mshr_uncacheable::total 90579 # number of ReadReq MSHR uncacheable
2904system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable
2905system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21647 # number of WriteReq MSHR uncacheable
2906system.l2c.WriteReq_mshr_uncacheable::total 38077 # number of WriteReq MSHR uncacheable
2907system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
2908system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses
2909system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 92 # number of overall MSHR uncacheable misses
2910system.l2c.overall_mshr_uncacheable_misses::cpu1.data 44340 # number of overall MSHR uncacheable misses
2911system.l2c.overall_mshr_uncacheable_misses::total 128656 # number of overall MSHR uncacheable misses
2912system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4765672001 # number of UpgradeReq MSHR miss cycles
2913system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4320405502 # number of UpgradeReq MSHR miss cycles
2914system.l2c.UpgradeReq_mshr_miss_latency::total 9086077503 # number of UpgradeReq MSHR miss cycles
2915system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 924485500 # number of SCUpgradeReq MSHR miss cycles
2916system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 848848000 # number of SCUpgradeReq MSHR miss cycles
2917system.l2c.SCUpgradeReq_mshr_miss_latency::total 1773333500 # number of SCUpgradeReq MSHR miss cycles
2918system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 61987301499 # number of ReadExReq MSHR miss cycles
2919system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17266471000 # number of ReadExReq MSHR miss cycles
2920system.l2c.ReadExReq_mshr_miss_latency::total 79253772499 # number of ReadExReq MSHR miss cycles
2921system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of ReadSharedReq MSHR miss cycles
2922system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 155216500 # number of ReadSharedReq MSHR miss cycles
2923system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7602474500 # number of ReadSharedReq MSHR miss cycles
2924system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14909949000 # number of ReadSharedReq MSHR miss cycles
2925system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of ReadSharedReq MSHR miss cycles
2926system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of ReadSharedReq MSHR miss cycles
2927system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 194848500 # number of ReadSharedReq MSHR miss cycles
2928system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7122979500 # number of ReadSharedReq MSHR miss cycles
2929system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13576100500 # number of ReadSharedReq MSHR miss cycles
2930system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of ReadSharedReq MSHR miss cycles
2931system.l2c.ReadSharedReq_mshr_miss_latency::total 97666151820 # number of ReadSharedReq MSHR miss cycles
2932system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of demand (read+write) MSHR miss cycles
2933system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 155216500 # number of demand (read+write) MSHR miss cycles
2934system.l2c.demand_mshr_miss_latency::cpu0.inst 7602474500 # number of demand (read+write) MSHR miss cycles
2935system.l2c.demand_mshr_miss_latency::cpu0.data 76897250499 # number of demand (read+write) MSHR miss cycles
2936system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of demand (read+write) MSHR miss cycles
2937system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of demand (read+write) MSHR miss cycles
2938system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 194848500 # number of demand (read+write) MSHR miss cycles
2939system.l2c.demand_mshr_miss_latency::cpu1.inst 7122979500 # number of demand (read+write) MSHR miss cycles
2940system.l2c.demand_mshr_miss_latency::cpu1.data 30842571500 # number of demand (read+write) MSHR miss cycles
2941system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of demand (read+write) MSHR miss cycles
2942system.l2c.demand_mshr_miss_latency::total 176919924319 # number of demand (read+write) MSHR miss cycles
2943system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 173355000 # number of overall MSHR miss cycles
2944system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 155216500 # number of overall MSHR miss cycles
2945system.l2c.overall_mshr_miss_latency::cpu0.inst 7602474500 # number of overall MSHR miss cycles
2946system.l2c.overall_mshr_miss_latency::cpu0.data 76897250499 # number of overall MSHR miss cycles
2947system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28124290398 # number of overall MSHR miss cycles
2948system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 218020500 # number of overall MSHR miss cycles
2949system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 194848500 # number of overall MSHR miss cycles
2950system.l2c.overall_mshr_miss_latency::cpu1.inst 7122979500 # number of overall MSHR miss cycles
2951system.l2c.overall_mshr_miss_latency::cpu1.data 30842571500 # number of overall MSHR miss cycles
2952system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25588917422 # number of overall MSHR miss cycles
2953system.l2c.overall_mshr_miss_latency::total 176919924319 # number of overall MSHR miss cycles
2954system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles
2955system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2374540500 # number of ReadReq MSHR uncacheable cycles
2956system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10279000 # number of ReadReq MSHR uncacheable cycles
2957system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3555600500 # number of ReadReq MSHR uncacheable cycles
2958system.l2c.ReadReq_mshr_uncacheable_latency::total 11838086000 # number of ReadReq MSHR uncacheable cycles
2959system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2488343500 # number of WriteReq MSHR uncacheable cycles
2960system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3486351500 # number of WriteReq MSHR uncacheable cycles
2961system.l2c.WriteReq_mshr_uncacheable_latency::total 5974695000 # number of WriteReq MSHR uncacheable cycles
2962system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles
2963system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4862884000 # number of overall MSHR uncacheable cycles
2964system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10279000 # number of overall MSHR uncacheable cycles
2965system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7041952000 # number of overall MSHR uncacheable cycles
2966system.l2c.overall_mshr_uncacheable_latency::total 17812781000 # number of overall MSHR uncacheable cycles
2967system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2968system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2969system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.288614 # mshr miss rate for UpgradeReq accesses
2970system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324686 # mshr miss rate for UpgradeReq accesses
2971system.l2c.UpgradeReq_mshr_miss_rate::total 0.304693 # mshr miss rate for UpgradeReq accesses
2972system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.227474 # mshr miss rate for SCUpgradeReq accesses
2973system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.229212 # mshr miss rate for SCUpgradeReq accesses
2974system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228302 # mshr miss rate for SCUpgradeReq accesses
2975system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743754 # mshr miss rate for ReadExReq accesses
2976system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.439009 # mshr miss rate for ReadExReq accesses
2977system.l2c.ReadExReq_mshr_miss_rate::total 0.643834 # mshr miss rate for ReadExReq accesses
2978system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for ReadSharedReq accesses
2979system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for ReadSharedReq accesses
2980system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for ReadSharedReq accesses
2981system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.163993 # mshr miss rate for ReadSharedReq accesses
2982system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for ReadSharedReq accesses
2983system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for ReadSharedReq accesses
2984system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for ReadSharedReq accesses
2985system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for ReadSharedReq accesses
2986system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167515 # mshr miss rate for ReadSharedReq accesses
2987system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for ReadSharedReq accesses
2988system.l2c.ReadSharedReq_mshr_miss_rate::total 0.186681 # mshr miss rate for ReadSharedReq accesses
2989system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for demand accesses
2990system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for demand accesses
2991system.l2c.demand_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for demand accesses
2992system.l2c.demand_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for demand accesses
2993system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for demand accesses
2994system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for demand accesses
2995system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for demand accesses
2996system.l2c.demand_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for demand accesses
2997system.l2c.demand_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for demand accesses
2998system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for demand accesses
2999system.l2c.demand_mshr_miss_rate::total 0.279962 # mshr miss rate for demand accesses
3000system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.183654 # mshr miss rate for overall accesses
3001system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.236874 # mshr miss rate for overall accesses
3002system.l2c.overall_mshr_miss_rate::cpu0.inst 0.086306 # mshr miss rate for overall accesses
3003system.l2c.overall_mshr_miss_rate::cpu0.data 0.439253 # mshr miss rate for overall accesses
3004system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.358056 # mshr miss rate for overall accesses
3005system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.206713 # mshr miss rate for overall accesses
3006system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.238525 # mshr miss rate for overall accesses
3007system.l2c.overall_mshr_miss_rate::cpu1.inst 0.086452 # mshr miss rate for overall accesses
3008system.l2c.overall_mshr_miss_rate::cpu1.data 0.257899 # mshr miss rate for overall accesses
3009system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.349357 # mshr miss rate for overall accesses
3010system.l2c.overall_mshr_miss_rate::total 0.279962 # mshr miss rate for overall accesses
3011system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73377.861964 # average UpgradeReq mshr miss latency
3012system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73523.799428 # average UpgradeReq mshr miss latency
3013system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73447.182525 # average UpgradeReq mshr miss latency
3014system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76403.760331 # average SCUpgradeReq mshr miss latency
3015system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76486.574158 # average SCUpgradeReq mshr miss latency
3016system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76443.378740 # average SCUpgradeReq mshr miss latency
3017system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129454.408093 # average ReadExReq mshr miss latency
3018system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 125228.249202 # average ReadExReq mshr miss latency
3019system.l2c.ReadExReq_avg_mshr_miss_latency::total 128509.558709 # average ReadExReq mshr miss latency
3020system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average ReadSharedReq mshr miss latency
3021system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average ReadSharedReq mshr miss latency
3022system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average ReadSharedReq mshr miss latency
3023system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127658.044796 # average ReadSharedReq mshr miss latency
3024system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average ReadSharedReq mshr miss latency
3025system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average ReadSharedReq mshr miss latency
3026system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average ReadSharedReq mshr miss latency
3027system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average ReadSharedReq mshr miss latency
3028system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128778.627801 # average ReadSharedReq mshr miss latency
3029system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average ReadSharedReq mshr miss latency
3030system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140016.532293 # average ReadSharedReq mshr miss latency
3031system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
3032system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
3033system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
3034system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
3035system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
3036system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
3037system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
3038system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
3039system.l2c.demand_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
3040system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
3041system.l2c.demand_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
3042system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 129659.685864 # average overall mshr miss latency
3043system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131316.835871 # average overall mshr miss latency
3044system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123891.442866 # average overall mshr miss latency
3045system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129102.163083 # average overall mshr miss latency
3046system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 154384.015008 # average overall mshr miss latency
3047system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130629.418814 # average overall mshr miss latency
3048system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129295.620438 # average overall mshr miss latency
3049system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123667.132539 # average overall mshr miss latency
3050system.l2c.overall_avg_mshr_miss_latency::cpu1.data 126766.617208 # average overall mshr miss latency
3051system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151874.728745 # average overall mshr miss latency
3052system.l2c.overall_avg_mshr_miss_latency::total 134616.848813 # average overall mshr miss latency
3053system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
3054system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251 # average ReadReq mshr uncacheable latency
3055system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency
3056system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511 # average ReadReq mshr uncacheable latency
3057system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077 # average ReadReq mshr uncacheable latency
3058system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285 # average WriteReq mshr uncacheable latency
3059system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899 # average WriteReq mshr uncacheable latency
3060system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827 # average WriteReq mshr uncacheable latency
3061system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
3062system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434 # average overall mshr uncacheable latency
3063system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency
3064system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280 # average overall mshr uncacheable latency
3065system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060 # average overall mshr uncacheable latency
3066system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3067system.membus.trans_dist::ReadReq 90579 # Transaction distribution
3068system.membus.trans_dist::ReadResp 797028 # Transaction distribution
3069system.membus.trans_dist::WriteReq 38077 # Transaction distribution
3070system.membus.trans_dist::WriteResp 38077 # Transaction distribution
3071system.membus.trans_dist::WritebackDirty 1072761 # Transaction distribution
3072system.membus.trans_dist::CleanEvict 234796 # Transaction distribution
3073system.membus.trans_dist::UpgradeReq 432847 # Transaction distribution
3074system.membus.trans_dist::SCUpgradeReq 303767 # Transaction distribution
3075system.membus.trans_dist::UpgradeResp 155875 # Transaction distribution
3076system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
3077system.membus.trans_dist::ReadExReq 628014 # Transaction distribution
3078system.membus.trans_dist::ReadExResp 607752 # Transaction distribution
3079system.membus.trans_dist::ReadSharedReq 706453 # Transaction distribution
3080system.membus.trans_dist::InvalidateReq 106976 # Transaction distribution
3081system.membus.trans_dist::InvalidateResp 106976 # Transaction distribution
3082system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122988 # Packet count per connected master and slave (bytes)
3083system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3084system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24302 # Packet count per connected master and slave (bytes)
3085system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4826718 # Packet count per connected master and slave (bytes)
3086system.membus.pkt_count_system.l2c.mem_side::total 4974060 # Packet count per connected master and slave (bytes)
3087system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342886 # Packet count per connected master and slave (bytes)
3088system.membus.pkt_count_system.iocache.mem_side::total 342886 # Packet count per connected master and slave (bytes)
3089system.membus.pkt_count::total 5316946 # Packet count per connected master and slave (bytes)
3090system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156003 # Cumulative packet size per connected master and slave (bytes)
3091system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3092system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48604 # Cumulative packet size per connected master and slave (bytes)
3093system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 148677184 # Cumulative packet size per connected master and slave (bytes)
3094system.membus.pkt_size_system.l2c.mem_side::total 148883115 # Cumulative packet size per connected master and slave (bytes)
3095system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268800 # Cumulative packet size per connected master and slave (bytes)
3096system.membus.pkt_size_system.iocache.mem_side::total 7268800 # Cumulative packet size per connected master and slave (bytes)
3097system.membus.pkt_size::total 156151915 # Cumulative packet size per connected master and slave (bytes)
3098system.membus.snoops 604039 # Total snoops (count)
3099system.membus.snoop_fanout::samples 3616779 # Request fanout histogram
3100system.membus.snoop_fanout::mean 1 # Request fanout histogram
3101system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3102system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3103system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3104system.membus.snoop_fanout::1 3616779 100.00% 100.00% # Request fanout histogram
3105system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3106system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3107system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3108system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3109system.membus.snoop_fanout::total 3616779 # Request fanout histogram
3110system.membus.reqLayer0.occupancy 110163500 # Layer occupancy (ticks)
3111system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3112system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
3113system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3114system.membus.reqLayer2.occupancy 20375999 # Layer occupancy (ticks)
3115system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3116system.membus.reqLayer5.occupancy 7677665405 # Layer occupancy (ticks)
3117system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3118system.membus.respLayer2.occupancy 7558802547 # Layer occupancy (ticks)
3119system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3120system.membus.respLayer3.occupancy 229140974 # Layer occupancy (ticks)
3121system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3122system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3123system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3124system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3125system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3126system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3127system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3128system.realview.ethernet.txBytes 966 # Bytes Transmitted

--- 37 unchanged lines hidden (view full) ---

3166system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3167system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3168system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3169system.realview.ethernet.droppedPackets 0 # number of packets dropped
3170system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3171system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3172system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3173system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3174system.toL2Bus.snoop_filter.tot_requests 11857284 # Total number of requests made to the snoop filter.
3175system.toL2Bus.snoop_filter.hit_single_requests 6410159 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3176system.toL2Bus.snoop_filter.hit_multi_requests 2032721 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3177system.toL2Bus.snoop_filter.tot_snoops 132920 # Total number of snoops made to the snoop filter.
3178system.toL2Bus.snoop_filter.hit_single_snoops 118959 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3179system.toL2Bus.snoop_filter.hit_multi_snoops 13961 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3180system.toL2Bus.trans_dist::ReadReq 90581 # Transaction distribution
3181system.toL2Bus.trans_dist::ReadResp 4604579 # Transaction distribution
3182system.toL2Bus.trans_dist::WriteReq 38077 # Transaction distribution
3183system.toL2Bus.trans_dist::WriteResp 38077 # Transaction distribution
3184system.toL2Bus.trans_dist::WritebackDirty 3658344 # Transaction distribution
3185system.toL2Bus.trans_dist::CleanEvict 1620073 # Transaction distribution
3186system.toL2Bus.trans_dist::UpgradeReq 706187 # Transaction distribution
3187system.toL2Bus.trans_dist::SCUpgradeReq 382180 # Transaction distribution
3188system.toL2Bus.trans_dist::UpgradeResp 1088365 # Transaction distribution
3189system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution
3190system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution
3191system.toL2Bus.trans_dist::ReadExReq 1100091 # Transaction distribution
3192system.toL2Bus.trans_dist::ReadExResp 1100091 # Transaction distribution
3193system.toL2Bus.trans_dist::ReadSharedReq 4521240 # Transaction distribution
3194system.toL2Bus.trans_dist::InvalidateReq 106976 # Transaction distribution
3195system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8903542 # Packet count per connected master and slave (bytes)
3196system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7167245 # Packet count per connected master and slave (bytes)
3197system.toL2Bus.pkt_count::total 16070787 # Packet count per connected master and slave (bytes)
3198system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267379155 # Cumulative packet size per connected master and slave (bytes)
3199system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202223448 # Cumulative packet size per connected master and slave (bytes)
3200system.toL2Bus.pkt_size::total 469602603 # Cumulative packet size per connected master and slave (bytes)
3201system.toL2Bus.snoops 2985982 # Total snoops (count)
3202system.toL2Bus.snoop_fanout::samples 8314965 # Request fanout histogram
3203system.toL2Bus.snoop_fanout::mean 0.369241 # Request fanout histogram
3204system.toL2Bus.snoop_fanout::stdev 0.486066 # Request fanout histogram
3205system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3206system.toL2Bus.snoop_fanout::0 5258700 63.24% 63.24% # Request fanout histogram
3207system.toL2Bus.snoop_fanout::1 3042304 36.59% 99.83% # Request fanout histogram
3208system.toL2Bus.snoop_fanout::2 13961 0.17% 100.00% # Request fanout histogram
3209system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3210system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3211system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3212system.toL2Bus.snoop_fanout::total 8314965 # Request fanout histogram
3213system.toL2Bus.reqLayer0.occupancy 8970776631 # Layer occupancy (ticks)
3214system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3215system.toL2Bus.snoopLayer0.occupancy 2598924 # Layer occupancy (ticks)
3216system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3217system.toL2Bus.respLayer0.occupancy 5002984602 # Layer occupancy (ticks)
3218system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3219system.toL2Bus.respLayer1.occupancy 4113788553 # Layer occupancy (ticks)
3220system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3221
3222---------- End Simulation Statistics ----------