1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.397611 # Number of seconds simulated
4sim_ticks 47397610926500 # Number of ticks simulated
5final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 110253 # Simulator instruction rate (inst/s)
8host_op_rate 129665 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5829907242 # Simulator tick rate (ticks/s)
10host_mem_usage 703216 # Number of bytes of host memory used
11host_seconds 8130.08 # Real time elapsed on the host
12sim_insts 896366789 # Number of instructions simulated
13sim_ops 1054186264 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory
27system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 79563472 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1673 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1224 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 121601 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 200061 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 246290 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2496 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2417 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 62410 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 195031 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 226610 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 7007 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1066820 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1242854 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1245457 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2259 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 1653 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 164195 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 270109 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 332560 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 3370 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 3264 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 84271 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 263327 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 305987 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9461 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1440456 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 164195 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 84271 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 248466 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1678200 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1678639 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1678200 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2259 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 1653 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 164195 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 270548 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 332560 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 3370 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 3264 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 84271 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 263327 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 305987 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9461 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3119095 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1066820 # Number of read requests accepted
84system.physmem.writeReqs 1912174 # Number of write requests accepted
85system.physmem.readBursts 1066820 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1912174 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 68253568 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 22912 # Total number of bytes read from write queue
89system.physmem.bytesWritten 119234048 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 68274168 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 122233360 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 358 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 49121 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 113360 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 61922 # Per bank write bursts
96system.physmem.perBankRdBursts::1 70972 # Per bank write bursts
97system.physmem.perBankRdBursts::2 57667 # Per bank write bursts
98system.physmem.perBankRdBursts::3 64982 # Per bank write bursts
99system.physmem.perBankRdBursts::4 65050 # Per bank write bursts
100system.physmem.perBankRdBursts::5 70572 # Per bank write bursts
101system.physmem.perBankRdBursts::6 72322 # Per bank write bursts
102system.physmem.perBankRdBursts::7 67337 # Per bank write bursts
103system.physmem.perBankRdBursts::8 57787 # Per bank write bursts
104system.physmem.perBankRdBursts::9 110760 # Per bank write bursts
105system.physmem.perBankRdBursts::10 57283 # Per bank write bursts
106system.physmem.perBankRdBursts::11 63297 # Per bank write bursts
107system.physmem.perBankRdBursts::12 60054 # Per bank write bursts
108system.physmem.perBankRdBursts::13 63124 # Per bank write bursts
109system.physmem.perBankRdBursts::14 62259 # Per bank write bursts
110system.physmem.perBankRdBursts::15 61074 # Per bank write bursts
111system.physmem.perBankWrBursts::0 110998 # Per bank write bursts
112system.physmem.perBankWrBursts::1 120192 # Per bank write bursts
113system.physmem.perBankWrBursts::2 114368 # Per bank write bursts
114system.physmem.perBankWrBursts::3 118573 # Per bank write bursts
115system.physmem.perBankWrBursts::4 116138 # Per bank write bursts
116system.physmem.perBankWrBursts::5 119482 # Per bank write bursts
117system.physmem.perBankWrBursts::6 124701 # Per bank write bursts
118system.physmem.perBankWrBursts::7 122822 # Per bank write bursts
119system.physmem.perBankWrBursts::8 112747 # Per bank write bursts
120system.physmem.perBankWrBursts::9 113706 # Per bank write bursts
121system.physmem.perBankWrBursts::10 111725 # Per bank write bursts
122system.physmem.perBankWrBursts::11 114999 # Per bank write bursts
123system.physmem.perBankWrBursts::12 115986 # Per bank write bursts
124system.physmem.perBankWrBursts::13 114347 # Per bank write bursts
125system.physmem.perBankWrBursts::14 116931 # Per bank write bursts
126system.physmem.perBankWrBursts::15 115317 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 309 # Number of times write queue was full causing retry
129system.physmem.totGap 47397609004000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 37 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1066778 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2601 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1909571 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 706521 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 126151 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 49462 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 37446 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 32271 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 29670 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 27253 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 24519 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 21077 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 5735 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 1704 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 1231 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 954 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 743 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 468 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 414 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 346 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 284 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 124 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 82 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see

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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 44683 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 64606 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 92963 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 104605 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 112793 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 111359 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 106848 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 102432 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 100351 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 96443 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 96232 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 115397 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 102859 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 98750 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 113669 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 102100 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 95328 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 90958 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 7555 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 6743 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 6847 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 8326 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 7904 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 7101 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 5905 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 7422 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 5868 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 5697 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 5505 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 5022 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 4736 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 3960 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 4047 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 3166 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 2471 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 1786 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 1553 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 1195 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 1041 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 906 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 935 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 725 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 739 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 598 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 535 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 533 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 628 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 443 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 770 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1060336 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 107.808098 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 246.499626 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 676218 63.77% 63.77% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 204682 19.30% 83.08% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 51639 4.87% 87.95% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 24739 2.33% 90.28% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 18449 1.74% 92.02% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 8607 0.81% 93.96% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7827 0.74% 94.70% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 82745 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 82742 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 82745 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 82745 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 19.971264 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-31 75024 90.67% 90.67% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::32-47 3669 4.43% 95.10% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::48-63 1611 1.95% 97.05% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::64-79 792 0.96% 98.01% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::80-95 419 0.51% 98.51% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::96-111 279 0.34% 98.85% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::112-127 435 0.53% 99.38% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::128-143 203 0.25% 99.62% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::144-159 68 0.08% 99.70% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::160-175 22 0.03% 99.73% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::176-191 73 0.09% 99.82% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::192-207 36 0.04% 99.86% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::208-223 10 0.01% 99.87% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::224-239 7 0.01% 99.88% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::240-255 4 0.00% 99.89% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::256-271 3 0.00% 99.89% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::272-287 1 0.00% 99.89% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::288-303 7 0.01% 99.90% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::320-335 7 0.01% 99.92% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::336-351 11 0.01% 99.93% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::352-367 22 0.03% 99.96% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::368-383 7 0.01% 99.97% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::384-399 2 0.00% 99.97% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::400-415 4 0.00% 99.98% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::464-479 1 0.00% 99.98% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::480-495 1 0.00% 99.98% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::544-559 1 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::592-607 1 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::656-671 1 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads
305system.physmem.totQLat 40375015102 # Total ticks spent queuing
306system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM
307system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers
308system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst
309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
310system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst
311system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
312system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s
313system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
314system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
316system.physmem.busUtil 0.03 # Data bus utilization in percentage
317system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
318system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
319system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
320system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing
321system.physmem.readRowHits 803348 # Number of row buffer hits during reads
322system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes
323system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads
324system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes
325system.physmem.avgGap 15910609.09 # Average gap between requests
326system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined
327system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ)
328system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ)
329system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ)
330system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ)
331system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
332system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ)
333system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ)
334system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ)
335system.physmem_0.averagePower 668.779401 # Core power per rank (mW)
336system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states
337system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states
338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
339system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states
340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
341system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ)
342system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ)
343system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ)
344system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ)
345system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
346system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ)
347system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ)
348system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ)
349system.physmem_1.averagePower 668.733509 # Core power per rank (mW)
350system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states
351system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states
352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
353system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states
354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
355system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory

--- 14 unchanged lines hidden (view full) ---

376system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
378system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
380system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
384system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
385system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
386system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
387system.cpu0.branchPred.lookups 133516333 # Number of BP lookups
388system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted
389system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect
390system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups
391system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits
392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
393system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage
394system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target.
395system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions.
396system.cpu_clk_domain.clock 500 # Clock period in ticks
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

418system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
419system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
420system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
421system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
422system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
423system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
424system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
425system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
426system.cpu0.dtb.walker.walks 274493 # Table walker walks requested
427system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors
428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate
429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate
430system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst
460system.cpu0.dtb.inst_hits 0 # ITB inst hits
461system.cpu0.dtb.inst_misses 0 # ITB inst misses
462system.cpu0.dtb.read_hits 84777209 # DTB read hits
463system.cpu0.dtb.read_misses 227212 # DTB read misses
464system.cpu0.dtb.write_hits 75760151 # DTB write hits
465system.cpu0.dtb.write_misses 47281 # DTB write misses
466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
468system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
469system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
470system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB
471system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions
472system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch
473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
474system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions
475system.cpu0.dtb.read_accesses 85004421 # DTB read accesses
476system.cpu0.dtb.write_accesses 75807432 # DTB write accesses
477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
478system.cpu0.dtb.hits 160537360 # DTB hits
479system.cpu0.dtb.misses 274493 # DTB misses
480system.cpu0.dtb.accesses 160811853 # DTB accesses
481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
510system.cpu0.itb.walker.walks 61212 # Table walker walks requested
511system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors
512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate
513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate
514system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
537system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
538system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
539system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated
540system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated
541system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated
542system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst
545system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
546system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst
547system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst
548system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst
549system.cpu0.itb.inst_hits 238748421 # ITB inst hits
550system.cpu0.itb.inst_misses 61212 # ITB inst misses
551system.cpu0.itb.read_hits 0 # DTB read hits
552system.cpu0.itb.read_misses 0 # DTB read misses
553system.cpu0.itb.write_hits 0 # DTB write hits
554system.cpu0.itb.write_misses 0 # DTB write misses
555system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
556system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
557system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
558system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
559system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB
560system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
561system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
562system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
563system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions
564system.cpu0.itb.read_accesses 0 # DTB read accesses
565system.cpu0.itb.write_accesses 0 # DTB write accesses
566system.cpu0.itb.inst_accesses 238809633 # ITB inst accesses
567system.cpu0.itb.hits 238748421 # DTB hits
568system.cpu0.itb.misses 61212 # DTB misses
569system.cpu0.itb.accesses 238809633 # DTB accesses
570system.cpu0.numCycles 949769690 # number of cpu cycles simulated
571system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
572system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
573system.cpu0.committedInsts 439719858 # Number of instructions committed
574system.cpu0.committedOps 516807751 # Number of ops (including micro ops) committed
575system.cpu0.discardedOps 45409758 # Number of ops (including micro ops) which were discarded before commit
576system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching
577system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
578system.cpu0.cpi 2.159943 # CPI: cycles per instruction
579system.cpu0.ipc 0.462975 # IPC: instructions per cycle
580system.cpu0.kern.inst.arm 0 # number of arm instructions executed
581system.cpu0.kern.inst.quiesce 12790 # number of quiesce instructions executed
582system.cpu0.tickCycles 712933683 # Number of cycles that the object actually ticked
583system.cpu0.idleCycles 236836007 # Total number of cycles that the object has spent stopped
584system.cpu0.dcache.tags.replacements 5519291 # number of replacements
585system.cpu0.dcache.tags.tagsinuse 480.702778 # Cycle average of tags in use
586system.cpu0.dcache.tags.total_refs 152151321 # Total number of references to valid blocks.
587system.cpu0.dcache.tags.sampled_refs 5519802 # Sample count of references to valid blocks.
588system.cpu0.dcache.tags.avg_refs 27.564634 # Average number of references to valid blocks.
589system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit.
590system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.702778 # Average occupied blocks per requestor
591system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938873 # Average percentage of cache occupancy
592system.cpu0.dcache.tags.occ_percent::total 0.938873 # Average percentage of cache occupancy
593system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
594system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
595system.cpu0.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id
596system.cpu0.dcache.tags.age_task_id_blocks_1024::2 207 # Occupied blocks per task id
597system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
598system.cpu0.dcache.tags.tag_accesses 323933952 # Number of tag accesses
599system.cpu0.dcache.tags.data_accesses 323933952 # Number of data accesses
600system.cpu0.dcache.ReadReq_hits::cpu0.data 77613049 # number of ReadReq hits
601system.cpu0.dcache.ReadReq_hits::total 77613049 # number of ReadReq hits
602system.cpu0.dcache.WriteReq_hits::cpu0.data 70091195 # number of WriteReq hits
603system.cpu0.dcache.WriteReq_hits::total 70091195 # number of WriteReq hits
604system.cpu0.dcache.SoftPFReq_hits::cpu0.data 268191 # number of SoftPFReq hits
605system.cpu0.dcache.SoftPFReq_hits::total 268191 # number of SoftPFReq hits
606system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249696 # number of WriteInvalidateReq hits
607system.cpu0.dcache.WriteInvalidateReq_hits::total 249696 # number of WriteInvalidateReq hits
608system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1731388 # number of LoadLockedReq hits
609system.cpu0.dcache.LoadLockedReq_hits::total 1731388 # number of LoadLockedReq hits
610system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1698549 # number of StoreCondReq hits
611system.cpu0.dcache.StoreCondReq_hits::total 1698549 # number of StoreCondReq hits
612system.cpu0.dcache.demand_hits::cpu0.data 147704244 # number of demand (read+write) hits
613system.cpu0.dcache.demand_hits::total 147704244 # number of demand (read+write) hits
614system.cpu0.dcache.overall_hits::cpu0.data 147972435 # number of overall hits
615system.cpu0.dcache.overall_hits::total 147972435 # number of overall hits
616system.cpu0.dcache.ReadReq_misses::cpu0.data 3327173 # number of ReadReq misses
617system.cpu0.dcache.ReadReq_misses::total 3327173 # number of ReadReq misses
618system.cpu0.dcache.WriteReq_misses::cpu0.data 2386267 # number of WriteReq misses
619system.cpu0.dcache.WriteReq_misses::total 2386267 # number of WriteReq misses
620system.cpu0.dcache.SoftPFReq_misses::cpu0.data 673594 # number of SoftPFReq misses
621system.cpu0.dcache.SoftPFReq_misses::total 673594 # number of SoftPFReq misses
622system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788040 # number of WriteInvalidateReq misses
623system.cpu0.dcache.WriteInvalidateReq_misses::total 788040 # number of WriteInvalidateReq misses
624system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148951 # number of LoadLockedReq misses
625system.cpu0.dcache.LoadLockedReq_misses::total 148951 # number of LoadLockedReq misses
626system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180566 # number of StoreCondReq misses
627system.cpu0.dcache.StoreCondReq_misses::total 180566 # number of StoreCondReq misses
628system.cpu0.dcache.demand_misses::cpu0.data 5713440 # number of demand (read+write) misses
629system.cpu0.dcache.demand_misses::total 5713440 # number of demand (read+write) misses
630system.cpu0.dcache.overall_misses::cpu0.data 6387034 # number of overall misses
631system.cpu0.dcache.overall_misses::total 6387034 # number of overall misses
632system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 50124059800 # number of ReadReq miss cycles
633system.cpu0.dcache.ReadReq_miss_latency::total 50124059800 # number of ReadReq miss cycles
634system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 46218650240 # number of WriteReq miss cycles
635system.cpu0.dcache.WriteReq_miss_latency::total 46218650240 # number of WriteReq miss cycles
636system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32570768827 # number of WriteInvalidateReq miss cycles
637system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32570768827 # number of WriteInvalidateReq miss cycles
638system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2177391616 # number of LoadLockedReq miss cycles
639system.cpu0.dcache.LoadLockedReq_miss_latency::total 2177391616 # number of LoadLockedReq miss cycles
640system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3839424984 # number of StoreCondReq miss cycles
641system.cpu0.dcache.StoreCondReq_miss_latency::total 3839424984 # number of StoreCondReq miss cycles
642system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3590500 # number of StoreCondFailReq miss cycles
643system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3590500 # number of StoreCondFailReq miss cycles
644system.cpu0.dcache.demand_miss_latency::cpu0.data 96342710040 # number of demand (read+write) miss cycles
645system.cpu0.dcache.demand_miss_latency::total 96342710040 # number of demand (read+write) miss cycles
646system.cpu0.dcache.overall_miss_latency::cpu0.data 96342710040 # number of overall miss cycles
647system.cpu0.dcache.overall_miss_latency::total 96342710040 # number of overall miss cycles
648system.cpu0.dcache.ReadReq_accesses::cpu0.data 80940222 # number of ReadReq accesses(hits+misses)
649system.cpu0.dcache.ReadReq_accesses::total 80940222 # number of ReadReq accesses(hits+misses)
650system.cpu0.dcache.WriteReq_accesses::cpu0.data 72477462 # number of WriteReq accesses(hits+misses)
651system.cpu0.dcache.WriteReq_accesses::total 72477462 # number of WriteReq accesses(hits+misses)
652system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 941785 # number of SoftPFReq accesses(hits+misses)
653system.cpu0.dcache.SoftPFReq_accesses::total 941785 # number of SoftPFReq accesses(hits+misses)
654system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037736 # number of WriteInvalidateReq accesses(hits+misses)
655system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037736 # number of WriteInvalidateReq accesses(hits+misses)
656system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1880339 # number of LoadLockedReq accesses(hits+misses)
657system.cpu0.dcache.LoadLockedReq_accesses::total 1880339 # number of LoadLockedReq accesses(hits+misses)
658system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1879115 # number of StoreCondReq accesses(hits+misses)
659system.cpu0.dcache.StoreCondReq_accesses::total 1879115 # number of StoreCondReq accesses(hits+misses)
660system.cpu0.dcache.demand_accesses::cpu0.data 153417684 # number of demand (read+write) accesses
661system.cpu0.dcache.demand_accesses::total 153417684 # number of demand (read+write) accesses
662system.cpu0.dcache.overall_accesses::cpu0.data 154359469 # number of overall (read+write) accesses
663system.cpu0.dcache.overall_accesses::total 154359469 # number of overall (read+write) accesses
664system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041107 # miss rate for ReadReq accesses
665system.cpu0.dcache.ReadReq_miss_rate::total 0.041107 # miss rate for ReadReq accesses
666system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032924 # miss rate for WriteReq accesses
667system.cpu0.dcache.WriteReq_miss_rate::total 0.032924 # miss rate for WriteReq accesses
668system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.715231 # miss rate for SoftPFReq accesses
669system.cpu0.dcache.SoftPFReq_miss_rate::total 0.715231 # miss rate for SoftPFReq accesses
670system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759384 # miss rate for WriteInvalidateReq accesses
671system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759384 # miss rate for WriteInvalidateReq accesses
672system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079215 # miss rate for LoadLockedReq accesses
673system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079215 # miss rate for LoadLockedReq accesses
674system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096091 # miss rate for StoreCondReq accesses
675system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096091 # miss rate for StoreCondReq accesses
676system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037241 # miss rate for demand accesses
677system.cpu0.dcache.demand_miss_rate::total 0.037241 # miss rate for demand accesses
678system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041378 # miss rate for overall accesses
679system.cpu0.dcache.overall_miss_rate::total 0.041378 # miss rate for overall accesses
680system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15065.059677 # average ReadReq miss latency
681system.cpu0.dcache.ReadReq_avg_miss_latency::total 15065.059677 # average ReadReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19368.599675 # average WriteReq miss latency
683system.cpu0.dcache.WriteReq_avg_miss_latency::total 19368.599675 # average WriteReq miss latency
684system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41331.364940 # average WriteInvalidateReq miss latency
685system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41331.364940 # average WriteInvalidateReq miss latency
686system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14618.173869 # average LoadLockedReq miss latency
687system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14618.173869 # average LoadLockedReq miss latency
688system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21263.277605 # average StoreCondReq miss latency
689system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21263.277605 # average StoreCondReq miss latency
690system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
691system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
692system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16862.469903 # average overall miss latency
693system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903 # average overall miss latency
694system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15084.107904 # average overall miss latency
695system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904 # average overall miss latency
696system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
697system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
698system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
699system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
700system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
701system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
702system.cpu0.dcache.fast_writes 0 # number of fast writes performed
703system.cpu0.dcache.cache_copies 0 # number of cache copies performed
704system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks
705system.cpu0.dcache.writebacks::total 3800112 # number of writebacks
706system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429398 # number of ReadReq MSHR hits
707system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits
708system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1005493 # number of WriteReq MSHR hits
709system.cpu0.dcache.WriteReq_mshr_hits::total 1005493 # number of WriteReq MSHR hits
710system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 83 # number of WriteInvalidateReq MSHR hits
711system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 83 # number of WriteInvalidateReq MSHR hits
712system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41403 # number of LoadLockedReq MSHR hits
713system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41403 # number of LoadLockedReq MSHR hits
714system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 51 # number of StoreCondReq MSHR hits
715system.cpu0.dcache.StoreCondReq_mshr_hits::total 51 # number of StoreCondReq MSHR hits
716system.cpu0.dcache.demand_mshr_hits::cpu0.data 1434891 # number of demand (read+write) MSHR hits
717system.cpu0.dcache.demand_mshr_hits::total 1434891 # number of demand (read+write) MSHR hits
718system.cpu0.dcache.overall_mshr_hits::cpu0.data 1434891 # number of overall MSHR hits
719system.cpu0.dcache.overall_mshr_hits::total 1434891 # number of overall MSHR hits
720system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2897775 # number of ReadReq MSHR misses
721system.cpu0.dcache.ReadReq_mshr_misses::total 2897775 # number of ReadReq MSHR misses
722system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380774 # number of WriteReq MSHR misses
723system.cpu0.dcache.WriteReq_mshr_misses::total 1380774 # number of WriteReq MSHR misses
724system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 667964 # number of SoftPFReq MSHR misses
725system.cpu0.dcache.SoftPFReq_mshr_misses::total 667964 # number of SoftPFReq MSHR misses
726system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 787957 # number of WriteInvalidateReq MSHR misses
727system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 787957 # number of WriteInvalidateReq MSHR misses
728system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 107548 # number of LoadLockedReq MSHR misses
729system.cpu0.dcache.LoadLockedReq_mshr_misses::total 107548 # number of LoadLockedReq MSHR misses
730system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180515 # number of StoreCondReq MSHR misses
731system.cpu0.dcache.StoreCondReq_mshr_misses::total 180515 # number of StoreCondReq MSHR misses
732system.cpu0.dcache.demand_mshr_misses::cpu0.data 4278549 # number of demand (read+write) MSHR misses
733system.cpu0.dcache.demand_mshr_misses::total 4278549 # number of demand (read+write) MSHR misses
734system.cpu0.dcache.overall_mshr_misses::cpu0.data 4946513 # number of overall MSHR misses
735system.cpu0.dcache.overall_mshr_misses::total 4946513 # number of overall MSHR misses
736system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37570974686 # number of ReadReq MSHR miss cycles
737system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37570974686 # number of ReadReq MSHR miss cycles
738system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24854865946 # number of WriteReq MSHR miss cycles
739system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24854865946 # number of WriteReq MSHR miss cycles
740system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14971801156 # number of SoftPFReq MSHR miss cycles
741system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14971801156 # number of SoftPFReq MSHR miss cycles
742system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31379224673 # number of WriteInvalidateReq MSHR miss cycles
743system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31379224673 # number of WriteInvalidateReq MSHR miss cycles
744system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1379388880 # number of LoadLockedReq MSHR miss cycles
745system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1379388880 # number of LoadLockedReq MSHR miss cycles
746system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3557992992 # number of StoreCondReq MSHR miss cycles
747system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3557992992 # number of StoreCondReq MSHR miss cycles
748system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq MSHR miss cycles
749system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2840500 # number of StoreCondFailReq MSHR miss cycles
750system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 62425840632 # number of demand (read+write) MSHR miss cycles
751system.cpu0.dcache.demand_mshr_miss_latency::total 62425840632 # number of demand (read+write) MSHR miss cycles
752system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77397641788 # number of overall MSHR miss cycles
753system.cpu0.dcache.overall_mshr_miss_latency::total 77397641788 # number of overall MSHR miss cycles
754system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5923264746 # number of ReadReq MSHR uncacheable cycles
755system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5923264746 # number of ReadReq MSHR uncacheable cycles
756system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5701581250 # number of WriteReq MSHR uncacheable cycles
757system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5701581250 # number of WriteReq MSHR uncacheable cycles
758system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11624845996 # number of overall MSHR uncacheable cycles
759system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11624845996 # number of overall MSHR uncacheable cycles
760system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035801 # mshr miss rate for ReadReq accesses
761system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035801 # mshr miss rate for ReadReq accesses
762system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019051 # mshr miss rate for WriteReq accesses
763system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019051 # mshr miss rate for WriteReq accesses
764system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.709253 # mshr miss rate for SoftPFReq accesses
765system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.709253 # mshr miss rate for SoftPFReq accesses
766system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759304 # mshr miss rate for WriteInvalidateReq accesses
767system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759304 # mshr miss rate for WriteInvalidateReq accesses
768system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057196 # mshr miss rate for LoadLockedReq accesses
769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057196 # mshr miss rate for LoadLockedReq accesses
770system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096064 # mshr miss rate for StoreCondReq accesses
771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096064 # mshr miss rate for StoreCondReq accesses
772system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027888 # mshr miss rate for demand accesses
773system.cpu0.dcache.demand_mshr_miss_rate::total 0.027888 # mshr miss rate for demand accesses
774system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032045 # mshr miss rate for overall accesses
775system.cpu0.dcache.overall_mshr_miss_rate::total 0.032045 # mshr miss rate for overall accesses
776system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147 # average ReadReq mshr miss latency
777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency
778system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393 # average WriteReq mshr miss latency
779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393 # average WriteReq mshr miss latency
780system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927 # average SoftPFReq mshr miss latency
781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency
782system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency
783system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency
784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency
785system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency
786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562 # average StoreCondReq mshr miss latency
787system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562 # average StoreCondReq mshr miss latency
788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
789system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
790system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209 # average overall mshr miss latency
791system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209 # average overall mshr miss latency
792system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608 # average overall mshr miss latency
793system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608 # average overall mshr miss latency
794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
795system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
797system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
799system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
800system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
801system.cpu0.icache.tags.replacements 9444901 # number of replacements
802system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use
803system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks.
804system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks.
805system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks.
806system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit.
807system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor
808system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
809system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
810system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
811system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id
812system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
813system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
814system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
815system.cpu0.icache.tags.tag_accesses 486538188 # Number of tag accesses
816system.cpu0.icache.tags.data_accesses 486538188 # Number of data accesses
817system.cpu0.icache.ReadReq_hits::cpu0.inst 229100961 # number of ReadReq hits
818system.cpu0.icache.ReadReq_hits::total 229100961 # number of ReadReq hits
819system.cpu0.icache.demand_hits::cpu0.inst 229100961 # number of demand (read+write) hits
820system.cpu0.icache.demand_hits::total 229100961 # number of demand (read+write) hits
821system.cpu0.icache.overall_hits::cpu0.inst 229100961 # number of overall hits
822system.cpu0.icache.overall_hits::total 229100961 # number of overall hits
823system.cpu0.icache.ReadReq_misses::cpu0.inst 9445422 # number of ReadReq misses
824system.cpu0.icache.ReadReq_misses::total 9445422 # number of ReadReq misses
825system.cpu0.icache.demand_misses::cpu0.inst 9445422 # number of demand (read+write) misses
826system.cpu0.icache.demand_misses::total 9445422 # number of demand (read+write) misses
827system.cpu0.icache.overall_misses::cpu0.inst 9445422 # number of overall misses
828system.cpu0.icache.overall_misses::total 9445422 # number of overall misses
829system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93680049293 # number of ReadReq miss cycles
830system.cpu0.icache.ReadReq_miss_latency::total 93680049293 # number of ReadReq miss cycles
831system.cpu0.icache.demand_miss_latency::cpu0.inst 93680049293 # number of demand (read+write) miss cycles
832system.cpu0.icache.demand_miss_latency::total 93680049293 # number of demand (read+write) miss cycles
833system.cpu0.icache.overall_miss_latency::cpu0.inst 93680049293 # number of overall miss cycles
834system.cpu0.icache.overall_miss_latency::total 93680049293 # number of overall miss cycles
835system.cpu0.icache.ReadReq_accesses::cpu0.inst 238546383 # number of ReadReq accesses(hits+misses)
836system.cpu0.icache.ReadReq_accesses::total 238546383 # number of ReadReq accesses(hits+misses)
837system.cpu0.icache.demand_accesses::cpu0.inst 238546383 # number of demand (read+write) accesses
838system.cpu0.icache.demand_accesses::total 238546383 # number of demand (read+write) accesses
839system.cpu0.icache.overall_accesses::cpu0.inst 238546383 # number of overall (read+write) accesses
840system.cpu0.icache.overall_accesses::total 238546383 # number of overall (read+write) accesses
841system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039596 # miss rate for ReadReq accesses
842system.cpu0.icache.ReadReq_miss_rate::total 0.039596 # miss rate for ReadReq accesses
843system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039596 # miss rate for demand accesses
844system.cpu0.icache.demand_miss_rate::total 0.039596 # miss rate for demand accesses
845system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039596 # miss rate for overall accesses
846system.cpu0.icache.overall_miss_rate::total 0.039596 # miss rate for overall accesses
847system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9918.037468 # average ReadReq miss latency
848system.cpu0.icache.ReadReq_avg_miss_latency::total 9918.037468 # average ReadReq miss latency
849system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency
850system.cpu0.icache.demand_avg_miss_latency::total 9918.037468 # average overall miss latency
851system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9918.037468 # average overall miss latency
852system.cpu0.icache.overall_avg_miss_latency::total 9918.037468 # average overall miss latency
853system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
854system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
855system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
856system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
857system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
858system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
859system.cpu0.icache.fast_writes 0 # number of fast writes performed
860system.cpu0.icache.cache_copies 0 # number of cache copies performed
861system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9445422 # number of ReadReq MSHR misses
862system.cpu0.icache.ReadReq_mshr_misses::total 9445422 # number of ReadReq MSHR misses
863system.cpu0.icache.demand_mshr_misses::cpu0.inst 9445422 # number of demand (read+write) MSHR misses
864system.cpu0.icache.demand_mshr_misses::total 9445422 # number of demand (read+write) MSHR misses
865system.cpu0.icache.overall_mshr_misses::cpu0.inst 9445422 # number of overall MSHR misses
866system.cpu0.icache.overall_mshr_misses::total 9445422 # number of overall MSHR misses
867system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84206359153 # number of ReadReq MSHR miss cycles
868system.cpu0.icache.ReadReq_mshr_miss_latency::total 84206359153 # number of ReadReq MSHR miss cycles
869system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84206359153 # number of demand (read+write) MSHR miss cycles
870system.cpu0.icache.demand_mshr_miss_latency::total 84206359153 # number of demand (read+write) MSHR miss cycles
871system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84206359153 # number of overall MSHR miss cycles
872system.cpu0.icache.overall_mshr_miss_latency::total 84206359153 # number of overall MSHR miss cycles
873system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles
874system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles
875system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles
876system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles
877system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for ReadReq accesses
878system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039596 # mshr miss rate for ReadReq accesses
879system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for demand accesses
880system.cpu0.icache.demand_mshr_miss_rate::total 0.039596 # mshr miss rate for demand accesses
881system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039596 # mshr miss rate for overall accesses
882system.cpu0.icache.overall_mshr_miss_rate::total 0.039596 # mshr miss rate for overall accesses
883system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average ReadReq mshr miss latency
884system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8915.044680 # average ReadReq mshr miss latency
885system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency
886system.cpu0.icache.demand_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency
887system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8915.044680 # average overall mshr miss latency
888system.cpu0.icache.overall_avg_mshr_miss_latency::total 8915.044680 # average overall mshr miss latency
889system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
890system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
891system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
892system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
893system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
894system.cpu0.l2cache.prefetcher.num_hwpf_issued 7452732 # number of hwpf issued
895system.cpu0.l2cache.prefetcher.pfIdentified 7456615 # number of prefetch candidates identified
896system.cpu0.l2cache.prefetcher.pfBufferHit 3365 # number of redundant prefetches already in prefetch queue
897system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
898system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
899system.cpu0.l2cache.prefetcher.pfSpanPage 953257 # number of prefetches not generated due to page crossing
900system.cpu0.l2cache.tags.replacements 2717195 # number of replacements
901system.cpu0.l2cache.tags.tagsinuse 16004.441587 # Cycle average of tags in use
902system.cpu0.l2cache.tags.total_refs 15093815 # Total number of references to valid blocks.
903system.cpu0.l2cache.tags.sampled_refs 2732791 # Sample count of references to valid blocks.
904system.cpu0.l2cache.tags.avg_refs 5.523223 # Average number of references to valid blocks.
905system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit.
906system.cpu0.l2cache.tags.occ_blocks::writebacks 4841.451480 # Average occupied blocks per requestor
907system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 32.729529 # Average occupied blocks per requestor
908system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 10.200147 # Average occupied blocks per requestor
909system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6443.890934 # Average occupied blocks per requestor
910system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3592.570226 # Average occupied blocks per requestor
911system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1083.599270 # Average occupied blocks per requestor
912system.cpu0.l2cache.tags.occ_percent::writebacks 0.295499 # Average percentage of cache occupancy
913system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001998 # Average percentage of cache occupancy
914system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000623 # Average percentage of cache occupancy
915system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.393304 # Average percentage of cache occupancy
916system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219273 # Average percentage of cache occupancy
917system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.066138 # Average percentage of cache occupancy
918system.cpu0.l2cache.tags.occ_percent::total 0.976834 # Average percentage of cache occupancy
919system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1333 # Occupied blocks per task id
920system.cpu0.l2cache.tags.occ_task_id_blocks::1023 97 # Occupied blocks per task id
921system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14166 # Occupied blocks per task id
922system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id
923system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id
924system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 727 # Occupied blocks per task id
925system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 336 # Occupied blocks per task id
926system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
927system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 73 # Occupied blocks per task id
928system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
929system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
930system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
931system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
932system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5419 # Occupied blocks per task id
933system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5745 # Occupied blocks per task id
934system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id
935system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081360 # Percentage of cache occupancy per task id
936system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005920 # Percentage of cache occupancy per task id
937system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.864624 # Percentage of cache occupancy per task id
938system.cpu0.l2cache.tags.tag_accesses 323522928 # Number of tag accesses
939system.cpu0.l2cache.tags.data_accesses 323522928 # Number of data accesses
940system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 471817 # number of ReadReq hits
941system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 144979 # number of ReadReq hits
942system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8688549 # number of ReadReq hits
943system.cpu0.l2cache.ReadReq_hits::cpu0.data 2694244 # number of ReadReq hits
944system.cpu0.l2cache.ReadReq_hits::total 11999589 # number of ReadReq hits
945system.cpu0.l2cache.Writeback_hits::writebacks 3800109 # number of Writeback hits
946system.cpu0.l2cache.Writeback_hits::total 3800109 # number of Writeback hits
947system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 203236 # number of WriteInvalidateReq hits
948system.cpu0.l2cache.WriteInvalidateReq_hits::total 203236 # number of WriteInvalidateReq hits
949system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 106799 # number of UpgradeReq hits
950system.cpu0.l2cache.UpgradeReq_hits::total 106799 # number of UpgradeReq hits
951system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33015 # number of SCUpgradeReq hits
952system.cpu0.l2cache.SCUpgradeReq_hits::total 33015 # number of SCUpgradeReq hits
953system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890572 # number of ReadExReq hits
954system.cpu0.l2cache.ReadExReq_hits::total 890572 # number of ReadExReq hits
955system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 471817 # number of demand (read+write) hits
956system.cpu0.l2cache.demand_hits::cpu0.itb.walker 144979 # number of demand (read+write) hits
957system.cpu0.l2cache.demand_hits::cpu0.inst 8688549 # number of demand (read+write) hits
958system.cpu0.l2cache.demand_hits::cpu0.data 3584816 # number of demand (read+write) hits
959system.cpu0.l2cache.demand_hits::total 12890161 # number of demand (read+write) hits
960system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 471817 # number of overall hits
961system.cpu0.l2cache.overall_hits::cpu0.itb.walker 144979 # number of overall hits
962system.cpu0.l2cache.overall_hits::cpu0.inst 8688549 # number of overall hits
963system.cpu0.l2cache.overall_hits::cpu0.data 3584816 # number of overall hits
964system.cpu0.l2cache.overall_hits::total 12890161 # number of overall hits
965system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11486 # number of ReadReq misses
966system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7971 # number of ReadReq misses
967system.cpu0.l2cache.ReadReq_misses::cpu0.inst 756872 # number of ReadReq misses
968system.cpu0.l2cache.ReadReq_misses::cpu0.data 978771 # number of ReadReq misses
969system.cpu0.l2cache.ReadReq_misses::total 1755100 # number of ReadReq misses
970system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
971system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses
972system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 582988 # number of WriteInvalidateReq misses
973system.cpu0.l2cache.WriteInvalidateReq_misses::total 582988 # number of WriteInvalidateReq misses
974system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124820 # number of UpgradeReq misses
975system.cpu0.l2cache.UpgradeReq_misses::total 124820 # number of UpgradeReq misses
976system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 147498 # number of SCUpgradeReq misses
977system.cpu0.l2cache.SCUpgradeReq_misses::total 147498 # number of SCUpgradeReq misses
978system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
979system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
980system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270733 # number of ReadExReq misses
981system.cpu0.l2cache.ReadExReq_misses::total 270733 # number of ReadExReq misses
982system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11486 # number of demand (read+write) misses
983system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7971 # number of demand (read+write) misses
984system.cpu0.l2cache.demand_misses::cpu0.inst 756872 # number of demand (read+write) misses
985system.cpu0.l2cache.demand_misses::cpu0.data 1249504 # number of demand (read+write) misses
986system.cpu0.l2cache.demand_misses::total 2025833 # number of demand (read+write) misses
987system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11486 # number of overall misses
988system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7971 # number of overall misses
989system.cpu0.l2cache.overall_misses::cpu0.inst 756872 # number of overall misses
990system.cpu0.l2cache.overall_misses::cpu0.data 1249504 # number of overall misses
991system.cpu0.l2cache.overall_misses::total 2025833 # number of overall misses
992system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 395323973 # number of ReadReq miss cycles
993system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 281388740 # number of ReadReq miss cycles
994system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22963858927 # number of ReadReq miss cycles
995system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32605245591 # number of ReadReq miss cycles
996system.cpu0.l2cache.ReadReq_miss_latency::total 56245817231 # number of ReadReq miss cycles
997system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 226701268 # number of WriteInvalidateReq miss cycles
998system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 226701268 # number of WriteInvalidateReq miss cycles
999system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2735720409 # number of UpgradeReq miss cycles
1000system.cpu0.l2cache.UpgradeReq_miss_latency::total 2735720409 # number of UpgradeReq miss cycles
1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3071526589 # number of SCUpgradeReq miss cycles
1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3071526589 # number of SCUpgradeReq miss cycles
1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2772000 # number of SCUpgradeFailReq miss cycles
1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2772000 # number of SCUpgradeFailReq miss cycles
1005system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13453990395 # number of ReadExReq miss cycles
1006system.cpu0.l2cache.ReadExReq_miss_latency::total 13453990395 # number of ReadExReq miss cycles
1007system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 395323973 # number of demand (read+write) miss cycles
1008system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 281388740 # number of demand (read+write) miss cycles
1009system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22963858927 # number of demand (read+write) miss cycles
1010system.cpu0.l2cache.demand_miss_latency::cpu0.data 46059235986 # number of demand (read+write) miss cycles
1011system.cpu0.l2cache.demand_miss_latency::total 69699807626 # number of demand (read+write) miss cycles
1012system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 395323973 # number of overall miss cycles
1013system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 281388740 # number of overall miss cycles
1014system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22963858927 # number of overall miss cycles
1015system.cpu0.l2cache.overall_miss_latency::cpu0.data 46059235986 # number of overall miss cycles
1016system.cpu0.l2cache.overall_miss_latency::total 69699807626 # number of overall miss cycles
1017system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 483303 # number of ReadReq accesses(hits+misses)
1018system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 152950 # number of ReadReq accesses(hits+misses)
1019system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9445421 # number of ReadReq accesses(hits+misses)
1020system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3673015 # number of ReadReq accesses(hits+misses)
1021system.cpu0.l2cache.ReadReq_accesses::total 13754689 # number of ReadReq accesses(hits+misses)
1022system.cpu0.l2cache.Writeback_accesses::writebacks 3800110 # number of Writeback accesses(hits+misses)
1023system.cpu0.l2cache.Writeback_accesses::total 3800110 # number of Writeback accesses(hits+misses)
1024system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 786224 # number of WriteInvalidateReq accesses(hits+misses)
1025system.cpu0.l2cache.WriteInvalidateReq_accesses::total 786224 # number of WriteInvalidateReq accesses(hits+misses)
1026system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 231619 # number of UpgradeReq accesses(hits+misses)
1027system.cpu0.l2cache.UpgradeReq_accesses::total 231619 # number of UpgradeReq accesses(hits+misses)
1028system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180513 # number of SCUpgradeReq accesses(hits+misses)
1029system.cpu0.l2cache.SCUpgradeReq_accesses::total 180513 # number of SCUpgradeReq accesses(hits+misses)
1030system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1031system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1032system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1161305 # number of ReadExReq accesses(hits+misses)
1033system.cpu0.l2cache.ReadExReq_accesses::total 1161305 # number of ReadExReq accesses(hits+misses)
1034system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 483303 # number of demand (read+write) accesses
1035system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 152950 # number of demand (read+write) accesses
1036system.cpu0.l2cache.demand_accesses::cpu0.inst 9445421 # number of demand (read+write) accesses
1037system.cpu0.l2cache.demand_accesses::cpu0.data 4834320 # number of demand (read+write) accesses
1038system.cpu0.l2cache.demand_accesses::total 14915994 # number of demand (read+write) accesses
1039system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 483303 # number of overall (read+write) accesses
1040system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 152950 # number of overall (read+write) accesses
1041system.cpu0.l2cache.overall_accesses::cpu0.inst 9445421 # number of overall (read+write) accesses
1042system.cpu0.l2cache.overall_accesses::cpu0.data 4834320 # number of overall (read+write) accesses
1043system.cpu0.l2cache.overall_accesses::total 14915994 # number of overall (read+write) accesses
1044system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for ReadReq accesses
1045system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052115 # miss rate for ReadReq accesses
1046system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.080131 # miss rate for ReadReq accesses
1047system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266476 # miss rate for ReadReq accesses
1048system.cpu0.l2cache.ReadReq_miss_rate::total 0.127600 # miss rate for ReadReq accesses
1049system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
1050system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
1051system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.741504 # miss rate for WriteInvalidateReq accesses
1052system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.741504 # miss rate for WriteInvalidateReq accesses
1053system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.538902 # miss rate for UpgradeReq accesses
1054system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.538902 # miss rate for UpgradeReq accesses
1055system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.817105 # miss rate for SCUpgradeReq accesses
1056system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.817105 # miss rate for SCUpgradeReq accesses
1057system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1058system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1059system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.233128 # miss rate for ReadExReq accesses
1060system.cpu0.l2cache.ReadExReq_miss_rate::total 0.233128 # miss rate for ReadExReq accesses
1061system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for demand accesses
1062system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052115 # miss rate for demand accesses
1063system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080131 # miss rate for demand accesses
1064system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258465 # miss rate for demand accesses
1065system.cpu0.l2cache.demand_miss_rate::total 0.135816 # miss rate for demand accesses
1066system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023766 # miss rate for overall accesses
1067system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052115 # miss rate for overall accesses
1068system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080131 # miss rate for overall accesses
1069system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258465 # miss rate for overall accesses
1070system.cpu0.l2cache.overall_miss_rate::total 0.135816 # miss rate for overall accesses
1071system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average ReadReq miss latency
1072system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35301.560657 # average ReadReq miss latency
1073system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30340.478875 # average ReadReq miss latency
1074system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33312.435280 # average ReadReq miss latency
1075system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32047.072663 # average ReadReq miss latency
1076system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 388.860951 # average WriteInvalidateReq miss latency
1077system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 388.860951 # average WriteInvalidateReq miss latency
1078system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21917.324219 # average UpgradeReq miss latency
1079system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21917.324219 # average UpgradeReq miss latency
1080system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20824.191440 # average SCUpgradeReq miss latency
1081system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20824.191440 # average SCUpgradeReq miss latency
1082system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1386000 # average SCUpgradeFailReq miss latency
1083system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1386000 # average SCUpgradeFailReq miss latency
1084system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49694.682196 # average ReadExReq miss latency
1085system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49694.682196 # average ReadExReq miss latency
1086system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average overall miss latency
1087system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35301.560657 # average overall miss latency
1088system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30340.478875 # average overall miss latency
1089system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36862.015637 # average overall miss latency
1090system.cpu0.l2cache.demand_avg_miss_latency::total 34405.505106 # average overall miss latency
1091system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34417.897702 # average overall miss latency
1092system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35301.560657 # average overall miss latency
1093system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30340.478875 # average overall miss latency
1094system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36862.015637 # average overall miss latency
1095system.cpu0.l2cache.overall_avg_miss_latency::total 34405.505106 # average overall miss latency
1096system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
1097system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1098system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1099system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1100system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked
1101system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1102system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1103system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1104system.cpu0.l2cache.writebacks::writebacks 1419293 # number of writebacks
1105system.cpu0.l2cache.writebacks::total 1419293 # number of writebacks
1106system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits
1107system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
1108system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 864 # number of ReadReq MSHR hits
1109system.cpu0.l2cache.ReadReq_mshr_hits::total 876 # number of ReadReq MSHR hits
1110system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 21 # number of WriteInvalidateReq MSHR hits
1111system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 21 # number of WriteInvalidateReq MSHR hits
1112system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9600 # number of ReadExReq MSHR hits
1113system.cpu0.l2cache.ReadExReq_mshr_hits::total 9600 # number of ReadExReq MSHR hits
1114system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits
1115system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
1116system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10464 # number of demand (read+write) MSHR hits
1117system.cpu0.l2cache.demand_mshr_hits::total 10476 # number of demand (read+write) MSHR hits
1118system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits
1119system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
1120system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10464 # number of overall MSHR hits
1121system.cpu0.l2cache.overall_mshr_hits::total 10476 # number of overall MSHR hits
1122system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11483 # number of ReadReq MSHR misses
1123system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7971 # number of ReadReq MSHR misses
1124system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 756863 # number of ReadReq MSHR misses
1125system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 977907 # number of ReadReq MSHR misses
1126system.cpu0.l2cache.ReadReq_mshr_misses::total 1754224 # number of ReadReq MSHR misses
1127system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
1128system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
1129system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 730042 # number of HardPFReq MSHR misses
1130system.cpu0.l2cache.HardPFReq_mshr_misses::total 730042 # number of HardPFReq MSHR misses
1131system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 582967 # number of WriteInvalidateReq MSHR misses
1132system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 582967 # number of WriteInvalidateReq MSHR misses
1133system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124820 # number of UpgradeReq MSHR misses
1134system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124820 # number of UpgradeReq MSHR misses
1135system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 147498 # number of SCUpgradeReq MSHR misses
1136system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 147498 # number of SCUpgradeReq MSHR misses
1137system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1139system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261133 # number of ReadExReq MSHR misses
1140system.cpu0.l2cache.ReadExReq_mshr_misses::total 261133 # number of ReadExReq MSHR misses
1141system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11483 # number of demand (read+write) MSHR misses
1142system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7971 # number of demand (read+write) MSHR misses
1143system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 756863 # number of demand (read+write) MSHR misses
1144system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1239040 # number of demand (read+write) MSHR misses
1145system.cpu0.l2cache.demand_mshr_misses::total 2015357 # number of demand (read+write) MSHR misses
1146system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11483 # number of overall MSHR misses
1147system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7971 # number of overall MSHR misses
1148system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 756863 # number of overall MSHR misses
1149system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1239040 # number of overall MSHR misses
1150system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 730042 # number of overall MSHR misses
1151system.cpu0.l2cache.overall_mshr_misses::total 2745399 # number of overall MSHR misses
1152system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of ReadReq MSHR miss cycles
1153system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 229236274 # number of ReadReq MSHR miss cycles
1154system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 18018194823 # number of ReadReq MSHR miss cycles
1155system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 26119410327 # number of ReadReq MSHR miss cycles
1156system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44687012445 # number of ReadReq MSHR miss cycles
1157system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38329201084 # number of HardPFReq MSHR miss cycles
1158system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38329201084 # number of HardPFReq MSHR miss cycles
1159system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25353006103 # number of WriteInvalidateReq MSHR miss cycles
1160system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25353006103 # number of WriteInvalidateReq MSHR miss cycles
1161system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529620082 # number of UpgradeReq MSHR miss cycles
1162system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529620082 # number of UpgradeReq MSHR miss cycles
1163system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2203543880 # number of SCUpgradeReq MSHR miss cycles
1164system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2203543880 # number of SCUpgradeReq MSHR miss cycles
1165system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2330000 # number of SCUpgradeFailReq MSHR miss cycles
1166system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2330000 # number of SCUpgradeFailReq MSHR miss cycles
1167system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10429150296 # number of ReadExReq MSHR miss cycles
1168system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10429150296 # number of ReadExReq MSHR miss cycles
1169system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of demand (read+write) MSHR miss cycles
1170system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 229236274 # number of demand (read+write) MSHR miss cycles
1171system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18018194823 # number of demand (read+write) MSHR miss cycles
1172system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36548560623 # number of demand (read+write) MSHR miss cycles
1173system.cpu0.l2cache.demand_mshr_miss_latency::total 55116162741 # number of demand (read+write) MSHR miss cycles
1174system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 320171021 # number of overall MSHR miss cycles
1175system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 229236274 # number of overall MSHR miss cycles
1176system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18018194823 # number of overall MSHR miss cycles
1177system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36548560623 # number of overall MSHR miss cycles
1178system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38329201084 # number of overall MSHR miss cycles
1179system.cpu0.l2cache.overall_mshr_miss_latency::total 93445363825 # number of overall MSHR miss cycles
1180system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles
1181system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5656823753 # number of ReadReq MSHR uncacheable cycles
1182system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10047894503 # number of ReadReq MSHR uncacheable cycles
1183system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452375000 # number of WriteReq MSHR uncacheable cycles
1184system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5452375000 # number of WriteReq MSHR uncacheable cycles
1185system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles
1186system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11109198753 # number of overall MSHR uncacheable cycles
1187system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15500269503 # number of overall MSHR uncacheable cycles
1188system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for ReadReq accesses
1189system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for ReadReq accesses
1190system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for ReadReq accesses
1191system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266241 # mshr miss rate for ReadReq accesses
1192system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.127536 # mshr miss rate for ReadReq accesses
1193system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
1194system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
1195system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1196system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1197system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741477 # mshr miss rate for WriteInvalidateReq accesses
1198system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741477 # mshr miss rate for WriteInvalidateReq accesses
1199system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.538902 # mshr miss rate for UpgradeReq accesses
1200system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.538902 # mshr miss rate for UpgradeReq accesses
1201system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817105 # mshr miss rate for SCUpgradeReq accesses
1202system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817105 # mshr miss rate for SCUpgradeReq accesses
1203system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1204system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1205system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224862 # mshr miss rate for ReadExReq accesses
1206system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224862 # mshr miss rate for ReadExReq accesses
1207system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for demand accesses
1208system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for demand accesses
1209system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for demand accesses
1210system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for demand accesses
1211system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135114 # mshr miss rate for demand accesses
1212system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for overall accesses
1213system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for overall accesses
1214system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for overall accesses
1215system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for overall accesses
1216system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1217system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses
1218system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency
1219system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency
1220system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency
1221system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency
1222system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency
1223system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency
1224system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency
1225system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency
1226system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency
1227system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency
1228system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency
1229system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency
1230system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency
1231system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency
1232system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency
1233system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency
1234system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency
1235system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
1236system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
1237system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
1238system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
1239system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency
1240system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
1241system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
1242system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
1243system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
1244system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency
1245system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency
1246system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1247system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1248system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1249system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1250system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1251system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1252system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1253system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1254system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1255system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution
1257system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution
1258system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution
1259system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution
1260system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution
1261system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
1262system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution
1263system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution
1264system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution
1265system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution
1266system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution
1267system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
1268system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
1269system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution
1270system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution
1271system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes)
1272system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes)
1273system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes)
1274system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes)
1275system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes)
1276system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes)
1277system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes)
1278system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes)
1279system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes)
1280system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes)
1281system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count)
1282system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram
1283system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram
1284system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram
1285system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1286system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1287system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1288system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1289system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram
1290system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram
1291system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1292system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1293system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1294system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram
1295system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks)
1296system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1297system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks)
1298system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1299system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks)
1300system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1301system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks)
1302system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1303system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks)
1304system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1305system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks)
1306system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1307system.cpu1.branchPred.lookups 139172899 # Number of BP lookups
1308system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted
1309system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect
1310system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups
1311system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits
1312system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1313system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage
1314system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target.
1315system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions.
1316system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1317system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1318system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1319system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1320system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1321system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1322system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1323system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1337system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1338system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1339system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1340system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1341system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1342system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1343system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1344system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1345system.cpu1.dtb.walker.walks 295412 # Table walker walks requested
1346system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors
1347system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate
1348system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate
1349system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency
1350system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1351system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency
1352system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency
1353system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency
1354system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency
1355system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency
1356system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency
1357system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency
1358system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency
1359system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency
1360system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency
1361system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency
1362system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
1363system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
1364system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1365system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1366system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency
1367system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution
1368system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution
1369system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution
1370system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated
1371system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated
1372system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated
1373system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst
1374system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1375system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst
1376system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst
1377system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1378system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst
1379system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst
1380system.cpu1.dtb.inst_hits 0 # ITB inst hits
1381system.cpu1.dtb.inst_misses 0 # ITB inst misses
1382system.cpu1.dtb.read_hits 90130445 # DTB read hits
1383system.cpu1.dtb.read_misses 246227 # DTB read misses
1384system.cpu1.dtb.write_hits 78064785 # DTB write hits
1385system.cpu1.dtb.write_misses 49185 # DTB write misses
1386system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1387system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1388system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
1389system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
1390system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB
1391system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions
1392system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch
1393system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1394system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions
1395system.cpu1.dtb.read_accesses 90376672 # DTB read accesses
1396system.cpu1.dtb.write_accesses 78113970 # DTB write accesses
1397system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1398system.cpu1.dtb.hits 168195230 # DTB hits
1399system.cpu1.dtb.misses 295412 # DTB misses
1400system.cpu1.dtb.accesses 168490642 # DTB accesses
1401system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1402system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1403system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1404system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1405system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1406system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1407system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1408system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1422system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1423system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1424system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1425system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1426system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1427system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1428system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1429system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1430system.cpu1.itb.walker.walks 68039 # Table walker walks requested
1431system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors
1432system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate
1433system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate
1434system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency
1435system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1436system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency
1437system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency
1438system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency
1439system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency
1440system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency
1441system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency
1442system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency
1443system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency
1444system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency
1445system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
1446system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency
1447system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1448system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1449system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency
1450system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution
1451system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution
1452system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution
1453system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated
1454system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated
1455system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated
1456system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1457system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst
1458system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst
1459system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1460system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst
1461system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst
1462system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst
1463system.cpu1.itb.inst_hits 249268487 # ITB inst hits
1464system.cpu1.itb.inst_misses 68039 # ITB inst misses
1465system.cpu1.itb.read_hits 0 # DTB read hits
1466system.cpu1.itb.read_misses 0 # DTB read misses
1467system.cpu1.itb.write_hits 0 # DTB write hits
1468system.cpu1.itb.write_misses 0 # DTB write misses
1469system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1470system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1471system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
1472system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
1473system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB
1474system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1475system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1476system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1477system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions
1478system.cpu1.itb.read_accesses 0 # DTB read accesses
1479system.cpu1.itb.write_accesses 0 # DTB write accesses
1480system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses
1481system.cpu1.itb.hits 249268487 # DTB hits
1482system.cpu1.itb.misses 68039 # DTB misses
1483system.cpu1.itb.accesses 249336526 # DTB accesses
1484system.cpu1.numCycles 932637373 # number of cpu cycles simulated
1485system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1486system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1487system.cpu1.committedInsts 456646931 # Number of instructions committed
1488system.cpu1.committedOps 537378513 # Number of ops (including micro ops) committed
1489system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit
1490system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching
1491system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1492system.cpu1.cpi 2.042360 # CPI: cycles per instruction
1493system.cpu1.ipc 0.489630 # IPC: instructions per cycle
1494system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1495system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed
1496system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked
1497system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped
1498system.cpu1.dcache.tags.replacements 5504177 # number of replacements
1499system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use
1500system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks.
1501system.cpu1.dcache.tags.sampled_refs 5504689 # Sample count of references to valid blocks.
1502system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks.
1503system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit.
1504system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.121005 # Average occupied blocks per requestor
1505system.cpu1.dcache.tags.occ_percent::cpu1.data 0.902580 # Average percentage of cache occupancy
1506system.cpu1.dcache.tags.occ_percent::total 0.902580 # Average percentage of cache occupancy
1507system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1508system.cpu1.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
1509system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
1510system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
1511system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1512system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1513system.cpu1.dcache.tags.tag_accesses 339217340 # Number of tag accesses
1514system.cpu1.dcache.tags.data_accesses 339217340 # Number of data accesses
1515system.cpu1.dcache.ReadReq_hits::cpu1.data 82545716 # number of ReadReq hits
1516system.cpu1.dcache.ReadReq_hits::total 82545716 # number of ReadReq hits
1517system.cpu1.dcache.WriteReq_hits::cpu1.data 72881068 # number of WriteReq hits
1518system.cpu1.dcache.WriteReq_hits::total 72881068 # number of WriteReq hits
1519system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234096 # number of SoftPFReq hits
1520system.cpu1.dcache.SoftPFReq_hits::total 234096 # number of SoftPFReq hits
1521system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75438 # number of WriteInvalidateReq hits
1522system.cpu1.dcache.WriteInvalidateReq_hits::total 75438 # number of WriteInvalidateReq hits
1523system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844359 # number of LoadLockedReq hits
1524system.cpu1.dcache.LoadLockedReq_hits::total 1844359 # number of LoadLockedReq hits
1525system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1835233 # number of StoreCondReq hits
1526system.cpu1.dcache.StoreCondReq_hits::total 1835233 # number of StoreCondReq hits
1527system.cpu1.dcache.demand_hits::cpu1.data 155426784 # number of demand (read+write) hits
1528system.cpu1.dcache.demand_hits::total 155426784 # number of demand (read+write) hits
1529system.cpu1.dcache.overall_hits::cpu1.data 155660880 # number of overall hits
1530system.cpu1.dcache.overall_hits::total 155660880 # number of overall hits
1531system.cpu1.dcache.ReadReq_misses::cpu1.data 3601145 # number of ReadReq misses
1532system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses
1533system.cpu1.dcache.WriteReq_misses::cpu1.data 2300638 # number of WriteReq misses
1534system.cpu1.dcache.WriteReq_misses::total 2300638 # number of WriteReq misses
1535system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662253 # number of SoftPFReq misses
1536system.cpu1.dcache.SoftPFReq_misses::total 662253 # number of SoftPFReq misses
1537system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 453115 # number of WriteInvalidateReq misses
1538system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses
1539system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 186074 # number of LoadLockedReq misses
1540system.cpu1.dcache.LoadLockedReq_misses::total 186074 # number of LoadLockedReq misses
1541system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193760 # number of StoreCondReq misses
1542system.cpu1.dcache.StoreCondReq_misses::total 193760 # number of StoreCondReq misses
1543system.cpu1.dcache.demand_misses::cpu1.data 5901783 # number of demand (read+write) misses
1544system.cpu1.dcache.demand_misses::total 5901783 # number of demand (read+write) misses
1545system.cpu1.dcache.overall_misses::cpu1.data 6564036 # number of overall misses
1546system.cpu1.dcache.overall_misses::total 6564036 # number of overall misses
1547system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55051091271 # number of ReadReq miss cycles
1548system.cpu1.dcache.ReadReq_miss_latency::total 55051091271 # number of ReadReq miss cycles
1549system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39953352540 # number of WriteReq miss cycles
1550system.cpu1.dcache.WriteReq_miss_latency::total 39953352540 # number of WriteReq miss cycles
1551system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12827340347 # number of WriteInvalidateReq miss cycles
1552system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12827340347 # number of WriteInvalidateReq miss cycles
1553system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2834422928 # number of LoadLockedReq miss cycles
1554system.cpu1.dcache.LoadLockedReq_miss_latency::total 2834422928 # number of LoadLockedReq miss cycles
1555system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4003287927 # number of StoreCondReq miss cycles
1556system.cpu1.dcache.StoreCondReq_miss_latency::total 4003287927 # number of StoreCondReq miss cycles
1557system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3321500 # number of StoreCondFailReq miss cycles
1558system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3321500 # number of StoreCondFailReq miss cycles
1559system.cpu1.dcache.demand_miss_latency::cpu1.data 95004443811 # number of demand (read+write) miss cycles
1560system.cpu1.dcache.demand_miss_latency::total 95004443811 # number of demand (read+write) miss cycles
1561system.cpu1.dcache.overall_miss_latency::cpu1.data 95004443811 # number of overall miss cycles
1562system.cpu1.dcache.overall_miss_latency::total 95004443811 # number of overall miss cycles
1563system.cpu1.dcache.ReadReq_accesses::cpu1.data 86146861 # number of ReadReq accesses(hits+misses)
1564system.cpu1.dcache.ReadReq_accesses::total 86146861 # number of ReadReq accesses(hits+misses)
1565system.cpu1.dcache.WriteReq_accesses::cpu1.data 75181706 # number of WriteReq accesses(hits+misses)
1566system.cpu1.dcache.WriteReq_accesses::total 75181706 # number of WriteReq accesses(hits+misses)
1567system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 896349 # number of SoftPFReq accesses(hits+misses)
1568system.cpu1.dcache.SoftPFReq_accesses::total 896349 # number of SoftPFReq accesses(hits+misses)
1569system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 528553 # number of WriteInvalidateReq accesses(hits+misses)
1570system.cpu1.dcache.WriteInvalidateReq_accesses::total 528553 # number of WriteInvalidateReq accesses(hits+misses)
1571system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2030433 # number of LoadLockedReq accesses(hits+misses)
1572system.cpu1.dcache.LoadLockedReq_accesses::total 2030433 # number of LoadLockedReq accesses(hits+misses)
1573system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028993 # number of StoreCondReq accesses(hits+misses)
1574system.cpu1.dcache.StoreCondReq_accesses::total 2028993 # number of StoreCondReq accesses(hits+misses)
1575system.cpu1.dcache.demand_accesses::cpu1.data 161328567 # number of demand (read+write) accesses
1576system.cpu1.dcache.demand_accesses::total 161328567 # number of demand (read+write) accesses
1577system.cpu1.dcache.overall_accesses::cpu1.data 162224916 # number of overall (read+write) accesses
1578system.cpu1.dcache.overall_accesses::total 162224916 # number of overall (read+write) accesses
1579system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041802 # miss rate for ReadReq accesses
1580system.cpu1.dcache.ReadReq_miss_rate::total 0.041802 # miss rate for ReadReq accesses
1581system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030601 # miss rate for WriteReq accesses
1582system.cpu1.dcache.WriteReq_miss_rate::total 0.030601 # miss rate for WriteReq accesses
1583system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.738834 # miss rate for SoftPFReq accesses
1584system.cpu1.dcache.SoftPFReq_miss_rate::total 0.738834 # miss rate for SoftPFReq accesses
1585system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.857274 # miss rate for WriteInvalidateReq accesses
1586system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.857274 # miss rate for WriteInvalidateReq accesses
1587system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091643 # miss rate for LoadLockedReq accesses
1588system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091643 # miss rate for LoadLockedReq accesses
1589system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095496 # miss rate for StoreCondReq accesses
1590system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095496 # miss rate for StoreCondReq accesses
1591system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036582 # miss rate for demand accesses
1592system.cpu1.dcache.demand_miss_rate::total 0.036582 # miss rate for demand accesses
1593system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040463 # miss rate for overall accesses
1594system.cpu1.dcache.overall_miss_rate::total 0.040463 # miss rate for overall accesses
1595system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15287.107648 # average ReadReq miss latency
1596system.cpu1.dcache.ReadReq_avg_miss_latency::total 15287.107648 # average ReadReq miss latency
1597system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17366.205609 # average WriteReq miss latency
1598system.cpu1.dcache.WriteReq_avg_miss_latency::total 17366.205609 # average WriteReq miss latency
1599system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28309.237935 # average WriteInvalidateReq miss latency
1600system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28309.237935 # average WriteInvalidateReq miss latency
1601system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15232.772596 # average LoadLockedReq miss latency
1602system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15232.772596 # average LoadLockedReq miss latency
1603system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20661.064859 # average StoreCondReq miss latency
1604system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency
1605system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1606system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1607system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16097.583359 # average overall miss latency
1608system.cpu1.dcache.demand_avg_miss_latency::total 16097.583359 # average overall miss latency
1609system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14473.480007 # average overall miss latency
1610system.cpu1.dcache.overall_avg_miss_latency::total 14473.480007 # average overall miss latency
1611system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1612system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1613system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1614system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1615system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1616system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1617system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1618system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1619system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks
1620system.cpu1.dcache.writebacks::total 3506045 # number of writebacks
1621system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits
1622system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits
1623system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # number of WriteReq MSHR hits
1624system.cpu1.dcache.WriteReq_mshr_hits::total 940543 # number of WriteReq MSHR hits
1625system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 72 # number of WriteInvalidateReq MSHR hits
1626system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 72 # number of WriteInvalidateReq MSHR hits
1627system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45181 # number of LoadLockedReq MSHR hits
1628system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45181 # number of LoadLockedReq MSHR hits
1629system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
1630system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
1631system.cpu1.dcache.demand_mshr_hits::cpu1.data 1350368 # number of demand (read+write) MSHR hits
1632system.cpu1.dcache.demand_mshr_hits::total 1350368 # number of demand (read+write) MSHR hits
1633system.cpu1.dcache.overall_mshr_hits::cpu1.data 1350368 # number of overall MSHR hits
1634system.cpu1.dcache.overall_mshr_hits::total 1350368 # number of overall MSHR hits
1635system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3191320 # number of ReadReq MSHR misses
1636system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses
1637system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1360095 # number of WriteReq MSHR misses
1638system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses
1639system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses
1640system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses
1641system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 453043 # number of WriteInvalidateReq MSHR misses
1642system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses
1643system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses
1644system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses
1645system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses
1646system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses
1647system.cpu1.dcache.demand_mshr_misses::cpu1.data 4551415 # number of demand (read+write) MSHR misses
1648system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses
1649system.cpu1.dcache.overall_mshr_misses::cpu1.data 5213364 # number of overall MSHR misses
1650system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses
1651system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42631813644 # number of ReadReq MSHR miss cycles
1652system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles
1653system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles
1654system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles
1655system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605448576 # number of SoftPFReq MSHR miss cycles
1656system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles
1657system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles
1658system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles
1659system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles
1660system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles
1661system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles
1662system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles
1663system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles
1664system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles
1665system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles
1666system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles
1667system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles
1668system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles
1669system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles
1670system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles
1671system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles
1672system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles
1673system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles
1674system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles
1675system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses
1676system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses
1677system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses
1678system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses
1679system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses
1680system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses
1681system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses
1682system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses
1683system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses
1684system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses
1685system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses
1686system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses
1687system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses
1688system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses
1689system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses
1690system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses
1691system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency
1692system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency
1693system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency
1694system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency
1695system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency
1696system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency
1697system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency
1698system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency
1699system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency
1700system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency
1701system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency
1702system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # average StoreCondReq mshr miss latency
1703system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1704system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1705system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997 # average overall mshr miss latency
1706system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997 # average overall mshr miss latency
1707system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220 # average overall mshr miss latency
1708system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220 # average overall mshr miss latency
1709system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1710system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1711system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1712system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1713system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1714system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1715system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1716system.cpu1.icache.tags.replacements 9392574 # number of replacements
1717system.cpu1.icache.tags.tagsinuse 507.206734 # Cycle average of tags in use
1718system.cpu1.icache.tags.total_refs 239643264 # Total number of references to valid blocks.
1719system.cpu1.icache.tags.sampled_refs 9393086 # Sample count of references to valid blocks.
1720system.cpu1.icache.tags.avg_refs 25.512730 # Average number of references to valid blocks.
1721system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit.
1722system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.206734 # Average occupied blocks per requestor
1723system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990638 # Average percentage of cache occupancy
1724system.cpu1.icache.tags.occ_percent::total 0.990638 # Average percentage of cache occupancy
1725system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1726system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
1727system.cpu1.icache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
1728system.cpu1.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
1729system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1730system.cpu1.icache.tags.tag_accesses 507465788 # Number of tag accesses
1731system.cpu1.icache.tags.data_accesses 507465788 # Number of data accesses
1732system.cpu1.icache.ReadReq_hits::cpu1.inst 239643264 # number of ReadReq hits
1733system.cpu1.icache.ReadReq_hits::total 239643264 # number of ReadReq hits
1734system.cpu1.icache.demand_hits::cpu1.inst 239643264 # number of demand (read+write) hits
1735system.cpu1.icache.demand_hits::total 239643264 # number of demand (read+write) hits
1736system.cpu1.icache.overall_hits::cpu1.inst 239643264 # number of overall hits
1737system.cpu1.icache.overall_hits::total 239643264 # number of overall hits
1738system.cpu1.icache.ReadReq_misses::cpu1.inst 9393087 # number of ReadReq misses
1739system.cpu1.icache.ReadReq_misses::total 9393087 # number of ReadReq misses
1740system.cpu1.icache.demand_misses::cpu1.inst 9393087 # number of demand (read+write) misses
1741system.cpu1.icache.demand_misses::total 9393087 # number of demand (read+write) misses
1742system.cpu1.icache.overall_misses::cpu1.inst 9393087 # number of overall misses
1743system.cpu1.icache.overall_misses::total 9393087 # number of overall misses
1744system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 93629377858 # number of ReadReq miss cycles
1745system.cpu1.icache.ReadReq_miss_latency::total 93629377858 # number of ReadReq miss cycles
1746system.cpu1.icache.demand_miss_latency::cpu1.inst 93629377858 # number of demand (read+write) miss cycles
1747system.cpu1.icache.demand_miss_latency::total 93629377858 # number of demand (read+write) miss cycles
1748system.cpu1.icache.overall_miss_latency::cpu1.inst 93629377858 # number of overall miss cycles
1749system.cpu1.icache.overall_miss_latency::total 93629377858 # number of overall miss cycles
1750system.cpu1.icache.ReadReq_accesses::cpu1.inst 249036351 # number of ReadReq accesses(hits+misses)
1751system.cpu1.icache.ReadReq_accesses::total 249036351 # number of ReadReq accesses(hits+misses)
1752system.cpu1.icache.demand_accesses::cpu1.inst 249036351 # number of demand (read+write) accesses
1753system.cpu1.icache.demand_accesses::total 249036351 # number of demand (read+write) accesses
1754system.cpu1.icache.overall_accesses::cpu1.inst 249036351 # number of overall (read+write) accesses
1755system.cpu1.icache.overall_accesses::total 249036351 # number of overall (read+write) accesses
1756system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037718 # miss rate for ReadReq accesses
1757system.cpu1.icache.ReadReq_miss_rate::total 0.037718 # miss rate for ReadReq accesses
1758system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037718 # miss rate for demand accesses
1759system.cpu1.icache.demand_miss_rate::total 0.037718 # miss rate for demand accesses
1760system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037718 # miss rate for overall accesses
1761system.cpu1.icache.overall_miss_rate::total 0.037718 # miss rate for overall accesses
1762system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9967.902763 # average ReadReq miss latency
1763system.cpu1.icache.ReadReq_avg_miss_latency::total 9967.902763 # average ReadReq miss latency
1764system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency
1765system.cpu1.icache.demand_avg_miss_latency::total 9967.902763 # average overall miss latency
1766system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9967.902763 # average overall miss latency
1767system.cpu1.icache.overall_avg_miss_latency::total 9967.902763 # average overall miss latency
1768system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1769system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1770system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1771system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1772system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1773system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1774system.cpu1.icache.fast_writes 0 # number of fast writes performed
1775system.cpu1.icache.cache_copies 0 # number of cache copies performed
1776system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9393087 # number of ReadReq MSHR misses
1777system.cpu1.icache.ReadReq_mshr_misses::total 9393087 # number of ReadReq MSHR misses
1778system.cpu1.icache.demand_mshr_misses::cpu1.inst 9393087 # number of demand (read+write) MSHR misses
1779system.cpu1.icache.demand_mshr_misses::total 9393087 # number of demand (read+write) MSHR misses
1780system.cpu1.icache.overall_mshr_misses::cpu1.inst 9393087 # number of overall MSHR misses
1781system.cpu1.icache.overall_mshr_misses::total 9393087 # number of overall MSHR misses
1782system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 84210400586 # number of ReadReq MSHR miss cycles
1783system.cpu1.icache.ReadReq_mshr_miss_latency::total 84210400586 # number of ReadReq MSHR miss cycles
1784system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 84210400586 # number of demand (read+write) MSHR miss cycles
1785system.cpu1.icache.demand_mshr_miss_latency::total 84210400586 # number of demand (read+write) MSHR miss cycles
1786system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 84210400586 # number of overall MSHR miss cycles
1787system.cpu1.icache.overall_mshr_miss_latency::total 84210400586 # number of overall MSHR miss cycles
1788system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles
1789system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles
1790system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles
1791system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles
1792system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for ReadReq accesses
1793system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037718 # mshr miss rate for ReadReq accesses
1794system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for demand accesses
1795system.cpu1.icache.demand_mshr_miss_rate::total 0.037718 # mshr miss rate for demand accesses
1796system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037718 # mshr miss rate for overall accesses
1797system.cpu1.icache.overall_mshr_miss_rate::total 0.037718 # mshr miss rate for overall accesses
1798system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average ReadReq mshr miss latency
1799system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8965.146451 # average ReadReq mshr miss latency
1800system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency
1801system.cpu1.icache.demand_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency
1802system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8965.146451 # average overall mshr miss latency
1803system.cpu1.icache.overall_avg_mshr_miss_latency::total 8965.146451 # average overall mshr miss latency
1804system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1805system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1806system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1807system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1808system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1809system.cpu1.l2cache.prefetcher.num_hwpf_issued 7598599 # number of hwpf issued
1810system.cpu1.l2cache.prefetcher.pfIdentified 7600232 # number of prefetch candidates identified
1811system.cpu1.l2cache.prefetcher.pfBufferHit 1400 # number of redundant prefetches already in prefetch queue
1812system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1813system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1814system.cpu1.l2cache.prefetcher.pfSpanPage 976472 # number of prefetches not generated due to page crossing
1815system.cpu1.l2cache.tags.replacements 2525133 # number of replacements
1816system.cpu1.l2cache.tags.tagsinuse 13593.944555 # Cycle average of tags in use
1817system.cpu1.l2cache.tags.total_refs 15352366 # Total number of references to valid blocks.
1818system.cpu1.l2cache.tags.sampled_refs 2541314 # Sample count of references to valid blocks.
1819system.cpu1.l2cache.tags.avg_refs 6.041113 # Average number of references to valid blocks.
1820system.cpu1.l2cache.tags.warmup_cycle 9806300117000 # Cycle when the warmup percentage was hit.
1821system.cpu1.l2cache.tags.occ_blocks::writebacks 4972.841269 # Average occupied blocks per requestor
1822system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.331762 # Average occupied blocks per requestor
1823system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.569688 # Average occupied blocks per requestor
1824system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4463.050805 # Average occupied blocks per requestor
1825system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3225.843213 # Average occupied blocks per requestor
1826system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 763.307818 # Average occupied blocks per requestor
1827system.cpu1.l2cache.tags.occ_percent::writebacks 0.303518 # Average percentage of cache occupancy
1828system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004964 # Average percentage of cache occupancy
1829system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005345 # Average percentage of cache occupancy
1830system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.272403 # Average percentage of cache occupancy
1831system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.196890 # Average percentage of cache occupancy
1832system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046589 # Average percentage of cache occupancy
1833system.cpu1.l2cache.tags.occ_percent::total 0.829709 # Average percentage of cache occupancy
1834system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1470 # Occupied blocks per task id
1835system.cpu1.l2cache.tags.occ_task_id_blocks::1023 73 # Occupied blocks per task id
1836system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14638 # Occupied blocks per task id
1837system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id
1838system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id
1839system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id
1840system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 569 # Occupied blocks per task id
1841system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 22 # Occupied blocks per task id
1842system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 26 # Occupied blocks per task id
1843system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
1844system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
1845system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1158 # Occupied blocks per task id
1846system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id
1847system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5264 # Occupied blocks per task id
1848system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5426 # Occupied blocks per task id
1849system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.089722 # Percentage of cache occupancy per task id
1850system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004456 # Percentage of cache occupancy per task id
1851system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.893433 # Percentage of cache occupancy per task id
1852system.cpu1.l2cache.tags.tag_accesses 318573099 # Number of tag accesses
1853system.cpu1.l2cache.tags.data_accesses 318573099 # Number of data accesses
1854system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 537712 # number of ReadReq hits
1855system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159577 # number of ReadReq hits
1856system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8583648 # number of ReadReq hits
1857system.cpu1.l2cache.ReadReq_hits::cpu1.data 2948596 # number of ReadReq hits
1858system.cpu1.l2cache.ReadReq_hits::total 12229533 # number of ReadReq hits
1859system.cpu1.l2cache.Writeback_hits::writebacks 3506045 # number of Writeback hits
1860system.cpu1.l2cache.Writeback_hits::total 3506045 # number of Writeback hits
1861system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 188584 # number of WriteInvalidateReq hits
1862system.cpu1.l2cache.WriteInvalidateReq_hits::total 188584 # number of WriteInvalidateReq hits
1863system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 74085 # number of UpgradeReq hits
1864system.cpu1.l2cache.UpgradeReq_hits::total 74085 # number of UpgradeReq hits
1865system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41733 # number of SCUpgradeReq hits
1866system.cpu1.l2cache.SCUpgradeReq_hits::total 41733 # number of SCUpgradeReq hits
1867system.cpu1.l2cache.ReadExReq_hits::cpu1.data 900308 # number of ReadExReq hits
1868system.cpu1.l2cache.ReadExReq_hits::total 900308 # number of ReadExReq hits
1869system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 537712 # number of demand (read+write) hits
1870system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159577 # number of demand (read+write) hits
1871system.cpu1.l2cache.demand_hits::cpu1.inst 8583648 # number of demand (read+write) hits
1872system.cpu1.l2cache.demand_hits::cpu1.data 3848904 # number of demand (read+write) hits
1873system.cpu1.l2cache.demand_hits::total 13129841 # number of demand (read+write) hits
1874system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 537712 # number of overall hits
1875system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159577 # number of overall hits
1876system.cpu1.l2cache.overall_hits::cpu1.inst 8583648 # number of overall hits
1877system.cpu1.l2cache.overall_hits::cpu1.data 3848904 # number of overall hits
1878system.cpu1.l2cache.overall_hits::total 13129841 # number of overall hits
1879system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13252 # number of ReadReq misses
1880system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9078 # number of ReadReq misses
1881system.cpu1.l2cache.ReadReq_misses::cpu1.inst 809439 # number of ReadReq misses
1882system.cpu1.l2cache.ReadReq_misses::cpu1.data 1045283 # number of ReadReq misses
1883system.cpu1.l2cache.ReadReq_misses::total 1877052 # number of ReadReq misses
1884system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 263334 # number of WriteInvalidateReq misses
1885system.cpu1.l2cache.WriteInvalidateReq_misses::total 263334 # number of WriteInvalidateReq misses
1886system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141894 # number of UpgradeReq misses
1887system.cpu1.l2cache.UpgradeReq_misses::total 141894 # number of UpgradeReq misses
1888system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151971 # number of SCUpgradeReq misses
1889system.cpu1.l2cache.SCUpgradeReq_misses::total 151971 # number of SCUpgradeReq misses
1890system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses
1891system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
1892system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245370 # number of ReadExReq misses
1893system.cpu1.l2cache.ReadExReq_misses::total 245370 # number of ReadExReq misses
1894system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13252 # number of demand (read+write) misses
1895system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9078 # number of demand (read+write) misses
1896system.cpu1.l2cache.demand_misses::cpu1.inst 809439 # number of demand (read+write) misses
1897system.cpu1.l2cache.demand_misses::cpu1.data 1290653 # number of demand (read+write) misses
1898system.cpu1.l2cache.demand_misses::total 2122422 # number of demand (read+write) misses
1899system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13252 # number of overall misses
1900system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9078 # number of overall misses
1901system.cpu1.l2cache.overall_misses::cpu1.inst 809439 # number of overall misses
1902system.cpu1.l2cache.overall_misses::cpu1.data 1290653 # number of overall misses
1903system.cpu1.l2cache.overall_misses::total 2122422 # number of overall misses
1904system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 492724981 # number of ReadReq miss cycles
1905system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 392484013 # number of ReadReq miss cycles
1906system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 23676424280 # number of ReadReq miss cycles
1907system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34749867857 # number of ReadReq miss cycles
1908system.cpu1.l2cache.ReadReq_miss_latency::total 59311501131 # number of ReadReq miss cycles
1909system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 207047946 # number of WriteInvalidateReq miss cycles
1910system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 207047946 # number of WriteInvalidateReq miss cycles
1911system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3083845016 # number of UpgradeReq miss cycles
1912system.cpu1.l2cache.UpgradeReq_miss_latency::total 3083845016 # number of UpgradeReq miss cycles
1913system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3158531415 # number of SCUpgradeReq miss cycles
1914system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3158531415 # number of SCUpgradeReq miss cycles
1915system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2735500 # number of SCUpgradeFailReq miss cycles
1916system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2735500 # number of SCUpgradeFailReq miss cycles
1917system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10633257356 # number of ReadExReq miss cycles
1918system.cpu1.l2cache.ReadExReq_miss_latency::total 10633257356 # number of ReadExReq miss cycles
1919system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492724981 # number of demand (read+write) miss cycles
1920system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 392484013 # number of demand (read+write) miss cycles
1921system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23676424280 # number of demand (read+write) miss cycles
1922system.cpu1.l2cache.demand_miss_latency::cpu1.data 45383125213 # number of demand (read+write) miss cycles
1923system.cpu1.l2cache.demand_miss_latency::total 69944758487 # number of demand (read+write) miss cycles
1924system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 492724981 # number of overall miss cycles
1925system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 392484013 # number of overall miss cycles
1926system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23676424280 # number of overall miss cycles
1927system.cpu1.l2cache.overall_miss_latency::cpu1.data 45383125213 # number of overall miss cycles
1928system.cpu1.l2cache.overall_miss_latency::total 69944758487 # number of overall miss cycles
1929system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 550964 # number of ReadReq accesses(hits+misses)
1930system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 168655 # number of ReadReq accesses(hits+misses)
1931system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9393087 # number of ReadReq accesses(hits+misses)
1932system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3993879 # number of ReadReq accesses(hits+misses)
1933system.cpu1.l2cache.ReadReq_accesses::total 14106585 # number of ReadReq accesses(hits+misses)
1934system.cpu1.l2cache.Writeback_accesses::writebacks 3506045 # number of Writeback accesses(hits+misses)
1935system.cpu1.l2cache.Writeback_accesses::total 3506045 # number of Writeback accesses(hits+misses)
1936system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 451918 # number of WriteInvalidateReq accesses(hits+misses)
1937system.cpu1.l2cache.WriteInvalidateReq_accesses::total 451918 # number of WriteInvalidateReq accesses(hits+misses)
1938system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 215979 # number of UpgradeReq accesses(hits+misses)
1939system.cpu1.l2cache.UpgradeReq_accesses::total 215979 # number of UpgradeReq accesses(hits+misses)
1940system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193704 # number of SCUpgradeReq accesses(hits+misses)
1941system.cpu1.l2cache.SCUpgradeReq_accesses::total 193704 # number of SCUpgradeReq accesses(hits+misses)
1942system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
1943system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
1944system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1145678 # number of ReadExReq accesses(hits+misses)
1945system.cpu1.l2cache.ReadExReq_accesses::total 1145678 # number of ReadExReq accesses(hits+misses)
1946system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 550964 # number of demand (read+write) accesses
1947system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 168655 # number of demand (read+write) accesses
1948system.cpu1.l2cache.demand_accesses::cpu1.inst 9393087 # number of demand (read+write) accesses
1949system.cpu1.l2cache.demand_accesses::cpu1.data 5139557 # number of demand (read+write) accesses
1950system.cpu1.l2cache.demand_accesses::total 15252263 # number of demand (read+write) accesses
1951system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 550964 # number of overall (read+write) accesses
1952system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 168655 # number of overall (read+write) accesses
1953system.cpu1.l2cache.overall_accesses::cpu1.inst 9393087 # number of overall (read+write) accesses
1954system.cpu1.l2cache.overall_accesses::cpu1.data 5139557 # number of overall (read+write) accesses
1955system.cpu1.l2cache.overall_accesses::total 15252263 # number of overall (read+write) accesses
1956system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for ReadReq accesses
1957system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053826 # miss rate for ReadReq accesses
1958system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.086174 # miss rate for ReadReq accesses
1959system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.261721 # miss rate for ReadReq accesses
1960system.cpu1.l2cache.ReadReq_miss_rate::total 0.133062 # miss rate for ReadReq accesses
1961system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.582703 # miss rate for WriteInvalidateReq accesses
1962system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.582703 # miss rate for WriteInvalidateReq accesses
1963system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.656981 # miss rate for UpgradeReq accesses
1964system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.656981 # miss rate for UpgradeReq accesses
1965system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.784553 # miss rate for SCUpgradeReq accesses
1966system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784553 # miss rate for SCUpgradeReq accesses
1967system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1968system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1969system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.214170 # miss rate for ReadExReq accesses
1970system.cpu1.l2cache.ReadExReq_miss_rate::total 0.214170 # miss rate for ReadExReq accesses
1971system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for demand accesses
1972system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053826 # miss rate for demand accesses
1973system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.086174 # miss rate for demand accesses
1974system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.251121 # miss rate for demand accesses
1975system.cpu1.l2cache.demand_miss_rate::total 0.139155 # miss rate for demand accesses
1976system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024052 # miss rate for overall accesses
1977system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053826 # miss rate for overall accesses
1978system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.086174 # miss rate for overall accesses
1979system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.251121 # miss rate for overall accesses
1980system.cpu1.l2cache.overall_miss_rate::total 0.139155 # miss rate for overall accesses
1981system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average ReadReq miss latency
1982system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43234.634611 # average ReadReq miss latency
1983system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29250.412051 # average ReadReq miss latency
1984system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 33244.459019 # average ReadReq miss latency
1985system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31598.219512 # average ReadReq miss latency
1986system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 786.256032 # average WriteInvalidateReq miss latency
1987system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 786.256032 # average WriteInvalidateReq miss latency
1988system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21733.441978 # average UpgradeReq miss latency
1989system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21733.441978 # average UpgradeReq miss latency
1990system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20783.777267 # average SCUpgradeReq miss latency
1991system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20783.777267 # average SCUpgradeReq miss latency
1992system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 303944.444444 # average SCUpgradeFailReq miss latency
1993system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 303944.444444 # average SCUpgradeFailReq miss latency
1994system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43335.604825 # average ReadExReq miss latency
1995system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43335.604825 # average ReadExReq miss latency
1996system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average overall miss latency
1997system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43234.634611 # average overall miss latency
1998system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29250.412051 # average overall miss latency
1999system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35162.917696 # average overall miss latency
2000system.cpu1.l2cache.demand_avg_miss_latency::total 32955.160890 # average overall miss latency
2001system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37181.178765 # average overall miss latency
2002system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43234.634611 # average overall miss latency
2003system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29250.412051 # average overall miss latency
2004system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35162.917696 # average overall miss latency
2005system.cpu1.l2cache.overall_avg_miss_latency::total 32955.160890 # average overall miss latency
2006system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2007system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2008system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2009system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2010system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2011system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2012system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2013system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2014system.cpu1.l2cache.writebacks::writebacks 1067908 # number of writebacks
2015system.cpu1.l2cache.writebacks::total 1067908 # number of writebacks
2016system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
2017system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
2018system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 828 # number of ReadReq MSHR hits
2019system.cpu1.l2cache.ReadReq_mshr_hits::total 832 # number of ReadReq MSHR hits
2020system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 3 # number of WriteInvalidateReq MSHR hits
2021system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 3 # number of WriteInvalidateReq MSHR hits
2022system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7579 # number of ReadExReq MSHR hits
2023system.cpu1.l2cache.ReadExReq_mshr_hits::total 7579 # number of ReadExReq MSHR hits
2024system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
2025system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2026system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8407 # number of demand (read+write) MSHR hits
2027system.cpu1.l2cache.demand_mshr_hits::total 8411 # number of demand (read+write) MSHR hits
2028system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
2029system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2030system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8407 # number of overall MSHR hits
2031system.cpu1.l2cache.overall_mshr_hits::total 8411 # number of overall MSHR hits
2032system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13252 # number of ReadReq MSHR misses
2033system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9075 # number of ReadReq MSHR misses
2034system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 809438 # number of ReadReq MSHR misses
2035system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1044455 # number of ReadReq MSHR misses
2036system.cpu1.l2cache.ReadReq_mshr_misses::total 1876220 # number of ReadReq MSHR misses
2037system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 726748 # number of HardPFReq MSHR misses
2038system.cpu1.l2cache.HardPFReq_mshr_misses::total 726748 # number of HardPFReq MSHR misses
2039system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 263331 # number of WriteInvalidateReq MSHR misses
2040system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 263331 # number of WriteInvalidateReq MSHR misses
2041system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 141894 # number of UpgradeReq MSHR misses
2042system.cpu1.l2cache.UpgradeReq_mshr_misses::total 141894 # number of UpgradeReq MSHR misses
2043system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 151971 # number of SCUpgradeReq MSHR misses
2044system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151971 # number of SCUpgradeReq MSHR misses
2045system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses
2046system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
2047system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237791 # number of ReadExReq MSHR misses
2048system.cpu1.l2cache.ReadExReq_mshr_misses::total 237791 # number of ReadExReq MSHR misses
2049system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13252 # number of demand (read+write) MSHR misses
2050system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9075 # number of demand (read+write) MSHR misses
2051system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 809438 # number of demand (read+write) MSHR misses
2052system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1282246 # number of demand (read+write) MSHR misses
2053system.cpu1.l2cache.demand_mshr_misses::total 2114011 # number of demand (read+write) MSHR misses
2054system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13252 # number of overall MSHR misses
2055system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9075 # number of overall MSHR misses
2056system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 809438 # number of overall MSHR misses
2057system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1282246 # number of overall MSHR misses
2058system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 726748 # number of overall MSHR misses
2059system.cpu1.l2cache.overall_mshr_misses::total 2840759 # number of overall MSHR misses
2060system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of ReadReq MSHR miss cycles
2061system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 332680003 # number of ReadReq MSHR miss cycles
2062system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 18392391220 # number of ReadReq MSHR miss cycles
2063system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 27845262298 # number of ReadReq MSHR miss cycles
2064system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 46976181530 # number of ReadReq MSHR miss cycles
2065system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33709821360 # number of HardPFReq MSHR miss cycles
2066system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 33709821360 # number of HardPFReq MSHR miss cycles
2067system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8640486821 # number of WriteInvalidateReq MSHR miss cycles
2068system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8640486821 # number of WriteInvalidateReq MSHR miss cycles
2069system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2764991628 # number of UpgradeReq MSHR miss cycles
2070system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2764991628 # number of UpgradeReq MSHR miss cycles
2071system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2248670832 # number of SCUpgradeReq MSHR miss cycles
2072system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2248670832 # number of SCUpgradeReq MSHR miss cycles
2073system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2352000 # number of SCUpgradeFailReq MSHR miss cycles
2074system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2352000 # number of SCUpgradeFailReq MSHR miss cycles
2075system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8035534729 # number of ReadExReq MSHR miss cycles
2076system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8035534729 # number of ReadExReq MSHR miss cycles
2077system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of demand (read+write) MSHR miss cycles
2078system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 332680003 # number of demand (read+write) MSHR miss cycles
2079system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18392391220 # number of demand (read+write) MSHR miss cycles
2080system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35880797027 # number of demand (read+write) MSHR miss cycles
2081system.cpu1.l2cache.demand_mshr_miss_latency::total 55011716259 # number of demand (read+write) MSHR miss cycles
2082system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405848009 # number of overall MSHR miss cycles
2083system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 332680003 # number of overall MSHR miss cycles
2084system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18392391220 # number of overall MSHR miss cycles
2085system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35880797027 # number of overall MSHR miss cycles
2086system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33709821360 # number of overall MSHR miss cycles
2087system.cpu1.l2cache.overall_mshr_miss_latency::total 88721537619 # number of overall MSHR miss cycles
2088system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7360000 # number of ReadReq MSHR uncacheable cycles
2089system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 459163000 # number of ReadReq MSHR uncacheable cycles
2090system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 466523000 # number of ReadReq MSHR uncacheable cycles
2091system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 519410999 # number of WriteReq MSHR uncacheable cycles
2092system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 519410999 # number of WriteReq MSHR uncacheable cycles
2093system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7360000 # number of overall MSHR uncacheable cycles
2094system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 978573999 # number of overall MSHR uncacheable cycles
2095system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 985933999 # number of overall MSHR uncacheable cycles
2096system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for ReadReq accesses
2097system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for ReadReq accesses
2098system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for ReadReq accesses
2099system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.261514 # mshr miss rate for ReadReq accesses
2100system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133003 # mshr miss rate for ReadReq accesses
2101system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2102system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2103system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.582696 # mshr miss rate for WriteInvalidateReq accesses
2104system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.582696 # mshr miss rate for WriteInvalidateReq accesses
2105system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.656981 # mshr miss rate for UpgradeReq accesses
2106system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.656981 # mshr miss rate for UpgradeReq accesses
2107system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784553 # mshr miss rate for SCUpgradeReq accesses
2108system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784553 # mshr miss rate for SCUpgradeReq accesses
2109system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2110system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2111system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207555 # mshr miss rate for ReadExReq accesses
2112system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207555 # mshr miss rate for ReadExReq accesses
2113system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses
2114system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses
2115system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses
2116system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses
2117system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses
2118system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses
2119system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses
2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses
2121system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses
2122system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2123system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses
2124system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency
2125system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency
2126system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency
2129system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency
2130system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency
2131system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency
2132system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency
2133system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency
2134system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency
2135system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency
2136system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency
2137system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency
2138system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency
2139system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency
2140system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency
2141system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
2142system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
2144system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
2145system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency
2146system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
2147system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
2150system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency
2151system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency
2152system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2153system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2154system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2155system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2156system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2157system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2158system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2159system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2160system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2161system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution
2162system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution
2163system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution
2164system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution
2165system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution
2166system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution
2167system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution
2168system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution
2169system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution
2170system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution
2171system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution
2172system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution
2175system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution
2176system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes)
2177system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes)
2178system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes)
2179system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes)
2180system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes)
2181system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes)
2182system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes)
2183system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes)
2184system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes)
2185system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes)
2186system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count)
2187system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram
2188system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram
2189system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram
2190system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2191system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2192system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2193system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2194system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram
2195system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram
2196system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2197system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2198system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2199system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram
2200system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks)
2201system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2202system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks)
2203system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2204system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks)
2205system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2206system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks)
2207system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2208system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks)
2209system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2210system.cpu1.toL2Bus.respLayer3.occupancy 656138927 # Layer occupancy (ticks)
2211system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2212system.iobus.trans_dist::ReadReq 40316 # Transaction distribution
2213system.iobus.trans_dist::ReadResp 40316 # Transaction distribution
2214system.iobus.trans_dist::WriteReq 136601 # Transaction distribution
2215system.iobus.trans_dist::WriteResp 29873 # Transaction distribution
2216system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2217system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47648 # Packet count per connected master and slave (bytes)
2218system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2219system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2220system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2221system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2222system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2223system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2224system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2225system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2226system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2227system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2228system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2229system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2230system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2231system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2232system.iobus.pkt_count_system.bridge.master::total 122530 # Packet count per connected master and slave (bytes)
2233system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231224 # Packet count per connected master and slave (bytes)
2234system.iobus.pkt_count_system.realview.ide.dma::total 231224 # Packet count per connected master and slave (bytes)
2235system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2236system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2237system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes)
2238system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47668 # Cumulative packet size per connected master and slave (bytes)
2239system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2240system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2241system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2242system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2243system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2244system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2245system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2246system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2247system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2248system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2249system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2250system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2251system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2252system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2253system.iobus.pkt_size_system.bridge.master::total 155660 # Cumulative packet size per connected master and slave (bytes)
2254system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338912 # Cumulative packet size per connected master and slave (bytes)
2255system.iobus.pkt_size_system.realview.ide.dma::total 7338912 # Cumulative packet size per connected master and slave (bytes)
2256system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2257system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2258system.iobus.pkt_size::total 7496658 # Cumulative packet size per connected master and slave (bytes)
2259system.iobus.reqLayer0.occupancy 36180000 # Layer occupancy (ticks)
2260system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2261system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2262system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2263system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2264system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2265system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2266system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2267system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2268system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2269system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2270system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2271system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2272system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2273system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
2274system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2275system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
2276system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2277system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2278system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2279system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
2280system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2281system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2282system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2283system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2284system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2285system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2286system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2287system.iobus.reqLayer27.occupancy 607453407 # Layer occupancy (ticks)
2288system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2289system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2290system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2291system.iobus.respLayer0.occupancy 92660000 # Layer occupancy (ticks)
2292system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2293system.iobus.respLayer3.occupancy 148582123 # Layer occupancy (ticks)
2294system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2295system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
2296system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2297system.iocache.tags.replacements 115592 # number of replacements
2298system.iocache.tags.tagsinuse 11.295153 # Cycle average of tags in use
2299system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2300system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks.
2301system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2302system.iocache.tags.warmup_cycle 9129697263000 # Cycle when the warmup percentage was hit.
2303system.iocache.tags.occ_blocks::realview.ethernet 7.412327 # Average occupied blocks per requestor
2304system.iocache.tags.occ_blocks::realview.ide 3.882827 # Average occupied blocks per requestor
2305system.iocache.tags.occ_percent::realview.ethernet 0.463270 # Average percentage of cache occupancy
2306system.iocache.tags.occ_percent::realview.ide 0.242677 # Average percentage of cache occupancy
2307system.iocache.tags.occ_percent::total 0.705947 # Average percentage of cache occupancy
2308system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2309system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2310system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2311system.iocache.tags.tag_accesses 1040865 # Number of tag accesses
2312system.iocache.tags.data_accesses 1040865 # Number of data accesses
2313system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2314system.iocache.ReadReq_misses::realview.ide 8884 # number of ReadReq misses
2315system.iocache.ReadReq_misses::total 8921 # number of ReadReq misses
2316system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2317system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2318system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2319system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2320system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2321system.iocache.demand_misses::realview.ide 8884 # number of demand (read+write) misses
2322system.iocache.demand_misses::total 8924 # number of demand (read+write) misses
2323system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2324system.iocache.overall_misses::realview.ide 8884 # number of overall misses
2325system.iocache.overall_misses::total 8924 # number of overall misses
2326system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
2327system.iocache.ReadReq_miss_latency::realview.ide 1659251745 # number of ReadReq miss cycles
2328system.iocache.ReadReq_miss_latency::total 1664447245 # number of ReadReq miss cycles
2329system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2330system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2331system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19947928539 # number of WriteInvalidateReq miss cycles
2332system.iocache.WriteInvalidateReq_miss_latency::total 19947928539 # number of WriteInvalidateReq miss cycles
2333system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
2334system.iocache.demand_miss_latency::realview.ide 1659251745 # number of demand (read+write) miss cycles
2335system.iocache.demand_miss_latency::total 1664816245 # number of demand (read+write) miss cycles
2336system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
2337system.iocache.overall_miss_latency::realview.ide 1659251745 # number of overall miss cycles
2338system.iocache.overall_miss_latency::total 1664816245 # number of overall miss cycles
2339system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2340system.iocache.ReadReq_accesses::realview.ide 8884 # number of ReadReq accesses(hits+misses)
2341system.iocache.ReadReq_accesses::total 8921 # number of ReadReq accesses(hits+misses)
2342system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2343system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2344system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
2345system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
2346system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2347system.iocache.demand_accesses::realview.ide 8884 # number of demand (read+write) accesses
2348system.iocache.demand_accesses::total 8924 # number of demand (read+write) accesses
2349system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2350system.iocache.overall_accesses::realview.ide 8884 # number of overall (read+write) accesses
2351system.iocache.overall_accesses::total 8924 # number of overall (read+write) accesses
2352system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2353system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2354system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2355system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2356system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2357system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2358system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2359system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2360system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2361system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2362system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2363system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2364system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2365system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
2366system.iocache.ReadReq_avg_miss_latency::realview.ide 186768.544012 # average ReadReq miss latency
2367system.iocache.ReadReq_avg_miss_latency::total 186576.308149 # average ReadReq miss latency
2368system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2369system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2370system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186904.360046 # average WriteInvalidateReq miss latency
2371system.iocache.WriteInvalidateReq_avg_miss_latency::total 186904.360046 # average WriteInvalidateReq miss latency
2372system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2373system.iocache.demand_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency
2374system.iocache.demand_avg_miss_latency::total 186554.935567 # average overall miss latency
2375system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2376system.iocache.overall_avg_miss_latency::realview.ide 186768.544012 # average overall miss latency
2377system.iocache.overall_avg_miss_latency::total 186554.935567 # average overall miss latency
2378system.iocache.blocked_cycles::no_mshrs 112960 # number of cycles access was blocked
2379system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2380system.iocache.blocked::no_mshrs 16486 # number of cycles access was blocked
2381system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2382system.iocache.avg_blocked_cycles::no_mshrs 6.851874 # average number of cycles each access was blocked
2383system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2384system.iocache.fast_writes 0 # number of fast writes performed
2385system.iocache.cache_copies 0 # number of cache copies performed
2386system.iocache.writebacks::writebacks 106678 # number of writebacks
2387system.iocache.writebacks::total 106678 # number of writebacks
2388system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2389system.iocache.ReadReq_mshr_misses::realview.ide 8884 # number of ReadReq MSHR misses
2390system.iocache.ReadReq_mshr_misses::total 8921 # number of ReadReq MSHR misses
2391system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2392system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2393system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
2394system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
2395system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2396system.iocache.demand_mshr_misses::realview.ide 8884 # number of demand (read+write) MSHR misses
2397system.iocache.demand_mshr_misses::total 8924 # number of demand (read+write) MSHR misses
2398system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2399system.iocache.overall_mshr_misses::realview.ide 8884 # number of overall MSHR misses
2400system.iocache.overall_mshr_misses::total 8924 # number of overall MSHR misses
2401system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
2402system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196099891 # number of ReadReq MSHR miss cycles
2403system.iocache.ReadReq_mshr_miss_latency::total 1199370391 # number of ReadReq MSHR miss cycles
2404system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
2405system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
2406system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14397972639 # number of WriteInvalidateReq MSHR miss cycles
2407system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14397972639 # number of WriteInvalidateReq MSHR miss cycles
2408system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
2409system.iocache.demand_mshr_miss_latency::realview.ide 1196099891 # number of demand (read+write) MSHR miss cycles
2410system.iocache.demand_mshr_miss_latency::total 1199583391 # number of demand (read+write) MSHR miss cycles
2411system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
2412system.iocache.overall_mshr_miss_latency::realview.ide 1196099891 # number of overall MSHR miss cycles
2413system.iocache.overall_mshr_miss_latency::total 1199583391 # number of overall MSHR miss cycles
2414system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2415system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2416system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2417system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2418system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2419system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2420system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2421system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2422system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2423system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2424system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2425system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2426system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2427system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
2428system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 134635.287145 # average ReadReq mshr miss latency
2429system.iocache.ReadReq_avg_mshr_miss_latency::total 134443.491873 # average ReadReq mshr miss latency
2430system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
2431system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
2432system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134903.424022 # average WriteInvalidateReq mshr miss latency
2433system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134903.424022 # average WriteInvalidateReq mshr miss latency
2434system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2435system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency
2436system.iocache.demand_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency
2437system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2438system.iocache.overall_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency
2439system.iocache.overall_avg_mshr_miss_latency::total 134422.163940 # average overall mshr miss latency
2440system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2441system.l2c.tags.replacements 1488066 # number of replacements
2442system.l2c.tags.tagsinuse 64457.051863 # Cycle average of tags in use
2443system.l2c.tags.total_refs 5017316 # Total number of references to valid blocks.
2444system.l2c.tags.sampled_refs 1548603 # Sample count of references to valid blocks.
2445system.l2c.tags.avg_refs 3.239898 # Average number of references to valid blocks.
2446system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit.
2447system.l2c.tags.occ_blocks::writebacks 16300.231028 # Average occupied blocks per requestor
2448system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.590542 # Average occupied blocks per requestor
2449system.l2c.tags.occ_blocks::cpu0.itb.walker 5.410855 # Average occupied blocks per requestor
2450system.l2c.tags.occ_blocks::cpu0.inst 3923.984358 # Average occupied blocks per requestor
2451system.l2c.tags.occ_blocks::cpu0.data 5628.040249 # Average occupied blocks per requestor
2452system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3900.550479 # Average occupied blocks per requestor
2453system.l2c.tags.occ_blocks::cpu1.dtb.walker 368.152358 # Average occupied blocks per requestor
2454system.l2c.tags.occ_blocks::cpu1.itb.walker 516.465158 # Average occupied blocks per requestor
2455system.l2c.tags.occ_blocks::cpu1.inst 4442.350927 # Average occupied blocks per requestor
2456system.l2c.tags.occ_blocks::cpu1.data 11307.713496 # Average occupied blocks per requestor
2457system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 18045.562414 # Average occupied blocks per requestor
2458system.l2c.tags.occ_percent::writebacks 0.248722 # Average percentage of cache occupancy
2459system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000284 # Average percentage of cache occupancy
2460system.l2c.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy
2461system.l2c.tags.occ_percent::cpu0.inst 0.059875 # Average percentage of cache occupancy
2462system.l2c.tags.occ_percent::cpu0.data 0.085877 # Average percentage of cache occupancy
2463system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.059518 # Average percentage of cache occupancy
2464system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005618 # Average percentage of cache occupancy
2465system.l2c.tags.occ_percent::cpu1.itb.walker 0.007881 # Average percentage of cache occupancy
2466system.l2c.tags.occ_percent::cpu1.inst 0.067785 # Average percentage of cache occupancy
2467system.l2c.tags.occ_percent::cpu1.data 0.172542 # Average percentage of cache occupancy
2468system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.275353 # Average percentage of cache occupancy
2469system.l2c.tags.occ_percent::total 0.983537 # Average percentage of cache occupancy
2470system.l2c.tags.occ_task_id_blocks::1022 10439 # Occupied blocks per task id
2471system.l2c.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id
2472system.l2c.tags.occ_task_id_blocks::1024 49850 # Occupied blocks per task id
2473system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
2474system.l2c.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id
2475system.l2c.tags.age_task_id_blocks_1022::3 337 # Occupied blocks per task id
2476system.l2c.tags.age_task_id_blocks_1022::4 10018 # Occupied blocks per task id
2477system.l2c.tags.age_task_id_blocks_1023::4 248 # Occupied blocks per task id
2478system.l2c.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
2479system.l2c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id
2480system.l2c.tags.age_task_id_blocks_1024::2 1727 # Occupied blocks per task id
2481system.l2c.tags.age_task_id_blocks_1024::3 4981 # Occupied blocks per task id
2482system.l2c.tags.age_task_id_blocks_1024::4 42979 # Occupied blocks per task id
2483system.l2c.tags.occ_task_id_percent::1022 0.159286 # Percentage of cache occupancy per task id
2484system.l2c.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id
2485system.l2c.tags.occ_task_id_percent::1024 0.760651 # Percentage of cache occupancy per task id
2486system.l2c.tags.tag_accesses 65141561 # Number of tag accesses
2487system.l2c.tags.data_accesses 65141561 # Number of data accesses
2488system.l2c.ReadReq_hits::cpu0.dtb.walker 6849 # number of ReadReq hits
2489system.l2c.ReadReq_hits::cpu0.itb.walker 4798 # number of ReadReq hits
2490system.l2c.ReadReq_hits::cpu0.inst 687325 # number of ReadReq hits
2491system.l2c.ReadReq_hits::cpu0.data 588389 # number of ReadReq hits
2492system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 296114 # number of ReadReq hits
2493system.l2c.ReadReq_hits::cpu1.dtb.walker 6913 # number of ReadReq hits
2494system.l2c.ReadReq_hits::cpu1.itb.walker 4145 # number of ReadReq hits
2495system.l2c.ReadReq_hits::cpu1.inst 746877 # number of ReadReq hits
2496system.l2c.ReadReq_hits::cpu1.data 598329 # number of ReadReq hits
2497system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 312912 # number of ReadReq hits
2498system.l2c.ReadReq_hits::total 3252651 # number of ReadReq hits
2499system.l2c.Writeback_hits::writebacks 2487202 # number of Writeback hits
2500system.l2c.Writeback_hits::total 2487202 # number of Writeback hits
2501system.l2c.WriteInvalidateReq_hits::cpu0.data 134878 # number of WriteInvalidateReq hits
2502system.l2c.WriteInvalidateReq_hits::cpu1.data 131392 # number of WriteInvalidateReq hits
2503system.l2c.WriteInvalidateReq_hits::total 266270 # number of WriteInvalidateReq hits
2504system.l2c.UpgradeReq_hits::cpu0.data 30237 # number of UpgradeReq hits
2505system.l2c.UpgradeReq_hits::cpu1.data 30181 # number of UpgradeReq hits
2506system.l2c.UpgradeReq_hits::total 60418 # number of UpgradeReq hits
2507system.l2c.SCUpgradeReq_hits::cpu0.data 6187 # number of SCUpgradeReq hits
2508system.l2c.SCUpgradeReq_hits::cpu1.data 6142 # number of SCUpgradeReq hits
2509system.l2c.SCUpgradeReq_hits::total 12329 # number of SCUpgradeReq hits
2510system.l2c.ReadExReq_hits::cpu0.data 56549 # number of ReadExReq hits
2511system.l2c.ReadExReq_hits::cpu1.data 53204 # number of ReadExReq hits
2512system.l2c.ReadExReq_hits::total 109753 # number of ReadExReq hits
2513system.l2c.demand_hits::cpu0.dtb.walker 6849 # number of demand (read+write) hits
2514system.l2c.demand_hits::cpu0.itb.walker 4798 # number of demand (read+write) hits
2515system.l2c.demand_hits::cpu0.inst 687325 # number of demand (read+write) hits
2516system.l2c.demand_hits::cpu0.data 644938 # number of demand (read+write) hits
2517system.l2c.demand_hits::cpu0.l2cache.prefetcher 296114 # number of demand (read+write) hits
2518system.l2c.demand_hits::cpu1.dtb.walker 6913 # number of demand (read+write) hits
2519system.l2c.demand_hits::cpu1.itb.walker 4145 # number of demand (read+write) hits
2520system.l2c.demand_hits::cpu1.inst 746877 # number of demand (read+write) hits
2521system.l2c.demand_hits::cpu1.data 651533 # number of demand (read+write) hits
2522system.l2c.demand_hits::cpu1.l2cache.prefetcher 312912 # number of demand (read+write) hits
2523system.l2c.demand_hits::total 3362404 # number of demand (read+write) hits
2524system.l2c.overall_hits::cpu0.dtb.walker 6849 # number of overall hits
2525system.l2c.overall_hits::cpu0.itb.walker 4798 # number of overall hits
2526system.l2c.overall_hits::cpu0.inst 687325 # number of overall hits
2527system.l2c.overall_hits::cpu0.data 644938 # number of overall hits
2528system.l2c.overall_hits::cpu0.l2cache.prefetcher 296114 # number of overall hits
2529system.l2c.overall_hits::cpu1.dtb.walker 6913 # number of overall hits
2530system.l2c.overall_hits::cpu1.itb.walker 4145 # number of overall hits
2531system.l2c.overall_hits::cpu1.inst 746877 # number of overall hits
2532system.l2c.overall_hits::cpu1.data 651533 # number of overall hits
2533system.l2c.overall_hits::cpu1.l2cache.prefetcher 312912 # number of overall hits
2534system.l2c.overall_hits::total 3362404 # number of overall hits
2535system.l2c.ReadReq_misses::cpu0.dtb.walker 1673 # number of ReadReq misses
2536system.l2c.ReadReq_misses::cpu0.itb.walker 1224 # number of ReadReq misses
2537system.l2c.ReadReq_misses::cpu0.inst 69538 # number of ReadReq misses
2538system.l2c.ReadReq_misses::cpu0.data 125760 # number of ReadReq misses
2539system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 246479 # number of ReadReq misses
2540system.l2c.ReadReq_misses::cpu1.dtb.walker 2496 # number of ReadReq misses
2541system.l2c.ReadReq_misses::cpu1.itb.walker 2417 # number of ReadReq misses
2542system.l2c.ReadReq_misses::cpu1.inst 62560 # number of ReadReq misses
2543system.l2c.ReadReq_misses::cpu1.data 141194 # number of ReadReq misses
2544system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 226658 # number of ReadReq misses
2545system.l2c.ReadReq_misses::total 879999 # number of ReadReq misses
2546system.l2c.WriteInvalidateReq_misses::cpu0.data 439420 # number of WriteInvalidateReq misses
2547system.l2c.WriteInvalidateReq_misses::cpu1.data 123627 # number of WriteInvalidateReq misses
2548system.l2c.WriteInvalidateReq_misses::total 563047 # number of WriteInvalidateReq misses
2549system.l2c.UpgradeReq_misses::cpu0.data 45454 # number of UpgradeReq misses
2550system.l2c.UpgradeReq_misses::cpu1.data 42845 # number of UpgradeReq misses
2551system.l2c.UpgradeReq_misses::total 88299 # number of UpgradeReq misses
2552system.l2c.SCUpgradeReq_misses::cpu0.data 9151 # number of SCUpgradeReq misses
2553system.l2c.SCUpgradeReq_misses::cpu1.data 8719 # number of SCUpgradeReq misses
2554system.l2c.SCUpgradeReq_misses::total 17870 # number of SCUpgradeReq misses
2555system.l2c.ReadExReq_misses::cpu0.data 76776 # number of ReadExReq misses
2556system.l2c.ReadExReq_misses::cpu1.data 56017 # number of ReadExReq misses
2557system.l2c.ReadExReq_misses::total 132793 # number of ReadExReq misses
2558system.l2c.demand_misses::cpu0.dtb.walker 1673 # number of demand (read+write) misses
2559system.l2c.demand_misses::cpu0.itb.walker 1224 # number of demand (read+write) misses
2560system.l2c.demand_misses::cpu0.inst 69538 # number of demand (read+write) misses
2561system.l2c.demand_misses::cpu0.data 202536 # number of demand (read+write) misses
2562system.l2c.demand_misses::cpu0.l2cache.prefetcher 246479 # number of demand (read+write) misses
2563system.l2c.demand_misses::cpu1.dtb.walker 2496 # number of demand (read+write) misses
2564system.l2c.demand_misses::cpu1.itb.walker 2417 # number of demand (read+write) misses
2565system.l2c.demand_misses::cpu1.inst 62560 # number of demand (read+write) misses
2566system.l2c.demand_misses::cpu1.data 197211 # number of demand (read+write) misses
2567system.l2c.demand_misses::cpu1.l2cache.prefetcher 226658 # number of demand (read+write) misses
2568system.l2c.demand_misses::total 1012792 # number of demand (read+write) misses
2569system.l2c.overall_misses::cpu0.dtb.walker 1673 # number of overall misses
2570system.l2c.overall_misses::cpu0.itb.walker 1224 # number of overall misses
2571system.l2c.overall_misses::cpu0.inst 69538 # number of overall misses
2572system.l2c.overall_misses::cpu0.data 202536 # number of overall misses
2573system.l2c.overall_misses::cpu0.l2cache.prefetcher 246479 # number of overall misses
2574system.l2c.overall_misses::cpu1.dtb.walker 2496 # number of overall misses
2575system.l2c.overall_misses::cpu1.itb.walker 2417 # number of overall misses
2576system.l2c.overall_misses::cpu1.inst 62560 # number of overall misses
2577system.l2c.overall_misses::cpu1.data 197211 # number of overall misses
2578system.l2c.overall_misses::cpu1.l2cache.prefetcher 226658 # number of overall misses
2579system.l2c.overall_misses::total 1012792 # number of overall misses
2580system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 154004272 # number of ReadReq miss cycles
2581system.l2c.ReadReq_miss_latency::cpu0.itb.walker 114242270 # number of ReadReq miss cycles
2582system.l2c.ReadReq_miss_latency::cpu0.inst 5875477080 # number of ReadReq miss cycles
2583system.l2c.ReadReq_miss_latency::cpu0.data 11741177980 # number of ReadReq miss cycles
2584system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of ReadReq miss cycles
2585system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 221714757 # number of ReadReq miss cycles
2586system.l2c.ReadReq_miss_latency::cpu1.itb.walker 213708998 # number of ReadReq miss cycles
2587system.l2c.ReadReq_miss_latency::cpu1.inst 5282320946 # number of ReadReq miss cycles
2588system.l2c.ReadReq_miss_latency::cpu1.data 12643416993 # number of ReadReq miss cycles
2589system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of ReadReq miss cycles
2590system.l2c.ReadReq_miss_latency::total 98556487149 # number of ReadReq miss cycles
2591system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 54522296 # number of WriteInvalidateReq miss cycles
2592system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41107699 # number of WriteInvalidateReq miss cycles
2593system.l2c.WriteInvalidateReq_miss_latency::total 95629995 # number of WriteInvalidateReq miss cycles
2594system.l2c.UpgradeReq_miss_latency::cpu0.data 273262934 # number of UpgradeReq miss cycles
2595system.l2c.UpgradeReq_miss_latency::cpu1.data 266190062 # number of UpgradeReq miss cycles
2596system.l2c.UpgradeReq_miss_latency::total 539452996 # number of UpgradeReq miss cycles
2597system.l2c.SCUpgradeReq_miss_latency::cpu0.data 48096984 # number of SCUpgradeReq miss cycles
2598system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56198212 # number of SCUpgradeReq miss cycles
2599system.l2c.SCUpgradeReq_miss_latency::total 104295196 # number of SCUpgradeReq miss cycles
2600system.l2c.ReadExReq_miss_latency::cpu0.data 6908017996 # number of ReadExReq miss cycles
2601system.l2c.ReadExReq_miss_latency::cpu1.data 4749633793 # number of ReadExReq miss cycles
2602system.l2c.ReadExReq_miss_latency::total 11657651789 # number of ReadExReq miss cycles
2603system.l2c.demand_miss_latency::cpu0.dtb.walker 154004272 # number of demand (read+write) miss cycles
2604system.l2c.demand_miss_latency::cpu0.itb.walker 114242270 # number of demand (read+write) miss cycles
2605system.l2c.demand_miss_latency::cpu0.inst 5875477080 # number of demand (read+write) miss cycles
2606system.l2c.demand_miss_latency::cpu0.data 18649195976 # number of demand (read+write) miss cycles
2607system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of demand (read+write) miss cycles
2608system.l2c.demand_miss_latency::cpu1.dtb.walker 221714757 # number of demand (read+write) miss cycles
2609system.l2c.demand_miss_latency::cpu1.itb.walker 213708998 # number of demand (read+write) miss cycles
2610system.l2c.demand_miss_latency::cpu1.inst 5282320946 # number of demand (read+write) miss cycles
2611system.l2c.demand_miss_latency::cpu1.data 17393050786 # number of demand (read+write) miss cycles
2612system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of demand (read+write) miss cycles
2613system.l2c.demand_miss_latency::total 110214138938 # number of demand (read+write) miss cycles
2614system.l2c.overall_miss_latency::cpu0.dtb.walker 154004272 # number of overall miss cycles
2615system.l2c.overall_miss_latency::cpu0.itb.walker 114242270 # number of overall miss cycles
2616system.l2c.overall_miss_latency::cpu0.inst 5875477080 # number of overall miss cycles
2617system.l2c.overall_miss_latency::cpu0.data 18649195976 # number of overall miss cycles
2618system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33542362820 # number of overall miss cycles
2619system.l2c.overall_miss_latency::cpu1.dtb.walker 221714757 # number of overall miss cycles
2620system.l2c.overall_miss_latency::cpu1.itb.walker 213708998 # number of overall miss cycles
2621system.l2c.overall_miss_latency::cpu1.inst 5282320946 # number of overall miss cycles
2622system.l2c.overall_miss_latency::cpu1.data 17393050786 # number of overall miss cycles
2623system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 28768061033 # number of overall miss cycles
2624system.l2c.overall_miss_latency::total 110214138938 # number of overall miss cycles
2625system.l2c.ReadReq_accesses::cpu0.dtb.walker 8522 # number of ReadReq accesses(hits+misses)
2626system.l2c.ReadReq_accesses::cpu0.itb.walker 6022 # number of ReadReq accesses(hits+misses)
2627system.l2c.ReadReq_accesses::cpu0.inst 756863 # number of ReadReq accesses(hits+misses)
2628system.l2c.ReadReq_accesses::cpu0.data 714149 # number of ReadReq accesses(hits+misses)
2629system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 542593 # number of ReadReq accesses(hits+misses)
2630system.l2c.ReadReq_accesses::cpu1.dtb.walker 9409 # number of ReadReq accesses(hits+misses)
2631system.l2c.ReadReq_accesses::cpu1.itb.walker 6562 # number of ReadReq accesses(hits+misses)
2632system.l2c.ReadReq_accesses::cpu1.inst 809437 # number of ReadReq accesses(hits+misses)
2633system.l2c.ReadReq_accesses::cpu1.data 739523 # number of ReadReq accesses(hits+misses)
2634system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 539570 # number of ReadReq accesses(hits+misses)
2635system.l2c.ReadReq_accesses::total 4132650 # number of ReadReq accesses(hits+misses)
2636system.l2c.Writeback_accesses::writebacks 2487202 # number of Writeback accesses(hits+misses)
2637system.l2c.Writeback_accesses::total 2487202 # number of Writeback accesses(hits+misses)
2638system.l2c.WriteInvalidateReq_accesses::cpu0.data 574298 # number of WriteInvalidateReq accesses(hits+misses)
2639system.l2c.WriteInvalidateReq_accesses::cpu1.data 255019 # number of WriteInvalidateReq accesses(hits+misses)
2640system.l2c.WriteInvalidateReq_accesses::total 829317 # number of WriteInvalidateReq accesses(hits+misses)
2641system.l2c.UpgradeReq_accesses::cpu0.data 75691 # number of UpgradeReq accesses(hits+misses)
2642system.l2c.UpgradeReq_accesses::cpu1.data 73026 # number of UpgradeReq accesses(hits+misses)
2643system.l2c.UpgradeReq_accesses::total 148717 # number of UpgradeReq accesses(hits+misses)
2644system.l2c.SCUpgradeReq_accesses::cpu0.data 15338 # number of SCUpgradeReq accesses(hits+misses)
2645system.l2c.SCUpgradeReq_accesses::cpu1.data 14861 # number of SCUpgradeReq accesses(hits+misses)
2646system.l2c.SCUpgradeReq_accesses::total 30199 # number of SCUpgradeReq accesses(hits+misses)
2647system.l2c.ReadExReq_accesses::cpu0.data 133325 # number of ReadExReq accesses(hits+misses)
2648system.l2c.ReadExReq_accesses::cpu1.data 109221 # number of ReadExReq accesses(hits+misses)
2649system.l2c.ReadExReq_accesses::total 242546 # number of ReadExReq accesses(hits+misses)
2650system.l2c.demand_accesses::cpu0.dtb.walker 8522 # number of demand (read+write) accesses
2651system.l2c.demand_accesses::cpu0.itb.walker 6022 # number of demand (read+write) accesses
2652system.l2c.demand_accesses::cpu0.inst 756863 # number of demand (read+write) accesses
2653system.l2c.demand_accesses::cpu0.data 847474 # number of demand (read+write) accesses
2654system.l2c.demand_accesses::cpu0.l2cache.prefetcher 542593 # number of demand (read+write) accesses
2655system.l2c.demand_accesses::cpu1.dtb.walker 9409 # number of demand (read+write) accesses
2656system.l2c.demand_accesses::cpu1.itb.walker 6562 # number of demand (read+write) accesses
2657system.l2c.demand_accesses::cpu1.inst 809437 # number of demand (read+write) accesses
2658system.l2c.demand_accesses::cpu1.data 848744 # number of demand (read+write) accesses
2659system.l2c.demand_accesses::cpu1.l2cache.prefetcher 539570 # number of demand (read+write) accesses
2660system.l2c.demand_accesses::total 4375196 # number of demand (read+write) accesses
2661system.l2c.overall_accesses::cpu0.dtb.walker 8522 # number of overall (read+write) accesses
2662system.l2c.overall_accesses::cpu0.itb.walker 6022 # number of overall (read+write) accesses
2663system.l2c.overall_accesses::cpu0.inst 756863 # number of overall (read+write) accesses
2664system.l2c.overall_accesses::cpu0.data 847474 # number of overall (read+write) accesses
2665system.l2c.overall_accesses::cpu0.l2cache.prefetcher 542593 # number of overall (read+write) accesses
2666system.l2c.overall_accesses::cpu1.dtb.walker 9409 # number of overall (read+write) accesses
2667system.l2c.overall_accesses::cpu1.itb.walker 6562 # number of overall (read+write) accesses
2668system.l2c.overall_accesses::cpu1.inst 809437 # number of overall (read+write) accesses
2669system.l2c.overall_accesses::cpu1.data 848744 # number of overall (read+write) accesses
2670system.l2c.overall_accesses::cpu1.l2cache.prefetcher 539570 # number of overall (read+write) accesses
2671system.l2c.overall_accesses::total 4375196 # number of overall (read+write) accesses
2672system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for ReadReq accesses
2673system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.203255 # miss rate for ReadReq accesses
2674system.l2c.ReadReq_miss_rate::cpu0.inst 0.091877 # miss rate for ReadReq accesses
2675system.l2c.ReadReq_miss_rate::cpu0.data 0.176098 # miss rate for ReadReq accesses
2676system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for ReadReq accesses
2677system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for ReadReq accesses
2678system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.368333 # miss rate for ReadReq accesses
2679system.l2c.ReadReq_miss_rate::cpu1.inst 0.077288 # miss rate for ReadReq accesses
2680system.l2c.ReadReq_miss_rate::cpu1.data 0.190926 # miss rate for ReadReq accesses
2681system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for ReadReq accesses
2682system.l2c.ReadReq_miss_rate::total 0.212938 # miss rate for ReadReq accesses
2683system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.765143 # miss rate for WriteInvalidateReq accesses
2684system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.484776 # miss rate for WriteInvalidateReq accesses
2685system.l2c.WriteInvalidateReq_miss_rate::total 0.678929 # miss rate for WriteInvalidateReq accesses
2686system.l2c.UpgradeReq_miss_rate::cpu0.data 0.600521 # miss rate for UpgradeReq accesses
2687system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586709 # miss rate for UpgradeReq accesses
2688system.l2c.UpgradeReq_miss_rate::total 0.593738 # miss rate for UpgradeReq accesses
2689system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.596623 # miss rate for SCUpgradeReq accesses
2690system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.586703 # miss rate for SCUpgradeReq accesses
2691system.l2c.SCUpgradeReq_miss_rate::total 0.591741 # miss rate for SCUpgradeReq accesses
2692system.l2c.ReadExReq_miss_rate::cpu0.data 0.575856 # miss rate for ReadExReq accesses
2693system.l2c.ReadExReq_miss_rate::cpu1.data 0.512878 # miss rate for ReadExReq accesses
2694system.l2c.ReadExReq_miss_rate::total 0.547496 # miss rate for ReadExReq accesses
2695system.l2c.demand_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for demand accesses
2696system.l2c.demand_miss_rate::cpu0.itb.walker 0.203255 # miss rate for demand accesses
2697system.l2c.demand_miss_rate::cpu0.inst 0.091877 # miss rate for demand accesses
2698system.l2c.demand_miss_rate::cpu0.data 0.238988 # miss rate for demand accesses
2699system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for demand accesses
2700system.l2c.demand_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for demand accesses
2701system.l2c.demand_miss_rate::cpu1.itb.walker 0.368333 # miss rate for demand accesses
2702system.l2c.demand_miss_rate::cpu1.inst 0.077288 # miss rate for demand accesses
2703system.l2c.demand_miss_rate::cpu1.data 0.232356 # miss rate for demand accesses
2704system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for demand accesses
2705system.l2c.demand_miss_rate::total 0.231485 # miss rate for demand accesses
2706system.l2c.overall_miss_rate::cpu0.dtb.walker 0.196315 # miss rate for overall accesses
2707system.l2c.overall_miss_rate::cpu0.itb.walker 0.203255 # miss rate for overall accesses
2708system.l2c.overall_miss_rate::cpu0.inst 0.091877 # miss rate for overall accesses
2709system.l2c.overall_miss_rate::cpu0.data 0.238988 # miss rate for overall accesses
2710system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.454261 # miss rate for overall accesses
2711system.l2c.overall_miss_rate::cpu1.dtb.walker 0.265278 # miss rate for overall accesses
2712system.l2c.overall_miss_rate::cpu1.itb.walker 0.368333 # miss rate for overall accesses
2713system.l2c.overall_miss_rate::cpu1.inst 0.077288 # miss rate for overall accesses
2714system.l2c.overall_miss_rate::cpu1.data 0.232356 # miss rate for overall accesses
2715system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.420072 # miss rate for overall accesses
2716system.l2c.overall_miss_rate::total 0.231485 # miss rate for overall accesses
2717system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average ReadReq miss latency
2718system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93335.187908 # average ReadReq miss latency
2719system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84493.040927 # average ReadReq miss latency
2720system.l2c.ReadReq_avg_miss_latency::cpu0.data 93361.784192 # average ReadReq miss latency
2721system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average ReadReq miss latency
2722system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average ReadReq miss latency
2723system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88419.113777 # average ReadReq miss latency
2724system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84436.076503 # average ReadReq miss latency
2725system.l2c.ReadReq_avg_miss_latency::cpu1.data 89546.418353 # average ReadReq miss latency
2726system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average ReadReq miss latency
2727system.l2c.ReadReq_avg_miss_latency::total 111996.135392 # average ReadReq miss latency
2728system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 124.077866 # average WriteInvalidateReq miss latency
2729system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 332.513925 # average WriteInvalidateReq miss latency
2730system.l2c.WriteInvalidateReq_avg_miss_latency::total 169.843716 # average WriteInvalidateReq miss latency
2731system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6011.856690 # average UpgradeReq miss latency
2732system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6212.861757 # average UpgradeReq miss latency
2733system.l2c.UpgradeReq_avg_miss_latency::total 6109.389642 # average UpgradeReq miss latency
2734system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5255.926565 # average SCUpgradeReq miss latency
2735system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6445.488244 # average SCUpgradeReq miss latency
2736system.l2c.SCUpgradeReq_avg_miss_latency::total 5836.328819 # average SCUpgradeReq miss latency
2737system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89976.268574 # average ReadExReq miss latency
2738system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84789.149597 # average ReadExReq miss latency
2739system.l2c.ReadExReq_avg_miss_latency::total 87788.149895 # average ReadExReq miss latency
2740system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average overall miss latency
2741system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93335.187908 # average overall miss latency
2742system.l2c.demand_avg_miss_latency::cpu0.inst 84493.040927 # average overall miss latency
2743system.l2c.demand_avg_miss_latency::cpu0.data 92078.425445 # average overall miss latency
2744system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average overall miss latency
2745system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average overall miss latency
2746system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88419.113777 # average overall miss latency
2747system.l2c.demand_avg_miss_latency::cpu1.inst 84436.076503 # average overall miss latency
2748system.l2c.demand_avg_miss_latency::cpu1.data 88195.135089 # average overall miss latency
2749system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average overall miss latency
2750system.l2c.demand_avg_miss_latency::total 108822.086804 # average overall miss latency
2751system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92052.762702 # average overall miss latency
2752system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93335.187908 # average overall miss latency
2753system.l2c.overall_avg_miss_latency::cpu0.inst 84493.040927 # average overall miss latency
2754system.l2c.overall_avg_miss_latency::cpu0.data 92078.425445 # average overall miss latency
2755system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136086.087740 # average overall miss latency
2756system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88828.027644 # average overall miss latency
2757system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88419.113777 # average overall miss latency
2758system.l2c.overall_avg_miss_latency::cpu1.inst 84436.076503 # average overall miss latency
2759system.l2c.overall_avg_miss_latency::cpu1.data 88195.135089 # average overall miss latency
2760system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 126922.769251 # average overall miss latency
2761system.l2c.overall_avg_miss_latency::total 108822.086804 # average overall miss latency
2762system.l2c.blocked_cycles::no_mshrs 2541 # number of cycles access was blocked
2763system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2764system.l2c.blocked::no_mshrs 29 # number of cycles access was blocked
2765system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2766system.l2c.avg_blocked_cycles::no_mshrs 87.620690 # average number of cycles each access was blocked
2767system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2768system.l2c.fast_writes 0 # number of fast writes performed
2769system.l2c.cache_copies 0 # number of cache copies performed
2770system.l2c.writebacks::writebacks 1136176 # number of writebacks
2771system.l2c.writebacks::total 1136176 # number of writebacks
2772system.l2c.ReadReq_mshr_hits::cpu0.inst 233 # number of ReadReq MSHR hits
2773system.l2c.ReadReq_mshr_hits::cpu0.data 34 # number of ReadReq MSHR hits
2774system.l2c.ReadReq_mshr_hits::cpu1.inst 216 # number of ReadReq MSHR hits
2775system.l2c.ReadReq_mshr_hits::cpu1.data 19 # number of ReadReq MSHR hits
2776system.l2c.ReadReq_mshr_hits::total 502 # number of ReadReq MSHR hits
2777system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits
2778system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
2779system.l2c.demand_mshr_hits::cpu0.inst 233 # number of demand (read+write) MSHR hits
2780system.l2c.demand_mshr_hits::cpu0.data 35 # number of demand (read+write) MSHR hits
2781system.l2c.demand_mshr_hits::cpu1.inst 216 # number of demand (read+write) MSHR hits
2782system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits
2783system.l2c.demand_mshr_hits::total 503 # number of demand (read+write) MSHR hits
2784system.l2c.overall_mshr_hits::cpu0.inst 233 # number of overall MSHR hits
2785system.l2c.overall_mshr_hits::cpu0.data 35 # number of overall MSHR hits
2786system.l2c.overall_mshr_hits::cpu1.inst 216 # number of overall MSHR hits
2787system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits
2788system.l2c.overall_mshr_hits::total 503 # number of overall MSHR hits
2789system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1673 # number of ReadReq MSHR misses
2790system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1224 # number of ReadReq MSHR misses
2791system.l2c.ReadReq_mshr_misses::cpu0.inst 69305 # number of ReadReq MSHR misses
2792system.l2c.ReadReq_mshr_misses::cpu0.data 125726 # number of ReadReq MSHR misses
2793system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of ReadReq MSHR misses
2794system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2496 # number of ReadReq MSHR misses
2795system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2417 # number of ReadReq MSHR misses
2796system.l2c.ReadReq_mshr_misses::cpu1.inst 62344 # number of ReadReq MSHR misses
2797system.l2c.ReadReq_mshr_misses::cpu1.data 141175 # number of ReadReq MSHR misses
2798system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of ReadReq MSHR misses
2799system.l2c.ReadReq_mshr_misses::total 879497 # number of ReadReq MSHR misses
2800system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 439420 # number of WriteInvalidateReq MSHR misses
2801system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 123627 # number of WriteInvalidateReq MSHR misses
2802system.l2c.WriteInvalidateReq_mshr_misses::total 563047 # number of WriteInvalidateReq MSHR misses
2803system.l2c.UpgradeReq_mshr_misses::cpu0.data 45454 # number of UpgradeReq MSHR misses
2804system.l2c.UpgradeReq_mshr_misses::cpu1.data 42845 # number of UpgradeReq MSHR misses
2805system.l2c.UpgradeReq_mshr_misses::total 88299 # number of UpgradeReq MSHR misses
2806system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9151 # number of SCUpgradeReq MSHR misses
2807system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8719 # number of SCUpgradeReq MSHR misses
2808system.l2c.SCUpgradeReq_mshr_misses::total 17870 # number of SCUpgradeReq MSHR misses
2809system.l2c.ReadExReq_mshr_misses::cpu0.data 76775 # number of ReadExReq MSHR misses
2810system.l2c.ReadExReq_mshr_misses::cpu1.data 56017 # number of ReadExReq MSHR misses
2811system.l2c.ReadExReq_mshr_misses::total 132792 # number of ReadExReq MSHR misses
2812system.l2c.demand_mshr_misses::cpu0.dtb.walker 1673 # number of demand (read+write) MSHR misses
2813system.l2c.demand_mshr_misses::cpu0.itb.walker 1224 # number of demand (read+write) MSHR misses
2814system.l2c.demand_mshr_misses::cpu0.inst 69305 # number of demand (read+write) MSHR misses
2815system.l2c.demand_mshr_misses::cpu0.data 202501 # number of demand (read+write) MSHR misses
2816system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of demand (read+write) MSHR misses
2817system.l2c.demand_mshr_misses::cpu1.dtb.walker 2496 # number of demand (read+write) MSHR misses
2818system.l2c.demand_mshr_misses::cpu1.itb.walker 2417 # number of demand (read+write) MSHR misses
2819system.l2c.demand_mshr_misses::cpu1.inst 62344 # number of demand (read+write) MSHR misses
2820system.l2c.demand_mshr_misses::cpu1.data 197192 # number of demand (read+write) MSHR misses
2821system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of demand (read+write) MSHR misses
2822system.l2c.demand_mshr_misses::total 1012289 # number of demand (read+write) MSHR misses
2823system.l2c.overall_mshr_misses::cpu0.dtb.walker 1673 # number of overall MSHR misses
2824system.l2c.overall_mshr_misses::cpu0.itb.walker 1224 # number of overall MSHR misses
2825system.l2c.overall_mshr_misses::cpu0.inst 69305 # number of overall MSHR misses
2826system.l2c.overall_mshr_misses::cpu0.data 202501 # number of overall MSHR misses
2827system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 246479 # number of overall MSHR misses
2828system.l2c.overall_mshr_misses::cpu1.dtb.walker 2496 # number of overall MSHR misses
2829system.l2c.overall_mshr_misses::cpu1.itb.walker 2417 # number of overall MSHR misses
2830system.l2c.overall_mshr_misses::cpu1.inst 62344 # number of overall MSHR misses
2831system.l2c.overall_mshr_misses::cpu1.data 197192 # number of overall MSHR misses
2832system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 226658 # number of overall MSHR misses
2833system.l2c.overall_mshr_misses::total 1012289 # number of overall MSHR misses
2834system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of ReadReq MSHR miss cycles
2835system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 98791728 # number of ReadReq MSHR miss cycles
2836system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4989728170 # number of ReadReq MSHR miss cycles
2837system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10164730770 # number of ReadReq MSHR miss cycles
2838system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of ReadReq MSHR miss cycles
2839system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of ReadReq MSHR miss cycles
2840system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 183250000 # number of ReadReq MSHR miss cycles
2841system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 4483732804 # number of ReadReq MSHR miss cycles
2842system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10872787757 # number of ReadReq MSHR miss cycles
2843system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of ReadReq MSHR miss cycles
2844system.l2c.ReadReq_mshr_miss_latency::total 87613531131 # number of ReadReq MSHR miss cycles
2845system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 14757449705 # number of WriteInvalidateReq MSHR miss cycles
2846system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3963940301 # number of WriteInvalidateReq MSHR miss cycles
2847system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18721390006 # number of WriteInvalidateReq MSHR miss cycles
2848system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 810939663 # number of UpgradeReq MSHR miss cycles
2849system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 762507595 # number of UpgradeReq MSHR miss cycles
2850system.l2c.UpgradeReq_mshr_miss_latency::total 1573447258 # number of UpgradeReq MSHR miss cycles
2851system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 163438118 # number of SCUpgradeReq MSHR miss cycles
2852system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 155376174 # number of SCUpgradeReq MSHR miss cycles
2853system.l2c.SCUpgradeReq_mshr_miss_latency::total 318814292 # number of SCUpgradeReq MSHR miss cycles
2854system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5948577254 # number of ReadExReq MSHR miss cycles
2855system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4049329707 # number of ReadExReq MSHR miss cycles
2856system.l2c.ReadExReq_mshr_miss_latency::total 9997906961 # number of ReadExReq MSHR miss cycles
2857system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of demand (read+write) MSHR miss cycles
2858system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 98791728 # number of demand (read+write) MSHR miss cycles
2859system.l2c.demand_mshr_miss_latency::cpu0.inst 4989728170 # number of demand (read+write) MSHR miss cycles
2860system.l2c.demand_mshr_miss_latency::cpu0.data 16113308024 # number of demand (read+write) MSHR miss cycles
2861system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of demand (read+write) MSHR miss cycles
2862system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of demand (read+write) MSHR miss cycles
2863system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 183250000 # number of demand (read+write) MSHR miss cycles
2864system.l2c.demand_mshr_miss_latency::cpu1.inst 4483732804 # number of demand (read+write) MSHR miss cycles
2865system.l2c.demand_mshr_miss_latency::cpu1.data 14922117464 # number of demand (read+write) MSHR miss cycles
2866system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of demand (read+write) MSHR miss cycles
2867system.l2c.demand_mshr_miss_latency::total 97611438092 # number of demand (read+write) MSHR miss cycles
2868system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 132900230 # number of overall MSHR miss cycles
2869system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 98791728 # number of overall MSHR miss cycles
2870system.l2c.overall_mshr_miss_latency::cpu0.inst 4989728170 # number of overall MSHR miss cycles
2871system.l2c.overall_mshr_miss_latency::cpu0.data 16113308024 # number of overall MSHR miss cycles
2872system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30516558464 # number of overall MSHR miss cycles
2873system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 190282243 # number of overall MSHR miss cycles
2874system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 183250000 # number of overall MSHR miss cycles
2875system.l2c.overall_mshr_miss_latency::cpu1.inst 4483732804 # number of overall MSHR miss cycles
2876system.l2c.overall_mshr_miss_latency::cpu1.data 14922117464 # number of overall MSHR miss cycles
2877system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25980768965 # number of overall MSHR miss cycles
2878system.l2c.overall_mshr_miss_latency::total 97611438092 # number of overall MSHR miss cycles
2879system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles
2880system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5006572250 # number of ReadReq MSHR uncacheable cycles
2881system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5293500 # number of ReadReq MSHR uncacheable cycles
2882system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 361466500 # number of ReadReq MSHR uncacheable cycles
2883system.l2c.ReadReq_mshr_uncacheable_latency::total 8561345000 # number of ReadReq MSHR uncacheable cycles
2884system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4837026001 # number of WriteReq MSHR uncacheable cycles
2885system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 427260001 # number of WriteReq MSHR uncacheable cycles
2886system.l2c.WriteReq_mshr_uncacheable_latency::total 5264286002 # number of WriteReq MSHR uncacheable cycles
2887system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles
2888system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9843598251 # number of overall MSHR uncacheable cycles
2889system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5293500 # number of overall MSHR uncacheable cycles
2890system.l2c.overall_mshr_uncacheable_latency::cpu1.data 788726501 # number of overall MSHR uncacheable cycles
2891system.l2c.overall_mshr_uncacheable_latency::total 13825631002 # number of overall MSHR uncacheable cycles
2892system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for ReadReq accesses
2893system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for ReadReq accesses
2894system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for ReadReq accesses
2895system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.176050 # mshr miss rate for ReadReq accesses
2896system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for ReadReq accesses
2897system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for ReadReq accesses
2898system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for ReadReq accesses
2899system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for ReadReq accesses
2900system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.190900 # mshr miss rate for ReadReq accesses
2901system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for ReadReq accesses
2902system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses
2903system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses
2904system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses
2905system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses
2906system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses
2907system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses
2908system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses
2909system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses
2910system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses
2911system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses
2912system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses
2913system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses
2914system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses
2915system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses
2916system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses
2917system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses
2918system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses
2919system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses
2920system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses
2921system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses
2922system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses
2923system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses
2924system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses
2925system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses
2926system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses
2927system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses
2928system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses
2929system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses
2930system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses
2931system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses
2932system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses
2933system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses
2934system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses
2935system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses
2936system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses
2937system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency
2938system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency
2939system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency
2940system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency
2941system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency
2942system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency
2943system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency
2944system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency
2945system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency
2946system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency
2947system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency
2948system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency
2949system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency
2950system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency
2951system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency
2952system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency
2953system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency
2954system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency
2955system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency
2956system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency
2957system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency
2958system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency
2959system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency
2960system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
2961system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
2962system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
2963system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
2964system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
2965system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
2966system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
2967system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
2968system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
2969system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
2970system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
2971system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
2972system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
2973system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
2974system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
2975system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
2976system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
2977system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
2978system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
2979system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
2980system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
2981system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
2982system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
2983system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
2984system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2985system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2986system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2987system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
2988system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2989system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2990system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
2991system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
2992system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2993system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2994system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2995system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2996system.membus.trans_dist::ReadReq 979077 # Transaction distribution
2997system.membus.trans_dist::ReadResp 979077 # Transaction distribution
2998system.membus.trans_dist::WriteReq 38187 # Transaction distribution
2999system.membus.trans_dist::WriteResp 38187 # Transaction distribution
3000system.membus.trans_dist::Writeback 1242854 # Transaction distribution
3001system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution
3002system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution
3003system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution
3004system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution
3005system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution
3006system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
3007system.membus.trans_dist::ReadExReq 145453 # Transaction distribution
3008system.membus.trans_dist::ReadExResp 128623 # Transaction distribution
3009system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes)
3010system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3011system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes)
3012system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes)
3013system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes)
3014system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes)
3015system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes)
3016system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes)
3017system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes)
3018system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3019system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes)
3020system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes)
3021system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes)
3022system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes)
3023system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes)
3024system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes)
3025system.membus.snoops 622043 # Total snoops (count)
3026system.membus.snoop_fanout::samples 3659684 # Request fanout histogram
3027system.membus.snoop_fanout::mean 1 # Request fanout histogram
3028system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3029system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3030system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3031system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram
3032system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3033system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3034system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3035system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3036system.membus.snoop_fanout::total 3659684 # Request fanout histogram
3037system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks)
3038system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3039system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
3040system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3041system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks)
3042system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3043system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks)
3044system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3045system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks)
3046system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3047system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks)
3048system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3049system.realview.ethernet.txBytes 966 # Bytes Transmitted
3050system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3051system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3052system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3053system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3054system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3055system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3083system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3084system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3085system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3086system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3087system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3088system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3089system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3090system.realview.ethernet.droppedPackets 0 # number of packets dropped
3091system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution
3092system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution
3093system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution
3094system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution
3095system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution
3096system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution
3097system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution
3098system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution
3099system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution
3100system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution
3101system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution
3102system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
3103system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution
3104system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution
3105system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes)
3106system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes)
3107system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes)
3108system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes)
3109system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes)
3110system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes)
3111system.toL2Bus.snoops 1618057 # Total snoops (count)
3112system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram
3113system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram
3114system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram
3115system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3116system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3117system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram
3118system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram
3119system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3120system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3121system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3122system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram
3123system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks)
3124system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3125system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks)
3126system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3127system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks)
3128system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3129system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks)
3130system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3131
3132---------- End Simulation Statistics ----------