1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.349475 # Number of seconds simulated
4sim_ticks 47349475204500 # Number of ticks simulated
5final_tick 47349475204500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 170024 # Simulator instruction rate (inst/s)
8host_op_rate 200007 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9521770968 # Simulator tick rate (ticks/s)
10host_mem_usage 827688 # Number of bytes of host memory used
11host_seconds 4972.76 # Real time elapsed on the host
12sim_insts 845490438 # Number of instructions simulated
13sim_ops 994586036 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.ide 457024 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 242432 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 409152 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 13269720 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 28432512 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 254656 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 419648 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 10291040 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 23441792 # Number of bytes read from this memory
25system.physmem.bytes_read::total 77217976 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 3825664 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 566400 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 4392064 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 33722560 # Number of bytes written to this memory
30system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.inst 56250828 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.inst 43534148 # Number of bytes written to this memory
33system.physmem.bytes_written::total 140338128 # Number of bytes written to this memory
34system.physmem.num_reads::realview.ide 7141 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.dtb.walker 3788 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 6393 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 207361 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 444258 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.dtb.walker 3979 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.itb.walker 6557 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.inst 160812 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.l2cache.prefetcher 366278 # Number of read requests responded to by this memory
43system.physmem.num_reads::total 1206567 # Number of read requests responded to by this memory
44system.physmem.num_writes::writebacks 526915 # Number of write requests responded to by this memory
45system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.inst 881196 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.inst 680222 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 2195061 # Number of write requests responded to by this memory
49system.physmem.bw_read::realview.ide 9652 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.dtb.walker 5120 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.itb.walker 8641 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.inst 280251 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.l2cache.prefetcher 600482 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.dtb.walker 5378 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.itb.walker 8863 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.inst 217342 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.l2cache.prefetcher 495080 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::total 1630810 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::cpu0.inst 80796 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu1.inst 11962 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::total 92758 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_write::writebacks 712206 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::realview.ide 144259 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.inst 1187993 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.inst 919422 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 2963879 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 712206 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::realview.ide 153911 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.dtb.walker 5120 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.itb.walker 8641 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.inst 1468243 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.l2cache.prefetcher 600482 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.dtb.walker 5378 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.itb.walker 8863 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.inst 1136764 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.l2cache.prefetcher 495080 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::total 4594689 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.readReqs 1206567 # Number of read requests accepted
79system.physmem.writeReqs 2195061 # Number of write requests accepted
80system.physmem.readBursts 1206567 # Number of DRAM read bursts, including those serviced by the write queue
81system.physmem.writeBursts 2195061 # Number of DRAM write bursts, including those merged in the write queue
82system.physmem.bytesReadDRAM 76928704 # Total number of bytes read from DRAM
83system.physmem.bytesReadWrQ 291584 # Total number of bytes read from write queue
84system.physmem.bytesWritten 135133184 # Total number of bytes written to DRAM
85system.physmem.bytesReadSys 77217976 # Total read bytes from the system interface side
86system.physmem.bytesWrittenSys 140338128 # Total written bytes from the system interface side
87system.physmem.servicedByWrQ 4556 # Number of DRAM read bursts serviced by the write queue
88system.physmem.mergedWrBursts 83588 # Number of DRAM write bursts merged with an existing one
89system.physmem.neitherReadNorWriteReqs 93227 # Number of requests that are neither read nor write
90system.physmem.perBankRdBursts::0 68916 # Per bank write bursts
91system.physmem.perBankRdBursts::1 78372 # Per bank write bursts
92system.physmem.perBankRdBursts::2 66961 # Per bank write bursts
93system.physmem.perBankRdBursts::3 74483 # Per bank write bursts
94system.physmem.perBankRdBursts::4 67860 # Per bank write bursts
95system.physmem.perBankRdBursts::5 84994 # Per bank write bursts
96system.physmem.perBankRdBursts::6 78873 # Per bank write bursts
97system.physmem.perBankRdBursts::7 74831 # Per bank write bursts
98system.physmem.perBankRdBursts::8 70689 # Per bank write bursts
99system.physmem.perBankRdBursts::9 121049 # Per bank write bursts
100system.physmem.perBankRdBursts::10 55712 # Per bank write bursts
101system.physmem.perBankRdBursts::11 71204 # Per bank write bursts
102system.physmem.perBankRdBursts::12 68805 # Per bank write bursts
103system.physmem.perBankRdBursts::13 80552 # Per bank write bursts
104system.physmem.perBankRdBursts::14 71313 # Per bank write bursts
105system.physmem.perBankRdBursts::15 67397 # Per bank write bursts
106system.physmem.perBankWrBursts::0 131295 # Per bank write bursts
107system.physmem.perBankWrBursts::1 120115 # Per bank write bursts
108system.physmem.perBankWrBursts::2 136218 # Per bank write bursts
109system.physmem.perBankWrBursts::3 122111 # Per bank write bursts
110system.physmem.perBankWrBursts::4 136290 # Per bank write bursts
111system.physmem.perBankWrBursts::5 134780 # Per bank write bursts
112system.physmem.perBankWrBursts::6 183921 # Per bank write bursts
113system.physmem.perBankWrBursts::7 113990 # Per bank write bursts
114system.physmem.perBankWrBursts::8 112648 # Per bank write bursts
115system.physmem.perBankWrBursts::9 120303 # Per bank write bursts
116system.physmem.perBankWrBursts::10 105255 # Per bank write bursts
117system.physmem.perBankWrBursts::11 150368 # Per bank write bursts
118system.physmem.perBankWrBursts::12 133266 # Per bank write bursts
119system.physmem.perBankWrBursts::13 132701 # Per bank write bursts
120system.physmem.perBankWrBursts::14 112511 # Per bank write bursts
121system.physmem.perBankWrBursts::15 165684 # Per bank write bursts
122system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
123system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
124system.physmem.totGap 47349473266500 # Total gap between requests
125system.physmem.readPktSize::0 0 # Read request sizes (log2)
126system.physmem.readPktSize::1 0 # Read request sizes (log2)
127system.physmem.readPktSize::2 0 # Read request sizes (log2)
128system.physmem.readPktSize::3 37 # Read request sizes (log2)
129system.physmem.readPktSize::4 5 # Read request sizes (log2)
130system.physmem.readPktSize::5 0 # Read request sizes (log2)
131system.physmem.readPktSize::6 1206525 # Read request sizes (log2)
132system.physmem.writePktSize::0 0 # Write request sizes (log2)
133system.physmem.writePktSize::1 0 # Write request sizes (log2)
134system.physmem.writePktSize::2 2 # Write request sizes (log2)
135system.physmem.writePktSize::3 2601 # Write request sizes (log2)
136system.physmem.writePktSize::4 0 # Write request sizes (log2)
137system.physmem.writePktSize::5 0 # Write request sizes (log2)
138system.physmem.writePktSize::6 2192458 # Write request sizes (log2)
139system.physmem.rdQLenPdf::0 701586 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::1 159041 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::2 78388 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::3 62534 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::4 48409 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::5 42357 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::6 36825 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::7 30566 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::8 24739 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::9 6356 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::10 3319 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::11 2365 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::12 1772 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::13 1348 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::14 953 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::15 724 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::17 212 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::18 134 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::19 92 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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178system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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180system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::15 77454 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::16 97715 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::17 98472 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::18 108608 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::19 137758 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::20 125184 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::21 127483 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::22 141417 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::23 129468 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::24 120366 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::25 126014 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::26 120082 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::27 115005 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::28 123737 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::29 112481 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::30 110136 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::31 106316 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::32 102758 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::33 5440 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::34 4456 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::35 3538 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::36 2946 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::37 2503 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::39 1740 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::40 1473 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::41 1128 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::42 896 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::43 630 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::44 501 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::46 392 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::47 367 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::48 336 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::49 298 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::50 282 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::51 248 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::55 156 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::59 48 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::61 21 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see
235system.physmem.bytesPerActivate::samples 691339 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::mean 306.739519 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::gmean 163.472793 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::stdev 357.323128 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::0-127 329714 47.69% 47.69% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::128-255 128094 18.53% 66.22% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::256-383 46159 6.68% 72.90% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::384-511 24419 3.53% 76.43% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::512-639 20272 2.93% 79.36% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::640-767 13585 1.97% 81.33% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::768-895 10457 1.51% 82.84% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::896-1023 11430 1.65% 84.49% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::1024-1151 107209 15.51% 100.00% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::total 691339 # Bytes accessed per row activation
249system.physmem.rdPerTurnAround::samples 99075 # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::mean 12.132152 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::stdev 222.564559 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::0-2047 99072 100.00% 100.00% # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::28672-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::total 99075 # Reads before turning the bus around for writes
257system.physmem.wrPerTurnAround::samples 99075 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::mean 21.311693 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::gmean 20.731664 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::stdev 6.258880 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::16-19 33791 34.11% 34.11% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::20-23 48957 49.41% 83.52% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::24-27 10331 10.43% 93.95% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::28-31 2038 2.06% 96.01% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::32-35 1546 1.56% 97.57% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::36-39 746 0.75% 98.32% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::40-43 511 0.52% 98.83% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::44-47 316 0.32% 99.15% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::48-51 116 0.12% 99.27% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::52-55 38 0.04% 99.31% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::56-59 31 0.03% 99.34% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::60-63 20 0.02% 99.36% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::64-67 438 0.44% 99.80% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::68-71 35 0.04% 99.84% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::72-75 39 0.04% 99.88% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::76-79 38 0.04% 99.92% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::80-83 24 0.02% 99.94% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::88-91 2 0.00% 99.94% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::92-95 1 0.00% 99.95% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::96-99 10 0.01% 99.96% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::104-107 7 0.01% 99.96% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::108-111 4 0.00% 99.97% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::112-115 3 0.00% 99.97% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::116-119 3 0.00% 99.97% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::128-131 17 0.02% 99.99% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::132-135 3 0.00% 99.99% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::total 99075 # Writes before turning the bus around for reads
293system.physmem.totQLat 32464480274 # Total ticks spent queuing
294system.physmem.totMemAccLat 55002186524 # Total ticks spent from burst creation until serviced by the DRAM
295system.physmem.totBusLat 6010055000 # Total ticks spent in databus transfers
296system.physmem.avgQLat 27008.47 # Average queueing delay per DRAM burst
297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
298system.physmem.avgMemAccLat 45758.47 # Average memory access latency per DRAM burst
299system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s
300system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s
301system.physmem.avgRdBWSys 1.63 # Average system read bandwidth in MiByte/s
302system.physmem.avgWrBWSys 2.96 # Average system write bandwidth in MiByte/s
303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
304system.physmem.busUtil 0.03 # Data bus utilization in percentage
305system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
306system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
307system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
308system.physmem.avgWrQLen 23.37 # Average write queue length when enqueuing
309system.physmem.readRowHits 944165 # Number of row buffer hits during reads
310system.physmem.writeRowHits 1677959 # Number of row buffer hits during writes
311system.physmem.readRowHitRate 78.55 # Row buffer hit rate for reads
312system.physmem.writeRowHitRate 79.47 # Row buffer hit rate for writes
313system.physmem.avgGap 13919650.61 # Average gap between requests
314system.physmem.pageHitRate 79.13 # Row buffer hit rate, read and write combined
315system.physmem.memoryStateTime::IDLE 45391806829500 # Time in different power states
316system.physmem.memoryStateTime::REF 1581102900000 # Time in different power states
317system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
318system.physmem.memoryStateTime::ACT 376561525500 # Time in different power states
319system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
320system.physmem.actEnergy::0 2682083880 # Energy for activate commands per rank (pJ)
321system.physmem.actEnergy::1 2544438960 # Energy for activate commands per rank (pJ)
322system.physmem.preEnergy::0 1463438625 # Energy for precharge commands per rank (pJ)
323system.physmem.preEnergy::1 1388334750 # Energy for precharge commands per rank (pJ)
324system.physmem.readEnergy::0 4643184000 # Energy for read commands per rank (pJ)
325system.physmem.readEnergy::1 4732392600 # Energy for read commands per rank (pJ)
326system.physmem.writeEnergy::0 6990105600 # Energy for write commands per rank (pJ)
327system.physmem.writeEnergy::1 6692129280 # Energy for write commands per rank (pJ)
328system.physmem.refreshEnergy::0 3092637272400 # Energy for refresh commands per rank (pJ)
329system.physmem.refreshEnergy::1 3092637272400 # Energy for refresh commands per rank (pJ)
330system.physmem.actBackEnergy::0 1220178523320 # Energy for active background per rank (pJ)
331system.physmem.actBackEnergy::1 1215644323230 # Energy for active background per rank (pJ)
332system.physmem.preBackEnergy::0 27339350706750 # Energy for precharge background per rank (pJ)
333system.physmem.preBackEnergy::1 27343328075250 # Energy for precharge background per rank (pJ)
334system.physmem.totalEnergy::0 31667945314575 # Total energy per rank (pJ)
335system.physmem.totalEnergy::1 31666966966470 # Total energy per rank (pJ)
336system.physmem.averagePower::0 668.813072 # Core power per rank (mW)
337system.physmem.averagePower::1 668.792410 # Core power per rank (mW)
338system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory
339system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory
340system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
341system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
342system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
343system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
344system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory
345system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
346system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
347system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s)
348system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
349system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
350system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
351system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s)
354system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
355system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
356system.membus.trans_dist::ReadReq 1114990 # Transaction distribution
357system.membus.trans_dist::ReadResp 1114990 # Transaction distribution
358system.membus.trans_dist::WriteReq 37937 # Transaction distribution
359system.membus.trans_dist::WriteResp 37937 # Transaction distribution
360system.membus.trans_dist::Writeback 526915 # Transaction distribution
361system.membus.trans_dist::WriteInvalidateReq 1665543 # Transaction distribution
362system.membus.trans_dist::WriteInvalidateResp 1665543 # Transaction distribution
363system.membus.trans_dist::UpgradeReq 343558 # Transaction distribution
364system.membus.trans_dist::SCUpgradeReq 290459 # Transaction distribution
365system.membus.trans_dist::UpgradeResp 93233 # Transaction distribution
366system.membus.trans_dist::ReadExReq 145423 # Transaction distribution
367system.membus.trans_dist::ReadExResp 131308 # Transaction distribution
368system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122918 # Packet count per connected master and slave (bytes)
369system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
370system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 23584 # Packet count per connected master and slave (bytes)
371system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6789962 # Packet count per connected master and slave (bytes)
372system.membus.pkt_count_system.l2c.mem_side::total 6936516 # Packet count per connected master and slave (bytes)
373system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229526 # Packet count per connected master and slave (bytes)
374system.membus.pkt_count_system.iocache.mem_side::total 229526 # Packet count per connected master and slave (bytes)
375system.membus.pkt_count::total 7166042 # Packet count per connected master and slave (bytes)
376system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156048 # Cumulative packet size per connected master and slave (bytes)
377system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
378system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 47168 # Cumulative packet size per connected master and slave (bytes)
379system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210268488 # Cumulative packet size per connected master and slave (bytes)
380system.membus.pkt_size_system.l2c.mem_side::total 210473028 # Cumulative packet size per connected master and slave (bytes)
381system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7287616 # Cumulative packet size per connected master and slave (bytes)
382system.membus.pkt_size_system.iocache.mem_side::total 7287616 # Cumulative packet size per connected master and slave (bytes)
383system.membus.pkt_size::total 217760644 # Cumulative packet size per connected master and slave (bytes)
384system.membus.snoops 556693 # Total snoops (count)
385system.membus.snoop_fanout::samples 3996553 # Request fanout histogram
386system.membus.snoop_fanout::mean 1 # Request fanout histogram
387system.membus.snoop_fanout::stdev 0 # Request fanout histogram
388system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
389system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
390system.membus.snoop_fanout::1 3996553 100.00% 100.00% # Request fanout histogram
391system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
392system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
393system.membus.snoop_fanout::min_value 1 # Request fanout histogram
394system.membus.snoop_fanout::max_value 1 # Request fanout histogram
395system.membus.snoop_fanout::total 3996553 # Request fanout histogram
396system.membus.reqLayer0.occupancy 106711482 # Layer occupancy (ticks)
397system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
398system.membus.reqLayer1.occupancy 35984 # Layer occupancy (ticks)
399system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
400system.membus.reqLayer2.occupancy 20060995 # Layer occupancy (ticks)
401system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
402system.membus.reqLayer5.occupancy 21791270978 # Layer occupancy (ticks)
403system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
404system.membus.respLayer2.occupancy 13392760110 # Layer occupancy (ticks)
405system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
406system.membus.respLayer3.occupancy 187374753 # Layer occupancy (ticks)
407system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
408system.cpu_clk_domain.clock 500 # Clock period in ticks
409system.l2c.tags.replacements 893379 # number of replacements
410system.l2c.tags.tagsinuse 64139.353797 # Cycle average of tags in use
411system.l2c.tags.total_refs 6866398 # Total number of references to valid blocks.
412system.l2c.tags.sampled_refs 953433 # Sample count of references to valid blocks.
413system.l2c.tags.avg_refs 7.201762 # Average number of references to valid blocks.
414system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
415system.l2c.tags.occ_blocks::writebacks 10411.534254 # Average occupied blocks per requestor
416system.l2c.tags.occ_blocks::cpu0.dtb.walker 170.665758 # Average occupied blocks per requestor
417system.l2c.tags.occ_blocks::cpu0.itb.walker 236.653363 # Average occupied blocks per requestor
418system.l2c.tags.occ_blocks::cpu0.inst 5522.014615 # Average occupied blocks per requestor
419system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 25703.497535 # Average occupied blocks per requestor
420system.l2c.tags.occ_blocks::cpu1.dtb.walker 145.004713 # Average occupied blocks per requestor
421system.l2c.tags.occ_blocks::cpu1.itb.walker 188.005532 # Average occupied blocks per requestor
422system.l2c.tags.occ_blocks::cpu1.inst 6322.307070 # Average occupied blocks per requestor
423system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 15439.670958 # Average occupied blocks per requestor
424system.l2c.tags.occ_percent::writebacks 0.158867 # Average percentage of cache occupancy
425system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002604 # Average percentage of cache occupancy
426system.l2c.tags.occ_percent::cpu0.itb.walker 0.003611 # Average percentage of cache occupancy
427system.l2c.tags.occ_percent::cpu0.inst 0.084259 # Average percentage of cache occupancy
428system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.392204 # Average percentage of cache occupancy
429system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002213 # Average percentage of cache occupancy
430system.l2c.tags.occ_percent::cpu1.itb.walker 0.002869 # Average percentage of cache occupancy
431system.l2c.tags.occ_percent::cpu1.inst 0.096471 # Average percentage of cache occupancy
432system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.235591 # Average percentage of cache occupancy
433system.l2c.tags.occ_percent::total 0.978689 # Average percentage of cache occupancy
434system.l2c.tags.occ_task_id_blocks::1022 36012 # Occupied blocks per task id
435system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id
436system.l2c.tags.occ_task_id_blocks::1024 23782 # Occupied blocks per task id
437system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
438system.l2c.tags.age_task_id_blocks_1022::1 41 # Occupied blocks per task id
439system.l2c.tags.age_task_id_blocks_1022::2 716 # Occupied blocks per task id
440system.l2c.tags.age_task_id_blocks_1022::3 1957 # Occupied blocks per task id
441system.l2c.tags.age_task_id_blocks_1022::4 33290 # Occupied blocks per task id
442system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
443system.l2c.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id
444system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
445system.l2c.tags.age_task_id_blocks_1023::3 51 # Occupied blocks per task id
446system.l2c.tags.age_task_id_blocks_1023::4 190 # Occupied blocks per task id
447system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id
448system.l2c.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id
449system.l2c.tags.age_task_id_blocks_1024::2 1450 # Occupied blocks per task id
450system.l2c.tags.age_task_id_blocks_1024::3 3907 # Occupied blocks per task id
451system.l2c.tags.age_task_id_blocks_1024::4 18298 # Occupied blocks per task id
452system.l2c.tags.occ_task_id_percent::1022 0.549500 # Percentage of cache occupancy per task id
453system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id
454system.l2c.tags.occ_task_id_percent::1024 0.362885 # Percentage of cache occupancy per task id
455system.l2c.tags.tag_accesses 80317062 # Number of tag accesses
456system.l2c.tags.data_accesses 80317062 # Number of data accesses
457system.l2c.ReadReq_hits::cpu0.dtb.walker 7070 # number of ReadReq hits
458system.l2c.ReadReq_hits::cpu0.itb.walker 4466 # number of ReadReq hits
459system.l2c.ReadReq_hits::cpu0.inst 557041 # number of ReadReq hits
460system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2033838 # number of ReadReq hits
461system.l2c.ReadReq_hits::cpu1.dtb.walker 7318 # number of ReadReq hits
462system.l2c.ReadReq_hits::cpu1.itb.walker 4580 # number of ReadReq hits
463system.l2c.ReadReq_hits::cpu1.inst 521752 # number of ReadReq hits
464system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1881001 # number of ReadReq hits
465system.l2c.ReadReq_hits::total 5017066 # number of ReadReq hits
466system.l2c.Writeback_hits::writebacks 1844732 # number of Writeback hits
467system.l2c.Writeback_hits::total 1844732 # number of Writeback hits
468system.l2c.UpgradeReq_hits::cpu0.inst 30097 # number of UpgradeReq hits
469system.l2c.UpgradeReq_hits::cpu1.inst 27244 # number of UpgradeReq hits
470system.l2c.UpgradeReq_hits::total 57341 # number of UpgradeReq hits
471system.l2c.SCUpgradeReq_hits::cpu0.inst 7329 # number of SCUpgradeReq hits
472system.l2c.SCUpgradeReq_hits::cpu1.inst 7124 # number of SCUpgradeReq hits
473system.l2c.SCUpgradeReq_hits::total 14453 # number of SCUpgradeReq hits
474system.l2c.ReadExReq_hits::cpu0.inst 51408 # number of ReadExReq hits
475system.l2c.ReadExReq_hits::cpu1.inst 52005 # number of ReadExReq hits
476system.l2c.ReadExReq_hits::total 103413 # number of ReadExReq hits
477system.l2c.demand_hits::cpu0.dtb.walker 7070 # number of demand (read+write) hits
478system.l2c.demand_hits::cpu0.itb.walker 4466 # number of demand (read+write) hits
479system.l2c.demand_hits::cpu0.inst 608449 # number of demand (read+write) hits
480system.l2c.demand_hits::cpu0.l2cache.prefetcher 2033838 # number of demand (read+write) hits
481system.l2c.demand_hits::cpu1.dtb.walker 7318 # number of demand (read+write) hits
482system.l2c.demand_hits::cpu1.itb.walker 4580 # number of demand (read+write) hits
483system.l2c.demand_hits::cpu1.inst 573757 # number of demand (read+write) hits
484system.l2c.demand_hits::cpu1.l2cache.prefetcher 1881001 # number of demand (read+write) hits
485system.l2c.demand_hits::total 5120479 # number of demand (read+write) hits
486system.l2c.overall_hits::cpu0.dtb.walker 7070 # number of overall hits
487system.l2c.overall_hits::cpu0.itb.walker 4466 # number of overall hits
488system.l2c.overall_hits::cpu0.inst 608449 # number of overall hits
489system.l2c.overall_hits::cpu0.l2cache.prefetcher 2033838 # number of overall hits
490system.l2c.overall_hits::cpu1.dtb.walker 7318 # number of overall hits
491system.l2c.overall_hits::cpu1.itb.walker 4580 # number of overall hits
492system.l2c.overall_hits::cpu1.inst 573757 # number of overall hits
493system.l2c.overall_hits::cpu1.l2cache.prefetcher 1881001 # number of overall hits
494system.l2c.overall_hits::total 5120479 # number of overall hits
495system.l2c.ReadReq_misses::cpu0.dtb.walker 3788 # number of ReadReq misses
496system.l2c.ReadReq_misses::cpu0.itb.walker 6393 # number of ReadReq misses
497system.l2c.ReadReq_misses::cpu0.inst 87512 # number of ReadReq misses
498system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 444466 # number of ReadReq misses
499system.l2c.ReadReq_misses::cpu1.dtb.walker 3979 # number of ReadReq misses
500system.l2c.ReadReq_misses::cpu1.itb.walker 6557 # number of ReadReq misses
501system.l2c.ReadReq_misses::cpu1.inst 97026 # number of ReadReq misses
502system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 366468 # number of ReadReq misses
503system.l2c.ReadReq_misses::total 1016189 # number of ReadReq misses
504system.l2c.UpgradeReq_misses::cpu0.inst 36620 # number of UpgradeReq misses
505system.l2c.UpgradeReq_misses::cpu1.inst 34601 # number of UpgradeReq misses
506system.l2c.UpgradeReq_misses::total 71221 # number of UpgradeReq misses
507system.l2c.SCUpgradeReq_misses::cpu0.inst 9478 # number of SCUpgradeReq misses
508system.l2c.SCUpgradeReq_misses::cpu1.inst 8512 # number of SCUpgradeReq misses
509system.l2c.SCUpgradeReq_misses::total 17990 # number of SCUpgradeReq misses
510system.l2c.ReadExReq_misses::cpu0.inst 69660 # number of ReadExReq misses
511system.l2c.ReadExReq_misses::cpu1.inst 65667 # number of ReadExReq misses
512system.l2c.ReadExReq_misses::total 135327 # number of ReadExReq misses
513system.l2c.demand_misses::cpu0.dtb.walker 3788 # number of demand (read+write) misses
514system.l2c.demand_misses::cpu0.itb.walker 6393 # number of demand (read+write) misses
515system.l2c.demand_misses::cpu0.inst 157172 # number of demand (read+write) misses
516system.l2c.demand_misses::cpu0.l2cache.prefetcher 444466 # number of demand (read+write) misses
517system.l2c.demand_misses::cpu1.dtb.walker 3979 # number of demand (read+write) misses
518system.l2c.demand_misses::cpu1.itb.walker 6557 # number of demand (read+write) misses
519system.l2c.demand_misses::cpu1.inst 162693 # number of demand (read+write) misses
520system.l2c.demand_misses::cpu1.l2cache.prefetcher 366468 # number of demand (read+write) misses
521system.l2c.demand_misses::total 1151516 # number of demand (read+write) misses
522system.l2c.overall_misses::cpu0.dtb.walker 3788 # number of overall misses
523system.l2c.overall_misses::cpu0.itb.walker 6393 # number of overall misses
524system.l2c.overall_misses::cpu0.inst 157172 # number of overall misses
525system.l2c.overall_misses::cpu0.l2cache.prefetcher 444466 # number of overall misses
526system.l2c.overall_misses::cpu1.dtb.walker 3979 # number of overall misses
527system.l2c.overall_misses::cpu1.itb.walker 6557 # number of overall misses
528system.l2c.overall_misses::cpu1.inst 162693 # number of overall misses
529system.l2c.overall_misses::cpu1.l2cache.prefetcher 366468 # number of overall misses
530system.l2c.overall_misses::total 1151516 # number of overall misses
531system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 295641239 # number of ReadReq miss cycles
532system.l2c.ReadReq_miss_latency::cpu0.itb.walker 507564744 # number of ReadReq miss cycles
533system.l2c.ReadReq_miss_latency::cpu0.inst 6935191428 # number of ReadReq miss cycles
534system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of ReadReq miss cycles
535system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 312400496 # number of ReadReq miss cycles
536system.l2c.ReadReq_miss_latency::cpu1.itb.walker 512318742 # number of ReadReq miss cycles
537system.l2c.ReadReq_miss_latency::cpu1.inst 7688372365 # number of ReadReq miss cycles
538system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of ReadReq miss cycles
539system.l2c.ReadReq_miss_latency::total 99681339970 # number of ReadReq miss cycles
540system.l2c.UpgradeReq_miss_latency::cpu0.inst 177719564 # number of UpgradeReq miss cycles
541system.l2c.UpgradeReq_miss_latency::cpu1.inst 161535756 # number of UpgradeReq miss cycles
542system.l2c.UpgradeReq_miss_latency::total 339255320 # number of UpgradeReq miss cycles
543system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 49426933 # number of SCUpgradeReq miss cycles
544system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 49799411 # number of SCUpgradeReq miss cycles
545system.l2c.SCUpgradeReq_miss_latency::total 99226344 # number of SCUpgradeReq miss cycles
546system.l2c.ReadExReq_miss_latency::cpu0.inst 5124274653 # number of ReadExReq miss cycles
547system.l2c.ReadExReq_miss_latency::cpu1.inst 4787449538 # number of ReadExReq miss cycles
548system.l2c.ReadExReq_miss_latency::total 9911724191 # number of ReadExReq miss cycles
549system.l2c.demand_miss_latency::cpu0.dtb.walker 295641239 # number of demand (read+write) miss cycles
550system.l2c.demand_miss_latency::cpu0.itb.walker 507564744 # number of demand (read+write) miss cycles
551system.l2c.demand_miss_latency::cpu0.inst 12059466081 # number of demand (read+write) miss cycles
552system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of demand (read+write) miss cycles
553system.l2c.demand_miss_latency::cpu1.dtb.walker 312400496 # number of demand (read+write) miss cycles
554system.l2c.demand_miss_latency::cpu1.itb.walker 512318742 # number of demand (read+write) miss cycles
555system.l2c.demand_miss_latency::cpu1.inst 12475821903 # number of demand (read+write) miss cycles
556system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of demand (read+write) miss cycles
557system.l2c.demand_miss_latency::total 109593064161 # number of demand (read+write) miss cycles
558system.l2c.overall_miss_latency::cpu0.dtb.walker 295641239 # number of overall miss cycles
559system.l2c.overall_miss_latency::cpu0.itb.walker 507564744 # number of overall miss cycles
560system.l2c.overall_miss_latency::cpu0.inst 12059466081 # number of overall miss cycles
561system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 45326284922 # number of overall miss cycles
562system.l2c.overall_miss_latency::cpu1.dtb.walker 312400496 # number of overall miss cycles
563system.l2c.overall_miss_latency::cpu1.itb.walker 512318742 # number of overall miss cycles
564system.l2c.overall_miss_latency::cpu1.inst 12475821903 # number of overall miss cycles
565system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 38103566034 # number of overall miss cycles
566system.l2c.overall_miss_latency::total 109593064161 # number of overall miss cycles
567system.l2c.ReadReq_accesses::cpu0.dtb.walker 10858 # number of ReadReq accesses(hits+misses)
568system.l2c.ReadReq_accesses::cpu0.itb.walker 10859 # number of ReadReq accesses(hits+misses)
569system.l2c.ReadReq_accesses::cpu0.inst 644553 # number of ReadReq accesses(hits+misses)
570system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2478304 # number of ReadReq accesses(hits+misses)
571system.l2c.ReadReq_accesses::cpu1.dtb.walker 11297 # number of ReadReq accesses(hits+misses)
572system.l2c.ReadReq_accesses::cpu1.itb.walker 11137 # number of ReadReq accesses(hits+misses)
573system.l2c.ReadReq_accesses::cpu1.inst 618778 # number of ReadReq accesses(hits+misses)
574system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2247469 # number of ReadReq accesses(hits+misses)
575system.l2c.ReadReq_accesses::total 6033255 # number of ReadReq accesses(hits+misses)
576system.l2c.Writeback_accesses::writebacks 1844732 # number of Writeback accesses(hits+misses)
577system.l2c.Writeback_accesses::total 1844732 # number of Writeback accesses(hits+misses)
578system.l2c.UpgradeReq_accesses::cpu0.inst 66717 # number of UpgradeReq accesses(hits+misses)
579system.l2c.UpgradeReq_accesses::cpu1.inst 61845 # number of UpgradeReq accesses(hits+misses)
580system.l2c.UpgradeReq_accesses::total 128562 # number of UpgradeReq accesses(hits+misses)
581system.l2c.SCUpgradeReq_accesses::cpu0.inst 16807 # number of SCUpgradeReq accesses(hits+misses)
582system.l2c.SCUpgradeReq_accesses::cpu1.inst 15636 # number of SCUpgradeReq accesses(hits+misses)
583system.l2c.SCUpgradeReq_accesses::total 32443 # number of SCUpgradeReq accesses(hits+misses)
584system.l2c.ReadExReq_accesses::cpu0.inst 121068 # number of ReadExReq accesses(hits+misses)
585system.l2c.ReadExReq_accesses::cpu1.inst 117672 # number of ReadExReq accesses(hits+misses)
586system.l2c.ReadExReq_accesses::total 238740 # number of ReadExReq accesses(hits+misses)
587system.l2c.demand_accesses::cpu0.dtb.walker 10858 # number of demand (read+write) accesses
588system.l2c.demand_accesses::cpu0.itb.walker 10859 # number of demand (read+write) accesses
589system.l2c.demand_accesses::cpu0.inst 765621 # number of demand (read+write) accesses
590system.l2c.demand_accesses::cpu0.l2cache.prefetcher 2478304 # number of demand (read+write) accesses
591system.l2c.demand_accesses::cpu1.dtb.walker 11297 # number of demand (read+write) accesses
592system.l2c.demand_accesses::cpu1.itb.walker 11137 # number of demand (read+write) accesses
593system.l2c.demand_accesses::cpu1.inst 736450 # number of demand (read+write) accesses
594system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2247469 # number of demand (read+write) accesses
595system.l2c.demand_accesses::total 6271995 # number of demand (read+write) accesses
596system.l2c.overall_accesses::cpu0.dtb.walker 10858 # number of overall (read+write) accesses
597system.l2c.overall_accesses::cpu0.itb.walker 10859 # number of overall (read+write) accesses
598system.l2c.overall_accesses::cpu0.inst 765621 # number of overall (read+write) accesses
599system.l2c.overall_accesses::cpu0.l2cache.prefetcher 2478304 # number of overall (read+write) accesses
600system.l2c.overall_accesses::cpu1.dtb.walker 11297 # number of overall (read+write) accesses
601system.l2c.overall_accesses::cpu1.itb.walker 11137 # number of overall (read+write) accesses
602system.l2c.overall_accesses::cpu1.inst 736450 # number of overall (read+write) accesses
603system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2247469 # number of overall (read+write) accesses
604system.l2c.overall_accesses::total 6271995 # number of overall (read+write) accesses
605system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for ReadReq accesses
606system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.588728 # miss rate for ReadReq accesses
607system.l2c.ReadReq_miss_rate::cpu0.inst 0.135772 # miss rate for ReadReq accesses
608system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for ReadReq accesses
609system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for ReadReq accesses
610system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.588758 # miss rate for ReadReq accesses
611system.l2c.ReadReq_miss_rate::cpu1.inst 0.156803 # miss rate for ReadReq accesses
612system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for ReadReq accesses
613system.l2c.ReadReq_miss_rate::total 0.168431 # miss rate for ReadReq accesses
614system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.548886 # miss rate for UpgradeReq accesses
615system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.559479 # miss rate for UpgradeReq accesses
616system.l2c.UpgradeReq_miss_rate::total 0.553982 # miss rate for UpgradeReq accesses
617system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.563932 # miss rate for SCUpgradeReq accesses
618system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.544385 # miss rate for SCUpgradeReq accesses
619system.l2c.SCUpgradeReq_miss_rate::total 0.554511 # miss rate for SCUpgradeReq accesses
620system.l2c.ReadExReq_miss_rate::cpu0.inst 0.575379 # miss rate for ReadExReq accesses
621system.l2c.ReadExReq_miss_rate::cpu1.inst 0.558051 # miss rate for ReadExReq accesses
622system.l2c.ReadExReq_miss_rate::total 0.566838 # miss rate for ReadExReq accesses
623system.l2c.demand_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for demand accesses
624system.l2c.demand_miss_rate::cpu0.itb.walker 0.588728 # miss rate for demand accesses
625system.l2c.demand_miss_rate::cpu0.inst 0.205287 # miss rate for demand accesses
626system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for demand accesses
627system.l2c.demand_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for demand accesses
628system.l2c.demand_miss_rate::cpu1.itb.walker 0.588758 # miss rate for demand accesses
629system.l2c.demand_miss_rate::cpu1.inst 0.220915 # miss rate for demand accesses
630system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for demand accesses
631system.l2c.demand_miss_rate::total 0.183596 # miss rate for demand accesses
632system.l2c.overall_miss_rate::cpu0.dtb.walker 0.348867 # miss rate for overall accesses
633system.l2c.overall_miss_rate::cpu0.itb.walker 0.588728 # miss rate for overall accesses
634system.l2c.overall_miss_rate::cpu0.inst 0.205287 # miss rate for overall accesses
635system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.179343 # miss rate for overall accesses
636system.l2c.overall_miss_rate::cpu1.dtb.walker 0.352217 # miss rate for overall accesses
637system.l2c.overall_miss_rate::cpu1.itb.walker 0.588758 # miss rate for overall accesses
638system.l2c.overall_miss_rate::cpu1.inst 0.220915 # miss rate for overall accesses
639system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.163058 # miss rate for overall accesses
640system.l2c.overall_miss_rate::total 0.183596 # miss rate for overall accesses
641system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average ReadReq miss latency
642system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79393.828250 # average ReadReq miss latency
643system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79248.462245 # average ReadReq miss latency
644system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average ReadReq miss latency
645system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average ReadReq miss latency
646system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 78133.100808 # average ReadReq miss latency
647system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79240.331097 # average ReadReq miss latency
648system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average ReadReq miss latency
649system.l2c.ReadReq_avg_miss_latency::total 98093.307416 # average ReadReq miss latency
650system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4853.073839 # average UpgradeReq miss latency
651system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4668.528540 # average UpgradeReq miss latency
652system.l2c.UpgradeReq_avg_miss_latency::total 4763.416970 # average UpgradeReq miss latency
653system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5214.911690 # average SCUpgradeReq miss latency
654system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5850.494713 # average SCUpgradeReq miss latency
655system.l2c.SCUpgradeReq_avg_miss_latency::total 5515.638911 # average SCUpgradeReq miss latency
656system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 73561.220973 # average ReadExReq miss latency
657system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 72904.952838 # average ReadExReq miss latency
658system.l2c.ReadExReq_avg_miss_latency::total 73242.768930 # average ReadExReq miss latency
659system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency
660system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency
661system.l2c.demand_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency
662system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency
663system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency
664system.l2c.demand_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency
665system.l2c.demand_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency
666system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency
667system.l2c.demand_avg_miss_latency::total 95172.854012 # average overall miss latency
668system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78046.789599 # average overall miss latency
669system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79393.828250 # average overall miss latency
670system.l2c.overall_avg_miss_latency::cpu0.inst 76727.827355 # average overall miss latency
671system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 101979.195084 # average overall miss latency
672system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 78512.313647 # average overall miss latency
673system.l2c.overall_avg_miss_latency::cpu1.itb.walker 78133.100808 # average overall miss latency
674system.l2c.overall_avg_miss_latency::cpu1.inst 76683.212572 # average overall miss latency
675system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 103975.152084 # average overall miss latency
676system.l2c.overall_avg_miss_latency::total 95172.854012 # average overall miss latency
677system.l2c.blocked_cycles::no_mshrs 9985 # number of cycles access was blocked
678system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
679system.l2c.blocked::no_mshrs 293 # number of cycles access was blocked
680system.l2c.blocked::no_targets 0 # number of cycles access was blocked
681system.l2c.avg_blocked_cycles::no_mshrs 34.078498 # average number of cycles each access was blocked
682system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
683system.l2c.fast_writes 0 # number of fast writes performed
684system.l2c.cache_copies 0 # number of cache copies performed
685system.l2c.writebacks::writebacks 526915 # number of writebacks
686system.l2c.writebacks::total 526915 # number of writebacks
687system.l2c.ReadReq_mshr_hits::cpu0.inst 41 # number of ReadReq MSHR hits
688system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 208 # number of ReadReq MSHR hits
689system.l2c.ReadReq_mshr_hits::cpu1.inst 31 # number of ReadReq MSHR hits
690system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 190 # number of ReadReq MSHR hits
691system.l2c.ReadReq_mshr_hits::total 470 # number of ReadReq MSHR hits
692system.l2c.demand_mshr_hits::cpu0.inst 41 # number of demand (read+write) MSHR hits
693system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 208 # number of demand (read+write) MSHR hits
694system.l2c.demand_mshr_hits::cpu1.inst 31 # number of demand (read+write) MSHR hits
695system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 190 # number of demand (read+write) MSHR hits
696system.l2c.demand_mshr_hits::total 470 # number of demand (read+write) MSHR hits
697system.l2c.overall_mshr_hits::cpu0.inst 41 # number of overall MSHR hits
698system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 208 # number of overall MSHR hits
699system.l2c.overall_mshr_hits::cpu1.inst 31 # number of overall MSHR hits
700system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 190 # number of overall MSHR hits
701system.l2c.overall_mshr_hits::total 470 # number of overall MSHR hits
702system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3788 # number of ReadReq MSHR misses
703system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 6393 # number of ReadReq MSHR misses
704system.l2c.ReadReq_mshr_misses::cpu0.inst 87471 # number of ReadReq MSHR misses
705system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of ReadReq MSHR misses
706system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3979 # number of ReadReq MSHR misses
707system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 6557 # number of ReadReq MSHR misses
708system.l2c.ReadReq_mshr_misses::cpu1.inst 96995 # number of ReadReq MSHR misses
709system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of ReadReq MSHR misses
710system.l2c.ReadReq_mshr_misses::total 1015719 # number of ReadReq MSHR misses
711system.l2c.UpgradeReq_mshr_misses::cpu0.inst 36620 # number of UpgradeReq MSHR misses
712system.l2c.UpgradeReq_mshr_misses::cpu1.inst 34601 # number of UpgradeReq MSHR misses
713system.l2c.UpgradeReq_mshr_misses::total 71221 # number of UpgradeReq MSHR misses
714system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9478 # number of SCUpgradeReq MSHR misses
715system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 8512 # number of SCUpgradeReq MSHR misses
716system.l2c.SCUpgradeReq_mshr_misses::total 17990 # number of SCUpgradeReq MSHR misses
717system.l2c.ReadExReq_mshr_misses::cpu0.inst 69660 # number of ReadExReq MSHR misses
718system.l2c.ReadExReq_mshr_misses::cpu1.inst 65667 # number of ReadExReq MSHR misses
719system.l2c.ReadExReq_mshr_misses::total 135327 # number of ReadExReq MSHR misses
720system.l2c.demand_mshr_misses::cpu0.dtb.walker 3788 # number of demand (read+write) MSHR misses
721system.l2c.demand_mshr_misses::cpu0.itb.walker 6393 # number of demand (read+write) MSHR misses
722system.l2c.demand_mshr_misses::cpu0.inst 157131 # number of demand (read+write) MSHR misses
723system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of demand (read+write) MSHR misses
724system.l2c.demand_mshr_misses::cpu1.dtb.walker 3979 # number of demand (read+write) MSHR misses
725system.l2c.demand_mshr_misses::cpu1.itb.walker 6557 # number of demand (read+write) MSHR misses
726system.l2c.demand_mshr_misses::cpu1.inst 162662 # number of demand (read+write) MSHR misses
727system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of demand (read+write) MSHR misses
728system.l2c.demand_mshr_misses::total 1151046 # number of demand (read+write) MSHR misses
729system.l2c.overall_mshr_misses::cpu0.dtb.walker 3788 # number of overall MSHR misses
730system.l2c.overall_mshr_misses::cpu0.itb.walker 6393 # number of overall MSHR misses
731system.l2c.overall_mshr_misses::cpu0.inst 157131 # number of overall MSHR misses
732system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 444258 # number of overall MSHR misses
733system.l2c.overall_mshr_misses::cpu1.dtb.walker 3979 # number of overall MSHR misses
734system.l2c.overall_mshr_misses::cpu1.itb.walker 6557 # number of overall MSHR misses
735system.l2c.overall_mshr_misses::cpu1.inst 162662 # number of overall MSHR misses
736system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 366278 # number of overall MSHR misses
737system.l2c.overall_mshr_misses::total 1151046 # number of overall MSHR misses
738system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of ReadReq MSHR miss cycles
739system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 428022244 # number of ReadReq MSHR miss cycles
740system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 5837610680 # number of ReadReq MSHR miss cycles
741system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of ReadReq MSHR miss cycles
742system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of ReadReq MSHR miss cycles
743system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 430600242 # number of ReadReq MSHR miss cycles
744system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 6471220731 # number of ReadReq MSHR miss cycles
745system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of ReadReq MSHR miss cycles
746system.l2c.ReadReq_mshr_miss_latency::total 87083288091 # number of ReadReq MSHR miss cycles
747system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 17889181875 # number of WriteInvalidateReq MSHR miss cycles
748system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 13903512484 # number of WriteInvalidateReq MSHR miss cycles
749system.l2c.WriteInvalidateReq_mshr_miss_latency::total 31792694359 # number of WriteInvalidateReq MSHR miss cycles
750system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 372768590 # number of UpgradeReq MSHR miss cycles
751system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 351692080 # number of UpgradeReq MSHR miss cycles
752system.l2c.UpgradeReq_mshr_miss_latency::total 724460670 # number of UpgradeReq MSHR miss cycles
753system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 96695300 # number of SCUpgradeReq MSHR miss cycles
754system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 86940850 # number of SCUpgradeReq MSHR miss cycles
755system.l2c.SCUpgradeReq_mshr_miss_latency::total 183636150 # number of SCUpgradeReq MSHR miss cycles
756system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 4247852269 # number of ReadExReq MSHR miss cycles
757system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3960733380 # number of ReadExReq MSHR miss cycles
758system.l2c.ReadExReq_mshr_miss_latency::total 8208585649 # number of ReadExReq MSHR miss cycles
759system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of demand (read+write) MSHR miss cycles
760system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 428022244 # number of demand (read+write) MSHR miss cycles
761system.l2c.demand_mshr_miss_latency::cpu0.inst 10085462949 # number of demand (read+write) MSHR miss cycles
762system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of demand (read+write) MSHR miss cycles
763system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of demand (read+write) MSHR miss cycles
764system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 430600242 # number of demand (read+write) MSHR miss cycles
765system.l2c.demand_mshr_miss_latency::cpu1.inst 10431954111 # number of demand (read+write) MSHR miss cycles
766system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of demand (read+write) MSHR miss cycles
767system.l2c.demand_mshr_miss_latency::total 95291873740 # number of demand (read+write) MSHR miss cycles
768system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 248599239 # number of overall MSHR miss cycles
769system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 428022244 # number of overall MSHR miss cycles
770system.l2c.overall_mshr_miss_latency::cpu0.inst 10085462949 # number of overall MSHR miss cycles
771system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39831799422 # number of overall MSHR miss cycles
772system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 262923496 # number of overall MSHR miss cycles
773system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 430600242 # number of overall MSHR miss cycles
774system.l2c.overall_mshr_miss_latency::cpu1.inst 10431954111 # number of overall MSHR miss cycles
775system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33572512037 # number of overall MSHR miss cycles
776system.l2c.overall_mshr_miss_latency::total 95291873740 # number of overall MSHR miss cycles
777system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4946669501 # number of ReadReq MSHR uncacheable cycles
778system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3170681000 # number of ReadReq MSHR uncacheable cycles
779system.l2c.ReadReq_mshr_uncacheable_latency::total 8117350501 # number of ReadReq MSHR uncacheable cycles
780system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2118382500 # number of WriteReq MSHR uncacheable cycles
781system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 3125324001 # number of WriteReq MSHR uncacheable cycles
782system.l2c.WriteReq_mshr_uncacheable_latency::total 5243706501 # number of WriteReq MSHR uncacheable cycles
783system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7065052001 # number of overall MSHR uncacheable cycles
784system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6296005001 # number of overall MSHR uncacheable cycles
785system.l2c.overall_mshr_uncacheable_latency::total 13361057002 # number of overall MSHR uncacheable cycles
786system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for ReadReq accesses
787system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for ReadReq accesses
788system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.135708 # mshr miss rate for ReadReq accesses
789system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for ReadReq accesses
790system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for ReadReq accesses
791system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for ReadReq accesses
792system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.156753 # mshr miss rate for ReadReq accesses
793system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for ReadReq accesses
794system.l2c.ReadReq_mshr_miss_rate::total 0.168353 # mshr miss rate for ReadReq accesses
795system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.548886 # mshr miss rate for UpgradeReq accesses
796system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.559479 # mshr miss rate for UpgradeReq accesses
797system.l2c.UpgradeReq_mshr_miss_rate::total 0.553982 # mshr miss rate for UpgradeReq accesses
798system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.563932 # mshr miss rate for SCUpgradeReq accesses
799system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.544385 # mshr miss rate for SCUpgradeReq accesses
800system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.554511 # mshr miss rate for SCUpgradeReq accesses
801system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.575379 # mshr miss rate for ReadExReq accesses
802system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.558051 # mshr miss rate for ReadExReq accesses
803system.l2c.ReadExReq_mshr_miss_rate::total 0.566838 # mshr miss rate for ReadExReq accesses
804system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for demand accesses
805system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for demand accesses
806system.l2c.demand_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for demand accesses
807system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for demand accesses
808system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for demand accesses
809system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for demand accesses
810system.l2c.demand_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for demand accesses
811system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for demand accesses
812system.l2c.demand_mshr_miss_rate::total 0.183522 # mshr miss rate for demand accesses
813system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.348867 # mshr miss rate for overall accesses
814system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.588728 # mshr miss rate for overall accesses
815system.l2c.overall_mshr_miss_rate::cpu0.inst 0.205233 # mshr miss rate for overall accesses
816system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.179259 # mshr miss rate for overall accesses
817system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.352217 # mshr miss rate for overall accesses
818system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.588758 # mshr miss rate for overall accesses
819system.l2c.overall_mshr_miss_rate::cpu1.inst 0.220873 # mshr miss rate for overall accesses
820system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.162974 # mshr miss rate for overall accesses
821system.l2c.overall_mshr_miss_rate::total 0.183522 # mshr miss rate for overall accesses
822system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average ReadReq mshr miss latency
823system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average ReadReq mshr miss latency
824system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 66737.669399 # average ReadReq mshr miss latency
825system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average ReadReq mshr miss latency
826system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average ReadReq mshr miss latency
827system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average ReadReq mshr miss latency
828system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 66717.054807 # average ReadReq mshr miss latency
829system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average ReadReq mshr miss latency
830system.l2c.ReadReq_avg_mshr_miss_latency::total 85735.610037 # average ReadReq mshr miss latency
831system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency
832system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency
833system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
834system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10179.371655 # average UpgradeReq mshr miss latency
835system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10164.217219 # average UpgradeReq mshr miss latency
836system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10172.009239 # average UpgradeReq mshr miss latency
837system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10202.078498 # average SCUpgradeReq mshr miss latency
838system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10213.915648 # average SCUpgradeReq mshr miss latency
839system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10207.679266 # average SCUpgradeReq mshr miss latency
840system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 60979.791401 # average ReadExReq mshr miss latency
841system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60315.430582 # average ReadExReq mshr miss latency
842system.l2c.ReadExReq_avg_mshr_miss_latency::total 60657.412408 # average ReadExReq mshr miss latency
843system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency
844system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency
845system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency
846system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency
847system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency
848system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency
849system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency
850system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency
851system.l2c.demand_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency
852system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65628.098997 # average overall mshr miss latency
853system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66951.704051 # average overall mshr miss latency
854system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64185.061821 # average overall mshr miss latency
855system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 89659.160717 # average overall mshr miss latency
856system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66077.782357 # average overall mshr miss latency
857system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65670.312948 # average overall mshr miss latency
858system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64132.705309 # average overall mshr miss latency
859system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 91658.554532 # average overall mshr miss latency
860system.l2c.overall_avg_mshr_miss_latency::total 82787.198548 # average overall mshr miss latency
861system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
862system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
863system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
864system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
865system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
866system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
867system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
868system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
869system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
870system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
871system.realview.ethernet.txBytes 966 # Bytes Transmitted
872system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
873system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
874system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
875system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
876system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
877system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
878system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
879system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
880system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
881system.realview.ethernet.totPackets 3 # Total Packets
882system.realview.ethernet.totBytes 966 # Total Bytes
883system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
884system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
885system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
886system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
887system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
888system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
889system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
890system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
891system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
892system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
893system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
894system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
895system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
896system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
897system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
898system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
899system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
900system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
901system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
902system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
903system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
904system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
905system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
906system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
907system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
908system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
909system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
910system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
911system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
912system.realview.ethernet.droppedPackets 0 # number of packets dropped
913system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
914system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
915system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
916system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
917system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
918system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
919system.toL2Bus.trans_dist::ReadReq 6929805 # Transaction distribution
920system.toL2Bus.trans_dist::ReadResp 6922247 # Transaction distribution
921system.toL2Bus.trans_dist::WriteReq 37937 # Transaction distribution
922system.toL2Bus.trans_dist::WriteResp 37937 # Transaction distribution
923system.toL2Bus.trans_dist::Writeback 1844732 # Transaction distribution
924system.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
925system.toL2Bus.trans_dist::WriteInvalidateResp 1558815 # Transaction distribution
926system.toL2Bus.trans_dist::UpgradeReq 396880 # Transaction distribution
927system.toL2Bus.trans_dist::SCUpgradeReq 304912 # Transaction distribution
928system.toL2Bus.trans_dist::UpgradeResp 701792 # Transaction distribution
929system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution
930system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
931system.toL2Bus.trans_dist::ReadExReq 286652 # Transaction distribution
932system.toL2Bus.trans_dist::ReadExResp 286652 # Transaction distribution
933system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10302950 # Packet count per connected master and slave (bytes)
934system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9169444 # Packet count per connected master and slave (bytes)
935system.toL2Bus.pkt_count::total 19472394 # Packet count per connected master and slave (bytes)
936system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 332778181 # Cumulative packet size per connected master and slave (bytes)
937system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290120831 # Cumulative packet size per connected master and slave (bytes)
938system.toL2Bus.pkt_size::total 622899012 # Cumulative packet size per connected master and slave (bytes)
939system.toL2Bus.snoops 1503135 # Total snoops (count)
940system.toL2Bus.snoop_fanout::samples 11338555 # Request fanout histogram
941system.toL2Bus.snoop_fanout::mean 1.010201 # Request fanout histogram
942system.toL2Bus.snoop_fanout::stdev 0.100485 # Request fanout histogram
943system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
944system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
945system.toL2Bus.snoop_fanout::1 11222888 98.98% 98.98% # Request fanout histogram
946system.toL2Bus.snoop_fanout::2 115667 1.02% 100.00% # Request fanout histogram
947system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
948system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
949system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
950system.toL2Bus.snoop_fanout::total 11338555 # Request fanout histogram
951system.toL2Bus.reqLayer0.occupancy 19325316227 # Layer occupancy (ticks)
952system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
953system.toL2Bus.snoopLayer0.occupancy 6157500 # Layer occupancy (ticks)
954system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
955system.toL2Bus.respLayer0.occupancy 17505808152 # Layer occupancy (ticks)
956system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
957system.toL2Bus.respLayer1.occupancy 16090621161 # Layer occupancy (ticks)
958system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
959system.iobus.trans_dist::ReadReq 40386 # Transaction distribution
960system.iobus.trans_dist::ReadResp 40386 # Transaction distribution
961system.iobus.trans_dist::WriteReq 136543 # Transaction distribution
962system.iobus.trans_dist::WriteResp 136730 # Transaction distribution
963system.iobus.trans_dist::WriteInvalidateReq 187 # Transaction distribution
964system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48036 # Packet count per connected master and slave (bytes)
965system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
966system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
967system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
968system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
969system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
970system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
971system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
972system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
973system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
974system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
975system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
976system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
977system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
978system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
979system.iobus.pkt_count_system.bridge.master::total 122918 # Packet count per connected master and slave (bytes)
980system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
981system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
982system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
983system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
984system.iobus.pkt_count::total 354232 # Packet count per connected master and slave (bytes)
985system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48056 # Cumulative packet size per connected master and slave (bytes)
986system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
988system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
989system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
990system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
991system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
992system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
993system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
994system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
995system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
996system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
997system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
998system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
999system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1000system.iobus.pkt_size_system.bridge.master::total 156048 # Cumulative packet size per connected master and slave (bytes)
1001system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
1002system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
1003system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1004system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1005system.iobus.pkt_size::total 7497086 # Cumulative packet size per connected master and slave (bytes)
1006system.iobus.reqLayer0.occupancy 36503000 # Layer occupancy (ticks)
1007system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1008system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1009system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1010system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1011system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1012system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1013system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1014system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1015system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1016system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1017system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1018system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1019system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1020system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1021system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1022system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1023system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1024system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1025system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1026system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1027system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1028system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1029system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1030system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1031system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1032system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1033system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1034system.iobus.reqLayer27.occupancy 982100345 # Layer occupancy (ticks)
1035system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1036system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1037system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1038system.iobus.respLayer0.occupancy 92919000 # Layer occupancy (ticks)
1039system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1040system.iobus.respLayer3.occupancy 179226247 # Layer occupancy (ticks)
1041system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1042system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
1043system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1044system.cpu0.branchPred.lookups 130284886 # Number of BP lookups
1045system.cpu0.branchPred.condPredicted 91971902 # Number of conditional branches predicted
1046system.cpu0.branchPred.condIncorrect 5996877 # Number of conditional branches incorrect
1047system.cpu0.branchPred.BTBLookups 97983342 # Number of BTB lookups
1048system.cpu0.branchPred.BTBHits 71203631 # Number of BTB hits
1049system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1050system.cpu0.branchPred.BTBHitPct 72.669119 # BTB Hit Percentage
1051system.cpu0.branchPred.usedRAS 15456951 # Number of times the RAS was used to get a target.
1052system.cpu0.branchPred.RASInCorrect 1030979 # Number of incorrect RAS predictions.
1053system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1054system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1055system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1056system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1057system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1058system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1059system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1060system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1068system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1069system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1070system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1071system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1072system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1073system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1074system.cpu0.dtb.inst_hits 0 # ITB inst hits
1075system.cpu0.dtb.inst_misses 0 # ITB inst misses
1076system.cpu0.dtb.read_hits 84560824 # DTB read hits
1077system.cpu0.dtb.read_misses 213472 # DTB read misses
1078system.cpu0.dtb.write_hits 73762718 # DTB write hits
1079system.cpu0.dtb.write_misses 44801 # DTB write misses
1080system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1081system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1082system.cpu0.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
1083system.cpu0.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
1084system.cpu0.dtb.flush_entries 35801 # Number of entries that have been flushed from TLB
1085system.cpu0.dtb.align_faults 1794 # Number of TLB faults due to alignment restrictions
1086system.cpu0.dtb.prefetch_faults 7921 # Number of TLB faults due to prefetch
1087system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1088system.cpu0.dtb.perms_faults 10648 # Number of TLB faults due to permissions restrictions
1089system.cpu0.dtb.read_accesses 84774296 # DTB read accesses
1090system.cpu0.dtb.write_accesses 73807519 # DTB write accesses
1091system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1092system.cpu0.dtb.hits 158323542 # DTB hits
1093system.cpu0.dtb.misses 258273 # DTB misses
1094system.cpu0.dtb.accesses 158581815 # DTB accesses
1095system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1096system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1097system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1098system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1099system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1100system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1101system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1102system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1108system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1109system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1110system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1111system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1112system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1113system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1114system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1115system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1116system.cpu0.itb.inst_hits 233888906 # ITB inst hits
1117system.cpu0.itb.inst_misses 61464 # ITB inst misses
1118system.cpu0.itb.read_hits 0 # DTB read hits
1119system.cpu0.itb.read_misses 0 # DTB read misses
1120system.cpu0.itb.write_hits 0 # DTB write hits
1121system.cpu0.itb.write_misses 0 # DTB write misses
1122system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
1123system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1124system.cpu0.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
1125system.cpu0.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
1126system.cpu0.itb.flush_entries 25786 # Number of entries that have been flushed from TLB
1127system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1128system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1129system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1130system.cpu0.itb.perms_faults 208811 # Number of TLB faults due to permissions restrictions
1131system.cpu0.itb.read_accesses 0 # DTB read accesses
1132system.cpu0.itb.write_accesses 0 # DTB write accesses
1133system.cpu0.itb.inst_accesses 233950370 # ITB inst accesses
1134system.cpu0.itb.hits 233888906 # DTB hits
1135system.cpu0.itb.misses 61464 # DTB misses
1136system.cpu0.itb.accesses 233950370 # DTB accesses
1137system.cpu0.numCycles 883850249 # number of cpu cycles simulated
1138system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1139system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1140system.cpu0.committedInsts 434327088 # Number of instructions committed
1141system.cpu0.committedOps 509859279 # Number of ops (including micro ops) committed
1142system.cpu0.discardedOps 43671037 # Number of ops (including micro ops) which were discarded before commit
1143system.cpu0.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching
1144system.cpu0.quiesceCycles 93815840018 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1145system.cpu0.cpi 2.034988 # CPI: cycles per instruction
1146system.cpu0.ipc 0.491403 # IPC: instructions per cycle
1147system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1148system.cpu0.kern.inst.quiesce 5406 # number of quiesce instructions executed
1149system.cpu0.tickCycles 675499590 # Number of cycles that the object actually ticked
1150system.cpu0.idleCycles 208350659 # Total number of cycles that the object has spent stopped
1151system.cpu0.icache.tags.replacements 9024677 # number of replacements
1152system.cpu0.icache.tags.tagsinuse 511.937426 # Cycle average of tags in use
1153system.cpu0.icache.tags.total_refs 224649292 # Total number of references to valid blocks.
1154system.cpu0.icache.tags.sampled_refs 9025189 # Sample count of references to valid blocks.
1155system.cpu0.icache.tags.avg_refs 24.891367 # Average number of references to valid blocks.
1156system.cpu0.icache.tags.warmup_cycle 16724996500 # Cycle when the warmup percentage was hit.
1157system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937426 # Average occupied blocks per requestor
1158system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy
1159system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy
1160system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1161system.cpu0.icache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
1162system.cpu0.icache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
1163system.cpu0.icache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
1164system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1165system.cpu0.icache.tags.tag_accesses 476374153 # Number of tag accesses
1166system.cpu0.icache.tags.data_accesses 476374153 # Number of data accesses
1167system.cpu0.icache.ReadReq_hits::cpu0.inst 224649292 # number of ReadReq hits
1168system.cpu0.icache.ReadReq_hits::total 224649292 # number of ReadReq hits
1169system.cpu0.icache.demand_hits::cpu0.inst 224649292 # number of demand (read+write) hits
1170system.cpu0.icache.demand_hits::total 224649292 # number of demand (read+write) hits
1171system.cpu0.icache.overall_hits::cpu0.inst 224649292 # number of overall hits
1172system.cpu0.icache.overall_hits::total 224649292 # number of overall hits
1173system.cpu0.icache.ReadReq_misses::cpu0.inst 9025190 # number of ReadReq misses
1174system.cpu0.icache.ReadReq_misses::total 9025190 # number of ReadReq misses
1175system.cpu0.icache.demand_misses::cpu0.inst 9025190 # number of demand (read+write) misses
1176system.cpu0.icache.demand_misses::total 9025190 # number of demand (read+write) misses
1177system.cpu0.icache.overall_misses::cpu0.inst 9025190 # number of overall misses
1178system.cpu0.icache.overall_misses::total 9025190 # number of overall misses
1179system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 76329373412 # number of ReadReq miss cycles
1180system.cpu0.icache.ReadReq_miss_latency::total 76329373412 # number of ReadReq miss cycles
1181system.cpu0.icache.demand_miss_latency::cpu0.inst 76329373412 # number of demand (read+write) miss cycles
1182system.cpu0.icache.demand_miss_latency::total 76329373412 # number of demand (read+write) miss cycles
1183system.cpu0.icache.overall_miss_latency::cpu0.inst 76329373412 # number of overall miss cycles
1184system.cpu0.icache.overall_miss_latency::total 76329373412 # number of overall miss cycles
1185system.cpu0.icache.ReadReq_accesses::cpu0.inst 233674482 # number of ReadReq accesses(hits+misses)
1186system.cpu0.icache.ReadReq_accesses::total 233674482 # number of ReadReq accesses(hits+misses)
1187system.cpu0.icache.demand_accesses::cpu0.inst 233674482 # number of demand (read+write) accesses
1188system.cpu0.icache.demand_accesses::total 233674482 # number of demand (read+write) accesses
1189system.cpu0.icache.overall_accesses::cpu0.inst 233674482 # number of overall (read+write) accesses
1190system.cpu0.icache.overall_accesses::total 233674482 # number of overall (read+write) accesses
1191system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038623 # miss rate for ReadReq accesses
1192system.cpu0.icache.ReadReq_miss_rate::total 0.038623 # miss rate for ReadReq accesses
1193system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038623 # miss rate for demand accesses
1194system.cpu0.icache.demand_miss_rate::total 0.038623 # miss rate for demand accesses
1195system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038623 # miss rate for overall accesses
1196system.cpu0.icache.overall_miss_rate::total 0.038623 # miss rate for overall accesses
1197system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8457.370251 # average ReadReq miss latency
1198system.cpu0.icache.ReadReq_avg_miss_latency::total 8457.370251 # average ReadReq miss latency
1199system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency
1200system.cpu0.icache.demand_avg_miss_latency::total 8457.370251 # average overall miss latency
1201system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8457.370251 # average overall miss latency
1202system.cpu0.icache.overall_avg_miss_latency::total 8457.370251 # average overall miss latency
1203system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1204system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1205system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1206system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1207system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1208system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1209system.cpu0.icache.fast_writes 0 # number of fast writes performed
1210system.cpu0.icache.cache_copies 0 # number of cache copies performed
1211system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9025190 # number of ReadReq MSHR misses
1212system.cpu0.icache.ReadReq_mshr_misses::total 9025190 # number of ReadReq MSHR misses
1213system.cpu0.icache.demand_mshr_misses::cpu0.inst 9025190 # number of demand (read+write) MSHR misses
1214system.cpu0.icache.demand_mshr_misses::total 9025190 # number of demand (read+write) MSHR misses
1215system.cpu0.icache.overall_mshr_misses::cpu0.inst 9025190 # number of overall MSHR misses
1216system.cpu0.icache.overall_mshr_misses::total 9025190 # number of overall MSHR misses
1217system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62781832574 # number of ReadReq MSHR miss cycles
1218system.cpu0.icache.ReadReq_mshr_miss_latency::total 62781832574 # number of ReadReq MSHR miss cycles
1219system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62781832574 # number of demand (read+write) MSHR miss cycles
1220system.cpu0.icache.demand_mshr_miss_latency::total 62781832574 # number of demand (read+write) MSHR miss cycles
1221system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62781832574 # number of overall MSHR miss cycles
1222system.cpu0.icache.overall_mshr_miss_latency::total 62781832574 # number of overall MSHR miss cycles
1223system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of ReadReq MSHR uncacheable cycles
1224system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713380500 # number of ReadReq MSHR uncacheable cycles
1225system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713380500 # number of overall MSHR uncacheable cycles
1226system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713380500 # number of overall MSHR uncacheable cycles
1227system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for ReadReq accesses
1228system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038623 # mshr miss rate for ReadReq accesses
1229system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for demand accesses
1230system.cpu0.icache.demand_mshr_miss_rate::total 0.038623 # mshr miss rate for demand accesses
1231system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038623 # mshr miss rate for overall accesses
1232system.cpu0.icache.overall_mshr_miss_rate::total 0.038623 # mshr miss rate for overall accesses
1233system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average ReadReq mshr miss latency
1234system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6956.289294 # average ReadReq mshr miss latency
1235system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency
1236system.cpu0.icache.demand_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency
1237system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6956.289294 # average overall mshr miss latency
1238system.cpu0.icache.overall_avg_mshr_miss_latency::total 6956.289294 # average overall mshr miss latency
1239system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1240system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1241system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1242system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1243system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1244system.cpu0.toL2Bus.trans_dist::ReadReq 16744363 # Transaction distribution
1245system.cpu0.toL2Bus.trans_dist::ReadResp 13538941 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::WriteReq 16377 # Transaction distribution
1247system.cpu0.toL2Bus.trans_dist::WriteResp 16377 # Transaction distribution
1248system.cpu0.toL2Bus.trans_dist::Writeback 2993146 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::HardPFReq 4286145 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
1251system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
1252system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 878594 # Transaction distribution
1253system.cpu0.toL2Bus.trans_dist::UpgradeReq 389729 # Transaction distribution
1254system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 340122 # Transaction distribution
1255system.cpu0.toL2Bus.trans_dist::UpgradeResp 446153 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
1257system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
1258system.cpu0.toL2Bus.trans_dist::ReadExReq 1234377 # Transaction distribution
1259system.cpu0.toL2Bus.trans_dist::ReadExResp 1099479 # Transaction distribution
1260system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18154960 # Packet count per connected master and slave (bytes)
1261system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15139641 # Packet count per connected master and slave (bytes)
1262system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 334891 # Packet count per connected master and slave (bytes)
1263system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1016427 # Packet count per connected master and slave (bytes)
1264system.cpu0.toL2Bus.pkt_count::total 34645919 # Packet count per connected master and slave (bytes)
1265system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 580958656 # Cumulative packet size per connected master and slave (bytes)
1266system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 555417413 # Cumulative packet size per connected master and slave (bytes)
1267system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1211560 # Cumulative packet size per connected master and slave (bytes)
1268system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3676024 # Cumulative packet size per connected master and slave (bytes)
1269system.cpu0.toL2Bus.pkt_size::total 1141263653 # Cumulative packet size per connected master and slave (bytes)
1270system.cpu0.toL2Bus.snoops 9180766 # Total snoops (count)
1271system.cpu0.toL2Bus.snoop_fanout::samples 27586114 # Request fanout histogram
1272system.cpu0.toL2Bus.snoop_fanout::mean 5.321691 # Request fanout histogram
1273system.cpu0.toL2Bus.snoop_fanout::stdev 0.467125 # Request fanout histogram
1274system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1275system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1276system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1277system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1278system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1279system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1280system.cpu0.toL2Bus.snoop_fanout::5 18711910 67.83% 67.83% # Request fanout histogram
1281system.cpu0.toL2Bus.snoop_fanout::6 8874204 32.17% 100.00% # Request fanout histogram
1282system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1283system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1284system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1285system.cpu0.toL2Bus.snoop_fanout::total 27586114 # Request fanout histogram
1286system.cpu0.toL2Bus.reqLayer0.occupancy 13279117937 # Layer occupancy (ticks)
1287system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1288system.cpu0.toL2Bus.snoopLayer0.occupancy 196246989 # Layer occupancy (ticks)
1289system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1290system.cpu0.toL2Bus.respLayer0.occupancy 13633302169 # Layer occupancy (ticks)
1291system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1292system.cpu0.toL2Bus.respLayer1.occupancy 7744080967 # Layer occupancy (ticks)
1293system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1294system.cpu0.toL2Bus.respLayer2.occupancy 184135419 # Layer occupancy (ticks)
1295system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1296system.cpu0.toL2Bus.respLayer3.occupancy 557460915 # Layer occupancy (ticks)
1297system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1298system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 80006652 # number of hwpf identified
1299system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1538976 # number of hwpf that were already in mshr
1300system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75387543 # number of hwpf that were already in the cache
1301system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49644 # number of hwpf that were already in the prefetch queue
1302system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1303system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2517 # number of hwpf removed because MSHR allocated
1304system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3027964 # number of hwpf issued
1305system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6795468 # number of hwpf spanning a virtual page
1306system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1307system.cpu0.l2cache.tags.replacements 3295318 # number of replacements
1308system.cpu0.l2cache.tags.tagsinuse 16239.521092 # Cycle average of tags in use
1309system.cpu0.l2cache.tags.total_refs 15183735 # Total number of references to valid blocks.
1310system.cpu0.l2cache.tags.sampled_refs 3311433 # Sample count of references to valid blocks.
1311system.cpu0.l2cache.tags.avg_refs 4.585246 # Average number of references to valid blocks.
1312system.cpu0.l2cache.tags.warmup_cycle 14515776000 # Cycle when the warmup percentage was hit.
1313system.cpu0.l2cache.tags.occ_blocks::writebacks 5108.942549 # Average occupied blocks per requestor
1314system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.019654 # Average occupied blocks per requestor
1315system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 70.169979 # Average occupied blocks per requestor
1316system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2735.324727 # Average occupied blocks per requestor
1317system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8261.064181 # Average occupied blocks per requestor
1318system.cpu0.l2cache.tags.occ_percent::writebacks 0.311825 # Average percentage of cache occupancy
1319system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003907 # Average percentage of cache occupancy
1320system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004283 # Average percentage of cache occupancy
1321system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.166951 # Average percentage of cache occupancy
1322system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.504215 # Average percentage of cache occupancy
1323system.cpu0.l2cache.tags.occ_percent::total 0.991182 # Average percentage of cache occupancy
1324system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10731 # Occupied blocks per task id
1325system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
1326system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5301 # Occupied blocks per task id
1327system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id
1328system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 730 # Occupied blocks per task id
1329system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2564 # Occupied blocks per task id
1330system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4307 # Occupied blocks per task id
1331system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 3014 # Occupied blocks per task id
1332system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
1333system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
1334system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
1335system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 30 # Occupied blocks per task id
1336system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
1337system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
1338system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 447 # Occupied blocks per task id
1339system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1426 # Occupied blocks per task id
1340system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2059 # Occupied blocks per task id
1341system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id
1342system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.654968 # Percentage of cache occupancy per task id
1343system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
1344system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.323547 # Percentage of cache occupancy per task id
1345system.cpu0.l2cache.tags.tag_accesses 302494843 # Number of tag accesses
1346system.cpu0.l2cache.tags.data_accesses 302494843 # Number of data accesses
1347system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 445653 # number of ReadReq hits
1348system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140462 # number of ReadReq hits
1349system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11717958 # number of ReadReq hits
1350system.cpu0.l2cache.ReadReq_hits::total 12304073 # number of ReadReq hits
1351system.cpu0.l2cache.Writeback_hits::writebacks 2993146 # number of Writeback hits
1352system.cpu0.l2cache.Writeback_hits::total 2993146 # number of Writeback hits
1353system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 70651 # number of UpgradeReq hits
1354system.cpu0.l2cache.UpgradeReq_hits::total 70651 # number of UpgradeReq hits
1355system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 35155 # number of SCUpgradeReq hits
1356system.cpu0.l2cache.SCUpgradeReq_hits::total 35155 # number of SCUpgradeReq hits
1357system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 863705 # number of ReadExReq hits
1358system.cpu0.l2cache.ReadExReq_hits::total 863705 # number of ReadExReq hits
1359system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 445653 # number of demand (read+write) hits
1360system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140462 # number of demand (read+write) hits
1361system.cpu0.l2cache.demand_hits::cpu0.inst 12581663 # number of demand (read+write) hits
1362system.cpu0.l2cache.demand_hits::total 13167778 # number of demand (read+write) hits
1363system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 445653 # number of overall hits
1364system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140462 # number of overall hits
1365system.cpu0.l2cache.overall_hits::cpu0.inst 12581663 # number of overall hits
1366system.cpu0.l2cache.overall_hits::total 13167778 # number of overall hits
1367system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13850 # number of ReadReq misses
1368system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10983 # number of ReadReq misses
1369system.cpu0.l2cache.ReadReq_misses::cpu0.inst 913042 # number of ReadReq misses
1370system.cpu0.l2cache.ReadReq_misses::total 937875 # number of ReadReq misses
1371system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 117562 # number of UpgradeReq misses
1372system.cpu0.l2cache.UpgradeReq_misses::total 117562 # number of UpgradeReq misses
1373system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 153389 # number of SCUpgradeReq misses
1374system.cpu0.l2cache.SCUpgradeReq_misses::total 153389 # number of SCUpgradeReq misses
1375system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 3 # number of SCUpgradeFailReq misses
1376system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
1377system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 228005 # number of ReadExReq misses
1378system.cpu0.l2cache.ReadExReq_misses::total 228005 # number of ReadExReq misses
1379system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13850 # number of demand (read+write) misses
1380system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10983 # number of demand (read+write) misses
1381system.cpu0.l2cache.demand_misses::cpu0.inst 1141047 # number of demand (read+write) misses
1382system.cpu0.l2cache.demand_misses::total 1165880 # number of demand (read+write) misses
1383system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13850 # number of overall misses
1384system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10983 # number of overall misses
1385system.cpu0.l2cache.overall_misses::cpu0.inst 1141047 # number of overall misses
1386system.cpu0.l2cache.overall_misses::total 1165880 # number of overall misses
1387system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 571410377 # number of ReadReq miss cycles
1388system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 698481694 # number of ReadReq miss cycles
1389system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26359609041 # number of ReadReq miss cycles
1390system.cpu0.l2cache.ReadReq_miss_latency::total 27629501112 # number of ReadReq miss cycles
1391system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2365914343 # number of UpgradeReq miss cycles
1392system.cpu0.l2cache.UpgradeReq_miss_latency::total 2365914343 # number of UpgradeReq miss cycles
1393system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 3101977603 # number of SCUpgradeReq miss cycles
1394system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3101977603 # number of SCUpgradeReq miss cycles
1395system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2176500 # number of SCUpgradeFailReq miss cycles
1396system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2176500 # number of SCUpgradeFailReq miss cycles
1397system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 9967705721 # number of ReadExReq miss cycles
1398system.cpu0.l2cache.ReadExReq_miss_latency::total 9967705721 # number of ReadExReq miss cycles
1399system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 571410377 # number of demand (read+write) miss cycles
1400system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 698481694 # number of demand (read+write) miss cycles
1401system.cpu0.l2cache.demand_miss_latency::cpu0.inst 36327314762 # number of demand (read+write) miss cycles
1402system.cpu0.l2cache.demand_miss_latency::total 37597206833 # number of demand (read+write) miss cycles
1403system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 571410377 # number of overall miss cycles
1404system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 698481694 # number of overall miss cycles
1405system.cpu0.l2cache.overall_miss_latency::cpu0.inst 36327314762 # number of overall miss cycles
1406system.cpu0.l2cache.overall_miss_latency::total 37597206833 # number of overall miss cycles
1407system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 459503 # number of ReadReq accesses(hits+misses)
1408system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151445 # number of ReadReq accesses(hits+misses)
1409system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12631000 # number of ReadReq accesses(hits+misses)
1410system.cpu0.l2cache.ReadReq_accesses::total 13241948 # number of ReadReq accesses(hits+misses)
1411system.cpu0.l2cache.Writeback_accesses::writebacks 2993146 # number of Writeback accesses(hits+misses)
1412system.cpu0.l2cache.Writeback_accesses::total 2993146 # number of Writeback accesses(hits+misses)
1413system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 188213 # number of UpgradeReq accesses(hits+misses)
1414system.cpu0.l2cache.UpgradeReq_accesses::total 188213 # number of UpgradeReq accesses(hits+misses)
1415system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 188544 # number of SCUpgradeReq accesses(hits+misses)
1416system.cpu0.l2cache.SCUpgradeReq_accesses::total 188544 # number of SCUpgradeReq accesses(hits+misses)
1417system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 3 # number of SCUpgradeFailReq accesses(hits+misses)
1418system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
1419system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1091710 # number of ReadExReq accesses(hits+misses)
1420system.cpu0.l2cache.ReadExReq_accesses::total 1091710 # number of ReadExReq accesses(hits+misses)
1421system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 459503 # number of demand (read+write) accesses
1422system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151445 # number of demand (read+write) accesses
1423system.cpu0.l2cache.demand_accesses::cpu0.inst 13722710 # number of demand (read+write) accesses
1424system.cpu0.l2cache.demand_accesses::total 14333658 # number of demand (read+write) accesses
1425system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 459503 # number of overall (read+write) accesses
1426system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151445 # number of overall (read+write) accesses
1427system.cpu0.l2cache.overall_accesses::cpu0.inst 13722710 # number of overall (read+write) accesses
1428system.cpu0.l2cache.overall_accesses::total 14333658 # number of overall (read+write) accesses
1429system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for ReadReq accesses
1430system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.072521 # miss rate for ReadReq accesses
1431system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.072286 # miss rate for ReadReq accesses
1432system.cpu0.l2cache.ReadReq_miss_rate::total 0.070826 # miss rate for ReadReq accesses
1433system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.624622 # miss rate for UpgradeReq accesses
1434system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.624622 # miss rate for UpgradeReq accesses
1435system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.813545 # miss rate for SCUpgradeReq accesses
1436system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813545 # miss rate for SCUpgradeReq accesses
1437system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses
1438system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1439system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.208851 # miss rate for ReadExReq accesses
1440system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208851 # miss rate for ReadExReq accesses
1441system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for demand accesses
1442system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.072521 # miss rate for demand accesses
1443system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.083150 # miss rate for demand accesses
1444system.cpu0.l2cache.demand_miss_rate::total 0.081339 # miss rate for demand accesses
1445system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.030141 # miss rate for overall accesses
1446system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.072521 # miss rate for overall accesses
1447system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.083150 # miss rate for overall accesses
1448system.cpu0.l2cache.overall_miss_rate::total 0.081339 # miss rate for overall accesses
1449system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average ReadReq miss latency
1450system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 63596.621506 # average ReadReq miss latency
1451system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 28870.094739 # average ReadReq miss latency
1452system.cpu0.l2cache.ReadReq_avg_miss_latency::total 29459.683979 # average ReadReq miss latency
1453system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 20124.822162 # average UpgradeReq miss latency
1454system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20124.822162 # average UpgradeReq miss latency
1455system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20222.946906 # average SCUpgradeReq miss latency
1456system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.946906 # average SCUpgradeReq miss latency
1457system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 725500 # average SCUpgradeFailReq miss latency
1458system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 725500 # average SCUpgradeFailReq miss latency
1459system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 43717.048841 # average ReadExReq miss latency
1460system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 43717.048841 # average ReadExReq miss latency
1461system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency
1462system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency
1463system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency
1464system.cpu0.l2cache.demand_avg_miss_latency::total 32247.921598 # average overall miss latency
1465system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 41257.066931 # average overall miss latency
1466system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 63596.621506 # average overall miss latency
1467system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31836.825969 # average overall miss latency
1468system.cpu0.l2cache.overall_avg_miss_latency::total 32247.921598 # average overall miss latency
1469system.cpu0.l2cache.blocked_cycles::no_mshrs 62612 # number of cycles access was blocked
1470system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1471system.cpu0.l2cache.blocked::no_mshrs 1060 # number of cycles access was blocked
1472system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1473system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 59.067925 # average number of cycles each access was blocked
1474system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1475system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1476system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1477system.cpu0.l2cache.writebacks::writebacks 1001402 # number of writebacks
1478system.cpu0.l2cache.writebacks::total 1001402 # number of writebacks
1479system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 72428 # number of ReadReq MSHR hits
1480system.cpu0.l2cache.ReadReq_mshr_hits::total 72428 # number of ReadReq MSHR hits
1481system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 6233 # number of ReadExReq MSHR hits
1482system.cpu0.l2cache.ReadExReq_mshr_hits::total 6233 # number of ReadExReq MSHR hits
1483system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 78661 # number of demand (read+write) MSHR hits
1484system.cpu0.l2cache.demand_mshr_hits::total 78661 # number of demand (read+write) MSHR hits
1485system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 78661 # number of overall MSHR hits
1486system.cpu0.l2cache.overall_mshr_hits::total 78661 # number of overall MSHR hits
1487system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13850 # number of ReadReq MSHR misses
1488system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10983 # number of ReadReq MSHR misses
1489system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 840614 # number of ReadReq MSHR misses
1490system.cpu0.l2cache.ReadReq_mshr_misses::total 865447 # number of ReadReq MSHR misses
1491system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of HardPFReq MSHR misses
1492system.cpu0.l2cache.HardPFReq_mshr_misses::total 3027916 # number of HardPFReq MSHR misses
1493system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 117562 # number of UpgradeReq MSHR misses
1494system.cpu0.l2cache.UpgradeReq_mshr_misses::total 117562 # number of UpgradeReq MSHR misses
1495system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 153389 # number of SCUpgradeReq MSHR misses
1496system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 153389 # number of SCUpgradeReq MSHR misses
1497system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 3 # number of SCUpgradeFailReq MSHR misses
1498system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
1499system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 221772 # number of ReadExReq MSHR misses
1500system.cpu0.l2cache.ReadExReq_mshr_misses::total 221772 # number of ReadExReq MSHR misses
1501system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13850 # number of demand (read+write) MSHR misses
1502system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10983 # number of demand (read+write) MSHR misses
1503system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1062386 # number of demand (read+write) MSHR misses
1504system.cpu0.l2cache.demand_mshr_misses::total 1087219 # number of demand (read+write) MSHR misses
1505system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13850 # number of overall MSHR misses
1506system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10983 # number of overall MSHR misses
1507system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1062386 # number of overall MSHR misses
1508system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3027916 # number of overall MSHR misses
1509system.cpu0.l2cache.overall_mshr_misses::total 4115135 # number of overall MSHR misses
1510system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of ReadReq MSHR miss cycles
1511system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 620302796 # number of ReadReq MSHR miss cycles
1512system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 19074448661 # number of ReadReq MSHR miss cycles
1513system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 20168472472 # number of ReadReq MSHR miss cycles
1514system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of HardPFReq MSHR miss cycles
1515system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 79252881469 # number of HardPFReq MSHR miss cycles
1516system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 33127814392 # number of WriteInvalidateReq MSHR miss cycles
1517system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 33127814392 # number of WriteInvalidateReq MSHR miss cycles
1518system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2005449750 # number of UpgradeReq MSHR miss cycles
1519system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2005449750 # number of UpgradeReq MSHR miss cycles
1520system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 2118741906 # number of SCUpgradeReq MSHR miss cycles
1521system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2118741906 # number of SCUpgradeReq MSHR miss cycles
1522system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1770500 # number of SCUpgradeFailReq MSHR miss cycles
1523system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1770500 # number of SCUpgradeFailReq MSHR miss cycles
1524system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 7853083593 # number of ReadExReq MSHR miss cycles
1525system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 7853083593 # number of ReadExReq MSHR miss cycles
1526system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of demand (read+write) MSHR miss cycles
1527system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 620302796 # number of demand (read+write) MSHR miss cycles
1528system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26927532254 # number of demand (read+write) MSHR miss cycles
1529system.cpu0.l2cache.demand_mshr_miss_latency::total 28021556065 # number of demand (read+write) MSHR miss cycles
1530system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 473721015 # number of overall MSHR miss cycles
1531system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 620302796 # number of overall MSHR miss cycles
1532system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26927532254 # number of overall MSHR miss cycles
1533system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 79252881469 # number of overall MSHR miss cycles
1534system.cpu0.l2cache.overall_mshr_miss_latency::total 107274437534 # number of overall MSHR miss cycles
1535system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6580252048 # number of ReadReq MSHR uncacheable cycles
1536system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6580252048 # number of ReadReq MSHR uncacheable cycles
1537system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2399021553 # number of WriteReq MSHR uncacheable cycles
1538system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2399021553 # number of WriteReq MSHR uncacheable cycles
1539system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 8979273601 # number of overall MSHR uncacheable cycles
1540system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8979273601 # number of overall MSHR uncacheable cycles
1541system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for ReadReq accesses
1542system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for ReadReq accesses
1543system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.066552 # mshr miss rate for ReadReq accesses
1544system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065356 # mshr miss rate for ReadReq accesses
1545system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1546system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1547system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.624622 # mshr miss rate for UpgradeReq accesses
1548system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.624622 # mshr miss rate for UpgradeReq accesses
1549system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813545 # mshr miss rate for SCUpgradeReq accesses
1550system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813545 # mshr miss rate for SCUpgradeReq accesses
1551system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
1552system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1553system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.203142 # mshr miss rate for ReadExReq accesses
1554system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.203142 # mshr miss rate for ReadExReq accesses
1555system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for demand accesses
1556system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for demand accesses
1557system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for demand accesses
1558system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075851 # mshr miss rate for demand accesses
1559system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.030141 # mshr miss rate for overall accesses
1560system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.072521 # mshr miss rate for overall accesses
1561system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077418 # mshr miss rate for overall accesses
1562system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1563system.cpu0.l2cache.overall_mshr_miss_rate::total 0.287096 # mshr miss rate for overall accesses
1564system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average ReadReq mshr miss latency
1565system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average ReadReq mshr miss latency
1566system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22691.090870 # average ReadReq mshr miss latency
1567system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23304.110445 # average ReadReq mshr miss latency
1568system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average HardPFReq mshr miss latency
1569system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 26174.068722 # average HardPFReq mshr miss latency
1570system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency
1571system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1572system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17058.656283 # average UpgradeReq mshr miss latency
1573system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17058.656283 # average UpgradeReq mshr miss latency
1574system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13812.867324 # average SCUpgradeReq mshr miss latency
1575system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13812.867324 # average SCUpgradeReq mshr miss latency
1576system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 590166.666667 # average SCUpgradeFailReq mshr miss latency
1577system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590166.666667 # average SCUpgradeFailReq mshr miss latency
1578system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35410.618081 # average ReadExReq mshr miss latency
1579system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35410.618081 # average ReadExReq mshr miss latency
1580system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency
1581system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency
1582system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency
1583system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25773.607769 # average overall mshr miss latency
1584system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34203.683394 # average overall mshr miss latency
1585system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56478.448147 # average overall mshr miss latency
1586system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25346.279275 # average overall mshr miss latency
1587system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 26174.068722 # average overall mshr miss latency
1588system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 26068.266906 # average overall mshr miss latency
1589system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1590system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1591system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
1592system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1593system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1594system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1595system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1596system.cpu0.dcache.tags.replacements 5337320 # number of replacements
1597system.cpu0.dcache.tags.tagsinuse 473.198574 # Cycle average of tags in use
1598system.cpu0.dcache.tags.total_refs 150291577 # Total number of references to valid blocks.
1599system.cpu0.dcache.tags.sampled_refs 5337832 # Sample count of references to valid blocks.
1600system.cpu0.dcache.tags.avg_refs 28.155921 # Average number of references to valid blocks.
1601system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit.
1602system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.198574 # Average occupied blocks per requestor
1603system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924216 # Average percentage of cache occupancy
1604system.cpu0.dcache.tags.occ_percent::total 0.924216 # Average percentage of cache occupancy
1605system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1606system.cpu0.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
1607system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
1608system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id
1609system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1610system.cpu0.dcache.tags.tag_accesses 319289852 # Number of tag accesses
1611system.cpu0.dcache.tags.data_accesses 319289852 # Number of data accesses
1612system.cpu0.dcache.ReadReq_hits::cpu0.inst 77767484 # number of ReadReq hits
1613system.cpu0.dcache.ReadReq_hits::total 77767484 # number of ReadReq hits
1614system.cpu0.dcache.WriteReq_hits::cpu0.inst 68524145 # number of WriteReq hits
1615system.cpu0.dcache.WriteReq_hits::total 68524145 # number of WriteReq hits
1616system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 878594 # number of WriteInvalidateReq hits
1617system.cpu0.dcache.WriteInvalidateReq_hits::total 878594 # number of WriteInvalidateReq hits
1618system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1744720 # number of LoadLockedReq hits
1619system.cpu0.dcache.LoadLockedReq_hits::total 1744720 # number of LoadLockedReq hits
1620system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1671495 # number of StoreCondReq hits
1621system.cpu0.dcache.StoreCondReq_hits::total 1671495 # number of StoreCondReq hits
1622system.cpu0.dcache.demand_hits::cpu0.inst 146291629 # number of demand (read+write) hits
1623system.cpu0.dcache.demand_hits::total 146291629 # number of demand (read+write) hits
1624system.cpu0.dcache.overall_hits::cpu0.inst 146291629 # number of overall hits
1625system.cpu0.dcache.overall_hits::total 146291629 # number of overall hits
1626system.cpu0.dcache.ReadReq_misses::cpu0.inst 3855307 # number of ReadReq misses
1627system.cpu0.dcache.ReadReq_misses::total 3855307 # number of ReadReq misses
1628system.cpu0.dcache.WriteReq_misses::cpu0.inst 2180509 # number of WriteReq misses
1629system.cpu0.dcache.WriteReq_misses::total 2180509 # number of WriteReq misses
1630system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 116717 # number of LoadLockedReq misses
1631system.cpu0.dcache.LoadLockedReq_misses::total 116717 # number of LoadLockedReq misses
1632system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 188600 # number of StoreCondReq misses
1633system.cpu0.dcache.StoreCondReq_misses::total 188600 # number of StoreCondReq misses
1634system.cpu0.dcache.demand_misses::cpu0.inst 6035816 # number of demand (read+write) misses
1635system.cpu0.dcache.demand_misses::total 6035816 # number of demand (read+write) misses
1636system.cpu0.dcache.overall_misses::cpu0.inst 6035816 # number of overall misses
1637system.cpu0.dcache.overall_misses::total 6035816 # number of overall misses
1638system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 52949262121 # number of ReadReq miss cycles
1639system.cpu0.dcache.ReadReq_miss_latency::total 52949262121 # number of ReadReq miss cycles
1640system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36682258766 # number of WriteReq miss cycles
1641system.cpu0.dcache.WriteReq_miss_latency::total 36682258766 # number of WriteReq miss cycles
1642system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1582680255 # number of LoadLockedReq miss cycles
1643system.cpu0.dcache.LoadLockedReq_miss_latency::total 1582680255 # number of LoadLockedReq miss cycles
1644system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3978646923 # number of StoreCondReq miss cycles
1645system.cpu0.dcache.StoreCondReq_miss_latency::total 3978646923 # number of StoreCondReq miss cycles
1646system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 2553000 # number of StoreCondFailReq miss cycles
1647system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2553000 # number of StoreCondFailReq miss cycles
1648system.cpu0.dcache.demand_miss_latency::cpu0.inst 89631520887 # number of demand (read+write) miss cycles
1649system.cpu0.dcache.demand_miss_latency::total 89631520887 # number of demand (read+write) miss cycles
1650system.cpu0.dcache.overall_miss_latency::cpu0.inst 89631520887 # number of overall miss cycles
1651system.cpu0.dcache.overall_miss_latency::total 89631520887 # number of overall miss cycles
1652system.cpu0.dcache.ReadReq_accesses::cpu0.inst 81622791 # number of ReadReq accesses(hits+misses)
1653system.cpu0.dcache.ReadReq_accesses::total 81622791 # number of ReadReq accesses(hits+misses)
1654system.cpu0.dcache.WriteReq_accesses::cpu0.inst 70704654 # number of WriteReq accesses(hits+misses)
1655system.cpu0.dcache.WriteReq_accesses::total 70704654 # number of WriteReq accesses(hits+misses)
1656system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 878594 # number of WriteInvalidateReq accesses(hits+misses)
1657system.cpu0.dcache.WriteInvalidateReq_accesses::total 878594 # number of WriteInvalidateReq accesses(hits+misses)
1658system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1861437 # number of LoadLockedReq accesses(hits+misses)
1659system.cpu0.dcache.LoadLockedReq_accesses::total 1861437 # number of LoadLockedReq accesses(hits+misses)
1660system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1860095 # number of StoreCondReq accesses(hits+misses)
1661system.cpu0.dcache.StoreCondReq_accesses::total 1860095 # number of StoreCondReq accesses(hits+misses)
1662system.cpu0.dcache.demand_accesses::cpu0.inst 152327445 # number of demand (read+write) accesses
1663system.cpu0.dcache.demand_accesses::total 152327445 # number of demand (read+write) accesses
1664system.cpu0.dcache.overall_accesses::cpu0.inst 152327445 # number of overall (read+write) accesses
1665system.cpu0.dcache.overall_accesses::total 152327445 # number of overall (read+write) accesses
1666system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.047233 # miss rate for ReadReq accesses
1667system.cpu0.dcache.ReadReq_miss_rate::total 0.047233 # miss rate for ReadReq accesses
1668system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030840 # miss rate for WriteReq accesses
1669system.cpu0.dcache.WriteReq_miss_rate::total 0.030840 # miss rate for WriteReq accesses
1670system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.062703 # miss rate for LoadLockedReq accesses
1671system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062703 # miss rate for LoadLockedReq accesses
1672system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.101393 # miss rate for StoreCondReq accesses
1673system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101393 # miss rate for StoreCondReq accesses
1674system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.039624 # miss rate for demand accesses
1675system.cpu0.dcache.demand_miss_rate::total 0.039624 # miss rate for demand accesses
1676system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.039624 # miss rate for overall accesses
1677system.cpu0.dcache.overall_miss_rate::total 0.039624 # miss rate for overall accesses
1678system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 13734.123410 # average ReadReq miss latency
1679system.cpu0.dcache.ReadReq_avg_miss_latency::total 13734.123410 # average ReadReq miss latency
1680system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 16822.796313 # average WriteReq miss latency
1681system.cpu0.dcache.WriteReq_avg_miss_latency::total 16822.796313 # average WriteReq miss latency
1682system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13559.980594 # average LoadLockedReq miss latency
1683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13559.980594 # average LoadLockedReq miss latency
1684system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21095.688881 # average StoreCondReq miss latency
1685system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21095.688881 # average StoreCondReq miss latency
1686system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
1687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1688system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency
1689system.cpu0.dcache.demand_avg_miss_latency::total 14849.942557 # average overall miss latency
1690system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14849.942557 # average overall miss latency
1691system.cpu0.dcache.overall_avg_miss_latency::total 14849.942557 # average overall miss latency
1692system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1693system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1694system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1695system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1696system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1697system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1698system.cpu0.dcache.fast_writes 878594 # number of fast writes performed
1699system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1700system.cpu0.dcache.writebacks::writebacks 2993146 # number of writebacks
1701system.cpu0.dcache.writebacks::total 2993146 # number of writebacks
1702system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 365860 # number of ReadReq MSHR hits
1703system.cpu0.dcache.ReadReq_mshr_hits::total 365860 # number of ReadReq MSHR hits
1704system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 900170 # number of WriteReq MSHR hits
1705system.cpu0.dcache.WriteReq_mshr_hits::total 900170 # number of WriteReq MSHR hits
1706system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 65 # number of LoadLockedReq MSHR hits
1707system.cpu0.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits
1708system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 53 # number of StoreCondReq MSHR hits
1709system.cpu0.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits
1710system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1266030 # number of demand (read+write) MSHR hits
1711system.cpu0.dcache.demand_mshr_hits::total 1266030 # number of demand (read+write) MSHR hits
1712system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1266030 # number of overall MSHR hits
1713system.cpu0.dcache.overall_mshr_hits::total 1266030 # number of overall MSHR hits
1714system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3489447 # number of ReadReq MSHR misses
1715system.cpu0.dcache.ReadReq_mshr_misses::total 3489447 # number of ReadReq MSHR misses
1716system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1279618 # number of WriteReq MSHR misses
1717system.cpu0.dcache.WriteReq_mshr_misses::total 1279618 # number of WriteReq MSHR misses
1718system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 116652 # number of LoadLockedReq MSHR misses
1719system.cpu0.dcache.LoadLockedReq_mshr_misses::total 116652 # number of LoadLockedReq MSHR misses
1720system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 188547 # number of StoreCondReq MSHR misses
1721system.cpu0.dcache.StoreCondReq_mshr_misses::total 188547 # number of StoreCondReq MSHR misses
1722system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4769065 # number of demand (read+write) MSHR misses
1723system.cpu0.dcache.demand_mshr_misses::total 4769065 # number of demand (read+write) MSHR misses
1724system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4769065 # number of overall MSHR misses
1725system.cpu0.dcache.overall_mshr_misses::total 4769065 # number of overall MSHR misses
1726system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 40912958493 # number of ReadReq MSHR miss cycles
1727system.cpu0.dcache.ReadReq_mshr_miss_latency::total 40912958493 # number of ReadReq MSHR miss cycles
1728system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19695838269 # number of WriteReq MSHR miss cycles
1729system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19695838269 # number of WriteReq MSHR miss cycles
1730system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 39725259601 # number of WriteInvalidateReq MSHR miss cycles
1731system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 39725259601 # number of WriteInvalidateReq MSHR miss cycles
1732system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1347811737 # number of LoadLockedReq MSHR miss cycles
1733system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1347811737 # number of LoadLockedReq MSHR miss cycles
1734system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3591126546 # number of StoreCondReq MSHR miss cycles
1735system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3591126546 # number of StoreCondReq MSHR miss cycles
1736system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2234500 # number of StoreCondFailReq MSHR miss cycles
1737system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2234500 # number of StoreCondFailReq MSHR miss cycles
1738system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 60608796762 # number of demand (read+write) MSHR miss cycles
1739system.cpu0.dcache.demand_mshr_miss_latency::total 60608796762 # number of demand (read+write) MSHR miss cycles
1740system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 60608796762 # number of overall MSHR miss cycles
1741system.cpu0.dcache.overall_mshr_miss_latency::total 60608796762 # number of overall MSHR miss cycles
1742system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2590105703 # number of ReadReq MSHR uncacheable cycles
1743system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2590105703 # number of ReadReq MSHR uncacheable cycles
1744system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2521930197 # number of WriteReq MSHR uncacheable cycles
1745system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2521930197 # number of WriteReq MSHR uncacheable cycles
1746system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 5112035900 # number of overall MSHR uncacheable cycles
1747system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5112035900 # number of overall MSHR uncacheable cycles
1748system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.042751 # mshr miss rate for ReadReq accesses
1749system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.042751 # mshr miss rate for ReadReq accesses
1750system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.018098 # mshr miss rate for WriteReq accesses
1751system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018098 # mshr miss rate for WriteReq accesses
1752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.062668 # mshr miss rate for LoadLockedReq accesses
1753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062668 # mshr miss rate for LoadLockedReq accesses
1754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.101364 # mshr miss rate for StoreCondReq accesses
1755system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101364 # mshr miss rate for StoreCondReq accesses
1756system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for demand accesses
1757system.cpu0.dcache.demand_mshr_miss_rate::total 0.031308 # mshr miss rate for demand accesses
1758system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031308 # mshr miss rate for overall accesses
1759system.cpu0.dcache.overall_mshr_miss_rate::total 0.031308 # mshr miss rate for overall accesses
1760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11724.768564 # average ReadReq mshr miss latency
1761system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11724.768564 # average ReadReq mshr miss latency
1762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 15391.967188 # average WriteReq mshr miss latency
1763system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15391.967188 # average WriteReq mshr miss latency
1764system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst inf # average WriteInvalidateReq mshr miss latency
1765system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11554.124550 # average LoadLockedReq mshr miss latency
1767system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11554.124550 # average LoadLockedReq mshr miss latency
1768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19046.320260 # average StoreCondReq mshr miss latency
1769system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19046.320260 # average StoreCondReq mshr miss latency
1770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
1771system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency
1773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency
1774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12708.737826 # average overall mshr miss latency
1775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12708.737826 # average overall mshr miss latency
1776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
1779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1783system.cpu1.branchPred.lookups 124419206 # Number of BP lookups
1784system.cpu1.branchPred.condPredicted 87805046 # Number of conditional branches predicted
1785system.cpu1.branchPred.condIncorrect 6051921 # Number of conditional branches incorrect
1786system.cpu1.branchPred.BTBLookups 92935126 # Number of BTB lookups
1787system.cpu1.branchPred.BTBHits 66733716 # Number of BTB hits
1788system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1789system.cpu1.branchPred.BTBHitPct 71.806774 # BTB Hit Percentage
1790system.cpu1.branchPred.usedRAS 14888837 # Number of times the RAS was used to get a target.
1791system.cpu1.branchPred.RASInCorrect 1052333 # Number of incorrect RAS predictions.
1792system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1793system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1794system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1795system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1796system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1797system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1798system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1799system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1807system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1808system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1809system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1810system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1811system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1812system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1813system.cpu1.dtb.inst_hits 0 # ITB inst hits
1814system.cpu1.dtb.inst_misses 0 # ITB inst misses
1815system.cpu1.dtb.read_hits 80858392 # DTB read hits
1816system.cpu1.dtb.read_misses 227532 # DTB read misses
1817system.cpu1.dtb.write_hits 71539111 # DTB write hits
1818system.cpu1.dtb.write_misses 46368 # DTB write misses
1819system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1820system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1821system.cpu1.dtb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
1822system.cpu1.dtb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
1823system.cpu1.dtb.flush_entries 35324 # Number of entries that have been flushed from TLB
1824system.cpu1.dtb.align_faults 1220 # Number of TLB faults due to alignment restrictions
1825system.cpu1.dtb.prefetch_faults 8196 # Number of TLB faults due to prefetch
1826system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1827system.cpu1.dtb.perms_faults 10514 # Number of TLB faults due to permissions restrictions
1828system.cpu1.dtb.read_accesses 81085924 # DTB read accesses
1829system.cpu1.dtb.write_accesses 71585479 # DTB write accesses
1830system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1831system.cpu1.dtb.hits 152397503 # DTB hits
1832system.cpu1.dtb.misses 273900 # DTB misses
1833system.cpu1.dtb.accesses 152671403 # DTB accesses
1834system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1835system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1836system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1837system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1838system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1839system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1840system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1841system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1847system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1848system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1849system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1850system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1851system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1852system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1853system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1854system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1855system.cpu1.itb.inst_hits 221287255 # ITB inst hits
1856system.cpu1.itb.inst_misses 68040 # ITB inst misses
1857system.cpu1.itb.read_hits 0 # DTB read hits
1858system.cpu1.itb.read_misses 0 # DTB read misses
1859system.cpu1.itb.write_hits 0 # DTB write hits
1860system.cpu1.itb.write_misses 0 # DTB write misses
1861system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1862system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1863system.cpu1.itb.flush_tlb_mva_asid 38216 # Number of times TLB was flushed by MVA & ASID
1864system.cpu1.itb.flush_tlb_asid 1002 # Number of times TLB was flushed by ASID
1865system.cpu1.itb.flush_entries 25097 # Number of entries that have been flushed from TLB
1866system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1867system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1868system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1869system.cpu1.itb.perms_faults 202601 # Number of TLB faults due to permissions restrictions
1870system.cpu1.itb.read_accesses 0 # DTB read accesses
1871system.cpu1.itb.write_accesses 0 # DTB write accesses
1872system.cpu1.itb.inst_accesses 221355295 # ITB inst accesses
1873system.cpu1.itb.hits 221287255 # DTB hits
1874system.cpu1.itb.misses 68040 # DTB misses
1875system.cpu1.itb.accesses 221355295 # DTB accesses
1876system.cpu1.numCycles 841372178 # number of cpu cycles simulated
1877system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1878system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1879system.cpu1.committedInsts 411163350 # Number of instructions committed
1880system.cpu1.committedOps 484726757 # Number of ops (including micro ops) committed
1881system.cpu1.discardedOps 42974941 # Number of ops (including micro ops) which were discarded before commit
1882system.cpu1.numFetchSuspends 4643 # Number of times Execute suspended instruction fetching
1883system.cpu1.quiesceCycles 93858235376 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1884system.cpu1.cpi 2.046321 # CPI: cycles per instruction
1885system.cpu1.ipc 0.488682 # IPC: instructions per cycle
1886system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1887system.cpu1.kern.inst.quiesce 13250 # number of quiesce instructions executed
1888system.cpu1.tickCycles 646022417 # Number of cycles that the object actually ticked
1889system.cpu1.idleCycles 195349761 # Total number of cycles that the object has spent stopped
1890system.cpu1.icache.tags.replacements 9199343 # number of replacements
1891system.cpu1.icache.tags.tagsinuse 507.111645 # Cycle average of tags in use
1892system.cpu1.icache.tags.total_refs 211878543 # Total number of references to valid blocks.
1893system.cpu1.icache.tags.sampled_refs 9199855 # Sample count of references to valid blocks.
1894system.cpu1.icache.tags.avg_refs 23.030639 # Average number of references to valid blocks.
1895system.cpu1.icache.tags.warmup_cycle 8364993861000 # Cycle when the warmup percentage was hit.
1896system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.111645 # Average occupied blocks per requestor
1897system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990452 # Average percentage of cache occupancy
1898system.cpu1.icache.tags.occ_percent::total 0.990452 # Average percentage of cache occupancy
1899system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1900system.cpu1.icache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
1901system.cpu1.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
1902system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1903system.cpu1.icache.tags.tag_accesses 451356678 # Number of tag accesses
1904system.cpu1.icache.tags.data_accesses 451356678 # Number of data accesses
1905system.cpu1.icache.ReadReq_hits::cpu1.inst 211878543 # number of ReadReq hits
1906system.cpu1.icache.ReadReq_hits::total 211878543 # number of ReadReq hits
1907system.cpu1.icache.demand_hits::cpu1.inst 211878543 # number of demand (read+write) hits
1908system.cpu1.icache.demand_hits::total 211878543 # number of demand (read+write) hits
1909system.cpu1.icache.overall_hits::cpu1.inst 211878543 # number of overall hits
1910system.cpu1.icache.overall_hits::total 211878543 # number of overall hits
1911system.cpu1.icache.ReadReq_misses::cpu1.inst 9199864 # number of ReadReq misses
1912system.cpu1.icache.ReadReq_misses::total 9199864 # number of ReadReq misses
1913system.cpu1.icache.demand_misses::cpu1.inst 9199864 # number of demand (read+write) misses
1914system.cpu1.icache.demand_misses::total 9199864 # number of demand (read+write) misses
1915system.cpu1.icache.overall_misses::cpu1.inst 9199864 # number of overall misses
1916system.cpu1.icache.overall_misses::total 9199864 # number of overall misses
1917system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 77780449816 # number of ReadReq miss cycles
1918system.cpu1.icache.ReadReq_miss_latency::total 77780449816 # number of ReadReq miss cycles
1919system.cpu1.icache.demand_miss_latency::cpu1.inst 77780449816 # number of demand (read+write) miss cycles
1920system.cpu1.icache.demand_miss_latency::total 77780449816 # number of demand (read+write) miss cycles
1921system.cpu1.icache.overall_miss_latency::cpu1.inst 77780449816 # number of overall miss cycles
1922system.cpu1.icache.overall_miss_latency::total 77780449816 # number of overall miss cycles
1923system.cpu1.icache.ReadReq_accesses::cpu1.inst 221078407 # number of ReadReq accesses(hits+misses)
1924system.cpu1.icache.ReadReq_accesses::total 221078407 # number of ReadReq accesses(hits+misses)
1925system.cpu1.icache.demand_accesses::cpu1.inst 221078407 # number of demand (read+write) accesses
1926system.cpu1.icache.demand_accesses::total 221078407 # number of demand (read+write) accesses
1927system.cpu1.icache.overall_accesses::cpu1.inst 221078407 # number of overall (read+write) accesses
1928system.cpu1.icache.overall_accesses::total 221078407 # number of overall (read+write) accesses
1929system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.041614 # miss rate for ReadReq accesses
1930system.cpu1.icache.ReadReq_miss_rate::total 0.041614 # miss rate for ReadReq accesses
1931system.cpu1.icache.demand_miss_rate::cpu1.inst 0.041614 # miss rate for demand accesses
1932system.cpu1.icache.demand_miss_rate::total 0.041614 # miss rate for demand accesses
1933system.cpu1.icache.overall_miss_rate::cpu1.inst 0.041614 # miss rate for overall accesses
1934system.cpu1.icache.overall_miss_rate::total 0.041614 # miss rate for overall accesses
1935system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8454.521699 # average ReadReq miss latency
1936system.cpu1.icache.ReadReq_avg_miss_latency::total 8454.521699 # average ReadReq miss latency
1937system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency
1938system.cpu1.icache.demand_avg_miss_latency::total 8454.521699 # average overall miss latency
1939system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8454.521699 # average overall miss latency
1940system.cpu1.icache.overall_avg_miss_latency::total 8454.521699 # average overall miss latency
1941system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1942system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1943system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1944system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1945system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1946system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1947system.cpu1.icache.fast_writes 0 # number of fast writes performed
1948system.cpu1.icache.cache_copies 0 # number of cache copies performed
1949system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9199864 # number of ReadReq MSHR misses
1950system.cpu1.icache.ReadReq_mshr_misses::total 9199864 # number of ReadReq MSHR misses
1951system.cpu1.icache.demand_mshr_misses::cpu1.inst 9199864 # number of demand (read+write) MSHR misses
1952system.cpu1.icache.demand_mshr_misses::total 9199864 # number of demand (read+write) MSHR misses
1953system.cpu1.icache.overall_mshr_misses::cpu1.inst 9199864 # number of overall MSHR misses
1954system.cpu1.icache.overall_mshr_misses::total 9199864 # number of overall MSHR misses
1955system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63970402202 # number of ReadReq MSHR miss cycles
1956system.cpu1.icache.ReadReq_mshr_miss_latency::total 63970402202 # number of ReadReq MSHR miss cycles
1957system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63970402202 # number of demand (read+write) MSHR miss cycles
1958system.cpu1.icache.demand_mshr_miss_latency::total 63970402202 # number of demand (read+write) MSHR miss cycles
1959system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63970402202 # number of overall MSHR miss cycles
1960system.cpu1.icache.overall_mshr_miss_latency::total 63970402202 # number of overall MSHR miss cycles
1961system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8551999 # number of ReadReq MSHR uncacheable cycles
1962system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8551999 # number of ReadReq MSHR uncacheable cycles
1963system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8551999 # number of overall MSHR uncacheable cycles
1964system.cpu1.icache.overall_mshr_uncacheable_latency::total 8551999 # number of overall MSHR uncacheable cycles
1965system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for ReadReq accesses
1966system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.041614 # mshr miss rate for ReadReq accesses
1967system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for demand accesses
1968system.cpu1.icache.demand_mshr_miss_rate::total 0.041614 # mshr miss rate for demand accesses
1969system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.041614 # mshr miss rate for overall accesses
1970system.cpu1.icache.overall_mshr_miss_rate::total 0.041614 # mshr miss rate for overall accesses
1971system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average ReadReq mshr miss latency
1972system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6953.407377 # average ReadReq mshr miss latency
1973system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency
1974system.cpu1.icache.demand_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency
1975system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6953.407377 # average overall mshr miss latency
1976system.cpu1.icache.overall_avg_mshr_miss_latency::total 6953.407377 # average overall mshr miss latency
1977system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1978system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1979system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1980system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1981system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1982system.cpu1.toL2Bus.trans_dist::ReadReq 16974832 # Transaction distribution
1983system.cpu1.toL2Bus.trans_dist::ReadResp 13523495 # Transaction distribution
1984system.cpu1.toL2Bus.trans_dist::WriteReq 21560 # Transaction distribution
1985system.cpu1.toL2Bus.trans_dist::WriteResp 21560 # Transaction distribution
1986system.cpu1.toL2Bus.trans_dist::Writeback 2756922 # Transaction distribution
1987system.cpu1.toL2Bus.trans_dist::HardPFReq 3912463 # Transaction distribution
1988system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1665553 # Transaction distribution
1989system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 680221 # Transaction distribution
1990system.cpu1.toL2Bus.trans_dist::UpgradeReq 382477 # Transaction distribution
1991system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337171 # Transaction distribution
1992system.cpu1.toL2Bus.trans_dist::UpgradeResp 432582 # Transaction distribution
1993system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
1994system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
1995system.cpu1.toL2Bus.trans_dist::ReadExReq 1151878 # Transaction distribution
1996system.cpu1.toL2Bus.trans_dist::ReadExResp 1012928 # Transaction distribution
1997system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18399906 # Packet count per connected master and slave (bytes)
1998system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13962178 # Packet count per connected master and slave (bytes)
1999system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 374507 # Packet count per connected master and slave (bytes)
2000system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1077414 # Packet count per connected master and slave (bytes)
2001system.cpu1.toL2Bus.pkt_count::total 33814005 # Packet count per connected master and slave (bytes)
2002system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 588796992 # Cumulative packet size per connected master and slave (bytes)
2003system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 509690879 # Cumulative packet size per connected master and slave (bytes)
2004system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1369000 # Cumulative packet size per connected master and slave (bytes)
2005system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3931224 # Cumulative packet size per connected master and slave (bytes)
2006system.cpu1.toL2Bus.pkt_size::total 1103788095 # Cumulative packet size per connected master and slave (bytes)
2007system.cpu1.toL2Bus.snoops 9217690 # Total snoops (count)
2008system.cpu1.toL2Bus.snoop_fanout::samples 27159033 # Request fanout histogram
2009system.cpu1.toL2Bus.snoop_fanout::mean 5.328913 # Request fanout histogram
2010system.cpu1.toL2Bus.snoop_fanout::stdev 0.469818 # Request fanout histogram
2011system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2012system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2013system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2014system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2015system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2016system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2017system.cpu1.toL2Bus.snoop_fanout::5 18226076 67.11% 67.11% # Request fanout histogram
2018system.cpu1.toL2Bus.snoop_fanout::6 8932957 32.89% 100.00% # Request fanout histogram
2019system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2020system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
2021system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
2022system.cpu1.toL2Bus.snoop_fanout::total 27159033 # Request fanout histogram
2023system.cpu1.toL2Bus.reqLayer0.occupancy 12584209028 # Layer occupancy (ticks)
2024system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2025system.cpu1.toL2Bus.snoopLayer0.occupancy 175099992 # Layer occupancy (ticks)
2026system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2027system.cpu1.toL2Bus.respLayer0.occupancy 13805070808 # Layer occupancy (ticks)
2028system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2029system.cpu1.toL2Bus.respLayer1.occupancy 7247611234 # Layer occupancy (ticks)
2030system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2031system.cpu1.toL2Bus.respLayer2.occupancy 204139691 # Layer occupancy (ticks)
2032system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2033system.cpu1.toL2Bus.respLayer3.occupancy 586587181 # Layer occupancy (ticks)
2034system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2035system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 79358164 # number of hwpf identified
2036system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 1355061 # number of hwpf that were already in mshr
2037system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 75203006 # number of hwpf that were already in the cache
2038system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 49096 # number of hwpf that were already in the prefetch queue
2039system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
2040system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 3073 # number of hwpf removed because MSHR allocated
2041system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2747928 # number of hwpf issued
2042system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6733876 # number of hwpf spanning a virtual page
2043system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
2044system.cpu1.l2cache.tags.replacements 3063828 # number of replacements
2045system.cpu1.l2cache.tags.tagsinuse 13784.638052 # Cycle average of tags in use
2046system.cpu1.l2cache.tags.total_refs 15005563 # Total number of references to valid blocks.
2047system.cpu1.l2cache.tags.sampled_refs 3079680 # Sample count of references to valid blocks.
2048system.cpu1.l2cache.tags.avg_refs 4.872442 # Average number of references to valid blocks.
2049system.cpu1.l2cache.tags.warmup_cycle 9994842368500 # Cycle when the warmup percentage was hit.
2050system.cpu1.l2cache.tags.occ_blocks::writebacks 2928.842366 # Average occupied blocks per requestor
2051system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.432287 # Average occupied blocks per requestor
2052system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 61.914602 # Average occupied blocks per requestor
2053system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.974382 # Average occupied blocks per requestor
2054system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 7961.474415 # Average occupied blocks per requestor
2055system.cpu1.l2cache.tags.occ_percent::writebacks 0.178762 # Average percentage of cache occupancy
2056system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004116 # Average percentage of cache occupancy
2057system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003779 # Average percentage of cache occupancy
2058system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168761 # Average percentage of cache occupancy
2059system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.485930 # Average percentage of cache occupancy
2060system.cpu1.l2cache.tags.occ_percent::total 0.841348 # Average percentage of cache occupancy
2061system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9851 # Occupied blocks per task id
2062system.cpu1.l2cache.tags.occ_task_id_blocks::1023 102 # Occupied blocks per task id
2063system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5899 # Occupied blocks per task id
2064system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 232 # Occupied blocks per task id
2065system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4639 # Occupied blocks per task id
2066system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3547 # Occupied blocks per task id
2067system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1433 # Occupied blocks per task id
2068system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
2069system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 75 # Occupied blocks per task id
2070system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id
2071system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
2072system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
2073system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2951 # Occupied blocks per task id
2074system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2204 # Occupied blocks per task id
2075system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 483 # Occupied blocks per task id
2076system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.601257 # Percentage of cache occupancy per task id
2077system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006226 # Percentage of cache occupancy per task id
2078system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.360046 # Percentage of cache occupancy per task id
2079system.cpu1.l2cache.tags.tag_accesses 294450591 # Number of tag accesses
2080system.cpu1.l2cache.tags.data_accesses 294450591 # Number of data accesses
2081system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 477253 # number of ReadReq hits
2082system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159835 # number of ReadReq hits
2083system.cpu1.l2cache.ReadReq_hits::cpu1.inst 11727223 # number of ReadReq hits
2084system.cpu1.l2cache.ReadReq_hits::total 12364311 # number of ReadReq hits
2085system.cpu1.l2cache.Writeback_hits::writebacks 2756922 # number of Writeback hits
2086system.cpu1.l2cache.Writeback_hits::total 2756922 # number of Writeback hits
2087system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 68490 # number of UpgradeReq hits
2088system.cpu1.l2cache.UpgradeReq_hits::total 68490 # number of UpgradeReq hits
2089system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 32200 # number of SCUpgradeReq hits
2090system.cpu1.l2cache.SCUpgradeReq_hits::total 32200 # number of SCUpgradeReq hits
2091system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 776956 # number of ReadExReq hits
2092system.cpu1.l2cache.ReadExReq_hits::total 776956 # number of ReadExReq hits
2093system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 477253 # number of demand (read+write) hits
2094system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159835 # number of demand (read+write) hits
2095system.cpu1.l2cache.demand_hits::cpu1.inst 12504179 # number of demand (read+write) hits
2096system.cpu1.l2cache.demand_hits::total 13141267 # number of demand (read+write) hits
2097system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 477253 # number of overall hits
2098system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159835 # number of overall hits
2099system.cpu1.l2cache.overall_hits::cpu1.inst 12504179 # number of overall hits
2100system.cpu1.l2cache.overall_hits::total 13141267 # number of overall hits
2101system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14150 # number of ReadReq misses
2102system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11290 # number of ReadReq misses
2103system.cpu1.l2cache.ReadReq_misses::cpu1.inst 893170 # number of ReadReq misses
2104system.cpu1.l2cache.ReadReq_misses::total 918610 # number of ReadReq misses
2105system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 118620 # number of UpgradeReq misses
2106system.cpu1.l2cache.UpgradeReq_misses::total 118620 # number of UpgradeReq misses
2107system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 151637 # number of SCUpgradeReq misses
2108system.cpu1.l2cache.SCUpgradeReq_misses::total 151637 # number of SCUpgradeReq misses
2109system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 5 # number of SCUpgradeFailReq misses
2110system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
2111system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 230937 # number of ReadExReq misses
2112system.cpu1.l2cache.ReadExReq_misses::total 230937 # number of ReadExReq misses
2113system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14150 # number of demand (read+write) misses
2114system.cpu1.l2cache.demand_misses::cpu1.itb.walker 11290 # number of demand (read+write) misses
2115system.cpu1.l2cache.demand_misses::cpu1.inst 1124107 # number of demand (read+write) misses
2116system.cpu1.l2cache.demand_misses::total 1149547 # number of demand (read+write) misses
2117system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14150 # number of overall misses
2118system.cpu1.l2cache.overall_misses::cpu1.itb.walker 11290 # number of overall misses
2119system.cpu1.l2cache.overall_misses::cpu1.inst 1124107 # number of overall misses
2120system.cpu1.l2cache.overall_misses::total 1149547 # number of overall misses
2121system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 593312131 # number of ReadReq miss cycles
2122system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 709102173 # number of ReadReq miss cycles
2123system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 26528840524 # number of ReadReq miss cycles
2124system.cpu1.l2cache.ReadReq_miss_latency::total 27831254828 # number of ReadReq miss cycles
2125system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2374329628 # number of UpgradeReq miss cycles
2126system.cpu1.l2cache.UpgradeReq_miss_latency::total 2374329628 # number of UpgradeReq miss cycles
2127system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 3078262421 # number of SCUpgradeReq miss cycles
2128system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3078262421 # number of SCUpgradeReq miss cycles
2129system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2493000 # number of SCUpgradeFailReq miss cycles
2130system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2493000 # number of SCUpgradeFailReq miss cycles
2131system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9672285471 # number of ReadExReq miss cycles
2132system.cpu1.l2cache.ReadExReq_miss_latency::total 9672285471 # number of ReadExReq miss cycles
2133system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 593312131 # number of demand (read+write) miss cycles
2134system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 709102173 # number of demand (read+write) miss cycles
2135system.cpu1.l2cache.demand_miss_latency::cpu1.inst 36201125995 # number of demand (read+write) miss cycles
2136system.cpu1.l2cache.demand_miss_latency::total 37503540299 # number of demand (read+write) miss cycles
2137system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 593312131 # number of overall miss cycles
2138system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 709102173 # number of overall miss cycles
2139system.cpu1.l2cache.overall_miss_latency::cpu1.inst 36201125995 # number of overall miss cycles
2140system.cpu1.l2cache.overall_miss_latency::total 37503540299 # number of overall miss cycles
2141system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 491403 # number of ReadReq accesses(hits+misses)
2142system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 171125 # number of ReadReq accesses(hits+misses)
2143system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 12620393 # number of ReadReq accesses(hits+misses)
2144system.cpu1.l2cache.ReadReq_accesses::total 13282921 # number of ReadReq accesses(hits+misses)
2145system.cpu1.l2cache.Writeback_accesses::writebacks 2756922 # number of Writeback accesses(hits+misses)
2146system.cpu1.l2cache.Writeback_accesses::total 2756922 # number of Writeback accesses(hits+misses)
2147system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 187110 # number of UpgradeReq accesses(hits+misses)
2148system.cpu1.l2cache.UpgradeReq_accesses::total 187110 # number of UpgradeReq accesses(hits+misses)
2149system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 183837 # number of SCUpgradeReq accesses(hits+misses)
2150system.cpu1.l2cache.SCUpgradeReq_accesses::total 183837 # number of SCUpgradeReq accesses(hits+misses)
2151system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 5 # number of SCUpgradeFailReq accesses(hits+misses)
2152system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
2153system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1007893 # number of ReadExReq accesses(hits+misses)
2154system.cpu1.l2cache.ReadExReq_accesses::total 1007893 # number of ReadExReq accesses(hits+misses)
2155system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 491403 # number of demand (read+write) accesses
2156system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 171125 # number of demand (read+write) accesses
2157system.cpu1.l2cache.demand_accesses::cpu1.inst 13628286 # number of demand (read+write) accesses
2158system.cpu1.l2cache.demand_accesses::total 14290814 # number of demand (read+write) accesses
2159system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 491403 # number of overall (read+write) accesses
2160system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 171125 # number of overall (read+write) accesses
2161system.cpu1.l2cache.overall_accesses::cpu1.inst 13628286 # number of overall (read+write) accesses
2162system.cpu1.l2cache.overall_accesses::total 14290814 # number of overall (read+write) accesses
2163system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for ReadReq accesses
2164system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065975 # miss rate for ReadReq accesses
2165system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.070772 # miss rate for ReadReq accesses
2166system.cpu1.l2cache.ReadReq_miss_rate::total 0.069157 # miss rate for ReadReq accesses
2167system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.633959 # miss rate for UpgradeReq accesses
2168system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.633959 # miss rate for UpgradeReq accesses
2169system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.824845 # miss rate for SCUpgradeReq accesses
2170system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.824845 # miss rate for SCUpgradeReq accesses
2171system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses
2172system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2173system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.229128 # miss rate for ReadExReq accesses
2174system.cpu1.l2cache.ReadExReq_miss_rate::total 0.229128 # miss rate for ReadExReq accesses
2175system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for demand accesses
2176system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065975 # miss rate for demand accesses
2177system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.082483 # miss rate for demand accesses
2178system.cpu1.l2cache.demand_miss_rate::total 0.080440 # miss rate for demand accesses
2179system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028795 # miss rate for overall accesses
2180system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065975 # miss rate for overall accesses
2181system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.082483 # miss rate for overall accesses
2182system.cpu1.l2cache.overall_miss_rate::total 0.080440 # miss rate for overall accesses
2183system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average ReadReq miss latency
2184system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 62807.986980 # average ReadReq miss latency
2185system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29701.893843 # average ReadReq miss latency
2186system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30297.138969 # average ReadReq miss latency
2187system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 20016.267307 # average UpgradeReq miss latency
2188system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20016.267307 # average UpgradeReq miss latency
2189system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20300.206552 # average SCUpgradeReq miss latency
2190system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20300.206552 # average SCUpgradeReq miss latency
2191system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 498600 # average SCUpgradeFailReq miss latency
2192system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498600 # average SCUpgradeFailReq miss latency
2193system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 41882.788254 # average ReadExReq miss latency
2194system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41882.788254 # average ReadExReq miss latency
2195system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency
2196system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency
2197system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency
2198system.cpu1.l2cache.demand_avg_miss_latency::total 32624.625439 # average overall miss latency
2199system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41930.185936 # average overall miss latency
2200system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 62807.986980 # average overall miss latency
2201system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32204.341753 # average overall miss latency
2202system.cpu1.l2cache.overall_avg_miss_latency::total 32624.625439 # average overall miss latency
2203system.cpu1.l2cache.blocked_cycles::no_mshrs 62499 # number of cycles access was blocked
2204system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2205system.cpu1.l2cache.blocked::no_mshrs 1018 # number of cycles access was blocked
2206system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2207system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 61.393910 # average number of cycles each access was blocked
2208system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2209system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2210system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2211system.cpu1.l2cache.writebacks::writebacks 843330 # number of writebacks
2212system.cpu1.l2cache.writebacks::total 843330 # number of writebacks
2213system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 70371 # number of ReadReq MSHR hits
2214system.cpu1.l2cache.ReadReq_mshr_hits::total 70371 # number of ReadReq MSHR hits
2215system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 5416 # number of ReadExReq MSHR hits
2216system.cpu1.l2cache.ReadExReq_mshr_hits::total 5416 # number of ReadExReq MSHR hits
2217system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 75787 # number of demand (read+write) MSHR hits
2218system.cpu1.l2cache.demand_mshr_hits::total 75787 # number of demand (read+write) MSHR hits
2219system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 75787 # number of overall MSHR hits
2220system.cpu1.l2cache.overall_mshr_hits::total 75787 # number of overall MSHR hits
2221system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14150 # number of ReadReq MSHR misses
2222system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 11290 # number of ReadReq MSHR misses
2223system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 822799 # number of ReadReq MSHR misses
2224system.cpu1.l2cache.ReadReq_mshr_misses::total 848239 # number of ReadReq MSHR misses
2225system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of HardPFReq MSHR misses
2226system.cpu1.l2cache.HardPFReq_mshr_misses::total 2747875 # number of HardPFReq MSHR misses
2227system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 118620 # number of UpgradeReq MSHR misses
2228system.cpu1.l2cache.UpgradeReq_mshr_misses::total 118620 # number of UpgradeReq MSHR misses
2229system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 151637 # number of SCUpgradeReq MSHR misses
2230system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151637 # number of SCUpgradeReq MSHR misses
2231system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 5 # number of SCUpgradeFailReq MSHR misses
2232system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
2233system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 225521 # number of ReadExReq MSHR misses
2234system.cpu1.l2cache.ReadExReq_mshr_misses::total 225521 # number of ReadExReq MSHR misses
2235system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14150 # number of demand (read+write) MSHR misses
2236system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 11290 # number of demand (read+write) MSHR misses
2237system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1048320 # number of demand (read+write) MSHR misses
2238system.cpu1.l2cache.demand_mshr_misses::total 1073760 # number of demand (read+write) MSHR misses
2239system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14150 # number of overall MSHR misses
2240system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 11290 # number of overall MSHR misses
2241system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1048320 # number of overall MSHR misses
2242system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 2747875 # number of overall MSHR misses
2243system.cpu1.l2cache.overall_mshr_misses::total 3821635 # number of overall MSHR misses
2244system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of ReadReq MSHR miss cycles
2245system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 628615807 # number of ReadReq MSHR miss cycles
2246system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 19412995328 # number of ReadReq MSHR miss cycles
2247system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 20535039404 # number of ReadReq MSHR miss cycles
2248system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of HardPFReq MSHR miss cycles
2249system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 69814591572 # number of HardPFReq MSHR miss cycles
2250system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 25734891864 # number of WriteInvalidateReq MSHR miss cycles
2251system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25734891864 # number of WriteInvalidateReq MSHR miss cycles
2252system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 1991641357 # number of UpgradeReq MSHR miss cycles
2253system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 1991641357 # number of UpgradeReq MSHR miss cycles
2254system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2078386327 # number of SCUpgradeReq MSHR miss cycles
2255system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2078386327 # number of SCUpgradeReq MSHR miss cycles
2256system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2045000 # number of SCUpgradeFailReq MSHR miss cycles
2257system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2045000 # number of SCUpgradeFailReq MSHR miss cycles
2258system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 7579512625 # number of ReadExReq MSHR miss cycles
2259system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7579512625 # number of ReadExReq MSHR miss cycles
2260system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of demand (read+write) MSHR miss cycles
2261system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 628615807 # number of demand (read+write) MSHR miss cycles
2262system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 26992507953 # number of demand (read+write) MSHR miss cycles
2263system.cpu1.l2cache.demand_mshr_miss_latency::total 28114552029 # number of demand (read+write) MSHR miss cycles
2264system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 493428269 # number of overall MSHR miss cycles
2265system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 628615807 # number of overall MSHR miss cycles
2266system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 26992507953 # number of overall MSHR miss cycles
2267system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 69814591572 # number of overall MSHR miss cycles
2268system.cpu1.l2cache.overall_mshr_miss_latency::total 97929143601 # number of overall MSHR miss cycles
2269system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3580047284 # number of ReadReq MSHR uncacheable cycles
2270system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3580047284 # number of ReadReq MSHR uncacheable cycles
2271system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3492978036 # number of WriteReq MSHR uncacheable cycles
2272system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3492978036 # number of WriteReq MSHR uncacheable cycles
2273system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7073025320 # number of overall MSHR uncacheable cycles
2274system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7073025320 # number of overall MSHR uncacheable cycles
2275system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for ReadReq accesses
2276system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for ReadReq accesses
2277system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.065196 # mshr miss rate for ReadReq accesses
2278system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.063859 # mshr miss rate for ReadReq accesses
2279system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2280system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2281system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.633959 # mshr miss rate for UpgradeReq accesses
2282system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.633959 # mshr miss rate for UpgradeReq accesses
2283system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.824845 # mshr miss rate for SCUpgradeReq accesses
2284system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824845 # mshr miss rate for SCUpgradeReq accesses
2285system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
2286system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2287system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.223755 # mshr miss rate for ReadExReq accesses
2288system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.223755 # mshr miss rate for ReadExReq accesses
2289system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for demand accesses
2290system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for demand accesses
2291system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for demand accesses
2292system.cpu1.l2cache.demand_mshr_miss_rate::total 0.075136 # mshr miss rate for demand accesses
2293system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028795 # mshr miss rate for overall accesses
2294system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065975 # mshr miss rate for overall accesses
2295system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076922 # mshr miss rate for overall accesses
2296system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2297system.cpu1.l2cache.overall_mshr_miss_rate::total 0.267419 # mshr miss rate for overall accesses
2298system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average ReadReq mshr miss latency
2299system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average ReadReq mshr miss latency
2300system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23593.848957 # average ReadReq mshr miss latency
2301system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24209.025291 # average ReadReq mshr miss latency
2302system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average HardPFReq mshr miss latency
2303system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 25406.756702 # average HardPFReq mshr miss latency
2304system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency
2305system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2306system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16790.097429 # average UpgradeReq mshr miss latency
2307system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16790.097429 # average UpgradeReq mshr miss latency
2308system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13706.327130 # average SCUpgradeReq mshr miss latency
2309system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13706.327130 # average SCUpgradeReq mshr miss latency
2310system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 409000 # average SCUpgradeFailReq mshr miss latency
2311system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 409000 # average SCUpgradeFailReq mshr miss latency
2312system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 33608.899504 # average ReadExReq mshr miss latency
2313system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33608.899504 # average ReadExReq mshr miss latency
2314system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency
2315system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency
2316system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency
2317system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26183.273757 # average overall mshr miss latency
2318system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34871.255760 # average overall mshr miss latency
2319system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55678.990877 # average overall mshr miss latency
2320system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 25748.347788 # average overall mshr miss latency
2321system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 25406.756702 # average overall mshr miss latency
2322system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25624.933726 # average overall mshr miss latency
2323system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2324system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2325system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
2326system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2327system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2328system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2329system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2330system.cpu1.dcache.tags.replacements 4834403 # number of replacements
2331system.cpu1.dcache.tags.tagsinuse 460.748614 # Cycle average of tags in use
2332system.cpu1.dcache.tags.total_refs 144950857 # Total number of references to valid blocks.
2333system.cpu1.dcache.tags.sampled_refs 4834915 # Sample count of references to valid blocks.
2334system.cpu1.dcache.tags.avg_refs 29.980022 # Average number of references to valid blocks.
2335system.cpu1.dcache.tags.warmup_cycle 8365240216000 # Cycle when the warmup percentage was hit.
2336system.cpu1.dcache.tags.occ_blocks::cpu1.inst 460.748614 # Average occupied blocks per requestor
2337system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.899900 # Average percentage of cache occupancy
2338system.cpu1.dcache.tags.occ_percent::total 0.899900 # Average percentage of cache occupancy
2339system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2340system.cpu1.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
2341system.cpu1.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id
2342system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2343system.cpu1.dcache.tags.tag_accesses 306842506 # Number of tag accesses
2344system.cpu1.dcache.tags.data_accesses 306842506 # Number of data accesses
2345system.cpu1.dcache.ReadReq_hits::cpu1.inst 74397461 # number of ReadReq hits
2346system.cpu1.dcache.ReadReq_hits::total 74397461 # number of ReadReq hits
2347system.cpu1.dcache.WriteReq_hits::cpu1.inst 66754653 # number of WriteReq hits
2348system.cpu1.dcache.WriteReq_hits::total 66754653 # number of WriteReq hits
2349system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 680221 # number of WriteInvalidateReq hits
2350system.cpu1.dcache.WriteInvalidateReq_hits::total 680221 # number of WriteInvalidateReq hits
2351system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1623333 # number of LoadLockedReq hits
2352system.cpu1.dcache.LoadLockedReq_hits::total 1623333 # number of LoadLockedReq hits
2353system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1553141 # number of StoreCondReq hits
2354system.cpu1.dcache.StoreCondReq_hits::total 1553141 # number of StoreCondReq hits
2355system.cpu1.dcache.demand_hits::cpu1.inst 141152114 # number of demand (read+write) hits
2356system.cpu1.dcache.demand_hits::total 141152114 # number of demand (read+write) hits
2357system.cpu1.dcache.overall_hits::cpu1.inst 141152114 # number of overall hits
2358system.cpu1.dcache.overall_hits::total 141152114 # number of overall hits
2359system.cpu1.dcache.ReadReq_misses::cpu1.inst 3628151 # number of ReadReq misses
2360system.cpu1.dcache.ReadReq_misses::total 3628151 # number of ReadReq misses
2361system.cpu1.dcache.WriteReq_misses::cpu1.inst 2024929 # number of WriteReq misses
2362system.cpu1.dcache.WriteReq_misses::total 2024929 # number of WriteReq misses
2363system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 114968 # number of LoadLockedReq misses
2364system.cpu1.dcache.LoadLockedReq_misses::total 114968 # number of LoadLockedReq misses
2365system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 183901 # number of StoreCondReq misses
2366system.cpu1.dcache.StoreCondReq_misses::total 183901 # number of StoreCondReq misses
2367system.cpu1.dcache.demand_misses::cpu1.inst 5653080 # number of demand (read+write) misses
2368system.cpu1.dcache.demand_misses::total 5653080 # number of demand (read+write) misses
2369system.cpu1.dcache.overall_misses::cpu1.inst 5653080 # number of overall misses
2370system.cpu1.dcache.overall_misses::total 5653080 # number of overall misses
2371system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 51111445827 # number of ReadReq miss cycles
2372system.cpu1.dcache.ReadReq_miss_latency::total 51111445827 # number of ReadReq miss cycles
2373system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 34750982270 # number of WriteReq miss cycles
2374system.cpu1.dcache.WriteReq_miss_latency::total 34750982270 # number of WriteReq miss cycles
2375system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1576484749 # number of LoadLockedReq miss cycles
2376system.cpu1.dcache.LoadLockedReq_miss_latency::total 1576484749 # number of LoadLockedReq miss cycles
2377system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3893749340 # number of StoreCondReq miss cycles
2378system.cpu1.dcache.StoreCondReq_miss_latency::total 3893749340 # number of StoreCondReq miss cycles
2379system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 2823500 # number of StoreCondFailReq miss cycles
2380system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2823500 # number of StoreCondFailReq miss cycles
2381system.cpu1.dcache.demand_miss_latency::cpu1.inst 85862428097 # number of demand (read+write) miss cycles
2382system.cpu1.dcache.demand_miss_latency::total 85862428097 # number of demand (read+write) miss cycles
2383system.cpu1.dcache.overall_miss_latency::cpu1.inst 85862428097 # number of overall miss cycles
2384system.cpu1.dcache.overall_miss_latency::total 85862428097 # number of overall miss cycles
2385system.cpu1.dcache.ReadReq_accesses::cpu1.inst 78025612 # number of ReadReq accesses(hits+misses)
2386system.cpu1.dcache.ReadReq_accesses::total 78025612 # number of ReadReq accesses(hits+misses)
2387system.cpu1.dcache.WriteReq_accesses::cpu1.inst 68779582 # number of WriteReq accesses(hits+misses)
2388system.cpu1.dcache.WriteReq_accesses::total 68779582 # number of WriteReq accesses(hits+misses)
2389system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 680221 # number of WriteInvalidateReq accesses(hits+misses)
2390system.cpu1.dcache.WriteInvalidateReq_accesses::total 680221 # number of WriteInvalidateReq accesses(hits+misses)
2391system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 1738301 # number of LoadLockedReq accesses(hits+misses)
2392system.cpu1.dcache.LoadLockedReq_accesses::total 1738301 # number of LoadLockedReq accesses(hits+misses)
2393system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 1737042 # number of StoreCondReq accesses(hits+misses)
2394system.cpu1.dcache.StoreCondReq_accesses::total 1737042 # number of StoreCondReq accesses(hits+misses)
2395system.cpu1.dcache.demand_accesses::cpu1.inst 146805194 # number of demand (read+write) accesses
2396system.cpu1.dcache.demand_accesses::total 146805194 # number of demand (read+write) accesses
2397system.cpu1.dcache.overall_accesses::cpu1.inst 146805194 # number of overall (read+write) accesses
2398system.cpu1.dcache.overall_accesses::total 146805194 # number of overall (read+write) accesses
2399system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046499 # miss rate for ReadReq accesses
2400system.cpu1.dcache.ReadReq_miss_rate::total 0.046499 # miss rate for ReadReq accesses
2401system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029441 # miss rate for WriteReq accesses
2402system.cpu1.dcache.WriteReq_miss_rate::total 0.029441 # miss rate for WriteReq accesses
2403system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.066138 # miss rate for LoadLockedReq accesses
2404system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066138 # miss rate for LoadLockedReq accesses
2405system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.105870 # miss rate for StoreCondReq accesses
2406system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105870 # miss rate for StoreCondReq accesses
2407system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.038507 # miss rate for demand accesses
2408system.cpu1.dcache.demand_miss_rate::total 0.038507 # miss rate for demand accesses
2409system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.038507 # miss rate for overall accesses
2410system.cpu1.dcache.overall_miss_rate::total 0.038507 # miss rate for overall accesses
2411system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14087.463787 # average ReadReq miss latency
2412system.cpu1.dcache.ReadReq_avg_miss_latency::total 14087.463787 # average ReadReq miss latency
2413system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 17161.580613 # average WriteReq miss latency
2414system.cpu1.dcache.WriteReq_avg_miss_latency::total 17161.580613 # average WriteReq miss latency
2415system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13712.378653 # average LoadLockedReq miss latency
2416system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13712.378653 # average LoadLockedReq miss latency
2417system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 21173.073230 # average StoreCondReq miss latency
2418system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21173.073230 # average StoreCondReq miss latency
2419system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
2420system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2421system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency
2422system.cpu1.dcache.demand_avg_miss_latency::total 15188.610120 # average overall miss latency
2423system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 15188.610120 # average overall miss latency
2424system.cpu1.dcache.overall_avg_miss_latency::total 15188.610120 # average overall miss latency
2425system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2426system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2427system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2428system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
2429system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2430system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2431system.cpu1.dcache.fast_writes 680221 # number of fast writes performed
2432system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2433system.cpu1.dcache.writebacks::writebacks 2756922 # number of writebacks
2434system.cpu1.dcache.writebacks::total 2756922 # number of writebacks
2435system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 322268 # number of ReadReq MSHR hits
2436system.cpu1.dcache.ReadReq_mshr_hits::total 322268 # number of ReadReq MSHR hits
2437system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 829273 # number of WriteReq MSHR hits
2438system.cpu1.dcache.WriteReq_mshr_hits::total 829273 # number of WriteReq MSHR hits
2439system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 78 # number of LoadLockedReq MSHR hits
2440system.cpu1.dcache.LoadLockedReq_mshr_hits::total 78 # number of LoadLockedReq MSHR hits
2441system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 59 # number of StoreCondReq MSHR hits
2442system.cpu1.dcache.StoreCondReq_mshr_hits::total 59 # number of StoreCondReq MSHR hits
2443system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1151541 # number of demand (read+write) MSHR hits
2444system.cpu1.dcache.demand_mshr_hits::total 1151541 # number of demand (read+write) MSHR hits
2445system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1151541 # number of overall MSHR hits
2446system.cpu1.dcache.overall_mshr_hits::total 1151541 # number of overall MSHR hits
2447system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3305883 # number of ReadReq MSHR misses
2448system.cpu1.dcache.ReadReq_mshr_misses::total 3305883 # number of ReadReq MSHR misses
2449system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1194736 # number of WriteReq MSHR misses
2450system.cpu1.dcache.WriteReq_mshr_misses::total 1194736 # number of WriteReq MSHR misses
2451system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 114890 # number of LoadLockedReq MSHR misses
2452system.cpu1.dcache.LoadLockedReq_mshr_misses::total 114890 # number of LoadLockedReq MSHR misses
2453system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 183842 # number of StoreCondReq MSHR misses
2454system.cpu1.dcache.StoreCondReq_mshr_misses::total 183842 # number of StoreCondReq MSHR misses
2455system.cpu1.dcache.demand_mshr_misses::cpu1.inst 4500619 # number of demand (read+write) MSHR misses
2456system.cpu1.dcache.demand_mshr_misses::total 4500619 # number of demand (read+write) MSHR misses
2457system.cpu1.dcache.overall_mshr_misses::cpu1.inst 4500619 # number of overall MSHR misses
2458system.cpu1.dcache.overall_mshr_misses::total 4500619 # number of overall MSHR misses
2459system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 39848912237 # number of ReadReq MSHR miss cycles
2460system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39848912237 # number of ReadReq MSHR miss cycles
2461system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 18776610903 # number of WriteReq MSHR miss cycles
2462system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18776610903 # number of WriteReq MSHR miss cycles
2463system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 30844406102 # number of WriteInvalidateReq MSHR miss cycles
2464system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30844406102 # number of WriteInvalidateReq MSHR miss cycles
2465system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1344930230 # number of LoadLockedReq MSHR miss cycles
2466system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1344930230 # number of LoadLockedReq MSHR miss cycles
2467system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3516398127 # number of StoreCondReq MSHR miss cycles
2468system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3516398127 # number of StoreCondReq MSHR miss cycles
2469system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2557000 # number of StoreCondFailReq MSHR miss cycles
2470system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2557000 # number of StoreCondFailReq MSHR miss cycles
2471system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 58625523140 # number of demand (read+write) MSHR miss cycles
2472system.cpu1.dcache.demand_mshr_miss_latency::total 58625523140 # number of demand (read+write) MSHR miss cycles
2473system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 58625523140 # number of overall MSHR miss cycles
2474system.cpu1.dcache.overall_mshr_miss_latency::total 58625523140 # number of overall MSHR miss cycles
2475system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3752867967 # number of ReadReq MSHR uncacheable cycles
2476system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3752867967 # number of ReadReq MSHR uncacheable cycles
2477system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3654726713 # number of WriteReq MSHR uncacheable cycles
2478system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3654726713 # number of WriteReq MSHR uncacheable cycles
2479system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 7407594680 # number of overall MSHR uncacheable cycles
2480system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7407594680 # number of overall MSHR uncacheable cycles
2481system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042369 # mshr miss rate for ReadReq accesses
2482system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042369 # mshr miss rate for ReadReq accesses
2483system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017371 # mshr miss rate for WriteReq accesses
2484system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017371 # mshr miss rate for WriteReq accesses
2485system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.066093 # mshr miss rate for LoadLockedReq accesses
2486system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066093 # mshr miss rate for LoadLockedReq accesses
2487system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.105836 # mshr miss rate for StoreCondReq accesses
2488system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105836 # mshr miss rate for StoreCondReq accesses
2489system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for demand accesses
2490system.cpu1.dcache.demand_mshr_miss_rate::total 0.030657 # mshr miss rate for demand accesses
2491system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030657 # mshr miss rate for overall accesses
2492system.cpu1.dcache.overall_mshr_miss_rate::total 0.030657 # mshr miss rate for overall accesses
2493system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12053.939065 # average ReadReq mshr miss latency
2494system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12053.939065 # average ReadReq mshr miss latency
2495system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 15716.117120 # average WriteReq mshr miss latency
2496system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15716.117120 # average WriteReq mshr miss latency
2497system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst inf # average WriteInvalidateReq mshr miss latency
2498system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2499system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11706.242754 # average LoadLockedReq mshr miss latency
2500system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11706.242754 # average LoadLockedReq mshr miss latency
2501system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 19127.283901 # average StoreCondReq mshr miss latency
2502system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19127.283901 # average StoreCondReq mshr miss latency
2503system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
2504system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2505system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency
2506system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency
2507system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 13026.102218 # average overall mshr miss latency
2508system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13026.102218 # average overall mshr miss latency
2509system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2510system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2511system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
2512system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2513system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2514system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2516system.iocache.tags.replacements 115612 # number of replacements
2517system.iocache.tags.tagsinuse 11.299913 # Cycle average of tags in use
2518system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2519system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
2520system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2521system.iocache.tags.warmup_cycle 9121131291000 # Cycle when the warmup percentage was hit.
2522system.iocache.tags.occ_blocks::realview.ethernet 7.419527 # Average occupied blocks per requestor
2523system.iocache.tags.occ_blocks::realview.ide 3.880386 # Average occupied blocks per requestor
2524system.iocache.tags.occ_percent::realview.ethernet 0.463720 # Average percentage of cache occupancy
2525system.iocache.tags.occ_percent::realview.ide 0.242524 # Average percentage of cache occupancy
2526system.iocache.tags.occ_percent::total 0.706245 # Average percentage of cache occupancy
2527system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2528system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2529system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2530system.iocache.tags.tag_accesses 1042406 # Number of tag accesses
2531system.iocache.tags.data_accesses 1042406 # Number of data accesses
2532system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits
2533system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits
2534system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2535system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
2536system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
2537system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2538system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2539system.iocache.WriteInvalidateReq_misses::realview.ide 187 # number of WriteInvalidateReq misses
2540system.iocache.WriteInvalidateReq_misses::total 187 # number of WriteInvalidateReq misses
2541system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2542system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses
2543system.iocache.demand_misses::total 8929 # number of demand (read+write) misses
2544system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2545system.iocache.overall_misses::realview.ide 8889 # number of overall misses
2546system.iocache.overall_misses::total 8929 # number of overall misses
2547system.iocache.ReadReq_miss_latency::realview.ethernet 5701000 # number of ReadReq miss cycles
2548system.iocache.ReadReq_miss_latency::realview.ide 1965059357 # number of ReadReq miss cycles
2549system.iocache.ReadReq_miss_latency::total 1970760357 # number of ReadReq miss cycles
2550system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles
2551system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles
2552system.iocache.demand_miss_latency::realview.ethernet 6058000 # number of demand (read+write) miss cycles
2553system.iocache.demand_miss_latency::realview.ide 1965059357 # number of demand (read+write) miss cycles
2554system.iocache.demand_miss_latency::total 1971117357 # number of demand (read+write) miss cycles
2555system.iocache.overall_miss_latency::realview.ethernet 6058000 # number of overall miss cycles
2556system.iocache.overall_miss_latency::realview.ide 1965059357 # number of overall miss cycles
2557system.iocache.overall_miss_latency::total 1971117357 # number of overall miss cycles
2558system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2559system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
2560system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
2561system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2562system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2563system.iocache.WriteInvalidateReq_accesses::realview.ide 106915 # number of WriteInvalidateReq accesses(hits+misses)
2564system.iocache.WriteInvalidateReq_accesses::total 106915 # number of WriteInvalidateReq accesses(hits+misses)
2565system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2566system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses
2567system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses
2568system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2569system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses
2570system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses
2571system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2572system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2573system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2574system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2575system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2576system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001749 # miss rate for WriteInvalidateReq accesses
2577system.iocache.WriteInvalidateReq_miss_rate::total 0.001749 # miss rate for WriteInvalidateReq accesses
2578system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2579system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2580system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2581system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2582system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2583system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2584system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154081.081081 # average ReadReq miss latency
2585system.iocache.ReadReq_avg_miss_latency::realview.ide 221066.414332 # average ReadReq miss latency
2586system.iocache.ReadReq_avg_miss_latency::total 220788.747143 # average ReadReq miss latency
2587system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency
2588system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency
2589system.iocache.demand_avg_miss_latency::realview.ethernet 151450 # average overall miss latency
2590system.iocache.demand_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency
2591system.iocache.demand_avg_miss_latency::total 220754.547766 # average overall miss latency
2592system.iocache.overall_avg_miss_latency::realview.ethernet 151450 # average overall miss latency
2593system.iocache.overall_avg_miss_latency::realview.ide 221066.414332 # average overall miss latency
2594system.iocache.overall_avg_miss_latency::total 220754.547766 # average overall miss latency
2595system.iocache.blocked_cycles::no_mshrs 54362 # number of cycles access was blocked
2596system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2597system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
2598system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2599system.iocache.avg_blocked_cycles::no_mshrs 9.902004 # average number of cycles each access was blocked
2600system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2601system.iocache.fast_writes 106728 # number of fast writes performed
2602system.iocache.cache_copies 0 # number of cache copies performed
2603system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2604system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
2605system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
2606system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2607system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2608system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2609system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses
2610system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses
2611system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2612system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses
2613system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses
2614system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3777000 # number of ReadReq MSHR miss cycles
2615system.iocache.ReadReq_mshr_miss_latency::realview.ide 1502702365 # number of ReadReq MSHR miss cycles
2616system.iocache.ReadReq_mshr_miss_latency::total 1506479365 # number of ReadReq MSHR miss cycles
2617system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
2618system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2619system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6627847227 # number of WriteInvalidateReq MSHR miss cycles
2620system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6627847227 # number of WriteInvalidateReq MSHR miss cycles
2621system.iocache.demand_mshr_miss_latency::realview.ethernet 3978000 # number of demand (read+write) MSHR miss cycles
2622system.iocache.demand_mshr_miss_latency::realview.ide 1502702365 # number of demand (read+write) MSHR miss cycles
2623system.iocache.demand_mshr_miss_latency::total 1506680365 # number of demand (read+write) MSHR miss cycles
2624system.iocache.overall_mshr_miss_latency::realview.ethernet 3978000 # number of overall MSHR miss cycles
2625system.iocache.overall_mshr_miss_latency::realview.ide 1502702365 # number of overall MSHR miss cycles
2626system.iocache.overall_mshr_miss_latency::total 1506680365 # number of overall MSHR miss cycles
2627system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2628system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2629system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2630system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2631system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2632system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2633system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2634system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2635system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2636system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2637system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2638system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102081.081081 # average ReadReq mshr miss latency
2639system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 169051.902914 # average ReadReq mshr miss latency
2640system.iocache.ReadReq_avg_mshr_miss_latency::total 168774.295877 # average ReadReq mshr miss latency
2641system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
2642system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2643system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
2644system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2645system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency
2646system.iocache.demand_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency
2647system.iocache.demand_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency
2648system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99450 # average overall mshr miss latency
2649system.iocache.overall_avg_mshr_miss_latency::realview.ide 169051.902914 # average overall mshr miss latency
2650system.iocache.overall_avg_mshr_miss_latency::total 168740.101355 # average overall mshr miss latency
2651system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2652
2653---------- End Simulation Statistics ----------