1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.310816 # Number of seconds simulated
4sim_ticks 47310816168000 # Number of ticks simulated
5final_tick 47310816168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 279196 # Simulator instruction rate (inst/s)
8host_op_rate 332505 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 15871048208 # Simulator tick rate (ticks/s)
10host_mem_usage 770320 # Number of bytes of host memory used
11host_seconds 2980.95 # Real time elapsed on the host
12sim_insts 832269934 # Number of instructions simulated
13sim_ops 991180133 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 133120 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 103552 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 5351360 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 14671112 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 17389824 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 166080 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.itb.walker 153792 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.inst 3559616 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.data 12274128 # Number of bytes read from this memory
26system.physmem.bytes_read::cpu1.l2cache.prefetcher 15128448 # Number of bytes read from this memory
27system.physmem.bytes_read::realview.ide 452672 # Number of bytes read from this memory
28system.physmem.bytes_read::total 69383704 # Number of bytes read from this memory
29system.physmem.bytes_inst_read::cpu0.inst 5351360 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::cpu1.inst 3559616 # Number of instructions bytes read from this memory
31system.physmem.bytes_inst_read::total 8910976 # Number of instructions bytes read from this memory
32system.physmem.bytes_written::writebacks 84006336 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35system.physmem.bytes_written::total 84026920 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 2080 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 1618 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 83615 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 229249 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 271716 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 2595 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 2403 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 55619 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 191796 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 236382 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 7073 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 1084146 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 1312599 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51system.physmem.num_writes::total 1315173 # Number of write requests responded to by this memory
52system.physmem.bw_read::cpu0.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.itb.walker 2189 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.inst 113111 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.data 310101 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.l2cache.prefetcher 367566 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.dtb.walker 3510 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.itb.walker 3251 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.inst 75239 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.data 259436 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.l2cache.prefetcher 319767 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::realview.ide 9568 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::total 1466551 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu0.inst 113111 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu1.inst 75239 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::total 188350 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_write::writebacks 1775626 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::total 1776062 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_total::writebacks 1775626 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.itb.walker 2189 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.inst 113111 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.data 310536 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.l2cache.prefetcher 367566 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.dtb.walker 3510 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.itb.walker 3251 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 75239 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.data 259436 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.l2cache.prefetcher 319767 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::realview.ide 9568 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::total 3242612 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.readReqs 1084146 # Number of read requests accepted
85system.physmem.writeReqs 1315173 # Number of write requests accepted
86system.physmem.readBursts 1084146 # Number of DRAM read bursts, including those serviced by the write queue
87system.physmem.writeBursts 1315173 # Number of DRAM write bursts, including those merged in the write queue
88system.physmem.bytesReadDRAM 69357696 # Total number of bytes read from DRAM
89system.physmem.bytesReadWrQ 27648 # Total number of bytes read from write queue
90system.physmem.bytesWritten 84025344 # Total number of bytes written to DRAM
91system.physmem.bytesReadSys 69383704 # Total read bytes from the system interface side
92system.physmem.bytesWrittenSys 84026920 # Total written bytes from the system interface side
93system.physmem.servicedByWrQ 432 # Number of DRAM read bursts serviced by the write queue
94system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one
95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96system.physmem.perBankRdBursts::0 69238 # Per bank write bursts
97system.physmem.perBankRdBursts::1 72128 # Per bank write bursts
98system.physmem.perBankRdBursts::2 62859 # Per bank write bursts
99system.physmem.perBankRdBursts::3 64909 # Per bank write bursts
100system.physmem.perBankRdBursts::4 64833 # Per bank write bursts
101system.physmem.perBankRdBursts::5 74280 # Per bank write bursts
102system.physmem.perBankRdBursts::6 68552 # Per bank write bursts
103system.physmem.perBankRdBursts::7 74109 # Per bank write bursts
104system.physmem.perBankRdBursts::8 62269 # Per bank write bursts
105system.physmem.perBankRdBursts::9 70311 # Per bank write bursts
106system.physmem.perBankRdBursts::10 59842 # Per bank write bursts
107system.physmem.perBankRdBursts::11 70232 # Per bank write bursts
108system.physmem.perBankRdBursts::12 64744 # Per bank write bursts
109system.physmem.perBankRdBursts::13 72876 # Per bank write bursts
110system.physmem.perBankRdBursts::14 66012 # Per bank write bursts
111system.physmem.perBankRdBursts::15 66520 # Per bank write bursts
112system.physmem.perBankWrBursts::0 83559 # Per bank write bursts
113system.physmem.perBankWrBursts::1 83793 # Per bank write bursts
114system.physmem.perBankWrBursts::2 79464 # Per bank write bursts
115system.physmem.perBankWrBursts::3 82775 # Per bank write bursts
116system.physmem.perBankWrBursts::4 80648 # Per bank write bursts
117system.physmem.perBankWrBursts::5 87124 # Per bank write bursts
118system.physmem.perBankWrBursts::6 80406 # Per bank write bursts
119system.physmem.perBankWrBursts::7 83854 # Per bank write bursts
120system.physmem.perBankWrBursts::8 77300 # Per bank write bursts
121system.physmem.perBankWrBursts::9 82321 # Per bank write bursts
122system.physmem.perBankWrBursts::10 78447 # Per bank write bursts
123system.physmem.perBankWrBursts::11 84798 # Per bank write bursts
124system.physmem.perBankWrBursts::12 79286 # Per bank write bursts
125system.physmem.perBankWrBursts::13 85569 # Per bank write bursts
126system.physmem.perBankWrBursts::14 81705 # Per bank write bursts
127system.physmem.perBankWrBursts::15 81847 # Per bank write bursts
128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129system.physmem.numWrRetry 404 # Number of times write queue was full causing retry
130system.physmem.totGap 47310814104000 # Total gap between requests
131system.physmem.readPktSize::0 0 # Read request sizes (log2)
132system.physmem.readPktSize::1 0 # Read request sizes (log2)
133system.physmem.readPktSize::2 0 # Read request sizes (log2)
134system.physmem.readPktSize::3 25 # Read request sizes (log2)
135system.physmem.readPktSize::4 5 # Read request sizes (log2)
136system.physmem.readPktSize::5 0 # Read request sizes (log2)
137system.physmem.readPktSize::6 1084116 # Read request sizes (log2)
138system.physmem.writePktSize::0 0 # Write request sizes (log2)
139system.physmem.writePktSize::1 0 # Write request sizes (log2)
140system.physmem.writePktSize::2 2 # Write request sizes (log2)
141system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142system.physmem.writePktSize::4 0 # Write request sizes (log2)
143system.physmem.writePktSize::5 0 # Write request sizes (log2)
144system.physmem.writePktSize::6 1312599 # Write request sizes (log2)
145system.physmem.rdQLenPdf::0 617903 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::1 194931 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::2 61099 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::3 46691 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::4 35439 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::5 32251 # What read queue length does an incoming req see
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184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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193system.physmem.wrQLenPdf::16 33833 # What write queue length does an incoming req see
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205system.physmem.wrQLenPdf::28 81110 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::29 82972 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::30 86524 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::31 78237 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::32 73594 # What write queue length does an incoming req see
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211system.physmem.wrQLenPdf::34 2994 # What write queue length does an incoming req see
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214system.physmem.wrQLenPdf::37 1465 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::38 1199 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::39 1020 # What write queue length does an incoming req see
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218system.physmem.wrQLenPdf::41 852 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::42 863 # What write queue length does an incoming req see
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228system.physmem.wrQLenPdf::51 686 # What write queue length does an incoming req see
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230system.physmem.wrQLenPdf::53 659 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::54 618 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::55 582 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::56 844 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::57 711 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::58 546 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::59 766 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::60 1149 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::61 1102 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::62 478 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::63 917 # What write queue length does an incoming req see
241system.physmem.bytesPerActivate::samples 1043685 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::mean 146.962350 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::gmean 99.815605 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::stdev 191.425821 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::0-127 685015 65.63% 65.63% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::128-255 212974 20.41% 86.04% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::256-383 53995 5.17% 91.21% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::384-511 24749 2.37% 93.59% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::512-639 18577 1.78% 95.36% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::640-767 11845 1.13% 96.50% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::768-895 7907 0.76% 97.26% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::896-1023 6706 0.64% 97.90% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::1024-1151 21917 2.10% 100.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::total 1043685 # Bytes accessed per row activation
255system.physmem.rdPerTurnAround::samples 65638 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::mean 16.510147 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::stdev 26.150337 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::0-255 65626 99.98% 99.98% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes
263system.physmem.rdPerTurnAround::total 65638 # Reads before turning the bus around for writes
264system.physmem.wrPerTurnAround::samples 65638 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::mean 20.002072 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::gmean 18.384137 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::stdev 13.246607 # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::16-19 57560 87.69% 87.69% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::20-23 2491 3.80% 91.49% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::24-27 689 1.05% 92.54% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::28-31 564 0.86% 93.40% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::32-35 947 1.44% 94.84% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::36-39 301 0.46% 95.30% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::40-43 320 0.49% 95.79% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::44-47 211 0.32% 96.11% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::48-51 208 0.32% 96.42% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::52-55 135 0.21% 96.63% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::56-59 147 0.22% 96.85% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::60-63 134 0.20% 97.06% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::64-67 619 0.94% 98.00% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::68-71 144 0.22% 98.22% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::72-75 133 0.20% 98.42% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::76-79 128 0.20% 98.62% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::80-83 93 0.14% 98.76% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::84-87 63 0.10% 98.86% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::88-91 64 0.10% 98.95% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::92-95 96 0.15% 99.10% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::96-99 75 0.11% 99.21% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::100-103 71 0.11% 99.32% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::104-107 89 0.14% 99.46% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::108-111 57 0.09% 99.54% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::112-115 53 0.08% 99.63% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::116-119 43 0.07% 99.69% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::120-123 44 0.07% 99.76% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::124-127 41 0.06% 99.82% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::128-131 43 0.07% 99.89% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::132-135 17 0.03% 99.91% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::136-139 9 0.01% 99.93% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::140-143 14 0.02% 99.95% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::144-147 4 0.01% 99.95% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::148-151 2 0.00% 99.96% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::152-155 2 0.00% 99.96% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::156-159 5 0.01% 99.97% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads
305system.physmem.wrPerTurnAround::164-167 2 0.00% 99.97% # Writes before turning the bus around for reads
306system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads
307system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads
308system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads
309system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads
310system.physmem.wrPerTurnAround::192-195 7 0.01% 100.00% # Writes before turning the bus around for reads
311system.physmem.wrPerTurnAround::total 65638 # Writes before turning the bus around for reads
312system.physmem.totQLat 57570179828 # Total ticks spent queuing
313system.physmem.totMemAccLat 77889817328 # Total ticks spent from burst creation until serviced by the DRAM
314system.physmem.totBusLat 5418570000 # Total ticks spent in databus transfers
315system.physmem.avgQLat 53123.04 # Average queueing delay per DRAM burst
316system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
317system.physmem.avgMemAccLat 71873.04 # Average memory access latency per DRAM burst
318system.physmem.avgRdBW 1.47 # Average DRAM read bandwidth in MiByte/s
319system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
320system.physmem.avgRdBWSys 1.47 # Average system read bandwidth in MiByte/s
321system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
322system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
323system.physmem.busUtil 0.03 # Data bus utilization in percentage
324system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
325system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
326system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
327system.physmem.avgWrQLen 24.92 # Average write queue length when enqueuing
328system.physmem.readRowHits 798943 # Number of row buffer hits during reads
329system.physmem.writeRowHits 553978 # Number of row buffer hits during writes
330system.physmem.readRowHitRate 73.72 # Row buffer hit rate for reads
331system.physmem.writeRowHitRate 42.19 # Row buffer hit rate for writes
332system.physmem.avgGap 19718434.32 # Average gap between requests
333system.physmem.pageHitRate 56.45 # Row buffer hit rate, read and write combined
334system.physmem_0.actEnergy 3802085700 # Energy for activate commands per rank (pJ)
335system.physmem_0.preEnergy 2020848885 # Energy for precharge commands per rank (pJ)
336system.physmem_0.readEnergy 3933483120 # Energy for read commands per rank (pJ)
337system.physmem_0.writeEnergy 3453672060 # Energy for write commands per rank (pJ)
338system.physmem_0.refreshEnergy 39277339920.000008 # Energy for refresh commands per rank (pJ)
339system.physmem_0.actBackEnergy 44911710750 # Energy for active background per rank (pJ)
340system.physmem_0.preBackEnergy 1916970240 # Energy for precharge background per rank (pJ)
341system.physmem_0.actPowerDownEnergy 82436275650 # Energy for active power-down per rank (pJ)
342system.physmem_0.prePowerDownEnergy 52427154240 # Energy for precharge power-down per rank (pJ)
343system.physmem_0.selfRefreshEnergy 11259457849125 # Energy for self refresh per rank (pJ)
344system.physmem_0.totalEnergy 11493654896520 # Total energy per rank (pJ)
345system.physmem_0.averagePower 242.939265 # Core power per rank (mW)
346system.physmem_0.totalIdleTime 47207292873414 # Total Idle time Per DRAM Rank
347system.physmem_0.memoryStateTime::IDLE 3245693994 # Time in different power states
348system.physmem_0.memoryStateTime::REF 16679736000 # Time in different power states
349system.physmem_0.memoryStateTime::SREF 46889984158000 # Time in different power states
350system.physmem_0.memoryStateTime::PRE_PDN 136529047983 # Time in different power states
351system.physmem_0.memoryStateTime::ACT 83596561092 # Time in different power states
352system.physmem_0.memoryStateTime::ACT_PDN 180780970931 # Time in different power states
353system.physmem_1.actEnergy 3649853760 # Energy for activate commands per rank (pJ)
354system.physmem_1.preEnergy 1939935690 # Energy for precharge commands per rank (pJ)
355system.physmem_1.readEnergy 3804234840 # Energy for read commands per rank (pJ)
356system.physmem_1.writeEnergy 3399645060 # Energy for write commands per rank (pJ)
357system.physmem_1.refreshEnergy 37874116800.000008 # Energy for refresh commands per rank (pJ)
358system.physmem_1.actBackEnergy 45213068040 # Energy for active background per rank (pJ)
359system.physmem_1.preBackEnergy 1883953920 # Energy for precharge background per rank (pJ)
360system.physmem_1.actPowerDownEnergy 76352255250 # Energy for active power-down per rank (pJ)
361system.physmem_1.prePowerDownEnergy 50620183680 # Energy for precharge power-down per rank (pJ)
362system.physmem_1.selfRefreshEnergy 11263627504680 # Energy for self refresh per rank (pJ)
363system.physmem_1.totalEnergy 11488379615340 # Total energy per rank (pJ)
364system.physmem_1.averagePower 242.827762 # Core power per rank (mW)
365system.physmem_1.totalIdleTime 47206725446684 # Total Idle time Per DRAM Rank
366system.physmem_1.memoryStateTime::IDLE 3212291316 # Time in different power states
367system.physmem_1.memoryStateTime::REF 16085928000 # Time in different power states
368system.physmem_1.memoryStateTime::SREF 46907462906500 # Time in different power states
369system.physmem_1.memoryStateTime::PRE_PDN 131823013391 # Time in different power states
370system.physmem_1.memoryStateTime::ACT 84792497000 # Time in different power states
371system.physmem_1.memoryStateTime::ACT_PDN 167439531793 # Time in different power states
372system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
373system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
374system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
375system.realview.nvmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
376system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
377system.realview.nvmem.bytes_read::total 1388 # Number of bytes read from this memory
378system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
379system.realview.nvmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
380system.realview.nvmem.bytes_inst_read::total 1344 # Number of instructions bytes read from this memory

--- 10 unchanged lines hidden (view full) ---

391system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
392system.realview.nvmem.bw_inst_read::cpu1.inst 14 # Instruction read bandwidth from this memory (bytes/s)
393system.realview.nvmem.bw_inst_read::total 28 # Instruction read bandwidth from this memory (bytes/s)
394system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
395system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
396system.realview.nvmem.bw_total::cpu1.inst 14 # Total bandwidth to/from this memory (bytes/s)
397system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
398system.realview.nvmem.bw_total::total 29 # Total bandwidth to/from this memory (bytes/s)
399system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
400system.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
401system.bridge.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
402system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
403system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
404system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
405system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
406system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
407system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
408system.cpu0.branchPred.lookups 116746639 # Number of BP lookups
409system.cpu0.branchPred.condPredicted 74661681 # Number of conditional branches predicted
410system.cpu0.branchPred.condIncorrect 6562912 # Number of conditional branches incorrect
411system.cpu0.branchPred.BTBLookups 81659728 # Number of BTB lookups
412system.cpu0.branchPred.BTBHits 48398116 # Number of BTB hits
413system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
414system.cpu0.branchPred.BTBHitPct 59.268035 # BTB Hit Percentage
415system.cpu0.branchPred.usedRAS 16692830 # Number of times the RAS was used to get a target.
416system.cpu0.branchPred.RASInCorrect 1123660 # Number of incorrect RAS predictions.
417system.cpu0.branchPred.indirectLookups 3717417 # Number of indirect predictor lookups.
418system.cpu0.branchPred.indirectHits 2487467 # Number of indirect target hits.
419system.cpu0.branchPred.indirectMisses 1229950 # Number of indirect misses.
420system.cpu0.branchPredindirectMispredicted 447789 # Number of mispredicted indirect branches.
421system.cpu_clk_domain.clock 500 # Clock period in ticks
422system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
423system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
424system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
425system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
426system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
427system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
428system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
429system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
430system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

444system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
445system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
446system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
447system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
448system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
449system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
450system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
451system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
452system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
453system.cpu0.dtb.walker.walks 291933 # Table walker walks requested
454system.cpu0.dtb.walker.walksLong 291933 # Table walker walks initiated with long descriptors
455system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10456 # Level at which table walker walks with long descriptors terminate
456system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84439 # Level at which table walker walks with long descriptors terminate
457system.cpu0.dtb.walker.walkWaitTime::samples 291933 # Table walker wait (enqueue to first request) latency
458system.cpu0.dtb.walker.walkWaitTime::0 291933 100.00% 100.00% # Table walker wait (enqueue to first request) latency
459system.cpu0.dtb.walker.walkWaitTime::total 291933 # Table walker wait (enqueue to first request) latency
460system.cpu0.dtb.walker.walkCompletionTime::samples 94895 # Table walker service (enqueue to completion) latency
461system.cpu0.dtb.walker.walkCompletionTime::mean 24023.404816 # Table walker service (enqueue to completion) latency
462system.cpu0.dtb.walker.walkCompletionTime::gmean 22175.510022 # Table walker service (enqueue to completion) latency
463system.cpu0.dtb.walker.walkCompletionTime::stdev 15850.715577 # Table walker service (enqueue to completion) latency
464system.cpu0.dtb.walker.walkCompletionTime::0-65535 93828 98.88% 98.88% # Table walker service (enqueue to completion) latency
465system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.82% 99.70% # Table walker service (enqueue to completion) latency
466system.cpu0.dtb.walker.walkCompletionTime::131072-196607 167 0.18% 99.88% # Table walker service (enqueue to completion) latency
467system.cpu0.dtb.walker.walkCompletionTime::196608-262143 53 0.06% 99.93% # Table walker service (enqueue to completion) latency
468system.cpu0.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
469system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.98% # Table walker service (enqueue to completion) latency
470system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
471system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
472system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
473system.cpu0.dtb.walker.walkCompletionTime::589824-655359 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
474system.cpu0.dtb.walker.walkCompletionTime::total 94895 # Table walker service (enqueue to completion) latency
475system.cpu0.dtb.walker.walksPending::samples 490774000 # Table walker pending requests distribution
476system.cpu0.dtb.walker.walksPending::0 490774000 100.00% 100.00% # Table walker pending requests distribution
477system.cpu0.dtb.walker.walksPending::total 490774000 # Table walker pending requests distribution
478system.cpu0.dtb.walker.walkPageSizes::4K 84439 88.98% 88.98% # Table walker page sizes translated
479system.cpu0.dtb.walker.walkPageSizes::2M 10456 11.02% 100.00% # Table walker page sizes translated
480system.cpu0.dtb.walker.walkPageSizes::total 94895 # Table walker page sizes translated
481system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 291933 # Table walker requests started/completed, data/inst
482system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 291933 # Table walker requests started/completed, data/inst
484system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94895 # Table walker requests started/completed, data/inst
485system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94895 # Table walker requests started/completed, data/inst
487system.cpu0.dtb.walker.walkRequestOrigin::total 386828 # Table walker requests started/completed, data/inst
488system.cpu0.dtb.inst_hits 0 # ITB inst hits
489system.cpu0.dtb.inst_misses 0 # ITB inst misses
490system.cpu0.dtb.read_hits 91107490 # DTB read hits
491system.cpu0.dtb.read_misses 238663 # DTB read misses
492system.cpu0.dtb.write_hits 81148084 # DTB write hits
493system.cpu0.dtb.write_misses 53270 # DTB write misses
494system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
495system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
496system.cpu0.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
497system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
498system.cpu0.dtb.flush_entries 37379 # Number of entries that have been flushed from TLB
499system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions
500system.cpu0.dtb.prefetch_faults 9352 # Number of TLB faults due to prefetch
501system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
502system.cpu0.dtb.perms_faults 11764 # Number of TLB faults due to permissions restrictions
503system.cpu0.dtb.read_accesses 91346153 # DTB read accesses
504system.cpu0.dtb.write_accesses 81201354 # DTB write accesses
505system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
506system.cpu0.dtb.hits 172255574 # DTB hits
507system.cpu0.dtb.misses 291933 # DTB misses
508system.cpu0.dtb.accesses 172547507 # DTB accesses
509system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
510system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
512system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
513system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
514system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
515system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
516system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
517system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

531system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
532system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
533system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
534system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
535system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
536system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
537system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
538system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
539system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
540system.cpu0.itb.walker.walks 65131 # Table walker walks requested
541system.cpu0.itb.walker.walksLong 65131 # Table walker walks initiated with long descriptors
542system.cpu0.itb.walker.walksLongTerminationLevel::Level2 651 # Level at which table walker walks with long descriptors terminate
543system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56721 # Level at which table walker walks with long descriptors terminate
544system.cpu0.itb.walker.walkWaitTime::samples 65131 # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::0 65131 100.00% 100.00% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::total 65131 # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkCompletionTime::samples 57372 # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walkCompletionTime::mean 26035.845012 # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walkCompletionTime::gmean 23914.977730 # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::stdev 19217.419826 # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::0-65535 56364 98.24% 98.24% # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::65536-131071 674 1.17% 99.42% # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::131072-196607 235 0.41% 99.83% # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.11% 99.94% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::262144-327679 11 0.02% 99.96% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::589824-655359 15 0.03% 100.00% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::total 57372 # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walksPending::samples 490003500 # Table walker pending requests distribution
561system.cpu0.itb.walker.walksPending::0 490003500 100.00% 100.00% # Table walker pending requests distribution
562system.cpu0.itb.walker.walksPending::total 490003500 # Table walker pending requests distribution
563system.cpu0.itb.walker.walkPageSizes::4K 56721 98.87% 98.87% # Table walker page sizes translated
564system.cpu0.itb.walker.walkPageSizes::2M 651 1.13% 100.00% # Table walker page sizes translated
565system.cpu0.itb.walker.walkPageSizes::total 57372 # Table walker page sizes translated
566system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
567system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65131 # Table walker requests started/completed, data/inst
568system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65131 # Table walker requests started/completed, data/inst
569system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
570system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57372 # Table walker requests started/completed, data/inst
571system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57372 # Table walker requests started/completed, data/inst
572system.cpu0.itb.walker.walkRequestOrigin::total 122503 # Table walker requests started/completed, data/inst
573system.cpu0.itb.inst_hits 201165320 # ITB inst hits
574system.cpu0.itb.inst_misses 65131 # ITB inst misses
575system.cpu0.itb.read_hits 0 # DTB read hits
576system.cpu0.itb.read_misses 0 # DTB read misses
577system.cpu0.itb.write_hits 0 # DTB write hits
578system.cpu0.itb.write_misses 0 # DTB write misses
579system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
580system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
581system.cpu0.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
582system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
583system.cpu0.itb.flush_entries 26201 # Number of entries that have been flushed from TLB
584system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
585system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
586system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
587system.cpu0.itb.perms_faults 173484 # Number of TLB faults due to permissions restrictions
588system.cpu0.itb.read_accesses 0 # DTB read accesses
589system.cpu0.itb.write_accesses 0 # DTB write accesses
590system.cpu0.itb.inst_accesses 201230451 # ITB inst accesses
591system.cpu0.itb.hits 201165320 # DTB hits
592system.cpu0.itb.misses 65131 # DTB misses
593system.cpu0.itb.accesses 201230451 # DTB accesses
594system.cpu0.numPwrStateTransitions 27066 # Number of power state transitions
595system.cpu0.pwrStateClkGateDist::samples 13533 # Distribution of time spent in the clock gated state
596system.cpu0.pwrStateClkGateDist::mean 3461850354.100126 # Distribution of time spent in the clock gated state
597system.cpu0.pwrStateClkGateDist::stdev 88555833572.600677 # Distribution of time spent in the clock gated state
598system.cpu0.pwrStateClkGateDist::underflows 3597 26.58% 26.58% # Distribution of time spent in the clock gated state
599system.cpu0.pwrStateClkGateDist::1000-5e+10 9910 73.23% 99.81% # Distribution of time spent in the clock gated state
600system.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state
601system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
602system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state
603system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
604system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
605system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
606system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
607system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
608system.cpu0.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
609system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
610system.cpu0.pwrStateClkGateDist::max_value 7470353817972 # Distribution of time spent in the clock gated state
611system.cpu0.pwrStateClkGateDist::total 13533 # Distribution of time spent in the clock gated state
612system.cpu0.pwrStateResidencyTicks::ON 461595325963 # Cumulative time (in ticks) in various power states
613system.cpu0.pwrStateResidencyTicks::CLK_GATED 46849220842037 # Cumulative time (in ticks) in various power states
614system.cpu0.numCycles 923231946 # number of cpu cycles simulated
615system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
616system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
617system.cpu0.committedInsts 433947137 # Number of instructions committed
618system.cpu0.committedOps 516803462 # Number of ops (including micro ops) committed
619system.cpu0.discardedOps 22098859 # Number of ops (including micro ops) which were discarded before commit
620system.cpu0.numFetchSuspends 4673 # Number of times Execute suspended instruction fetching
621system.cpu0.quiesceCycles 93699151861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
622system.cpu0.cpi 2.127522 # CPI: cycles per instruction
623system.cpu0.ipc 0.470030 # IPC: instructions per cycle
624system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction
625system.cpu0.op_class_0::IntAlu 346907240 67.13% 67.13% # Class of committed instruction
626system.cpu0.op_class_0::IntMult 1217129 0.24% 67.36% # Class of committed instruction
627system.cpu0.op_class_0::IntDiv 58486 0.01% 67.37% # Class of committed instruction
628system.cpu0.op_class_0::FloatAdd 8 0.00% 67.37% # Class of committed instruction
629system.cpu0.op_class_0::FloatCmp 13 0.00% 67.37% # Class of committed instruction
630system.cpu0.op_class_0::FloatCvt 21 0.00% 67.37% # Class of committed instruction
631system.cpu0.op_class_0::FloatMult 0 0.00% 67.37% # Class of committed instruction
632system.cpu0.op_class_0::FloatMultAcc 0 0.00% 67.37% # Class of committed instruction
633system.cpu0.op_class_0::FloatDiv 0 0.00% 67.37% # Class of committed instruction
634system.cpu0.op_class_0::FloatMisc 70436 0.01% 67.39% # Class of committed instruction
635system.cpu0.op_class_0::FloatSqrt 0 0.00% 67.39% # Class of committed instruction
636system.cpu0.op_class_0::SimdAdd 0 0.00% 67.39% # Class of committed instruction
637system.cpu0.op_class_0::SimdAddAcc 0 0.00% 67.39% # Class of committed instruction
638system.cpu0.op_class_0::SimdAlu 0 0.00% 67.39% # Class of committed instruction
639system.cpu0.op_class_0::SimdCmp 0 0.00% 67.39% # Class of committed instruction
640system.cpu0.op_class_0::SimdCvt 0 0.00% 67.39% # Class of committed instruction
641system.cpu0.op_class_0::SimdMisc 0 0.00% 67.39% # Class of committed instruction
642system.cpu0.op_class_0::SimdMult 0 0.00% 67.39% # Class of committed instruction
643system.cpu0.op_class_0::SimdMultAcc 0 0.00% 67.39% # Class of committed instruction
644system.cpu0.op_class_0::SimdShift 0 0.00% 67.39% # Class of committed instruction
645system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 67.39% # Class of committed instruction
646system.cpu0.op_class_0::SimdSqrt 0 0.00% 67.39% # Class of committed instruction
647system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 67.39% # Class of committed instruction
648system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 67.39% # Class of committed instruction
649system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 67.39% # Class of committed instruction
650system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 67.39% # Class of committed instruction
651system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 67.39% # Class of committed instruction
652system.cpu0.op_class_0::SimdFloatMisc 0 0.00% 67.39% # Class of committed instruction
653system.cpu0.op_class_0::SimdFloatMult 0 0.00% 67.39% # Class of committed instruction
654system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 67.39% # Class of committed instruction
655system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 67.39% # Class of committed instruction
656system.cpu0.op_class_0::MemRead 87685666 16.97% 84.35% # Class of committed instruction
657system.cpu0.op_class_0::MemWrite 80429583 15.56% 99.92% # Class of committed instruction
658system.cpu0.op_class_0::FloatMemRead 59649 0.01% 99.93% # Class of committed instruction
659system.cpu0.op_class_0::FloatMemWrite 375230 0.07% 100.00% # Class of committed instruction
660system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
661system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
662system.cpu0.op_class_0::total 516803462 # Class of committed instruction
663system.cpu0.kern.inst.arm 0 # number of arm instructions executed
664system.cpu0.kern.inst.quiesce 13533 # number of quiesce instructions executed
665system.cpu0.tickCycles 653190940 # Number of cycles that the object actually ticked
666system.cpu0.idleCycles 270041006 # Total number of cycles that the object has spent stopped
667system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
668system.cpu0.dcache.tags.replacements 6005277 # number of replacements
669system.cpu0.dcache.tags.tagsinuse 502.540168 # Cycle average of tags in use
670system.cpu0.dcache.tags.total_refs 163513084 # Total number of references to valid blocks.
671system.cpu0.dcache.tags.sampled_refs 6005789 # Sample count of references to valid blocks.
672system.cpu0.dcache.tags.avg_refs 27.225912 # Average number of references to valid blocks.
673system.cpu0.dcache.tags.warmup_cycle 500703000 # Cycle when the warmup percentage was hit.
674system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.540168 # Average occupied blocks per requestor
675system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981524 # Average percentage of cache occupancy
676system.cpu0.dcache.tags.occ_percent::total 0.981524 # Average percentage of cache occupancy
677system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
678system.cpu0.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
679system.cpu0.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
680system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
681system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
682system.cpu0.dcache.tags.tag_accesses 347779597 # Number of tag accesses
683system.cpu0.dcache.tags.data_accesses 347779597 # Number of data accesses
684system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
685system.cpu0.dcache.ReadReq_hits::cpu0.data 83636950 # number of ReadReq hits
686system.cpu0.dcache.ReadReq_hits::total 83636950 # number of ReadReq hits
687system.cpu0.dcache.WriteReq_hits::cpu0.data 75142855 # number of WriteReq hits
688system.cpu0.dcache.WriteReq_hits::total 75142855 # number of WriteReq hits
689system.cpu0.dcache.SoftPFReq_hits::cpu0.data 275029 # number of SoftPFReq hits
690system.cpu0.dcache.SoftPFReq_hits::total 275029 # number of SoftPFReq hits
691system.cpu0.dcache.WriteLineReq_hits::cpu0.data 178111 # number of WriteLineReq hits
692system.cpu0.dcache.WriteLineReq_hits::total 178111 # number of WriteLineReq hits
693system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878303 # number of LoadLockedReq hits
694system.cpu0.dcache.LoadLockedReq_hits::total 1878303 # number of LoadLockedReq hits
695system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1839620 # number of StoreCondReq hits
696system.cpu0.dcache.StoreCondReq_hits::total 1839620 # number of StoreCondReq hits
697system.cpu0.dcache.demand_hits::cpu0.data 158957916 # number of demand (read+write) hits
698system.cpu0.dcache.demand_hits::total 158957916 # number of demand (read+write) hits
699system.cpu0.dcache.overall_hits::cpu0.data 159232945 # number of overall hits
700system.cpu0.dcache.overall_hits::total 159232945 # number of overall hits
701system.cpu0.dcache.ReadReq_misses::cpu0.data 3392683 # number of ReadReq misses
702system.cpu0.dcache.ReadReq_misses::total 3392683 # number of ReadReq misses
703system.cpu0.dcache.WriteReq_misses::cpu0.data 2596834 # number of WriteReq misses
704system.cpu0.dcache.WriteReq_misses::total 2596834 # number of WriteReq misses
705system.cpu0.dcache.SoftPFReq_misses::cpu0.data 729933 # number of SoftPFReq misses
706system.cpu0.dcache.SoftPFReq_misses::total 729933 # number of SoftPFReq misses
707system.cpu0.dcache.WriteLineReq_misses::cpu0.data 807715 # number of WriteLineReq misses
708system.cpu0.dcache.WriteLineReq_misses::total 807715 # number of WriteLineReq misses
709system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 164864 # number of LoadLockedReq misses
710system.cpu0.dcache.LoadLockedReq_misses::total 164864 # number of LoadLockedReq misses
711system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202355 # number of StoreCondReq misses
712system.cpu0.dcache.StoreCondReq_misses::total 202355 # number of StoreCondReq misses
713system.cpu0.dcache.demand_misses::cpu0.data 6797232 # number of demand (read+write) misses
714system.cpu0.dcache.demand_misses::total 6797232 # number of demand (read+write) misses
715system.cpu0.dcache.overall_misses::cpu0.data 7527165 # number of overall misses
716system.cpu0.dcache.overall_misses::total 7527165 # number of overall misses
717system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55240233000 # number of ReadReq miss cycles
718system.cpu0.dcache.ReadReq_miss_latency::total 55240233000 # number of ReadReq miss cycles
719system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 55000663500 # number of WriteReq miss cycles
720system.cpu0.dcache.WriteReq_miss_latency::total 55000663500 # number of WriteReq miss cycles
721system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 26000939500 # number of WriteLineReq miss cycles
722system.cpu0.dcache.WriteLineReq_miss_latency::total 26000939500 # number of WriteLineReq miss cycles
723system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2528136500 # number of LoadLockedReq miss cycles
724system.cpu0.dcache.LoadLockedReq_miss_latency::total 2528136500 # number of LoadLockedReq miss cycles
725system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4851897500 # number of StoreCondReq miss cycles
726system.cpu0.dcache.StoreCondReq_miss_latency::total 4851897500 # number of StoreCondReq miss cycles
727system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2304500 # number of StoreCondFailReq miss cycles
728system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2304500 # number of StoreCondFailReq miss cycles
729system.cpu0.dcache.demand_miss_latency::cpu0.data 136241836000 # number of demand (read+write) miss cycles
730system.cpu0.dcache.demand_miss_latency::total 136241836000 # number of demand (read+write) miss cycles
731system.cpu0.dcache.overall_miss_latency::cpu0.data 136241836000 # number of overall miss cycles
732system.cpu0.dcache.overall_miss_latency::total 136241836000 # number of overall miss cycles
733system.cpu0.dcache.ReadReq_accesses::cpu0.data 87029633 # number of ReadReq accesses(hits+misses)
734system.cpu0.dcache.ReadReq_accesses::total 87029633 # number of ReadReq accesses(hits+misses)
735system.cpu0.dcache.WriteReq_accesses::cpu0.data 77739689 # number of WriteReq accesses(hits+misses)
736system.cpu0.dcache.WriteReq_accesses::total 77739689 # number of WriteReq accesses(hits+misses)
737system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1004962 # number of SoftPFReq accesses(hits+misses)
738system.cpu0.dcache.SoftPFReq_accesses::total 1004962 # number of SoftPFReq accesses(hits+misses)
739system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 985826 # number of WriteLineReq accesses(hits+misses)
740system.cpu0.dcache.WriteLineReq_accesses::total 985826 # number of WriteLineReq accesses(hits+misses)
741system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2043167 # number of LoadLockedReq accesses(hits+misses)
742system.cpu0.dcache.LoadLockedReq_accesses::total 2043167 # number of LoadLockedReq accesses(hits+misses)
743system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2041975 # number of StoreCondReq accesses(hits+misses)
744system.cpu0.dcache.StoreCondReq_accesses::total 2041975 # number of StoreCondReq accesses(hits+misses)
745system.cpu0.dcache.demand_accesses::cpu0.data 165755148 # number of demand (read+write) accesses
746system.cpu0.dcache.demand_accesses::total 165755148 # number of demand (read+write) accesses
747system.cpu0.dcache.overall_accesses::cpu0.data 166760110 # number of overall (read+write) accesses
748system.cpu0.dcache.overall_accesses::total 166760110 # number of overall (read+write) accesses
749system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038983 # miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_miss_rate::total 0.038983 # miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033404 # miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_miss_rate::total 0.033404 # miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.726329 # miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_miss_rate::total 0.726329 # miss rate for SoftPFReq accesses
755system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.819328 # miss rate for WriteLineReq accesses
756system.cpu0.dcache.WriteLineReq_miss_rate::total 0.819328 # miss rate for WriteLineReq accesses
757system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.080690 # miss rate for LoadLockedReq accesses
758system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.080690 # miss rate for LoadLockedReq accesses
759system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099098 # miss rate for StoreCondReq accesses
760system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099098 # miss rate for StoreCondReq accesses
761system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041008 # miss rate for demand accesses
762system.cpu0.dcache.demand_miss_rate::total 0.041008 # miss rate for demand accesses
763system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045138 # miss rate for overall accesses
764system.cpu0.dcache.overall_miss_rate::total 0.045138 # miss rate for overall accesses
765system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16282.167535 # average ReadReq miss latency
766system.cpu0.dcache.ReadReq_avg_miss_latency::total 16282.167535 # average ReadReq miss latency
767system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21179.891938 # average WriteReq miss latency
768system.cpu0.dcache.WriteReq_avg_miss_latency::total 21179.891938 # average WriteReq miss latency
769system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32190.734975 # average WriteLineReq miss latency
770system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32190.734975 # average WriteLineReq miss latency
771system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15334.678887 # average LoadLockedReq miss latency
772system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15334.678887 # average LoadLockedReq miss latency
773system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23977.156482 # average StoreCondReq miss latency
774system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23977.156482 # average StoreCondReq miss latency
775system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
776system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
777system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20043.723092 # average overall miss latency
778system.cpu0.dcache.demand_avg_miss_latency::total 20043.723092 # average overall miss latency
779system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18100.019861 # average overall miss latency
780system.cpu0.dcache.overall_avg_miss_latency::total 18100.019861 # average overall miss latency
781system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
782system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
783system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
784system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
785system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
786system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
787system.cpu0.dcache.writebacks::writebacks 6005280 # number of writebacks
788system.cpu0.dcache.writebacks::total 6005280 # number of writebacks
789system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 217816 # number of ReadReq MSHR hits
790system.cpu0.dcache.ReadReq_mshr_hits::total 217816 # number of ReadReq MSHR hits
791system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1084214 # number of WriteReq MSHR hits
792system.cpu0.dcache.WriteReq_mshr_hits::total 1084214 # number of WriteReq MSHR hits
793system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 111 # number of WriteLineReq MSHR hits
794system.cpu0.dcache.WriteLineReq_mshr_hits::total 111 # number of WriteLineReq MSHR hits
795system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44378 # number of LoadLockedReq MSHR hits
796system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44378 # number of LoadLockedReq MSHR hits
797system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 58 # number of StoreCondReq MSHR hits
798system.cpu0.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
799system.cpu0.dcache.demand_mshr_hits::cpu0.data 1302141 # number of demand (read+write) MSHR hits
800system.cpu0.dcache.demand_mshr_hits::total 1302141 # number of demand (read+write) MSHR hits
801system.cpu0.dcache.overall_mshr_hits::cpu0.data 1302141 # number of overall MSHR hits
802system.cpu0.dcache.overall_mshr_hits::total 1302141 # number of overall MSHR hits
803system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3174867 # number of ReadReq MSHR misses
804system.cpu0.dcache.ReadReq_mshr_misses::total 3174867 # number of ReadReq MSHR misses
805system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1512620 # number of WriteReq MSHR misses
806system.cpu0.dcache.WriteReq_mshr_misses::total 1512620 # number of WriteReq MSHR misses
807system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 727670 # number of SoftPFReq MSHR misses
808system.cpu0.dcache.SoftPFReq_mshr_misses::total 727670 # number of SoftPFReq MSHR misses
809system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 807604 # number of WriteLineReq MSHR misses
810system.cpu0.dcache.WriteLineReq_mshr_misses::total 807604 # number of WriteLineReq MSHR misses
811system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 120486 # number of LoadLockedReq MSHR misses
812system.cpu0.dcache.LoadLockedReq_mshr_misses::total 120486 # number of LoadLockedReq MSHR misses
813system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202297 # number of StoreCondReq MSHR misses
814system.cpu0.dcache.StoreCondReq_mshr_misses::total 202297 # number of StoreCondReq MSHR misses
815system.cpu0.dcache.demand_mshr_misses::cpu0.data 5495091 # number of demand (read+write) MSHR misses
816system.cpu0.dcache.demand_mshr_misses::total 5495091 # number of demand (read+write) MSHR misses
817system.cpu0.dcache.overall_mshr_misses::cpu0.data 6222761 # number of overall MSHR misses
818system.cpu0.dcache.overall_mshr_misses::total 6222761 # number of overall MSHR misses
819system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
820system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32770 # number of ReadReq MSHR uncacheable
821system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
822system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
823system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
824system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65503 # number of overall MSHR uncacheable misses
825system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46331358000 # number of ReadReq MSHR miss cycles
826system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46331358000 # number of ReadReq MSHR miss cycles
827system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30906822000 # number of WriteReq MSHR miss cycles
828system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30906822000 # number of WriteReq MSHR miss cycles
829system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18329110000 # number of SoftPFReq MSHR miss cycles
830system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18329110000 # number of SoftPFReq MSHR miss cycles
831system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 25186211500 # number of WriteLineReq MSHR miss cycles
832system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 25186211500 # number of WriteLineReq MSHR miss cycles
833system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1650103500 # number of LoadLockedReq MSHR miss cycles
834system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1650103500 # number of LoadLockedReq MSHR miss cycles
835system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4648318000 # number of StoreCondReq MSHR miss cycles
836system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4648318000 # number of StoreCondReq MSHR miss cycles
837system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1886000 # number of StoreCondFailReq MSHR miss cycles
838system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1886000 # number of StoreCondFailReq MSHR miss cycles
839system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102424391500 # number of demand (read+write) MSHR miss cycles
840system.cpu0.dcache.demand_mshr_miss_latency::total 102424391500 # number of demand (read+write) MSHR miss cycles
841system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 120753501500 # number of overall MSHR miss cycles
842system.cpu0.dcache.overall_mshr_miss_latency::total 120753501500 # number of overall MSHR miss cycles
843system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6287102500 # number of ReadReq MSHR uncacheable cycles
844system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6287102500 # number of ReadReq MSHR uncacheable cycles
845system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6287102500 # number of overall MSHR uncacheable cycles
846system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6287102500 # number of overall MSHR uncacheable cycles
847system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036480 # mshr miss rate for ReadReq accesses
848system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036480 # mshr miss rate for ReadReq accesses
849system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019458 # mshr miss rate for WriteReq accesses
850system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019458 # mshr miss rate for WriteReq accesses
851system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.724077 # mshr miss rate for SoftPFReq accesses
852system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.724077 # mshr miss rate for SoftPFReq accesses
853system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.819216 # mshr miss rate for WriteLineReq accesses
854system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.819216 # mshr miss rate for WriteLineReq accesses
855system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058970 # mshr miss rate for LoadLockedReq accesses
856system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058970 # mshr miss rate for LoadLockedReq accesses
857system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099069 # mshr miss rate for StoreCondReq accesses
858system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099069 # mshr miss rate for StoreCondReq accesses
859system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033152 # mshr miss rate for demand accesses
860system.cpu0.dcache.demand_mshr_miss_rate::total 0.033152 # mshr miss rate for demand accesses
861system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037316 # mshr miss rate for overall accesses
862system.cpu0.dcache.overall_mshr_miss_rate::total 0.037316 # mshr miss rate for overall accesses
863system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14593.165005 # average ReadReq mshr miss latency
864system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14593.165005 # average ReadReq mshr miss latency
865system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20432.641377 # average WriteReq mshr miss latency
866system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20432.641377 # average WriteReq mshr miss latency
867system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25188.766886 # average SoftPFReq mshr miss latency
868system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25188.766886 # average SoftPFReq mshr miss latency
869system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31186.338230 # average WriteLineReq mshr miss latency
870system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31186.338230 # average WriteLineReq mshr miss latency
871system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13695.396146 # average LoadLockedReq mshr miss latency
872system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13695.396146 # average LoadLockedReq mshr miss latency
873system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22977.691216 # average StoreCondReq mshr miss latency
874system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22977.691216 # average StoreCondReq mshr miss latency
875system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
876system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
877system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18639.253017 # average overall mshr miss latency
878system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18639.253017 # average overall mshr miss latency
879system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19405.132465 # average overall mshr miss latency
880system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19405.132465 # average overall mshr miss latency
881system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191855.431797 # average ReadReq mshr uncacheable latency
882system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191855.431797 # average ReadReq mshr uncacheable latency
883system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95981.901592 # average overall mshr uncacheable latency
884system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95981.901592 # average overall mshr uncacheable latency
885system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
886system.cpu0.icache.tags.replacements 9998472 # number of replacements
887system.cpu0.icache.tags.tagsinuse 511.981180 # Cycle average of tags in use
888system.cpu0.icache.tags.total_refs 190986664 # Total number of references to valid blocks.
889system.cpu0.icache.tags.sampled_refs 9998984 # Sample count of references to valid blocks.
890system.cpu0.icache.tags.avg_refs 19.100607 # Average number of references to valid blocks.
891system.cpu0.icache.tags.warmup_cycle 18008070000 # Cycle when the warmup percentage was hit.
892system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.981180 # Average occupied blocks per requestor
893system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999963 # Average percentage of cache occupancy
894system.cpu0.icache.tags.occ_percent::total 0.999963 # Average percentage of cache occupancy
895system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
896system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
897system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
898system.cpu0.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
899system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
900system.cpu0.icache.tags.tag_accesses 411970312 # Number of tag accesses
901system.cpu0.icache.tags.data_accesses 411970312 # Number of data accesses
902system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
903system.cpu0.icache.ReadReq_hits::cpu0.inst 190986664 # number of ReadReq hits
904system.cpu0.icache.ReadReq_hits::total 190986664 # number of ReadReq hits
905system.cpu0.icache.demand_hits::cpu0.inst 190986664 # number of demand (read+write) hits
906system.cpu0.icache.demand_hits::total 190986664 # number of demand (read+write) hits
907system.cpu0.icache.overall_hits::cpu0.inst 190986664 # number of overall hits
908system.cpu0.icache.overall_hits::total 190986664 # number of overall hits
909system.cpu0.icache.ReadReq_misses::cpu0.inst 9998995 # number of ReadReq misses
910system.cpu0.icache.ReadReq_misses::total 9998995 # number of ReadReq misses
911system.cpu0.icache.demand_misses::cpu0.inst 9998995 # number of demand (read+write) misses
912system.cpu0.icache.demand_misses::total 9998995 # number of demand (read+write) misses
913system.cpu0.icache.overall_misses::cpu0.inst 9998995 # number of overall misses
914system.cpu0.icache.overall_misses::total 9998995 # number of overall misses
915system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 104315202000 # number of ReadReq miss cycles
916system.cpu0.icache.ReadReq_miss_latency::total 104315202000 # number of ReadReq miss cycles
917system.cpu0.icache.demand_miss_latency::cpu0.inst 104315202000 # number of demand (read+write) miss cycles
918system.cpu0.icache.demand_miss_latency::total 104315202000 # number of demand (read+write) miss cycles
919system.cpu0.icache.overall_miss_latency::cpu0.inst 104315202000 # number of overall miss cycles
920system.cpu0.icache.overall_miss_latency::total 104315202000 # number of overall miss cycles
921system.cpu0.icache.ReadReq_accesses::cpu0.inst 200985659 # number of ReadReq accesses(hits+misses)
922system.cpu0.icache.ReadReq_accesses::total 200985659 # number of ReadReq accesses(hits+misses)
923system.cpu0.icache.demand_accesses::cpu0.inst 200985659 # number of demand (read+write) accesses
924system.cpu0.icache.demand_accesses::total 200985659 # number of demand (read+write) accesses
925system.cpu0.icache.overall_accesses::cpu0.inst 200985659 # number of overall (read+write) accesses
926system.cpu0.icache.overall_accesses::total 200985659 # number of overall (read+write) accesses
927system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.049750 # miss rate for ReadReq accesses
928system.cpu0.icache.ReadReq_miss_rate::total 0.049750 # miss rate for ReadReq accesses
929system.cpu0.icache.demand_miss_rate::cpu0.inst 0.049750 # miss rate for demand accesses
930system.cpu0.icache.demand_miss_rate::total 0.049750 # miss rate for demand accesses
931system.cpu0.icache.overall_miss_rate::cpu0.inst 0.049750 # miss rate for overall accesses
932system.cpu0.icache.overall_miss_rate::total 0.049750 # miss rate for overall accesses
933system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10432.568673 # average ReadReq miss latency
934system.cpu0.icache.ReadReq_avg_miss_latency::total 10432.568673 # average ReadReq miss latency
935system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
936system.cpu0.icache.demand_avg_miss_latency::total 10432.568673 # average overall miss latency
937system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10432.568673 # average overall miss latency
938system.cpu0.icache.overall_avg_miss_latency::total 10432.568673 # average overall miss latency
939system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
940system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
941system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
942system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
943system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
944system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
945system.cpu0.icache.writebacks::writebacks 9998472 # number of writebacks
946system.cpu0.icache.writebacks::total 9998472 # number of writebacks
947system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9998995 # number of ReadReq MSHR misses
948system.cpu0.icache.ReadReq_mshr_misses::total 9998995 # number of ReadReq MSHR misses
949system.cpu0.icache.demand_mshr_misses::cpu0.inst 9998995 # number of demand (read+write) MSHR misses
950system.cpu0.icache.demand_mshr_misses::total 9998995 # number of demand (read+write) MSHR misses
951system.cpu0.icache.overall_mshr_misses::cpu0.inst 9998995 # number of overall MSHR misses
952system.cpu0.icache.overall_mshr_misses::total 9998995 # number of overall MSHR misses
953system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
954system.cpu0.icache.ReadReq_mshr_uncacheable::total 4283 # number of ReadReq MSHR uncacheable
955system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
956system.cpu0.icache.overall_mshr_uncacheable_misses::total 4283 # number of overall MSHR uncacheable misses
957system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 99315705000 # number of ReadReq MSHR miss cycles
958system.cpu0.icache.ReadReq_mshr_miss_latency::total 99315705000 # number of ReadReq MSHR miss cycles
959system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 99315705000 # number of demand (read+write) MSHR miss cycles
960system.cpu0.icache.demand_mshr_miss_latency::total 99315705000 # number of demand (read+write) MSHR miss cycles
961system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 99315705000 # number of overall MSHR miss cycles
962system.cpu0.icache.overall_mshr_miss_latency::total 99315705000 # number of overall MSHR miss cycles
963system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 427814500 # number of ReadReq MSHR uncacheable cycles
964system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 427814500 # number of ReadReq MSHR uncacheable cycles
965system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 427814500 # number of overall MSHR uncacheable cycles
966system.cpu0.icache.overall_mshr_uncacheable_latency::total 427814500 # number of overall MSHR uncacheable cycles
967system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for ReadReq accesses
968system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.049750 # mshr miss rate for ReadReq accesses
969system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for demand accesses
970system.cpu0.icache.demand_mshr_miss_rate::total 0.049750 # mshr miss rate for demand accesses
971system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.049750 # mshr miss rate for overall accesses
972system.cpu0.icache.overall_mshr_miss_rate::total 0.049750 # mshr miss rate for overall accesses
973system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average ReadReq mshr miss latency
974system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9932.568723 # average ReadReq mshr miss latency
975system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
976system.cpu0.icache.demand_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
977system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9932.568723 # average overall mshr miss latency
978system.cpu0.icache.overall_avg_mshr_miss_latency::total 9932.568723 # average overall mshr miss latency
979system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average ReadReq mshr uncacheable latency
980system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 99886.644875 # average ReadReq mshr uncacheable latency
981system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 99886.644875 # average overall mshr uncacheable latency
982system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 99886.644875 # average overall mshr uncacheable latency
983system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
984system.cpu0.l2cache.prefetcher.num_hwpf_issued 8169933 # number of hwpf issued
985system.cpu0.l2cache.prefetcher.pfIdentified 8171403 # number of prefetch candidates identified
986system.cpu0.l2cache.prefetcher.pfBufferHit 1304 # number of redundant prefetches already in prefetch queue
987system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
988system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
989system.cpu0.l2cache.prefetcher.pfSpanPage 1047741 # number of prefetches not generated due to page crossing
990system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
991system.cpu0.l2cache.tags.replacements 2932551 # number of replacements
992system.cpu0.l2cache.tags.tagsinuse 15705.924224 # Cycle average of tags in use
993system.cpu0.l2cache.tags.total_refs 14272950 # Total number of references to valid blocks.
994system.cpu0.l2cache.tags.sampled_refs 2948325 # Sample count of references to valid blocks.
995system.cpu0.l2cache.tags.avg_refs 4.841037 # Average number of references to valid blocks.
996system.cpu0.l2cache.tags.warmup_cycle 1130072000 # Cycle when the warmup percentage was hit.
997system.cpu0.l2cache.tags.occ_blocks::writebacks 15376.526197 # Average occupied blocks per requestor
998system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 37.361518 # Average occupied blocks per requestor
999system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 20.248621 # Average occupied blocks per requestor
1000system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 271.787888 # Average occupied blocks per requestor
1001system.cpu0.l2cache.tags.occ_percent::writebacks 0.938509 # Average percentage of cache occupancy
1002system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002280 # Average percentage of cache occupancy
1003system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001236 # Average percentage of cache occupancy
1004system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016589 # Average percentage of cache occupancy
1005system.cpu0.l2cache.tags.occ_percent::total 0.958614 # Average percentage of cache occupancy
1006system.cpu0.l2cache.tags.occ_task_id_blocks::1022 362 # Occupied blocks per task id
1007system.cpu0.l2cache.tags.occ_task_id_blocks::1023 46 # Occupied blocks per task id
1008system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15366 # Occupied blocks per task id
1009system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id
1010system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 176 # Occupied blocks per task id
1011system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 107 # Occupied blocks per task id
1012system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id
1013system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
1014system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
1015system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
1016system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
1017system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2130 # Occupied blocks per task id
1018system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6262 # Occupied blocks per task id
1019system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5229 # Occupied blocks per task id
1020system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id
1021system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.022095 # Percentage of cache occupancy per task id
1022system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002808 # Percentage of cache occupancy per task id
1023system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.937866 # Percentage of cache occupancy per task id
1024system.cpu0.l2cache.tags.tag_accesses 549297414 # Number of tag accesses
1025system.cpu0.l2cache.tags.data_accesses 549297414 # Number of data accesses
1026system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1027system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539317 # number of ReadReq hits
1028system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 165054 # number of ReadReq hits
1029system.cpu0.l2cache.ReadReq_hits::total 704371 # number of ReadReq hits
1030system.cpu0.l2cache.WritebackDirty_hits::writebacks 3976191 # number of WritebackDirty hits
1031system.cpu0.l2cache.WritebackDirty_hits::total 3976191 # number of WritebackDirty hits
1032system.cpu0.l2cache.WritebackClean_hits::writebacks 12024318 # number of WritebackClean hits
1033system.cpu0.l2cache.WritebackClean_hits::total 12024318 # number of WritebackClean hits
1034system.cpu0.l2cache.ReadExReq_hits::cpu0.data 971762 # number of ReadExReq hits
1035system.cpu0.l2cache.ReadExReq_hits::total 971762 # number of ReadExReq hits
1036system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9224160 # number of ReadCleanReq hits
1037system.cpu0.l2cache.ReadCleanReq_hits::total 9224160 # number of ReadCleanReq hits
1038system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2947596 # number of ReadSharedReq hits
1039system.cpu0.l2cache.ReadSharedReq_hits::total 2947596 # number of ReadSharedReq hits
1040system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 209682 # number of InvalidateReq hits
1041system.cpu0.l2cache.InvalidateReq_hits::total 209682 # number of InvalidateReq hits
1042system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539317 # number of demand (read+write) hits
1043system.cpu0.l2cache.demand_hits::cpu0.itb.walker 165054 # number of demand (read+write) hits
1044system.cpu0.l2cache.demand_hits::cpu0.inst 9224160 # number of demand (read+write) hits
1045system.cpu0.l2cache.demand_hits::cpu0.data 3919358 # number of demand (read+write) hits
1046system.cpu0.l2cache.demand_hits::total 13847889 # number of demand (read+write) hits
1047system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539317 # number of overall hits
1048system.cpu0.l2cache.overall_hits::cpu0.itb.walker 165054 # number of overall hits
1049system.cpu0.l2cache.overall_hits::cpu0.inst 9224160 # number of overall hits
1050system.cpu0.l2cache.overall_hits::cpu0.data 3919358 # number of overall hits
1051system.cpu0.l2cache.overall_hits::total 13847889 # number of overall hits
1052system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 21966 # number of ReadReq misses
1053system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10468 # number of ReadReq misses
1054system.cpu0.l2cache.ReadReq_misses::total 32434 # number of ReadReq misses
1055system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
1056system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
1057system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257791 # number of UpgradeReq misses
1058system.cpu0.l2cache.UpgradeReq_misses::total 257791 # number of UpgradeReq misses
1059system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202293 # number of SCUpgradeReq misses
1060system.cpu0.l2cache.SCUpgradeReq_misses::total 202293 # number of SCUpgradeReq misses
1061system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
1062system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
1063system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289245 # number of ReadExReq misses
1064system.cpu0.l2cache.ReadExReq_misses::total 289245 # number of ReadExReq misses
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1066system.cpu0.l2cache.ReadCleanReq_misses::total 774834 # number of ReadCleanReq misses
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1085system.cpu0.l2cache.UpgradeReq_miss_latency::total 860565000 # number of UpgradeReq miss cycles
1086system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 334549500 # number of SCUpgradeReq miss cycles
1087system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 334549500 # number of SCUpgradeReq miss cycles
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1089system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1814999 # number of SCUpgradeFailReq miss cycles
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1093system.cpu0.l2cache.ReadCleanReq_miss_latency::total 28621690500 # number of ReadCleanReq miss cycles
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1095system.cpu0.l2cache.ReadSharedReq_miss_latency::total 40818686990 # number of ReadSharedReq miss cycles
1096system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 104000 # number of InvalidateReq miss cycles
1097system.cpu0.l2cache.InvalidateReq_miss_latency::total 104000 # number of InvalidateReq miss cycles
1098system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 715984000 # number of demand (read+write) miss cycles
1099system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 391759500 # number of demand (read+write) miss cycles
1100system.cpu0.l2cache.demand_miss_latency::cpu0.inst 28621690500 # number of demand (read+write) miss cycles
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1103system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 715984000 # number of overall miss cycles
1104system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 391759500 # number of overall miss cycles
1105system.cpu0.l2cache.overall_miss_latency::cpu0.inst 28621690500 # number of overall miss cycles
1106system.cpu0.l2cache.overall_miss_latency::cpu0.data 56627066487 # number of overall miss cycles
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1109system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175522 # number of ReadReq accesses(hits+misses)
1110system.cpu0.l2cache.ReadReq_accesses::total 736805 # number of ReadReq accesses(hits+misses)
1111system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3976191 # number of WritebackDirty accesses(hits+misses)
1112system.cpu0.l2cache.WritebackDirty_accesses::total 3976191 # number of WritebackDirty accesses(hits+misses)
1113system.cpu0.l2cache.WritebackClean_accesses::writebacks 12024319 # number of WritebackClean accesses(hits+misses)
1114system.cpu0.l2cache.WritebackClean_accesses::total 12024319 # number of WritebackClean accesses(hits+misses)
1115system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257791 # number of UpgradeReq accesses(hits+misses)
1116system.cpu0.l2cache.UpgradeReq_accesses::total 257791 # number of UpgradeReq accesses(hits+misses)
1117system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202293 # number of SCUpgradeReq accesses(hits+misses)
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1119system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
1120system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
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1122system.cpu0.l2cache.ReadExReq_accesses::total 1261007 # number of ReadExReq accesses(hits+misses)
1123system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9998994 # number of ReadCleanReq accesses(hits+misses)
1124system.cpu0.l2cache.ReadCleanReq_accesses::total 9998994 # number of ReadCleanReq accesses(hits+misses)
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1126system.cpu0.l2cache.ReadSharedReq_accesses::total 4022749 # number of ReadSharedReq accesses(hits+misses)
1127system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 807604 # number of InvalidateReq accesses(hits+misses)
1128system.cpu0.l2cache.InvalidateReq_accesses::total 807604 # number of InvalidateReq accesses(hits+misses)
1129system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 561283 # number of demand (read+write) accesses
1130system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175522 # number of demand (read+write) accesses
1131system.cpu0.l2cache.demand_accesses::cpu0.inst 9998994 # number of demand (read+write) accesses
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1135system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175522 # number of overall (read+write) accesses
1136system.cpu0.l2cache.overall_accesses::cpu0.inst 9998994 # number of overall (read+write) accesses
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1140system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059639 # miss rate for ReadReq accesses
1141system.cpu0.l2cache.ReadReq_miss_rate::total 0.044020 # miss rate for ReadReq accesses
1142system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1143system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1144system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1145system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1146system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1147system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1148system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1149system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1150system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229376 # miss rate for ReadExReq accesses
1151system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229376 # miss rate for ReadExReq accesses
1152system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.077491 # miss rate for ReadCleanReq accesses
1153system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.077491 # miss rate for ReadCleanReq accesses
1154system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267268 # miss rate for ReadSharedReq accesses
1155system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267268 # miss rate for ReadSharedReq accesses
1156system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.740365 # miss rate for InvalidateReq accesses
1157system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.740365 # miss rate for InvalidateReq accesses
1158system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for demand accesses
1159system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059639 # miss rate for demand accesses
1160system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.077491 # miss rate for demand accesses
1161system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258225 # miss rate for demand accesses
1162system.cpu0.l2cache.demand_miss_rate::total 0.135563 # miss rate for demand accesses
1163system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039135 # miss rate for overall accesses
1164system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059639 # miss rate for overall accesses
1165system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.077491 # miss rate for overall accesses
1166system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258225 # miss rate for overall accesses
1167system.cpu0.l2cache.overall_miss_rate::total 0.135563 # miss rate for overall accesses
1168system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average ReadReq miss latency
1169system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37424.484142 # average ReadReq miss latency
1170system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34153.773818 # average ReadReq miss latency
1171system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3338.227479 # average UpgradeReq miss latency
1172system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3338.227479 # average UpgradeReq miss latency
1173system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1653.786834 # average SCUpgradeReq miss latency
1174system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1653.786834 # average SCUpgradeReq miss latency
1175system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 453749.750000 # average SCUpgradeFailReq miss latency
1176system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 453749.750000 # average SCUpgradeFailReq miss latency
1177system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54653.942149 # average ReadExReq miss latency
1178system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54653.942149 # average ReadExReq miss latency
1179system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 36939.125671 # average ReadCleanReq miss latency
1180system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 36939.125671 # average ReadCleanReq miss latency
1181system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37965.468161 # average ReadSharedReq miss latency
1182system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37965.468161 # average ReadSharedReq miss latency
1183system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.173936 # average InvalidateReq miss latency
1184system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.173936 # average InvalidateReq miss latency
1185system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
1186system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
1187system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
1188system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
1189system.cpu0.l2cache.demand_avg_miss_latency::total 39765.093015 # average overall miss latency
1190system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32595.101521 # average overall miss latency
1191system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37424.484142 # average overall miss latency
1192system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 36939.125671 # average overall miss latency
1193system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41503.334428 # average overall miss latency
1194system.cpu0.l2cache.overall_avg_miss_latency::total 39765.093015 # average overall miss latency
1195system.cpu0.l2cache.blocked_cycles::no_mshrs 92 # number of cycles access was blocked
1196system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1197system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1198system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1199system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 92 # average number of cycles each access was blocked
1200system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1201system.cpu0.l2cache.unused_prefetches 48917 # number of HardPF blocks evicted w/o reference
1202system.cpu0.l2cache.writebacks::writebacks 1795601 # number of writebacks
1203system.cpu0.l2cache.writebacks::total 1795601 # number of writebacks
1204system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 23 # number of ReadReq MSHR hits
1205system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 90 # number of ReadReq MSHR hits
1206system.cpu0.l2cache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
1207system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10129 # number of ReadExReq MSHR hits
1208system.cpu0.l2cache.ReadExReq_mshr_hits::total 10129 # number of ReadExReq MSHR hits
1209system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 11 # number of ReadCleanReq MSHR hits
1210system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
1211system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 992 # number of ReadSharedReq MSHR hits
1212system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 992 # number of ReadSharedReq MSHR hits
1213system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 2 # number of InvalidateReq MSHR hits
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1215system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 23 # number of demand (read+write) MSHR hits
1216system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 90 # number of demand (read+write) MSHR hits
1217system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
1218system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11121 # number of demand (read+write) MSHR hits
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1220system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 23 # number of overall MSHR hits
1221system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 90 # number of overall MSHR hits
1222system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
1223system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11121 # number of overall MSHR hits
1224system.cpu0.l2cache.overall_mshr_hits::total 11245 # number of overall MSHR hits
1225system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 21943 # number of ReadReq MSHR misses
1226system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10378 # number of ReadReq MSHR misses
1227system.cpu0.l2cache.ReadReq_mshr_misses::total 32321 # number of ReadReq MSHR misses
1228system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
1229system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
1230system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 836449 # number of HardPFReq MSHR misses
1231system.cpu0.l2cache.HardPFReq_mshr_misses::total 836449 # number of HardPFReq MSHR misses
1232system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257791 # number of UpgradeReq MSHR misses
1233system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257791 # number of UpgradeReq MSHR misses
1234system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202293 # number of SCUpgradeReq MSHR misses
1235system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202293 # number of SCUpgradeReq MSHR misses
1236system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses
1237system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
1238system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279116 # number of ReadExReq MSHR misses
1239system.cpu0.l2cache.ReadExReq_mshr_misses::total 279116 # number of ReadExReq MSHR misses
1240system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 774823 # number of ReadCleanReq MSHR misses
1241system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 774823 # number of ReadCleanReq MSHR misses
1242system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074161 # number of ReadSharedReq MSHR misses
1243system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074161 # number of ReadSharedReq MSHR misses
1244system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 597920 # number of InvalidateReq MSHR misses
1245system.cpu0.l2cache.InvalidateReq_mshr_misses::total 597920 # number of InvalidateReq MSHR misses
1246system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 21943 # number of demand (read+write) MSHR misses
1247system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10378 # number of demand (read+write) MSHR misses
1248system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 774823 # number of demand (read+write) MSHR misses
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1251system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 21943 # number of overall MSHR misses
1252system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10378 # number of overall MSHR misses
1253system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 774823 # number of overall MSHR misses
1254system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1353277 # number of overall MSHR misses
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1256system.cpu0.l2cache.overall_mshr_misses::total 2996870 # number of overall MSHR misses
1257system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
1258system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
1259system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 37053 # number of ReadReq MSHR uncacheable
1260system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
1261system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32733 # number of WriteReq MSHR uncacheable
1262system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
1263system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
1264system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69786 # number of overall MSHR uncacheable misses
1265system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of ReadReq MSHR miss cycles
1266system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 328079000 # number of ReadReq MSHR miss cycles
1267system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 911857500 # number of ReadReq MSHR miss cycles
1268system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of HardPFReq MSHR miss cycles
1269system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 44903675775 # number of HardPFReq MSHR miss cycles
1270system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4788332493 # number of UpgradeReq MSHR miss cycles
1271system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4788332493 # number of UpgradeReq MSHR miss cycles
1272system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3126512997 # number of SCUpgradeReq MSHR miss cycles
1273system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3126512997 # number of SCUpgradeReq MSHR miss cycles
1274system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1538999 # number of SCUpgradeFailReq MSHR miss cycles
1275system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1538999 # number of SCUpgradeFailReq MSHR miss cycles
1276system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12740129497 # number of ReadExReq MSHR miss cycles
1277system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12740129497 # number of ReadExReq MSHR miss cycles
1278system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23972456500 # number of ReadCleanReq MSHR miss cycles
1279system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23972456500 # number of ReadCleanReq MSHR miss cycles
1280system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34238693990 # number of ReadSharedReq MSHR miss cycles
1281system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34238693990 # number of ReadSharedReq MSHR miss cycles
1282system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18919213000 # number of InvalidateReq MSHR miss cycles
1283system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18919213000 # number of InvalidateReq MSHR miss cycles
1284system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of demand (read+write) MSHR miss cycles
1285system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 328079000 # number of demand (read+write) MSHR miss cycles
1286system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23972456500 # number of demand (read+write) MSHR miss cycles
1287system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46978823487 # number of demand (read+write) MSHR miss cycles
1288system.cpu0.l2cache.demand_mshr_miss_latency::total 71863137487 # number of demand (read+write) MSHR miss cycles
1289system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 583778500 # number of overall MSHR miss cycles
1290system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 328079000 # number of overall MSHR miss cycles
1291system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23972456500 # number of overall MSHR miss cycles
1292system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46978823487 # number of overall MSHR miss cycles
1293system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44903675775 # number of overall MSHR miss cycles
1294system.cpu0.l2cache.overall_mshr_miss_latency::total 116766813262 # number of overall MSHR miss cycles
1295system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 393550500 # number of ReadReq MSHR uncacheable cycles
1296system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6024557000 # number of ReadReq MSHR uncacheable cycles
1297system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6418107500 # number of ReadReq MSHR uncacheable cycles
1298system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 393550500 # number of overall MSHR uncacheable cycles
1299system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6024557000 # number of overall MSHR uncacheable cycles
1300system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6418107500 # number of overall MSHR uncacheable cycles
1301system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for ReadReq accesses
1302system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for ReadReq accesses
1303system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadReq accesses
1304system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1305system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1306system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1307system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1308system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1309system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1310system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1311system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1312system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1313system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1314system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221344 # mshr miss rate for ReadExReq accesses
1315system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221344 # mshr miss rate for ReadExReq accesses
1316system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for ReadCleanReq accesses
1317system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077490 # mshr miss rate for ReadCleanReq accesses
1318system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.267022 # mshr miss rate for ReadSharedReq accesses
1319system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267022 # mshr miss rate for ReadSharedReq accesses
1320system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.740363 # mshr miss rate for InvalidateReq accesses
1321system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.740363 # mshr miss rate for InvalidateReq accesses
1322system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for demand accesses
1323system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for demand accesses
1324system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for demand accesses
1325system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for demand accesses
1326system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134861 # mshr miss rate for demand accesses
1327system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039094 # mshr miss rate for overall accesses
1328system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059126 # mshr miss rate for overall accesses
1329system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.077490 # mshr miss rate for overall accesses
1330system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256120 # mshr miss rate for overall accesses
1331system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1332system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187076 # mshr miss rate for overall accesses
1333system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average ReadReq mshr miss latency
1334system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average ReadReq mshr miss latency
1335system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28212.539835 # average ReadReq mshr miss latency
1336system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average HardPFReq mshr miss latency
1337system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53683.698319 # average HardPFReq mshr miss latency
1338system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18574.475032 # average UpgradeReq mshr miss latency
1339system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18574.475032 # average UpgradeReq mshr miss latency
1340system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15455.369177 # average SCUpgradeReq mshr miss latency
1341system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15455.369177 # average SCUpgradeReq mshr miss latency
1342system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 384749.750000 # average SCUpgradeFailReq mshr miss latency
1343system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 384749.750000 # average SCUpgradeFailReq mshr miss latency
1344system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45644.568914 # average ReadExReq mshr miss latency
1345system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45644.568914 # average ReadExReq mshr miss latency
1346system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average ReadCleanReq mshr miss latency
1347system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30939.268065 # average ReadCleanReq mshr miss latency
1348system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31874.825087 # average ReadSharedReq mshr miss latency
1349system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31874.825087 # average ReadSharedReq mshr miss latency
1350system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31641.712938 # average InvalidateReq mshr miss latency
1351system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31641.712938 # average InvalidateReq mshr miss latency
1352system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
1353system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
1354system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
1355system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
1356system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33263.487759 # average overall mshr miss latency
1357system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26604.315727 # average overall mshr miss latency
1358system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 31612.931201 # average overall mshr miss latency
1359system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30939.268065 # average overall mshr miss latency
1360system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34714.861397 # average overall mshr miss latency
1361system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53683.698319 # average overall mshr miss latency
1362system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38962.922403 # average overall mshr miss latency
1363system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average ReadReq mshr uncacheable latency
1364system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183843.667989 # average ReadReq mshr uncacheable latency
1365system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173214.247159 # average ReadReq mshr uncacheable latency
1366system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 91886.644875 # average overall mshr uncacheable latency
1367system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91973.756927 # average overall mshr uncacheable latency
1368system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 91968.410569 # average overall mshr uncacheable latency
1369system.cpu0.toL2Bus.snoop_filter.tot_requests 32883708 # Total number of requests made to the snoop filter.
1370system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16795845 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1371system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3253 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1372system.cpu0.toL2Bus.snoop_filter.tot_snoops 670544 # Total number of snoops made to the snoop filter.
1373system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 670518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1374system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 26 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1375system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1376system.cpu0.toL2Bus.trans_dist::ReadReq 856926 # Transaction distribution
1377system.cpu0.toL2Bus.trans_dist::ReadResp 14963454 # Transaction distribution
1378system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1379system.cpu0.toL2Bus.trans_dist::WriteReq 32733 # Transaction distribution
1380system.cpu0.toL2Bus.trans_dist::WriteResp 32733 # Transaction distribution
1381system.cpu0.toL2Bus.trans_dist::WritebackDirty 5790144 # Transaction distribution
1382system.cpu0.toL2Bus.trans_dist::WritebackClean 12027561 # Transaction distribution
1383system.cpu0.toL2Bus.trans_dist::CleanEvict 1570458 # Transaction distribution
1384system.cpu0.toL2Bus.trans_dist::HardPFReq 1077933 # Transaction distribution
1385system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
1386system.cpu0.toL2Bus.trans_dist::UpgradeReq 422877 # Transaction distribution
1387system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361846 # Transaction distribution
1388system.cpu0.toL2Bus.trans_dist::UpgradeResp 518769 # Transaction distribution
1389system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
1390system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
1391system.cpu0.toL2Bus.trans_dist::ReadExReq 1292875 # Transaction distribution
1392system.cpu0.toL2Bus.trans_dist::ReadExResp 1268569 # Transaction distribution
1393system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9998995 # Transaction distribution
1394system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5030713 # Transaction distribution
1395system.cpu0.toL2Bus.trans_dist::InvalidateReq 860724 # Transaction distribution
1396system.cpu0.toL2Bus.trans_dist::InvalidateResp 808588 # Transaction distribution
1397system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 30005026 # Packet count per connected master and slave (bytes)
1398system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19391293 # Packet count per connected master and slave (bytes)
1399system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370102 # Packet count per connected master and slave (bytes)
1400system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1186574 # Packet count per connected master and slave (bytes)
1401system.cpu0.toL2Bus.pkt_count::total 50952995 # Packet count per connected master and slave (bytes)
1402system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1280111872 # Cumulative packet size per connected master and slave (bytes)
1403system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 728610541 # Cumulative packet size per connected master and slave (bytes)
1404system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404176 # Cumulative packet size per connected master and slave (bytes)
1405system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4490264 # Cumulative packet size per connected master and slave (bytes)
1406system.cpu0.toL2Bus.pkt_size::total 2014616853 # Cumulative packet size per connected master and slave (bytes)
1407system.cpu0.toL2Bus.snoops 6115163 # Total snoops (count)
1408system.cpu0.toL2Bus.snoopTraffic 122669856 # Total snoop traffic (bytes)
1409system.cpu0.toL2Bus.snoop_fanout::samples 23320085 # Request fanout histogram
1410system.cpu0.toL2Bus.snoop_fanout::mean 0.043025 # Request fanout histogram
1411system.cpu0.toL2Bus.snoop_fanout::stdev 0.202918 # Request fanout histogram
1412system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1413system.cpu0.toL2Bus.snoop_fanout::0 22316772 95.70% 95.70% # Request fanout histogram
1414system.cpu0.toL2Bus.snoop_fanout::1 1003287 4.30% 100.00% # Request fanout histogram
1415system.cpu0.toL2Bus.snoop_fanout::2 26 0.00% 100.00% # Request fanout histogram
1416system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1417system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1418system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1419system.cpu0.toL2Bus.snoop_fanout::total 23320085 # Request fanout histogram
1420system.cpu0.toL2Bus.reqLayer0.occupancy 32742058478 # Layer occupancy (ticks)
1421system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1422system.cpu0.toL2Bus.snoopLayer0.occupancy 168693686 # Layer occupancy (ticks)
1423system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1424system.cpu0.toL2Bus.respLayer0.occupancy 15007733348 # Layer occupancy (ticks)
1425system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1426system.cpu0.toL2Bus.respLayer1.occupancy 8612588664 # Layer occupancy (ticks)
1427system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1428system.cpu0.toL2Bus.respLayer2.occupancy 194673313 # Layer occupancy (ticks)
1429system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1430system.cpu0.toL2Bus.respLayer3.occupancy 625412257 # Layer occupancy (ticks)
1431system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1432system.cpu1.branchPred.lookups 106657949 # Number of BP lookups
1433system.cpu1.branchPred.condPredicted 68318136 # Number of conditional branches predicted
1434system.cpu1.branchPred.condIncorrect 5862525 # Number of conditional branches incorrect
1435system.cpu1.branchPred.BTBLookups 74400025 # Number of BTB lookups
1436system.cpu1.branchPred.BTBHits 44246966 # Number of BTB hits
1437system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1438system.cpu1.branchPred.BTBHitPct 59.471709 # BTB Hit Percentage
1439system.cpu1.branchPred.usedRAS 15290670 # Number of times the RAS was used to get a target.
1440system.cpu1.branchPred.RASInCorrect 972922 # Number of incorrect RAS predictions.
1441system.cpu1.branchPred.indirectLookups 3525874 # Number of indirect predictor lookups.
1442system.cpu1.branchPred.indirectHits 2416919 # Number of indirect target hits.
1443system.cpu1.branchPred.indirectMisses 1108955 # Number of indirect misses.
1444system.cpu1.branchPredindirectMispredicted 399586 # Number of mispredicted indirect branches.
1445system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1446system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1447system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1448system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1449system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1450system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1451system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1452system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1453system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1467system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1468system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1469system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1470system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1471system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1472system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1473system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1474system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1475system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1476system.cpu1.dtb.walker.walks 277975 # Table walker walks requested
1477system.cpu1.dtb.walker.walksLong 277975 # Table walker walks initiated with long descriptors
1478system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11649 # Level at which table walker walks with long descriptors terminate
1479system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87046 # Level at which table walker walks with long descriptors terminate
1480system.cpu1.dtb.walker.walkWaitTime::samples 277975 # Table walker wait (enqueue to first request) latency
1481system.cpu1.dtb.walker.walkWaitTime::0 277975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1482system.cpu1.dtb.walker.walkWaitTime::total 277975 # Table walker wait (enqueue to first request) latency
1483system.cpu1.dtb.walker.walkCompletionTime::samples 98695 # Table walker service (enqueue to completion) latency
1484system.cpu1.dtb.walker.walkCompletionTime::mean 24377.552054 # Table walker service (enqueue to completion) latency
1485system.cpu1.dtb.walker.walkCompletionTime::gmean 22321.248739 # Table walker service (enqueue to completion) latency
1486system.cpu1.dtb.walker.walkCompletionTime::stdev 18122.441336 # Table walker service (enqueue to completion) latency
1487system.cpu1.dtb.walker.walkCompletionTime::0-65535 97210 98.50% 98.50% # Table walker service (enqueue to completion) latency
1488system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1115 1.13% 99.63% # Table walker service (enqueue to completion) latency
1489system.cpu1.dtb.walker.walkCompletionTime::131072-196607 185 0.19% 99.81% # Table walker service (enqueue to completion) latency
1490system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.88% # Table walker service (enqueue to completion) latency
1491system.cpu1.dtb.walker.walkCompletionTime::262144-327679 61 0.06% 99.95% # Table walker service (enqueue to completion) latency
1492system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.98% # Table walker service (enqueue to completion) latency
1493system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
1494system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1495system.cpu1.dtb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
1496system.cpu1.dtb.walker.walkCompletionTime::total 98695 # Table walker service (enqueue to completion) latency
1497system.cpu1.dtb.walker.walksPending::samples -466757760 # Table walker pending requests distribution
1498system.cpu1.dtb.walker.walksPending::0 -466757760 100.00% 100.00% # Table walker pending requests distribution
1499system.cpu1.dtb.walker.walksPending::total -466757760 # Table walker pending requests distribution
1500system.cpu1.dtb.walker.walkPageSizes::4K 87046 88.20% 88.20% # Table walker page sizes translated
1501system.cpu1.dtb.walker.walkPageSizes::2M 11649 11.80% 100.00% # Table walker page sizes translated
1502system.cpu1.dtb.walker.walkPageSizes::total 98695 # Table walker page sizes translated
1503system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 277975 # Table walker requests started/completed, data/inst
1504system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1505system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 277975 # Table walker requests started/completed, data/inst
1506system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98695 # Table walker requests started/completed, data/inst
1507system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1508system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98695 # Table walker requests started/completed, data/inst
1509system.cpu1.dtb.walker.walkRequestOrigin::total 376670 # Table walker requests started/completed, data/inst
1510system.cpu1.dtb.inst_hits 0 # ITB inst hits
1511system.cpu1.dtb.inst_misses 0 # ITB inst misses
1512system.cpu1.dtb.read_hits 85144665 # DTB read hits
1513system.cpu1.dtb.read_misses 232605 # DTB read misses
1514system.cpu1.dtb.write_hits 73861979 # DTB write hits
1515system.cpu1.dtb.write_misses 45370 # DTB write misses
1516system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1517system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1518system.cpu1.dtb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
1519system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
1520system.cpu1.dtb.flush_entries 39387 # Number of entries that have been flushed from TLB
1521system.cpu1.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions
1522system.cpu1.dtb.prefetch_faults 7458 # Number of TLB faults due to prefetch
1523system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1524system.cpu1.dtb.perms_faults 10689 # Number of TLB faults due to permissions restrictions
1525system.cpu1.dtb.read_accesses 85377270 # DTB read accesses
1526system.cpu1.dtb.write_accesses 73907349 # DTB write accesses
1527system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1528system.cpu1.dtb.hits 159006644 # DTB hits
1529system.cpu1.dtb.misses 277975 # DTB misses
1530system.cpu1.dtb.accesses 159284619 # DTB accesses
1531system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1532system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1533system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1534system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1535system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1536system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1537system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1538system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1539system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1553system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1554system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1555system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1556system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1557system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1558system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1559system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1560system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1561system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1562system.cpu1.itb.walker.walks 63204 # Table walker walks requested
1563system.cpu1.itb.walker.walksLong 63204 # Table walker walks initiated with long descriptors
1564system.cpu1.itb.walker.walksLongTerminationLevel::Level2 495 # Level at which table walker walks with long descriptors terminate
1565system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53495 # Level at which table walker walks with long descriptors terminate
1566system.cpu1.itb.walker.walkWaitTime::samples 63204 # Table walker wait (enqueue to first request) latency
1567system.cpu1.itb.walker.walkWaitTime::0 63204 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1568system.cpu1.itb.walker.walkWaitTime::total 63204 # Table walker wait (enqueue to first request) latency
1569system.cpu1.itb.walker.walkCompletionTime::samples 53990 # Table walker service (enqueue to completion) latency
1570system.cpu1.itb.walker.walkCompletionTime::mean 26610.918689 # Table walker service (enqueue to completion) latency
1571system.cpu1.itb.walker.walkCompletionTime::gmean 23983.875694 # Table walker service (enqueue to completion) latency
1572system.cpu1.itb.walker.walkCompletionTime::stdev 21231.525332 # Table walker service (enqueue to completion) latency
1573system.cpu1.itb.walker.walkCompletionTime::0-65535 52488 97.22% 97.22% # Table walker service (enqueue to completion) latency
1574system.cpu1.itb.walker.walkCompletionTime::65536-131071 1070 1.98% 99.20% # Table walker service (enqueue to completion) latency
1575system.cpu1.itb.walker.walkCompletionTime::131072-196607 308 0.57% 99.77% # Table walker service (enqueue to completion) latency
1576system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.14% 99.91% # Table walker service (enqueue to completion) latency
1577system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.94% # Table walker service (enqueue to completion) latency
1578system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.97% # Table walker service (enqueue to completion) latency
1579system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
1580system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1581system.cpu1.itb.walker.walkCompletionTime::589824-655359 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
1582system.cpu1.itb.walker.walkCompletionTime::total 53990 # Table walker service (enqueue to completion) latency
1583system.cpu1.itb.walker.walksPending::samples -467394260 # Table walker pending requests distribution
1584system.cpu1.itb.walker.walksPending::0 -467394260 100.00% 100.00% # Table walker pending requests distribution
1585system.cpu1.itb.walker.walksPending::total -467394260 # Table walker pending requests distribution
1586system.cpu1.itb.walker.walkPageSizes::4K 53495 99.08% 99.08% # Table walker page sizes translated
1587system.cpu1.itb.walker.walkPageSizes::2M 495 0.92% 100.00% # Table walker page sizes translated
1588system.cpu1.itb.walker.walkPageSizes::total 53990 # Table walker page sizes translated
1589system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1590system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63204 # Table walker requests started/completed, data/inst
1591system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63204 # Table walker requests started/completed, data/inst
1592system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1593system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53990 # Table walker requests started/completed, data/inst
1594system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53990 # Table walker requests started/completed, data/inst
1595system.cpu1.itb.walker.walkRequestOrigin::total 117194 # Table walker requests started/completed, data/inst
1596system.cpu1.itb.inst_hits 184175570 # ITB inst hits
1597system.cpu1.itb.inst_misses 63204 # ITB inst misses
1598system.cpu1.itb.read_hits 0 # DTB read hits
1599system.cpu1.itb.read_misses 0 # DTB read misses
1600system.cpu1.itb.write_hits 0 # DTB write hits
1601system.cpu1.itb.write_misses 0 # DTB write misses
1602system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1603system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1604system.cpu1.itb.flush_tlb_mva_asid 43122 # Number of times TLB was flushed by MVA & ASID
1605system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID
1606system.cpu1.itb.flush_entries 27907 # Number of entries that have been flushed from TLB
1607system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1608system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1609system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1610system.cpu1.itb.perms_faults 163451 # Number of TLB faults due to permissions restrictions
1611system.cpu1.itb.read_accesses 0 # DTB read accesses
1612system.cpu1.itb.write_accesses 0 # DTB write accesses
1613system.cpu1.itb.inst_accesses 184238774 # ITB inst accesses
1614system.cpu1.itb.hits 184175570 # DTB hits
1615system.cpu1.itb.misses 63204 # DTB misses
1616system.cpu1.itb.accesses 184238774 # DTB accesses
1617system.cpu1.numPwrStateTransitions 10058 # Number of power state transitions
1618system.cpu1.pwrStateClkGateDist::samples 5029 # Distribution of time spent in the clock gated state
1619system.cpu1.pwrStateClkGateDist::mean 9328191006.192484 # Distribution of time spent in the clock gated state
1620system.cpu1.pwrStateClkGateDist::stdev 208028914614.416260 # Distribution of time spent in the clock gated state
1621system.cpu1.pwrStateClkGateDist::underflows 3721 73.99% 73.99% # Distribution of time spent in the clock gated state
1622system.cpu1.pwrStateClkGateDist::1000-5e+10 1288 25.61% 99.60% # Distribution of time spent in the clock gated state
1623system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.10% 99.70% # Distribution of time spent in the clock gated state
1624system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
1625system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.76% # Distribution of time spent in the clock gated state
1626system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
1627system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state
1628system.cpu1.pwrStateClkGateDist::overflows 10 0.20% 100.00% # Distribution of time spent in the clock gated state
1629system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1630system.cpu1.pwrStateClkGateDist::max_value 11813597602000 # Distribution of time spent in the clock gated state
1631system.cpu1.pwrStateClkGateDist::total 5029 # Distribution of time spent in the clock gated state
1632system.cpu1.pwrStateResidencyTicks::ON 399343597858 # Cumulative time (in ticks) in various power states
1633system.cpu1.pwrStateResidencyTicks::CLK_GATED 46911472570142 # Cumulative time (in ticks) in various power states
1634system.cpu1.numCycles 798693745 # number of cpu cycles simulated
1635system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1636system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1637system.cpu1.committedInsts 398322797 # Number of instructions committed
1638system.cpu1.committedOps 474376671 # Number of ops (including micro ops) committed
1639system.cpu1.discardedOps 19914789 # Number of ops (including micro ops) which were discarded before commit
1640system.cpu1.numFetchSuspends 5029 # Number of times Execute suspended instruction fetching
1641system.cpu1.quiesceCycles 93823705865 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1642system.cpu1.cpi 2.005142 # CPI: cycles per instruction
1643system.cpu1.ipc 0.498718 # IPC: instructions per cycle
1644system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1645system.cpu1.op_class_0::IntAlu 317550239 66.94% 66.94% # Class of committed instruction
1646system.cpu1.op_class_0::IntMult 1035693 0.22% 67.16% # Class of committed instruction
1647system.cpu1.op_class_0::IntDiv 58506 0.01% 67.17% # Class of committed instruction
1648system.cpu1.op_class_0::FloatAdd 0 0.00% 67.17% # Class of committed instruction
1649system.cpu1.op_class_0::FloatCmp 0 0.00% 67.17% # Class of committed instruction
1650system.cpu1.op_class_0::FloatCvt 0 0.00% 67.17% # Class of committed instruction
1651system.cpu1.op_class_0::FloatMult 0 0.00% 67.17% # Class of committed instruction
1652system.cpu1.op_class_0::FloatMultAcc 0 0.00% 67.17% # Class of committed instruction
1653system.cpu1.op_class_0::FloatDiv 0 0.00% 67.17% # Class of committed instruction
1654system.cpu1.op_class_0::FloatMisc 40875 0.01% 67.18% # Class of committed instruction
1655system.cpu1.op_class_0::FloatSqrt 0 0.00% 67.18% # Class of committed instruction
1656system.cpu1.op_class_0::SimdAdd 0 0.00% 67.18% # Class of committed instruction
1657system.cpu1.op_class_0::SimdAddAcc 0 0.00% 67.18% # Class of committed instruction
1658system.cpu1.op_class_0::SimdAlu 0 0.00% 67.18% # Class of committed instruction
1659system.cpu1.op_class_0::SimdCmp 0 0.00% 67.18% # Class of committed instruction
1660system.cpu1.op_class_0::SimdCvt 0 0.00% 67.18% # Class of committed instruction
1661system.cpu1.op_class_0::SimdMisc 0 0.00% 67.18% # Class of committed instruction
1662system.cpu1.op_class_0::SimdMult 0 0.00% 67.18% # Class of committed instruction
1663system.cpu1.op_class_0::SimdMultAcc 0 0.00% 67.18% # Class of committed instruction
1664system.cpu1.op_class_0::SimdShift 0 0.00% 67.18% # Class of committed instruction
1665system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 67.18% # Class of committed instruction
1666system.cpu1.op_class_0::SimdSqrt 0 0.00% 67.18% # Class of committed instruction
1667system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 67.18% # Class of committed instruction
1668system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 67.18% # Class of committed instruction
1669system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 67.18% # Class of committed instruction
1670system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 67.18% # Class of committed instruction
1671system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 67.18% # Class of committed instruction
1672system.cpu1.op_class_0::SimdFloatMisc 0 0.00% 67.18% # Class of committed instruction
1673system.cpu1.op_class_0::SimdFloatMult 0 0.00% 67.18% # Class of committed instruction
1674system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 67.18% # Class of committed instruction
1675system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 67.18% # Class of committed instruction
1676system.cpu1.op_class_0::MemRead 82080782 17.30% 84.48% # Class of committed instruction
1677system.cpu1.op_class_0::MemWrite 73258893 15.44% 99.93% # Class of committed instruction
1678system.cpu1.op_class_0::FloatMemRead 48388 0.01% 99.94% # Class of committed instruction
1679system.cpu1.op_class_0::FloatMemWrite 303295 0.06% 100.00% # Class of committed instruction
1680system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1681system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1682system.cpu1.op_class_0::total 474376671 # Class of committed instruction
1683system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1684system.cpu1.kern.inst.quiesce 5029 # number of quiesce instructions executed
1685system.cpu1.tickCycles 594788003 # Number of cycles that the object actually ticked
1686system.cpu1.idleCycles 203905742 # Total number of cycles that the object has spent stopped
1687system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1688system.cpu1.dcache.tags.replacements 5132038 # number of replacements
1689system.cpu1.dcache.tags.tagsinuse 426.485512 # Cycle average of tags in use
1690system.cpu1.dcache.tags.total_refs 151527650 # Total number of references to valid blocks.
1691system.cpu1.dcache.tags.sampled_refs 5132550 # Sample count of references to valid blocks.
1692system.cpu1.dcache.tags.avg_refs 29.522878 # Average number of references to valid blocks.
1693system.cpu1.dcache.tags.warmup_cycle 8373589022500 # Cycle when the warmup percentage was hit.
1694system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.485512 # Average occupied blocks per requestor
1695system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832980 # Average percentage of cache occupancy
1696system.cpu1.dcache.tags.occ_percent::total 0.832980 # Average percentage of cache occupancy
1697system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1698system.cpu1.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
1699system.cpu1.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
1700system.cpu1.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
1701system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1702system.cpu1.dcache.tags.tag_accesses 320787282 # Number of tag accesses
1703system.cpu1.dcache.tags.data_accesses 320787282 # Number of data accesses
1704system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1705system.cpu1.dcache.ReadReq_hits::cpu1.data 78335043 # number of ReadReq hits
1706system.cpu1.dcache.ReadReq_hits::total 78335043 # number of ReadReq hits
1707system.cpu1.dcache.WriteReq_hits::cpu1.data 68878259 # number of WriteReq hits
1708system.cpu1.dcache.WriteReq_hits::total 68878259 # number of WriteReq hits
1709system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235022 # number of SoftPFReq hits
1710system.cpu1.dcache.SoftPFReq_hits::total 235022 # number of SoftPFReq hits
1711system.cpu1.dcache.WriteLineReq_hits::cpu1.data 144067 # number of WriteLineReq hits
1712system.cpu1.dcache.WriteLineReq_hits::total 144067 # number of WriteLineReq hits
1713system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753147 # number of LoadLockedReq hits
1714system.cpu1.dcache.LoadLockedReq_hits::total 1753147 # number of LoadLockedReq hits
1715system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1717747 # number of StoreCondReq hits
1716system.cpu1.dcache.StoreCondReq_hits::total 1717747 # number of StoreCondReq hits
1717system.cpu1.dcache.demand_hits::cpu1.data 147357369 # number of demand (read+write) hits
1718system.cpu1.dcache.demand_hits::total 147357369 # number of demand (read+write) hits
1719system.cpu1.dcache.overall_hits::cpu1.data 147592391 # number of overall hits
1720system.cpu1.dcache.overall_hits::total 147592391 # number of overall hits
1721system.cpu1.dcache.ReadReq_misses::cpu1.data 3132424 # number of ReadReq misses
1722system.cpu1.dcache.ReadReq_misses::total 3132424 # number of ReadReq misses
1723system.cpu1.dcache.WriteReq_misses::cpu1.data 2174513 # number of WriteReq misses
1724system.cpu1.dcache.WriteReq_misses::total 2174513 # number of WriteReq misses
1725system.cpu1.dcache.SoftPFReq_misses::cpu1.data 607658 # number of SoftPFReq misses
1726system.cpu1.dcache.SoftPFReq_misses::total 607658 # number of SoftPFReq misses
1727system.cpu1.dcache.WriteLineReq_misses::cpu1.data 439275 # number of WriteLineReq misses
1728system.cpu1.dcache.WriteLineReq_misses::total 439275 # number of WriteLineReq misses
1729system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 165234 # number of LoadLockedReq misses
1730system.cpu1.dcache.LoadLockedReq_misses::total 165234 # number of LoadLockedReq misses
1731system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199402 # number of StoreCondReq misses
1732system.cpu1.dcache.StoreCondReq_misses::total 199402 # number of StoreCondReq misses
1733system.cpu1.dcache.demand_misses::cpu1.data 5746212 # number of demand (read+write) misses
1734system.cpu1.dcache.demand_misses::total 5746212 # number of demand (read+write) misses
1735system.cpu1.dcache.overall_misses::cpu1.data 6353870 # number of overall misses
1736system.cpu1.dcache.overall_misses::total 6353870 # number of overall misses
1737system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50822417500 # number of ReadReq miss cycles
1738system.cpu1.dcache.ReadReq_miss_latency::total 50822417500 # number of ReadReq miss cycles
1739system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 41404734500 # number of WriteReq miss cycles
1740system.cpu1.dcache.WriteReq_miss_latency::total 41404734500 # number of WriteReq miss cycles
1741system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10557419500 # number of WriteLineReq miss cycles
1742system.cpu1.dcache.WriteLineReq_miss_latency::total 10557419500 # number of WriteLineReq miss cycles
1743system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2612130500 # number of LoadLockedReq miss cycles
1744system.cpu1.dcache.LoadLockedReq_miss_latency::total 2612130500 # number of LoadLockedReq miss cycles
1745system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4773809500 # number of StoreCondReq miss cycles
1746system.cpu1.dcache.StoreCondReq_miss_latency::total 4773809500 # number of StoreCondReq miss cycles
1747system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2292000 # number of StoreCondFailReq miss cycles
1748system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2292000 # number of StoreCondFailReq miss cycles
1749system.cpu1.dcache.demand_miss_latency::cpu1.data 102784571500 # number of demand (read+write) miss cycles
1750system.cpu1.dcache.demand_miss_latency::total 102784571500 # number of demand (read+write) miss cycles
1751system.cpu1.dcache.overall_miss_latency::cpu1.data 102784571500 # number of overall miss cycles
1752system.cpu1.dcache.overall_miss_latency::total 102784571500 # number of overall miss cycles
1753system.cpu1.dcache.ReadReq_accesses::cpu1.data 81467467 # number of ReadReq accesses(hits+misses)
1754system.cpu1.dcache.ReadReq_accesses::total 81467467 # number of ReadReq accesses(hits+misses)
1755system.cpu1.dcache.WriteReq_accesses::cpu1.data 71052772 # number of WriteReq accesses(hits+misses)
1756system.cpu1.dcache.WriteReq_accesses::total 71052772 # number of WriteReq accesses(hits+misses)
1757system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842680 # number of SoftPFReq accesses(hits+misses)
1758system.cpu1.dcache.SoftPFReq_accesses::total 842680 # number of SoftPFReq accesses(hits+misses)
1759system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 583342 # number of WriteLineReq accesses(hits+misses)
1760system.cpu1.dcache.WriteLineReq_accesses::total 583342 # number of WriteLineReq accesses(hits+misses)
1761system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1918381 # number of LoadLockedReq accesses(hits+misses)
1762system.cpu1.dcache.LoadLockedReq_accesses::total 1918381 # number of LoadLockedReq accesses(hits+misses)
1763system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1917149 # number of StoreCondReq accesses(hits+misses)
1764system.cpu1.dcache.StoreCondReq_accesses::total 1917149 # number of StoreCondReq accesses(hits+misses)
1765system.cpu1.dcache.demand_accesses::cpu1.data 153103581 # number of demand (read+write) accesses
1766system.cpu1.dcache.demand_accesses::total 153103581 # number of demand (read+write) accesses
1767system.cpu1.dcache.overall_accesses::cpu1.data 153946261 # number of overall (read+write) accesses
1768system.cpu1.dcache.overall_accesses::total 153946261 # number of overall (read+write) accesses
1769system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038450 # miss rate for ReadReq accesses
1770system.cpu1.dcache.ReadReq_miss_rate::total 0.038450 # miss rate for ReadReq accesses
1771system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030604 # miss rate for WriteReq accesses
1772system.cpu1.dcache.WriteReq_miss_rate::total 0.030604 # miss rate for WriteReq accesses
1773system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.721102 # miss rate for SoftPFReq accesses
1774system.cpu1.dcache.SoftPFReq_miss_rate::total 0.721102 # miss rate for SoftPFReq accesses
1775system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.753032 # miss rate for WriteLineReq accesses
1776system.cpu1.dcache.WriteLineReq_miss_rate::total 0.753032 # miss rate for WriteLineReq accesses
1777system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086132 # miss rate for LoadLockedReq accesses
1778system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086132 # miss rate for LoadLockedReq accesses
1779system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104010 # miss rate for StoreCondReq accesses
1780system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104010 # miss rate for StoreCondReq accesses
1781system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037532 # miss rate for demand accesses
1782system.cpu1.dcache.demand_miss_rate::total 0.037532 # miss rate for demand accesses
1783system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041273 # miss rate for overall accesses
1784system.cpu1.dcache.overall_miss_rate::total 0.041273 # miss rate for overall accesses
1785system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16224.629073 # average ReadReq miss latency
1786system.cpu1.dcache.ReadReq_avg_miss_latency::total 16224.629073 # average ReadReq miss latency
1787system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19040.922956 # average WriteReq miss latency
1788system.cpu1.dcache.WriteReq_avg_miss_latency::total 19040.922956 # average WriteReq miss latency
1789system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24033.736270 # average WriteLineReq miss latency
1790system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24033.736270 # average WriteLineReq miss latency
1791system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15808.674365 # average LoadLockedReq miss latency
1792system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15808.674365 # average LoadLockedReq miss latency
1793system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23940.629984 # average StoreCondReq miss latency
1794system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23940.629984 # average StoreCondReq miss latency
1795system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1796system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1797system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17887.361535 # average overall miss latency
1798system.cpu1.dcache.demand_avg_miss_latency::total 17887.361535 # average overall miss latency
1799system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16176.687830 # average overall miss latency
1800system.cpu1.dcache.overall_avg_miss_latency::total 16176.687830 # average overall miss latency
1801system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1802system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1803system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1804system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1805system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1806system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1807system.cpu1.dcache.writebacks::writebacks 5132050 # number of writebacks
1808system.cpu1.dcache.writebacks::total 5132050 # number of writebacks
1809system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 160382 # number of ReadReq MSHR hits
1810system.cpu1.dcache.ReadReq_mshr_hits::total 160382 # number of ReadReq MSHR hits
1811system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 885255 # number of WriteReq MSHR hits
1812system.cpu1.dcache.WriteReq_mshr_hits::total 885255 # number of WriteReq MSHR hits
1813system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 52 # number of WriteLineReq MSHR hits
1814system.cpu1.dcache.WriteLineReq_mshr_hits::total 52 # number of WriteLineReq MSHR hits
1815system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 41570 # number of LoadLockedReq MSHR hits
1816system.cpu1.dcache.LoadLockedReq_mshr_hits::total 41570 # number of LoadLockedReq MSHR hits
1817system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits
1818system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits
1819system.cpu1.dcache.demand_mshr_hits::cpu1.data 1045689 # number of demand (read+write) MSHR hits
1820system.cpu1.dcache.demand_mshr_hits::total 1045689 # number of demand (read+write) MSHR hits
1821system.cpu1.dcache.overall_mshr_hits::cpu1.data 1045689 # number of overall MSHR hits
1822system.cpu1.dcache.overall_mshr_hits::total 1045689 # number of overall MSHR hits
1823system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2972042 # number of ReadReq MSHR misses
1824system.cpu1.dcache.ReadReq_mshr_misses::total 2972042 # number of ReadReq MSHR misses
1825system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1289258 # number of WriteReq MSHR misses
1826system.cpu1.dcache.WriteReq_mshr_misses::total 1289258 # number of WriteReq MSHR misses
1827system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 607473 # number of SoftPFReq MSHR misses
1828system.cpu1.dcache.SoftPFReq_mshr_misses::total 607473 # number of SoftPFReq MSHR misses
1829system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 439223 # number of WriteLineReq MSHR misses
1830system.cpu1.dcache.WriteLineReq_mshr_misses::total 439223 # number of WriteLineReq MSHR misses
1831system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 123664 # number of LoadLockedReq MSHR misses
1832system.cpu1.dcache.LoadLockedReq_mshr_misses::total 123664 # number of LoadLockedReq MSHR misses
1833system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199344 # number of StoreCondReq MSHR misses
1834system.cpu1.dcache.StoreCondReq_mshr_misses::total 199344 # number of StoreCondReq MSHR misses
1835system.cpu1.dcache.demand_mshr_misses::cpu1.data 4700523 # number of demand (read+write) MSHR misses
1836system.cpu1.dcache.demand_mshr_misses::total 4700523 # number of demand (read+write) MSHR misses
1837system.cpu1.dcache.overall_mshr_misses::cpu1.data 5307996 # number of overall MSHR misses
1838system.cpu1.dcache.overall_mshr_misses::total 5307996 # number of overall MSHR misses
1839system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
1840system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5330 # number of ReadReq MSHR uncacheable
1841system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
1842system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
1843system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
1844system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10596 # number of overall MSHR uncacheable misses
1845system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43920578500 # number of ReadReq MSHR miss cycles
1846system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43920578500 # number of ReadReq MSHR miss cycles
1847system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24016685500 # number of WriteReq MSHR miss cycles
1848system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24016685500 # number of WriteReq MSHR miss cycles
1849system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14415408000 # number of SoftPFReq MSHR miss cycles
1850system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14415408000 # number of SoftPFReq MSHR miss cycles
1851system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10114952000 # number of WriteLineReq MSHR miss cycles
1852system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10114952000 # number of WriteLineReq MSHR miss cycles
1853system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1723729000 # number of LoadLockedReq MSHR miss cycles
1854system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1723729000 # number of LoadLockedReq MSHR miss cycles
1855system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4572940000 # number of StoreCondReq MSHR miss cycles
1856system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4572940000 # number of StoreCondReq MSHR miss cycles
1857system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2004000 # number of StoreCondFailReq MSHR miss cycles
1858system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2004000 # number of StoreCondFailReq MSHR miss cycles
1859system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78052216000 # number of demand (read+write) MSHR miss cycles
1860system.cpu1.dcache.demand_mshr_miss_latency::total 78052216000 # number of demand (read+write) MSHR miss cycles
1861system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 92467624000 # number of overall MSHR miss cycles
1862system.cpu1.dcache.overall_mshr_miss_latency::total 92467624000 # number of overall MSHR miss cycles
1863system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 634565500 # number of ReadReq MSHR uncacheable cycles
1864system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 634565500 # number of ReadReq MSHR uncacheable cycles
1865system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 634565500 # number of overall MSHR uncacheable cycles
1866system.cpu1.dcache.overall_mshr_uncacheable_latency::total 634565500 # number of overall MSHR uncacheable cycles
1867system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036481 # mshr miss rate for ReadReq accesses
1868system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036481 # mshr miss rate for ReadReq accesses
1869system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018145 # mshr miss rate for WriteReq accesses
1870system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018145 # mshr miss rate for WriteReq accesses
1871system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.720882 # mshr miss rate for SoftPFReq accesses
1872system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.720882 # mshr miss rate for SoftPFReq accesses
1873system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.752943 # mshr miss rate for WriteLineReq accesses
1874system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.752943 # mshr miss rate for WriteLineReq accesses
1875system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064463 # mshr miss rate for LoadLockedReq accesses
1876system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064463 # mshr miss rate for LoadLockedReq accesses
1877system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103979 # mshr miss rate for StoreCondReq accesses
1878system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103979 # mshr miss rate for StoreCondReq accesses
1879system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030702 # mshr miss rate for demand accesses
1880system.cpu1.dcache.demand_mshr_miss_rate::total 0.030702 # mshr miss rate for demand accesses
1881system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034480 # mshr miss rate for overall accesses
1882system.cpu1.dcache.overall_mshr_miss_rate::total 0.034480 # mshr miss rate for overall accesses
1883system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14777.913132 # average ReadReq mshr miss latency
1884system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14777.913132 # average ReadReq mshr miss latency
1885system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18628.300542 # average WriteReq mshr miss latency
1886system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18628.300542 # average WriteReq mshr miss latency
1887system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23730.121339 # average SoftPFReq mshr miss latency
1888system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23730.121339 # average SoftPFReq mshr miss latency
1889system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23029.194737 # average WriteLineReq mshr miss latency
1890system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23029.194737 # average WriteLineReq mshr miss latency
1891system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13938.810001 # average LoadLockedReq mshr miss latency
1892system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13938.810001 # average LoadLockedReq mshr miss latency
1893system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22939.943013 # average StoreCondReq mshr miss latency
1894system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22939.943013 # average StoreCondReq mshr miss latency
1895system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1896system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1897system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16605.006719 # average overall mshr miss latency
1898system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16605.006719 # average overall mshr miss latency
1899system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17420.439654 # average overall mshr miss latency
1900system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17420.439654 # average overall mshr miss latency
1901system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 119055.440901 # average ReadReq mshr uncacheable latency
1902system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 119055.440901 # average ReadReq mshr uncacheable latency
1903system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 59887.268781 # average overall mshr uncacheable latency
1904system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 59887.268781 # average overall mshr uncacheable latency
1905system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1906system.cpu1.icache.tags.replacements 8722673 # number of replacements
1907system.cpu1.icache.tags.tagsinuse 507.263120 # Cycle average of tags in use
1908system.cpu1.icache.tags.total_refs 175283400 # Total number of references to valid blocks.
1909system.cpu1.icache.tags.sampled_refs 8723185 # Sample count of references to valid blocks.
1910system.cpu1.icache.tags.avg_refs 20.093968 # Average number of references to valid blocks.
1911system.cpu1.icache.tags.warmup_cycle 8363988306000 # Cycle when the warmup percentage was hit.
1912system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.263120 # Average occupied blocks per requestor
1913system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990748 # Average percentage of cache occupancy
1914system.cpu1.icache.tags.occ_percent::total 0.990748 # Average percentage of cache occupancy
1915system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1916system.cpu1.icache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id
1917system.cpu1.icache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id
1918system.cpu1.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
1919system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1920system.cpu1.icache.tags.tag_accesses 376736355 # Number of tag accesses
1921system.cpu1.icache.tags.data_accesses 376736355 # Number of data accesses
1922system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
1923system.cpu1.icache.ReadReq_hits::cpu1.inst 175283400 # number of ReadReq hits
1924system.cpu1.icache.ReadReq_hits::total 175283400 # number of ReadReq hits
1925system.cpu1.icache.demand_hits::cpu1.inst 175283400 # number of demand (read+write) hits
1926system.cpu1.icache.demand_hits::total 175283400 # number of demand (read+write) hits
1927system.cpu1.icache.overall_hits::cpu1.inst 175283400 # number of overall hits
1928system.cpu1.icache.overall_hits::total 175283400 # number of overall hits
1929system.cpu1.icache.ReadReq_misses::cpu1.inst 8723185 # number of ReadReq misses
1930system.cpu1.icache.ReadReq_misses::total 8723185 # number of ReadReq misses
1931system.cpu1.icache.demand_misses::cpu1.inst 8723185 # number of demand (read+write) misses
1932system.cpu1.icache.demand_misses::total 8723185 # number of demand (read+write) misses
1933system.cpu1.icache.overall_misses::cpu1.inst 8723185 # number of overall misses
1934system.cpu1.icache.overall_misses::total 8723185 # number of overall misses
1935system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 89772651500 # number of ReadReq miss cycles
1936system.cpu1.icache.ReadReq_miss_latency::total 89772651500 # number of ReadReq miss cycles
1937system.cpu1.icache.demand_miss_latency::cpu1.inst 89772651500 # number of demand (read+write) miss cycles
1938system.cpu1.icache.demand_miss_latency::total 89772651500 # number of demand (read+write) miss cycles
1939system.cpu1.icache.overall_miss_latency::cpu1.inst 89772651500 # number of overall miss cycles
1940system.cpu1.icache.overall_miss_latency::total 89772651500 # number of overall miss cycles
1941system.cpu1.icache.ReadReq_accesses::cpu1.inst 184006585 # number of ReadReq accesses(hits+misses)
1942system.cpu1.icache.ReadReq_accesses::total 184006585 # number of ReadReq accesses(hits+misses)
1943system.cpu1.icache.demand_accesses::cpu1.inst 184006585 # number of demand (read+write) accesses
1944system.cpu1.icache.demand_accesses::total 184006585 # number of demand (read+write) accesses
1945system.cpu1.icache.overall_accesses::cpu1.inst 184006585 # number of overall (read+write) accesses
1946system.cpu1.icache.overall_accesses::total 184006585 # number of overall (read+write) accesses
1947system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.047407 # miss rate for ReadReq accesses
1948system.cpu1.icache.ReadReq_miss_rate::total 0.047407 # miss rate for ReadReq accesses
1949system.cpu1.icache.demand_miss_rate::cpu1.inst 0.047407 # miss rate for demand accesses
1950system.cpu1.icache.demand_miss_rate::total 0.047407 # miss rate for demand accesses
1951system.cpu1.icache.overall_miss_rate::cpu1.inst 0.047407 # miss rate for overall accesses
1952system.cpu1.icache.overall_miss_rate::total 0.047407 # miss rate for overall accesses
1953system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10291.269932 # average ReadReq miss latency
1954system.cpu1.icache.ReadReq_avg_miss_latency::total 10291.269932 # average ReadReq miss latency
1955system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
1956system.cpu1.icache.demand_avg_miss_latency::total 10291.269932 # average overall miss latency
1957system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10291.269932 # average overall miss latency
1958system.cpu1.icache.overall_avg_miss_latency::total 10291.269932 # average overall miss latency
1959system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1960system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1961system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1962system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1963system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1964system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1965system.cpu1.icache.writebacks::writebacks 8722673 # number of writebacks
1966system.cpu1.icache.writebacks::total 8722673 # number of writebacks
1967system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8723185 # number of ReadReq MSHR misses
1968system.cpu1.icache.ReadReq_mshr_misses::total 8723185 # number of ReadReq MSHR misses
1969system.cpu1.icache.demand_mshr_misses::cpu1.inst 8723185 # number of demand (read+write) MSHR misses
1970system.cpu1.icache.demand_mshr_misses::total 8723185 # number of demand (read+write) MSHR misses
1971system.cpu1.icache.overall_mshr_misses::cpu1.inst 8723185 # number of overall MSHR misses
1972system.cpu1.icache.overall_mshr_misses::total 8723185 # number of overall MSHR misses
1973system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
1974system.cpu1.icache.ReadReq_mshr_uncacheable::total 95 # number of ReadReq MSHR uncacheable
1975system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
1976system.cpu1.icache.overall_mshr_uncacheable_misses::total 95 # number of overall MSHR uncacheable misses
1977system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85411059000 # number of ReadReq MSHR miss cycles
1978system.cpu1.icache.ReadReq_mshr_miss_latency::total 85411059000 # number of ReadReq MSHR miss cycles
1979system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85411059000 # number of demand (read+write) MSHR miss cycles
1980system.cpu1.icache.demand_mshr_miss_latency::total 85411059000 # number of demand (read+write) MSHR miss cycles
1981system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85411059000 # number of overall MSHR miss cycles
1982system.cpu1.icache.overall_mshr_miss_latency::total 85411059000 # number of overall MSHR miss cycles
1983system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9620500 # number of ReadReq MSHR uncacheable cycles
1984system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9620500 # number of ReadReq MSHR uncacheable cycles
1985system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9620500 # number of overall MSHR uncacheable cycles
1986system.cpu1.icache.overall_mshr_uncacheable_latency::total 9620500 # number of overall MSHR uncacheable cycles
1987system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for ReadReq accesses
1988system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.047407 # mshr miss rate for ReadReq accesses
1989system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for demand accesses
1990system.cpu1.icache.demand_mshr_miss_rate::total 0.047407 # mshr miss rate for demand accesses
1991system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.047407 # mshr miss rate for overall accesses
1992system.cpu1.icache.overall_mshr_miss_rate::total 0.047407 # mshr miss rate for overall accesses
1993system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average ReadReq mshr miss latency
1994system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9791.269932 # average ReadReq mshr miss latency
1995system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
1996system.cpu1.icache.demand_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
1997system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9791.269932 # average overall mshr miss latency
1998system.cpu1.icache.overall_avg_mshr_miss_latency::total 9791.269932 # average overall mshr miss latency
1999system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average ReadReq mshr uncacheable latency
2000system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101268.421053 # average ReadReq mshr uncacheable latency
2001system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101268.421053 # average overall mshr uncacheable latency
2002system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101268.421053 # average overall mshr uncacheable latency
2003system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2004system.cpu1.l2cache.prefetcher.num_hwpf_issued 7056390 # number of hwpf issued
2005system.cpu1.l2cache.prefetcher.pfIdentified 7056554 # number of prefetch candidates identified
2006system.cpu1.l2cache.prefetcher.pfBufferHit 145 # number of redundant prefetches already in prefetch queue
2007system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2008system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2009system.cpu1.l2cache.prefetcher.pfSpanPage 902638 # number of prefetches not generated due to page crossing
2010system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2011system.cpu1.l2cache.tags.replacements 2217652 # number of replacements
2012system.cpu1.l2cache.tags.tagsinuse 13067.579403 # Cycle average of tags in use
2013system.cpu1.l2cache.tags.total_refs 12709221 # Total number of references to valid blocks.
2014system.cpu1.l2cache.tags.sampled_refs 2233219 # Sample count of references to valid blocks.
2015system.cpu1.l2cache.tags.avg_refs 5.690987 # Average number of references to valid blocks.
2016system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2017system.cpu1.l2cache.tags.occ_blocks::writebacks 12703.923602 # Average occupied blocks per requestor
2018system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 30.973948 # Average occupied blocks per requestor
2019system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 15.153172 # Average occupied blocks per requestor
2020system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 317.528681 # Average occupied blocks per requestor
2021system.cpu1.l2cache.tags.occ_percent::writebacks 0.775386 # Average percentage of cache occupancy
2022system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001890 # Average percentage of cache occupancy
2023system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000925 # Average percentage of cache occupancy
2024system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019380 # Average percentage of cache occupancy
2025system.cpu1.l2cache.tags.occ_percent::total 0.797582 # Average percentage of cache occupancy
2026system.cpu1.l2cache.tags.occ_task_id_blocks::1022 287 # Occupied blocks per task id
2027system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id
2028system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id
2029system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 85 # Occupied blocks per task id
2030system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 84 # Occupied blocks per task id
2031system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
2032system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
2033system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
2034system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 27 # Occupied blocks per task id
2035system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 19 # Occupied blocks per task id
2036system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
2037system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 328 # Occupied blocks per task id
2038system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1567 # Occupied blocks per task id
2039system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id
2040system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5612 # Occupied blocks per task id
2041system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2311 # Occupied blocks per task id
2042system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017517 # Percentage of cache occupancy per task id
2043system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id
2044system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id
2045system.cpu1.l2cache.tags.tag_accesses 477362276 # Number of tag accesses
2046system.cpu1.l2cache.tags.data_accesses 477362276 # Number of data accesses
2047system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2048system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532002 # number of ReadReq hits
2049system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 159372 # number of ReadReq hits
2050system.cpu1.l2cache.ReadReq_hits::total 691374 # number of ReadReq hits
2051system.cpu1.l2cache.WritebackDirty_hits::writebacks 3201676 # number of WritebackDirty hits
2052system.cpu1.l2cache.WritebackDirty_hits::total 3201676 # number of WritebackDirty hits
2053system.cpu1.l2cache.WritebackClean_hits::writebacks 10651334 # number of WritebackClean hits
2054system.cpu1.l2cache.WritebackClean_hits::total 10651334 # number of WritebackClean hits
2055system.cpu1.l2cache.ReadExReq_hits::cpu1.data 860878 # number of ReadExReq hits
2056system.cpu1.l2cache.ReadExReq_hits::total 860878 # number of ReadExReq hits
2057system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8051210 # number of ReadCleanReq hits
2058system.cpu1.l2cache.ReadCleanReq_hits::total 8051210 # number of ReadCleanReq hits
2059system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2757056 # number of ReadSharedReq hits
2060system.cpu1.l2cache.ReadSharedReq_hits::total 2757056 # number of ReadSharedReq hits
2061system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173091 # number of InvalidateReq hits
2062system.cpu1.l2cache.InvalidateReq_hits::total 173091 # number of InvalidateReq hits
2063system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532002 # number of demand (read+write) hits
2064system.cpu1.l2cache.demand_hits::cpu1.itb.walker 159372 # number of demand (read+write) hits
2065system.cpu1.l2cache.demand_hits::cpu1.inst 8051210 # number of demand (read+write) hits
2066system.cpu1.l2cache.demand_hits::cpu1.data 3617934 # number of demand (read+write) hits
2067system.cpu1.l2cache.demand_hits::total 12360518 # number of demand (read+write) hits
2068system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532002 # number of overall hits
2069system.cpu1.l2cache.overall_hits::cpu1.itb.walker 159372 # number of overall hits
2070system.cpu1.l2cache.overall_hits::cpu1.inst 8051210 # number of overall hits
2071system.cpu1.l2cache.overall_hits::cpu1.data 3617934 # number of overall hits
2072system.cpu1.l2cache.overall_hits::total 12360518 # number of overall hits
2073system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21589 # number of ReadReq misses
2074system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10425 # number of ReadReq misses
2075system.cpu1.l2cache.ReadReq_misses::total 32014 # number of ReadReq misses
2076system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 206575 # number of UpgradeReq misses
2077system.cpu1.l2cache.UpgradeReq_misses::total 206575 # number of UpgradeReq misses
2078system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199341 # number of SCUpgradeReq misses
2079system.cpu1.l2cache.SCUpgradeReq_misses::total 199341 # number of SCUpgradeReq misses
2080system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2081system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2082system.cpu1.l2cache.ReadExReq_misses::cpu1.data 222346 # number of ReadExReq misses
2083system.cpu1.l2cache.ReadExReq_misses::total 222346 # number of ReadExReq misses
2084system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 671975 # number of ReadCleanReq misses
2085system.cpu1.l2cache.ReadCleanReq_misses::total 671975 # number of ReadCleanReq misses
2086system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 945788 # number of ReadSharedReq misses
2087system.cpu1.l2cache.ReadSharedReq_misses::total 945788 # number of ReadSharedReq misses
2088system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 266132 # number of InvalidateReq misses
2089system.cpu1.l2cache.InvalidateReq_misses::total 266132 # number of InvalidateReq misses
2090system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21589 # number of demand (read+write) misses
2091system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10425 # number of demand (read+write) misses
2092system.cpu1.l2cache.demand_misses::cpu1.inst 671975 # number of demand (read+write) misses
2093system.cpu1.l2cache.demand_misses::cpu1.data 1168134 # number of demand (read+write) misses
2094system.cpu1.l2cache.demand_misses::total 1872123 # number of demand (read+write) misses
2095system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21589 # number of overall misses
2096system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10425 # number of overall misses
2097system.cpu1.l2cache.overall_misses::cpu1.inst 671975 # number of overall misses
2098system.cpu1.l2cache.overall_misses::cpu1.data 1168134 # number of overall misses
2099system.cpu1.l2cache.overall_misses::total 1872123 # number of overall misses
2100system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 733662000 # number of ReadReq miss cycles
2101system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 446226000 # number of ReadReq miss cycles
2102system.cpu1.l2cache.ReadReq_miss_latency::total 1179888000 # number of ReadReq miss cycles
2103system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 870385500 # number of UpgradeReq miss cycles
2104system.cpu1.l2cache.UpgradeReq_miss_latency::total 870385500 # number of UpgradeReq miss cycles
2105system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 311325000 # number of SCUpgradeReq miss cycles
2106system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 311325000 # number of SCUpgradeReq miss cycles
2107system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1930000 # number of SCUpgradeFailReq miss cycles
2108system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1930000 # number of SCUpgradeFailReq miss cycles
2109system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11310487497 # number of ReadExReq miss cycles
2110system.cpu1.l2cache.ReadExReq_miss_latency::total 11310487497 # number of ReadExReq miss cycles
2111system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 23715219500 # number of ReadCleanReq miss cycles
2112system.cpu1.l2cache.ReadCleanReq_miss_latency::total 23715219500 # number of ReadCleanReq miss cycles
2113system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36332241992 # number of ReadSharedReq miss cycles
2114system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36332241992 # number of ReadSharedReq miss cycles
2115system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 733662000 # number of demand (read+write) miss cycles
2116system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 446226000 # number of demand (read+write) miss cycles
2117system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23715219500 # number of demand (read+write) miss cycles
2118system.cpu1.l2cache.demand_miss_latency::cpu1.data 47642729489 # number of demand (read+write) miss cycles
2119system.cpu1.l2cache.demand_miss_latency::total 72537836989 # number of demand (read+write) miss cycles
2120system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 733662000 # number of overall miss cycles
2121system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 446226000 # number of overall miss cycles
2122system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23715219500 # number of overall miss cycles
2123system.cpu1.l2cache.overall_miss_latency::cpu1.data 47642729489 # number of overall miss cycles
2124system.cpu1.l2cache.overall_miss_latency::total 72537836989 # number of overall miss cycles
2125system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 553591 # number of ReadReq accesses(hits+misses)
2126system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169797 # number of ReadReq accesses(hits+misses)
2127system.cpu1.l2cache.ReadReq_accesses::total 723388 # number of ReadReq accesses(hits+misses)
2128system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3201676 # number of WritebackDirty accesses(hits+misses)
2129system.cpu1.l2cache.WritebackDirty_accesses::total 3201676 # number of WritebackDirty accesses(hits+misses)
2130system.cpu1.l2cache.WritebackClean_accesses::writebacks 10651334 # number of WritebackClean accesses(hits+misses)
2131system.cpu1.l2cache.WritebackClean_accesses::total 10651334 # number of WritebackClean accesses(hits+misses)
2132system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 206575 # number of UpgradeReq accesses(hits+misses)
2133system.cpu1.l2cache.UpgradeReq_accesses::total 206575 # number of UpgradeReq accesses(hits+misses)
2134system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199341 # number of SCUpgradeReq accesses(hits+misses)
2135system.cpu1.l2cache.SCUpgradeReq_accesses::total 199341 # number of SCUpgradeReq accesses(hits+misses)
2136system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2137system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2138system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1083224 # number of ReadExReq accesses(hits+misses)
2139system.cpu1.l2cache.ReadExReq_accesses::total 1083224 # number of ReadExReq accesses(hits+misses)
2140system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8723185 # number of ReadCleanReq accesses(hits+misses)
2141system.cpu1.l2cache.ReadCleanReq_accesses::total 8723185 # number of ReadCleanReq accesses(hits+misses)
2142system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3702844 # number of ReadSharedReq accesses(hits+misses)
2143system.cpu1.l2cache.ReadSharedReq_accesses::total 3702844 # number of ReadSharedReq accesses(hits+misses)
2144system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 439223 # number of InvalidateReq accesses(hits+misses)
2145system.cpu1.l2cache.InvalidateReq_accesses::total 439223 # number of InvalidateReq accesses(hits+misses)
2146system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 553591 # number of demand (read+write) accesses
2147system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169797 # number of demand (read+write) accesses
2148system.cpu1.l2cache.demand_accesses::cpu1.inst 8723185 # number of demand (read+write) accesses
2149system.cpu1.l2cache.demand_accesses::cpu1.data 4786068 # number of demand (read+write) accesses
2150system.cpu1.l2cache.demand_accesses::total 14232641 # number of demand (read+write) accesses
2151system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 553591 # number of overall (read+write) accesses
2152system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169797 # number of overall (read+write) accesses
2153system.cpu1.l2cache.overall_accesses::cpu1.inst 8723185 # number of overall (read+write) accesses
2154system.cpu1.l2cache.overall_accesses::cpu1.data 4786068 # number of overall (read+write) accesses
2155system.cpu1.l2cache.overall_accesses::total 14232641 # number of overall (read+write) accesses
2156system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for ReadReq accesses
2157system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.061397 # miss rate for ReadReq accesses
2158system.cpu1.l2cache.ReadReq_miss_rate::total 0.044256 # miss rate for ReadReq accesses
2159system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
2160system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
2161system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2162system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2163system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2164system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2165system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.205263 # miss rate for ReadExReq accesses
2166system.cpu1.l2cache.ReadExReq_miss_rate::total 0.205263 # miss rate for ReadExReq accesses
2167system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.077033 # miss rate for ReadCleanReq accesses
2168system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.077033 # miss rate for ReadCleanReq accesses
2169system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255422 # miss rate for ReadSharedReq accesses
2170system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255422 # miss rate for ReadSharedReq accesses
2171system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.605915 # miss rate for InvalidateReq accesses
2172system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.605915 # miss rate for InvalidateReq accesses
2173system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for demand accesses
2174system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.061397 # miss rate for demand accesses
2175system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.077033 # miss rate for demand accesses
2176system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244070 # miss rate for demand accesses
2177system.cpu1.l2cache.demand_miss_rate::total 0.131537 # miss rate for demand accesses
2178system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038998 # miss rate for overall accesses
2179system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.061397 # miss rate for overall accesses
2180system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.077033 # miss rate for overall accesses
2181system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244070 # miss rate for overall accesses
2182system.cpu1.l2cache.overall_miss_rate::total 0.131537 # miss rate for overall accesses
2183system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average ReadReq miss latency
2184system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42803.453237 # average ReadReq miss latency
2185system.cpu1.l2cache.ReadReq_avg_miss_latency::total 36855.375773 # average ReadReq miss latency
2186system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4213.411594 # average UpgradeReq miss latency
2187system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4213.411594 # average UpgradeReq miss latency
2188system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1561.771036 # average SCUpgradeReq miss latency
2189system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1561.771036 # average SCUpgradeReq miss latency
2190system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 643333.333333 # average SCUpgradeFailReq miss latency
2191system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 643333.333333 # average SCUpgradeFailReq miss latency
2192system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50868.859782 # average ReadExReq miss latency
2193system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50868.859782 # average ReadExReq miss latency
2194system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35291.818148 # average ReadCleanReq miss latency
2195system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35291.818148 # average ReadCleanReq miss latency
2196system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38414.784277 # average ReadSharedReq miss latency
2197system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38414.784277 # average ReadSharedReq miss latency
2198system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
2199system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
2200system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
2201system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
2202system.cpu1.l2cache.demand_avg_miss_latency::total 38746.298715 # average overall miss latency
2203system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33983.139562 # average overall miss latency
2204system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42803.453237 # average overall miss latency
2205system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35291.818148 # average overall miss latency
2206system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40785.328985 # average overall miss latency
2207system.cpu1.l2cache.overall_avg_miss_latency::total 38746.298715 # average overall miss latency
2208system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2209system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2210system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2211system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2212system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2213system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2214system.cpu1.l2cache.unused_prefetches 44670 # number of HardPF blocks evicted w/o reference
2215system.cpu1.l2cache.writebacks::writebacks 1164875 # number of writebacks
2216system.cpu1.l2cache.writebacks::total 1164875 # number of writebacks
2217system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 19 # number of ReadReq MSHR hits
2218system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 106 # number of ReadReq MSHR hits
2219system.cpu1.l2cache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
2220system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8703 # number of ReadExReq MSHR hits
2221system.cpu1.l2cache.ReadExReq_mshr_hits::total 8703 # number of ReadExReq MSHR hits
2222system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
2223system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2224system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 710 # number of ReadSharedReq MSHR hits
2225system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 710 # number of ReadSharedReq MSHR hits
2226system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 19 # number of demand (read+write) MSHR hits
2227system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 106 # number of demand (read+write) MSHR hits
2228system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2229system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9413 # number of demand (read+write) MSHR hits
2230system.cpu1.l2cache.demand_mshr_hits::total 9539 # number of demand (read+write) MSHR hits
2231system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 19 # number of overall MSHR hits
2232system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 106 # number of overall MSHR hits
2233system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2234system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9413 # number of overall MSHR hits
2235system.cpu1.l2cache.overall_mshr_hits::total 9539 # number of overall MSHR hits
2236system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21570 # number of ReadReq MSHR misses
2237system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10319 # number of ReadReq MSHR misses
2238system.cpu1.l2cache.ReadReq_mshr_misses::total 31889 # number of ReadReq MSHR misses
2239system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of HardPFReq MSHR misses
2240system.cpu1.l2cache.HardPFReq_mshr_misses::total 740053 # number of HardPFReq MSHR misses
2241system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 206575 # number of UpgradeReq MSHR misses
2242system.cpu1.l2cache.UpgradeReq_mshr_misses::total 206575 # number of UpgradeReq MSHR misses
2243system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199341 # number of SCUpgradeReq MSHR misses
2244system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199341 # number of SCUpgradeReq MSHR misses
2245system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2246system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2247system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 213643 # number of ReadExReq MSHR misses
2248system.cpu1.l2cache.ReadExReq_mshr_misses::total 213643 # number of ReadExReq MSHR misses
2249system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 671974 # number of ReadCleanReq MSHR misses
2250system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 671974 # number of ReadCleanReq MSHR misses
2251system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 945078 # number of ReadSharedReq MSHR misses
2252system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 945078 # number of ReadSharedReq MSHR misses
2253system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 266132 # number of InvalidateReq MSHR misses
2254system.cpu1.l2cache.InvalidateReq_mshr_misses::total 266132 # number of InvalidateReq MSHR misses
2255system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21570 # number of demand (read+write) MSHR misses
2256system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10319 # number of demand (read+write) MSHR misses
2257system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 671974 # number of demand (read+write) MSHR misses
2258system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1158721 # number of demand (read+write) MSHR misses
2259system.cpu1.l2cache.demand_mshr_misses::total 1862584 # number of demand (read+write) MSHR misses
2260system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21570 # number of overall MSHR misses
2261system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10319 # number of overall MSHR misses
2262system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 671974 # number of overall MSHR misses
2263system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1158721 # number of overall MSHR misses
2264system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 740053 # number of overall MSHR misses
2265system.cpu1.l2cache.overall_mshr_misses::total 2602637 # number of overall MSHR misses
2266system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
2267system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5330 # number of ReadReq MSHR uncacheable
2268system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5425 # number of ReadReq MSHR uncacheable
2269system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
2270system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5266 # number of WriteReq MSHR uncacheable
2271system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 95 # number of overall MSHR uncacheable misses
2272system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10596 # number of overall MSHR uncacheable misses
2273system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10691 # number of overall MSHR uncacheable misses
2274system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of ReadReq MSHR miss cycles
2275system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 382493500 # number of ReadReq MSHR miss cycles
2276system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 986284000 # number of ReadReq MSHR miss cycles
2277system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of HardPFReq MSHR miss cycles
2278system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 37370954173 # number of HardPFReq MSHR miss cycles
2279system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3898631994 # number of UpgradeReq MSHR miss cycles
2280system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3898631994 # number of UpgradeReq MSHR miss cycles
2281system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3073389997 # number of SCUpgradeReq MSHR miss cycles
2282system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3073389997 # number of SCUpgradeReq MSHR miss cycles
2283system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1642000 # number of SCUpgradeFailReq MSHR miss cycles
2284system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1642000 # number of SCUpgradeFailReq MSHR miss cycles
2285system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8857402997 # number of ReadExReq MSHR miss cycles
2286system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8857402997 # number of ReadExReq MSHR miss cycles
2287system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 19683346000 # number of ReadCleanReq MSHR miss cycles
2288system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 19683346000 # number of ReadCleanReq MSHR miss cycles
2289system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30564768492 # number of ReadSharedReq MSHR miss cycles
2290system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30564768492 # number of ReadSharedReq MSHR miss cycles
2291system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6658115000 # number of InvalidateReq MSHR miss cycles
2292system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6658115000 # number of InvalidateReq MSHR miss cycles
2293system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of demand (read+write) MSHR miss cycles
2294system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 382493500 # number of demand (read+write) MSHR miss cycles
2295system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 19683346000 # number of demand (read+write) MSHR miss cycles
2296system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39422171489 # number of demand (read+write) MSHR miss cycles
2297system.cpu1.l2cache.demand_mshr_miss_latency::total 60091801489 # number of demand (read+write) MSHR miss cycles
2298system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 603790500 # number of overall MSHR miss cycles
2299system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 382493500 # number of overall MSHR miss cycles
2300system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 19683346000 # number of overall MSHR miss cycles
2301system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39422171489 # number of overall MSHR miss cycles
2302system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37370954173 # number of overall MSHR miss cycles
2303system.cpu1.l2cache.overall_mshr_miss_latency::total 97462755662 # number of overall MSHR miss cycles
2304system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8860500 # number of ReadReq MSHR uncacheable cycles
2305system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 591855500 # number of ReadReq MSHR uncacheable cycles
2306system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 600716000 # number of ReadReq MSHR uncacheable cycles
2307system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8860500 # number of overall MSHR uncacheable cycles
2308system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 591855500 # number of overall MSHR uncacheable cycles
2309system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 600716000 # number of overall MSHR uncacheable cycles
2310system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for ReadReq accesses
2311system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for ReadReq accesses
2312system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.044083 # mshr miss rate for ReadReq accesses
2313system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2314system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2315system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2316system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2317system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2318system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2319system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2320system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2321system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197229 # mshr miss rate for ReadExReq accesses
2322system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197229 # mshr miss rate for ReadExReq accesses
2323system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for ReadCleanReq accesses
2324system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077033 # mshr miss rate for ReadCleanReq accesses
2325system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255230 # mshr miss rate for ReadSharedReq accesses
2326system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255230 # mshr miss rate for ReadSharedReq accesses
2327system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.605915 # mshr miss rate for InvalidateReq accesses
2328system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.605915 # mshr miss rate for InvalidateReq accesses
2329system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for demand accesses
2330system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for demand accesses
2331system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for demand accesses
2332system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for demand accesses
2333system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130867 # mshr miss rate for demand accesses
2334system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038964 # mshr miss rate for overall accesses
2335system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.060773 # mshr miss rate for overall accesses
2336system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.077033 # mshr miss rate for overall accesses
2337system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242103 # mshr miss rate for overall accesses
2338system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2339system.cpu1.l2cache.overall_mshr_miss_rate::total 0.182864 # mshr miss rate for overall accesses
2340system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average ReadReq mshr miss latency
2341system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average ReadReq mshr miss latency
2342system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 30928.658785 # average ReadReq mshr miss latency
2343system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average HardPFReq mshr miss latency
2344system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50497.672698 # average HardPFReq mshr miss latency
2345system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18872.719322 # average UpgradeReq mshr miss latency
2346system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18872.719322 # average UpgradeReq mshr miss latency
2347system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15417.751476 # average SCUpgradeReq mshr miss latency
2348system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15417.751476 # average SCUpgradeReq mshr miss latency
2349system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 547333.333333 # average SCUpgradeFailReq mshr miss latency
2350system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 547333.333333 # average SCUpgradeFailReq mshr miss latency
2351system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 41458.896369 # average ReadExReq mshr miss latency
2352system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 41458.896369 # average ReadExReq mshr miss latency
2353system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average ReadCleanReq mshr miss latency
2354system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29291.826767 # average ReadCleanReq mshr miss latency
2355system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32341.000946 # average ReadSharedReq mshr miss latency
2356system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32341.000946 # average ReadSharedReq mshr miss latency
2357system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 25018.092526 # average InvalidateReq mshr miss latency
2358system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 25018.092526 # average InvalidateReq mshr miss latency
2359system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
2360system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
2361system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
2362system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
2363system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32262.599426 # average overall mshr miss latency
2364system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27992.141864 # average overall mshr miss latency
2365system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 37066.915399 # average overall mshr miss latency
2366system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29291.826767 # average overall mshr miss latency
2367system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34022.142939 # average overall mshr miss latency
2368system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50497.672698 # average overall mshr miss latency
2369system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37447.694650 # average overall mshr miss latency
2370system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average ReadReq mshr uncacheable latency
2371system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111042.307692 # average ReadReq mshr uncacheable latency
2372system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110731.059908 # average ReadReq mshr uncacheable latency
2373system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93268.421053 # average overall mshr uncacheable latency
2374system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 55856.502454 # average overall mshr uncacheable latency
2375system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 56188.943972 # average overall mshr uncacheable latency
2376system.cpu1.toL2Bus.snoop_filter.tot_requests 28529787 # Total number of requests made to the snoop filter.
2377system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14583123 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2378system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1708 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2379system.cpu1.toL2Bus.snoop_filter.tot_snoops 606717 # Total number of snoops made to the snoop filter.
2380system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 606667 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2381system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 50 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2382system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2383system.cpu1.toL2Bus.trans_dist::ReadReq 808882 # Transaction distribution
2384system.cpu1.toL2Bus.trans_dist::ReadResp 13324164 # Transaction distribution
2385system.cpu1.toL2Bus.trans_dist::WriteReq 5266 # Transaction distribution
2386system.cpu1.toL2Bus.trans_dist::WriteResp 5266 # Transaction distribution
2387system.cpu1.toL2Bus.trans_dist::WritebackDirty 4382442 # Transaction distribution
2388system.cpu1.toL2Bus.trans_dist::WritebackClean 10653044 # Transaction distribution
2389system.cpu1.toL2Bus.trans_dist::CleanEvict 1404546 # Transaction distribution
2390system.cpu1.toL2Bus.trans_dist::HardPFReq 947399 # Transaction distribution
2391system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
2392system.cpu1.toL2Bus.trans_dist::UpgradeReq 393688 # Transaction distribution
2393system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362209 # Transaction distribution
2394system.cpu1.toL2Bus.trans_dist::UpgradeResp 470974 # Transaction distribution
2395system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
2396system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
2397system.cpu1.toL2Bus.trans_dist::ReadExReq 1116382 # Transaction distribution
2398system.cpu1.toL2Bus.trans_dist::ReadExResp 1090257 # Transaction distribution
2399system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8723185 # Transaction distribution
2400system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4832581 # Transaction distribution
2401system.cpu1.toL2Bus.trans_dist::InvalidateReq 501349 # Transaction distribution
2402system.cpu1.toL2Bus.trans_dist::InvalidateResp 440463 # Transaction distribution
2403system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26169233 # Packet count per connected master and slave (bytes)
2404system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16578335 # Packet count per connected master and slave (bytes)
2405system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 358731 # Packet count per connected master and slave (bytes)
2406system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1168114 # Packet count per connected master and slave (bytes)
2407system.cpu1.toL2Bus.pkt_count::total 44274413 # Packet count per connected master and slave (bytes)
2408system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1116540992 # Cumulative packet size per connected master and slave (bytes)
2409system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 640957756 # Cumulative packet size per connected master and slave (bytes)
2410system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1358376 # Cumulative packet size per connected master and slave (bytes)
2411system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4428728 # Cumulative packet size per connected master and slave (bytes)
2412system.cpu1.toL2Bus.pkt_size::total 1763285852 # Cumulative packet size per connected master and slave (bytes)
2413system.cpu1.toL2Bus.snoops 5350505 # Total snoops (count)
2414system.cpu1.toL2Bus.snoopTraffic 82373864 # Total snoop traffic (bytes)
2415system.cpu1.toL2Bus.snoop_fanout::samples 20276302 # Request fanout histogram
2416system.cpu1.toL2Bus.snoop_fanout::mean 0.045824 # Request fanout histogram
2417system.cpu1.toL2Bus.snoop_fanout::stdev 0.209116 # Request fanout histogram
2418system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2419system.cpu1.toL2Bus.snoop_fanout::0 19347205 95.42% 95.42% # Request fanout histogram
2420system.cpu1.toL2Bus.snoop_fanout::1 929047 4.58% 100.00% # Request fanout histogram
2421system.cpu1.toL2Bus.snoop_fanout::2 50 0.00% 100.00% # Request fanout histogram
2422system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2423system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2424system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2425system.cpu1.toL2Bus.snoop_fanout::total 20276302 # Request fanout histogram
2426system.cpu1.toL2Bus.reqLayer0.occupancy 28368994985 # Layer occupancy (ticks)
2427system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2428system.cpu1.toL2Bus.snoopLayer0.occupancy 177802789 # Layer occupancy (ticks)
2429system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2430system.cpu1.toL2Bus.respLayer0.occupancy 13087773257 # Layer occupancy (ticks)
2431system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2432system.cpu1.toL2Bus.respLayer1.occupancy 7613339196 # Layer occupancy (ticks)
2433system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2434system.cpu1.toL2Bus.respLayer2.occupancy 189022822 # Layer occupancy (ticks)
2435system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2436system.cpu1.toL2Bus.respLayer3.occupancy 614644257 # Layer occupancy (ticks)
2437system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2438system.iobus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2439system.iobus.trans_dist::ReadReq 40225 # Transaction distribution
2440system.iobus.trans_dist::ReadResp 40225 # Transaction distribution
2441system.iobus.trans_dist::WriteReq 136513 # Transaction distribution
2442system.iobus.trans_dist::WriteResp 136513 # Transaction distribution
2443system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47228 # Packet count per connected master and slave (bytes)
2444system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2445system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2446system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2447system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2448system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2449system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2450system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2451system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2452system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2453system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2454system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2455system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2456system.iobus.pkt_count_system.bridge.master::total 122162 # Packet count per connected master and slave (bytes)
2457system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
2458system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
2459system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2460system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2461system.iobus.pkt_count::total 353476 # Packet count per connected master and slave (bytes)
2462system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47248 # Cumulative packet size per connected master and slave (bytes)
2463system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2464system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2465system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2466system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2467system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2468system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2469system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2470system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2471system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2472system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2473system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2474system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2475system.iobus.pkt_size_system.bridge.master::total 155269 # Cumulative packet size per connected master and slave (bytes)
2476system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
2477system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
2478system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2479system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2480system.iobus.pkt_size::total 7496307 # Cumulative packet size per connected master and slave (bytes)
2481system.iobus.reqLayer0.occupancy 42338500 # Layer occupancy (ticks)
2482system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2483system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks)
2484system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2485system.iobus.reqLayer2.occupancy 320000 # Layer occupancy (ticks)
2486system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2487system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
2488system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2489system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
2490system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2491system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2492system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2493system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
2494system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2495system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
2496system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2497system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
2498system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2499system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
2500system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2501system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
2502system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2503system.iobus.reqLayer23.occupancy 25881501 # Layer occupancy (ticks)
2504system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2505system.iobus.reqLayer24.occupancy 34511002 # Layer occupancy (ticks)
2506system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2507system.iobus.reqLayer25.occupancy 570151601 # Layer occupancy (ticks)
2508system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2509system.iobus.respLayer0.occupancy 92380000 # Layer occupancy (ticks)
2510system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2511system.iobus.respLayer3.occupancy 147930000 # Layer occupancy (ticks)
2512system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2513system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2514system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2515system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2516system.iocache.tags.replacements 115597 # number of replacements
2517system.iocache.tags.tagsinuse 11.280611 # Cycle average of tags in use
2518system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2519system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks.
2520system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2521system.iocache.tags.warmup_cycle 9162473233000 # Cycle when the warmup percentage was hit.
2522system.iocache.tags.occ_blocks::realview.ethernet 3.844749 # Average occupied blocks per requestor
2523system.iocache.tags.occ_blocks::realview.ide 7.435862 # Average occupied blocks per requestor
2524system.iocache.tags.occ_percent::realview.ethernet 0.240297 # Average percentage of cache occupancy
2525system.iocache.tags.occ_percent::realview.ide 0.464741 # Average percentage of cache occupancy
2526system.iocache.tags.occ_percent::total 0.705038 # Average percentage of cache occupancy
2527system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2528system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2529system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2530system.iocache.tags.tag_accesses 1040910 # Number of tag accesses
2531system.iocache.tags.data_accesses 1040910 # Number of data accesses
2532system.iocache.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2533system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2534system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
2535system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
2536system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2537system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2538system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
2539system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
2540system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2541system.iocache.demand_misses::realview.ide 115617 # number of demand (read+write) misses
2542system.iocache.demand_misses::total 115657 # number of demand (read+write) misses
2543system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2544system.iocache.overall_misses::realview.ide 115617 # number of overall misses
2545system.iocache.overall_misses::total 115657 # number of overall misses
2546system.iocache.ReadReq_miss_latency::realview.ethernet 5196500 # number of ReadReq miss cycles
2547system.iocache.ReadReq_miss_latency::realview.ide 1980206431 # number of ReadReq miss cycles
2548system.iocache.ReadReq_miss_latency::total 1985402931 # number of ReadReq miss cycles
2549system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2550system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2551system.iocache.WriteLineReq_miss_latency::realview.ide 13190432670 # number of WriteLineReq miss cycles
2552system.iocache.WriteLineReq_miss_latency::total 13190432670 # number of WriteLineReq miss cycles
2553system.iocache.demand_miss_latency::realview.ethernet 5565500 # number of demand (read+write) miss cycles
2554system.iocache.demand_miss_latency::realview.ide 15170639101 # number of demand (read+write) miss cycles
2555system.iocache.demand_miss_latency::total 15176204601 # number of demand (read+write) miss cycles
2556system.iocache.overall_miss_latency::realview.ethernet 5565500 # number of overall miss cycles
2557system.iocache.overall_miss_latency::realview.ide 15170639101 # number of overall miss cycles
2558system.iocache.overall_miss_latency::total 15176204601 # number of overall miss cycles
2559system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2560system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
2561system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
2562system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2563system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2564system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
2565system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
2566system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2567system.iocache.demand_accesses::realview.ide 115617 # number of demand (read+write) accesses
2568system.iocache.demand_accesses::total 115657 # number of demand (read+write) accesses
2569system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2570system.iocache.overall_accesses::realview.ide 115617 # number of overall (read+write) accesses
2571system.iocache.overall_accesses::total 115657 # number of overall (read+write) accesses
2572system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2573system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2574system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2575system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2576system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2577system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2578system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2579system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2580system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2581system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2582system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2583system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2584system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2585system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140445.945946 # average ReadReq miss latency
2586system.iocache.ReadReq_avg_miss_latency::realview.ide 222770.438857 # average ReadReq miss latency
2587system.iocache.ReadReq_avg_miss_latency::total 222429.187878 # average ReadReq miss latency
2588system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2589system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2590system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123589.242467 # average WriteLineReq miss latency
2591system.iocache.WriteLineReq_avg_miss_latency::total 123589.242467 # average WriteLineReq miss latency
2592system.iocache.demand_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2593system.iocache.demand_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
2594system.iocache.demand_avg_miss_latency::total 131217.346127 # average overall miss latency
2595system.iocache.overall_avg_miss_latency::realview.ethernet 139137.500000 # average overall miss latency
2596system.iocache.overall_avg_miss_latency::realview.ide 131214.605992 # average overall miss latency
2597system.iocache.overall_avg_miss_latency::total 131217.346127 # average overall miss latency
2598system.iocache.blocked_cycles::no_mshrs 49271 # number of cycles access was blocked
2599system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2600system.iocache.blocked::no_mshrs 3583 # number of cycles access was blocked
2601system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2602system.iocache.avg_blocked_cycles::no_mshrs 13.751326 # average number of cycles each access was blocked
2603system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2604system.iocache.writebacks::writebacks 106693 # number of writebacks
2605system.iocache.writebacks::total 106693 # number of writebacks
2606system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2607system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
2608system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
2609system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2610system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2611system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
2612system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
2613system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2614system.iocache.demand_mshr_misses::realview.ide 115617 # number of demand (read+write) MSHR misses
2615system.iocache.demand_mshr_misses::total 115657 # number of demand (read+write) MSHR misses
2616system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2617system.iocache.overall_mshr_misses::realview.ide 115617 # number of overall MSHR misses
2618system.iocache.overall_mshr_misses::total 115657 # number of overall MSHR misses
2619system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3346500 # number of ReadReq MSHR miss cycles
2620system.iocache.ReadReq_mshr_miss_latency::realview.ide 1535756431 # number of ReadReq MSHR miss cycles
2621system.iocache.ReadReq_mshr_miss_latency::total 1539102931 # number of ReadReq MSHR miss cycles
2622system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2623system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2624system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7847855187 # number of WriteLineReq MSHR miss cycles
2625system.iocache.WriteLineReq_mshr_miss_latency::total 7847855187 # number of WriteLineReq MSHR miss cycles
2626system.iocache.demand_mshr_miss_latency::realview.ethernet 3565500 # number of demand (read+write) MSHR miss cycles
2627system.iocache.demand_mshr_miss_latency::realview.ide 9383611618 # number of demand (read+write) MSHR miss cycles
2628system.iocache.demand_mshr_miss_latency::total 9387177118 # number of demand (read+write) MSHR miss cycles
2629system.iocache.overall_mshr_miss_latency::realview.ethernet 3565500 # number of overall MSHR miss cycles
2630system.iocache.overall_mshr_miss_latency::realview.ide 9383611618 # number of overall MSHR miss cycles
2631system.iocache.overall_mshr_miss_latency::total 9387177118 # number of overall MSHR miss cycles
2632system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2633system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2634system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2635system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2636system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2637system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2638system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2639system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2640system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2641system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2642system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2643system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2644system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2645system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90445.945946 # average ReadReq mshr miss latency
2646system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 172770.438857 # average ReadReq mshr miss latency
2647system.iocache.ReadReq_avg_mshr_miss_latency::total 172429.187878 # average ReadReq mshr miss latency
2648system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2649system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2650system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73531.361845 # average WriteLineReq mshr miss latency
2651system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73531.361845 # average WriteLineReq mshr miss latency
2652system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2653system.iocache.demand_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
2654system.iocache.demand_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
2655system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89137.500000 # average overall mshr miss latency
2656system.iocache.overall_avg_mshr_miss_latency::realview.ide 81161.175415 # average overall mshr miss latency
2657system.iocache.overall_avg_mshr_miss_latency::total 81163.934029 # average overall mshr miss latency
2658system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2659system.l2c.tags.replacements 1609900 # number of replacements
2660system.l2c.tags.tagsinuse 65157.020292 # Cycle average of tags in use
2661system.l2c.tags.total_refs 7484861 # Total number of references to valid blocks.
2662system.l2c.tags.sampled_refs 1671770 # Sample count of references to valid blocks.
2663system.l2c.tags.avg_refs 4.477207 # Average number of references to valid blocks.
2664system.l2c.tags.warmup_cycle 3329231500 # Cycle when the warmup percentage was hit.
2665system.l2c.tags.occ_blocks::writebacks 10396.250510 # Average occupied blocks per requestor
2666system.l2c.tags.occ_blocks::cpu0.dtb.walker 173.300313 # Average occupied blocks per requestor
2667system.l2c.tags.occ_blocks::cpu0.itb.walker 163.171529 # Average occupied blocks per requestor
2668system.l2c.tags.occ_blocks::cpu0.inst 4900.186700 # Average occupied blocks per requestor
2669system.l2c.tags.occ_blocks::cpu0.data 12808.046984 # Average occupied blocks per requestor
2670system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9631.875704 # Average occupied blocks per requestor
2671system.l2c.tags.occ_blocks::cpu1.dtb.walker 290.820455 # Average occupied blocks per requestor
2672system.l2c.tags.occ_blocks::cpu1.itb.walker 308.484030 # Average occupied blocks per requestor
2673system.l2c.tags.occ_blocks::cpu1.inst 3535.017429 # Average occupied blocks per requestor
2674system.l2c.tags.occ_blocks::cpu1.data 11523.081214 # Average occupied blocks per requestor
2675system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11426.785423 # Average occupied blocks per requestor
2676system.l2c.tags.occ_percent::writebacks 0.158634 # Average percentage of cache occupancy
2677system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002644 # Average percentage of cache occupancy
2678system.l2c.tags.occ_percent::cpu0.itb.walker 0.002490 # Average percentage of cache occupancy
2679system.l2c.tags.occ_percent::cpu0.inst 0.074771 # Average percentage of cache occupancy
2680system.l2c.tags.occ_percent::cpu0.data 0.195435 # Average percentage of cache occupancy
2681system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.146971 # Average percentage of cache occupancy
2682system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004438 # Average percentage of cache occupancy
2683system.l2c.tags.occ_percent::cpu1.itb.walker 0.004707 # Average percentage of cache occupancy
2684system.l2c.tags.occ_percent::cpu1.inst 0.053940 # Average percentage of cache occupancy
2685system.l2c.tags.occ_percent::cpu1.data 0.175828 # Average percentage of cache occupancy
2686system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.174359 # Average percentage of cache occupancy
2687system.l2c.tags.occ_percent::total 0.994217 # Average percentage of cache occupancy
2688system.l2c.tags.occ_task_id_blocks::1022 10593 # Occupied blocks per task id
2689system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id
2690system.l2c.tags.occ_task_id_blocks::1024 51026 # Occupied blocks per task id
2691system.l2c.tags.age_task_id_blocks_1022::2 126 # Occupied blocks per task id
2692system.l2c.tags.age_task_id_blocks_1022::3 461 # Occupied blocks per task id
2693system.l2c.tags.age_task_id_blocks_1022::4 10006 # Occupied blocks per task id
2694system.l2c.tags.age_task_id_blocks_1023::4 251 # Occupied blocks per task id
2695system.l2c.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
2696system.l2c.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
2697system.l2c.tags.age_task_id_blocks_1024::2 1785 # Occupied blocks per task id
2698system.l2c.tags.age_task_id_blocks_1024::3 4614 # Occupied blocks per task id
2699system.l2c.tags.age_task_id_blocks_1024::4 44401 # Occupied blocks per task id
2700system.l2c.tags.occ_task_id_percent::1022 0.161636 # Percentage of cache occupancy per task id
2701system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id
2702system.l2c.tags.occ_task_id_percent::1024 0.778595 # Percentage of cache occupancy per task id
2703system.l2c.tags.tag_accesses 82772579 # Number of tag accesses
2704system.l2c.tags.data_accesses 82772579 # Number of data accesses
2705system.l2c.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
2706system.l2c.WritebackDirty_hits::writebacks 2960473 # number of WritebackDirty hits
2707system.l2c.WritebackDirty_hits::total 2960473 # number of WritebackDirty hits
2708system.l2c.UpgradeReq_hits::cpu0.data 214775 # number of UpgradeReq hits
2709system.l2c.UpgradeReq_hits::cpu1.data 151269 # number of UpgradeReq hits
2710system.l2c.UpgradeReq_hits::total 366044 # number of UpgradeReq hits
2711system.l2c.SCUpgradeReq_hits::cpu0.data 56896 # number of SCUpgradeReq hits
2712system.l2c.SCUpgradeReq_hits::cpu1.data 55474 # number of SCUpgradeReq hits
2713system.l2c.SCUpgradeReq_hits::total 112370 # number of SCUpgradeReq hits
2714system.l2c.ReadExReq_hits::cpu0.data 67148 # number of ReadExReq hits
2715system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits
2716system.l2c.ReadExReq_hits::total 118780 # number of ReadExReq hits
2717system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 14203 # number of ReadSharedReq hits
2718system.l2c.ReadSharedReq_hits::cpu0.itb.walker 6226 # number of ReadSharedReq hits
2719system.l2c.ReadSharedReq_hits::cpu0.inst 695308 # number of ReadSharedReq hits
2720system.l2c.ReadSharedReq_hits::cpu0.data 685955 # number of ReadSharedReq hits
2721system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 328258 # number of ReadSharedReq hits
2722system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12341 # number of ReadSharedReq hits
2723system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4684 # number of ReadSharedReq hits
2724system.l2c.ReadSharedReq_hits::cpu1.inst 616265 # number of ReadSharedReq hits
2725system.l2c.ReadSharedReq_hits::cpu1.data 560248 # number of ReadSharedReq hits
2726system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 290505 # number of ReadSharedReq hits
2727system.l2c.ReadSharedReq_hits::total 3213993 # number of ReadSharedReq hits
2728system.l2c.InvalidateReq_hits::cpu0.data 136732 # number of InvalidateReq hits
2729system.l2c.InvalidateReq_hits::cpu1.data 122714 # number of InvalidateReq hits
2730system.l2c.InvalidateReq_hits::total 259446 # number of InvalidateReq hits
2731system.l2c.demand_hits::cpu0.dtb.walker 14203 # number of demand (read+write) hits
2732system.l2c.demand_hits::cpu0.itb.walker 6226 # number of demand (read+write) hits
2733system.l2c.demand_hits::cpu0.inst 695308 # number of demand (read+write) hits
2734system.l2c.demand_hits::cpu0.data 753103 # number of demand (read+write) hits
2735system.l2c.demand_hits::cpu0.l2cache.prefetcher 328258 # number of demand (read+write) hits
2736system.l2c.demand_hits::cpu1.dtb.walker 12341 # number of demand (read+write) hits
2737system.l2c.demand_hits::cpu1.itb.walker 4684 # number of demand (read+write) hits
2738system.l2c.demand_hits::cpu1.inst 616265 # number of demand (read+write) hits
2739system.l2c.demand_hits::cpu1.data 611880 # number of demand (read+write) hits
2740system.l2c.demand_hits::cpu1.l2cache.prefetcher 290505 # number of demand (read+write) hits
2741system.l2c.demand_hits::total 3332773 # number of demand (read+write) hits
2742system.l2c.overall_hits::cpu0.dtb.walker 14203 # number of overall hits
2743system.l2c.overall_hits::cpu0.itb.walker 6226 # number of overall hits
2744system.l2c.overall_hits::cpu0.inst 695308 # number of overall hits
2745system.l2c.overall_hits::cpu0.data 753103 # number of overall hits
2746system.l2c.overall_hits::cpu0.l2cache.prefetcher 328258 # number of overall hits
2747system.l2c.overall_hits::cpu1.dtb.walker 12341 # number of overall hits
2748system.l2c.overall_hits::cpu1.itb.walker 4684 # number of overall hits
2749system.l2c.overall_hits::cpu1.inst 616265 # number of overall hits
2750system.l2c.overall_hits::cpu1.data 611880 # number of overall hits
2751system.l2c.overall_hits::cpu1.l2cache.prefetcher 290505 # number of overall hits
2752system.l2c.overall_hits::total 3332773 # number of overall hits
2753system.l2c.UpgradeReq_misses::cpu0.data 20148 # number of UpgradeReq misses
2754system.l2c.UpgradeReq_misses::cpu1.data 22532 # number of UpgradeReq misses
2755system.l2c.UpgradeReq_misses::total 42680 # number of UpgradeReq misses
2756system.l2c.SCUpgradeReq_misses::cpu0.data 632 # number of SCUpgradeReq misses
2757system.l2c.SCUpgradeReq_misses::cpu1.data 942 # number of SCUpgradeReq misses
2758system.l2c.SCUpgradeReq_misses::total 1574 # number of SCUpgradeReq misses
2759system.l2c.ReadExReq_misses::cpu0.data 82382 # number of ReadExReq misses
2760system.l2c.ReadExReq_misses::cpu1.data 53449 # number of ReadExReq misses
2761system.l2c.ReadExReq_misses::total 135831 # number of ReadExReq misses
2762system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2080 # number of ReadSharedReq misses
2763system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1618 # number of ReadSharedReq misses
2764system.l2c.ReadSharedReq_misses::cpu0.inst 79514 # number of ReadSharedReq misses
2765system.l2c.ReadSharedReq_misses::cpu0.data 147489 # number of ReadSharedReq misses
2766system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 271925 # number of ReadSharedReq misses
2767system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq misses
2768system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2403 # number of ReadSharedReq misses
2769system.l2c.ReadSharedReq_misses::cpu1.inst 55709 # number of ReadSharedReq misses
2770system.l2c.ReadSharedReq_misses::cpu1.data 138924 # number of ReadSharedReq misses
2771system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 236410 # number of ReadSharedReq misses
2772system.l2c.ReadSharedReq_misses::total 938667 # number of ReadSharedReq misses
2773system.l2c.InvalidateReq_misses::cpu0.data 422083 # number of InvalidateReq misses
2774system.l2c.InvalidateReq_misses::cpu1.data 110180 # number of InvalidateReq misses
2775system.l2c.InvalidateReq_misses::total 532263 # number of InvalidateReq misses
2776system.l2c.demand_misses::cpu0.dtb.walker 2080 # number of demand (read+write) misses
2777system.l2c.demand_misses::cpu0.itb.walker 1618 # number of demand (read+write) misses
2778system.l2c.demand_misses::cpu0.inst 79514 # number of demand (read+write) misses
2779system.l2c.demand_misses::cpu0.data 229871 # number of demand (read+write) misses
2780system.l2c.demand_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) misses
2781system.l2c.demand_misses::cpu1.dtb.walker 2595 # number of demand (read+write) misses
2782system.l2c.demand_misses::cpu1.itb.walker 2403 # number of demand (read+write) misses
2783system.l2c.demand_misses::cpu1.inst 55709 # number of demand (read+write) misses
2784system.l2c.demand_misses::cpu1.data 192373 # number of demand (read+write) misses
2785system.l2c.demand_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) misses
2786system.l2c.demand_misses::total 1074498 # number of demand (read+write) misses
2787system.l2c.overall_misses::cpu0.dtb.walker 2080 # number of overall misses
2788system.l2c.overall_misses::cpu0.itb.walker 1618 # number of overall misses
2789system.l2c.overall_misses::cpu0.inst 79514 # number of overall misses
2790system.l2c.overall_misses::cpu0.data 229871 # number of overall misses
2791system.l2c.overall_misses::cpu0.l2cache.prefetcher 271925 # number of overall misses
2792system.l2c.overall_misses::cpu1.dtb.walker 2595 # number of overall misses
2793system.l2c.overall_misses::cpu1.itb.walker 2403 # number of overall misses
2794system.l2c.overall_misses::cpu1.inst 55709 # number of overall misses
2795system.l2c.overall_misses::cpu1.data 192373 # number of overall misses
2796system.l2c.overall_misses::cpu1.l2cache.prefetcher 236410 # number of overall misses
2797system.l2c.overall_misses::total 1074498 # number of overall misses
2798system.l2c.UpgradeReq_miss_latency::cpu0.data 146038500 # number of UpgradeReq miss cycles
2799system.l2c.UpgradeReq_miss_latency::cpu1.data 131790500 # number of UpgradeReq miss cycles
2800system.l2c.UpgradeReq_miss_latency::total 277829000 # number of UpgradeReq miss cycles
2801system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10352000 # number of SCUpgradeReq miss cycles
2802system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8549500 # number of SCUpgradeReq miss cycles
2803system.l2c.SCUpgradeReq_miss_latency::total 18901500 # number of SCUpgradeReq miss cycles
2804system.l2c.ReadExReq_miss_latency::cpu0.data 8710976500 # number of ReadExReq miss cycles
2805system.l2c.ReadExReq_miss_latency::cpu1.data 5673543000 # number of ReadExReq miss cycles
2806system.l2c.ReadExReq_miss_latency::total 14384519500 # number of ReadExReq miss cycles
2807system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 219387000 # number of ReadSharedReq miss cycles
2808system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 170599500 # number of ReadSharedReq miss cycles
2809system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8581562500 # number of ReadSharedReq miss cycles
2810system.l2c.ReadSharedReq_miss_latency::cpu0.data 16399499000 # number of ReadSharedReq miss cycles
2811system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of ReadSharedReq miss cycles
2812system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257094000 # number of ReadSharedReq miss cycles
2813system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 237286000 # number of ReadSharedReq miss cycles
2814system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6184697999 # number of ReadSharedReq miss cycles
2815system.l2c.ReadSharedReq_miss_latency::cpu1.data 15199077000 # number of ReadSharedReq miss cycles
2816system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of ReadSharedReq miss cycles
2817system.l2c.ReadSharedReq_miss_latency::total 118434367320 # number of ReadSharedReq miss cycles
2818system.l2c.demand_miss_latency::cpu0.dtb.walker 219387000 # number of demand (read+write) miss cycles
2819system.l2c.demand_miss_latency::cpu0.itb.walker 170599500 # number of demand (read+write) miss cycles
2820system.l2c.demand_miss_latency::cpu0.inst 8581562500 # number of demand (read+write) miss cycles
2821system.l2c.demand_miss_latency::cpu0.data 25110475500 # number of demand (read+write) miss cycles
2822system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of demand (read+write) miss cycles
2823system.l2c.demand_miss_latency::cpu1.dtb.walker 257094000 # number of demand (read+write) miss cycles
2824system.l2c.demand_miss_latency::cpu1.itb.walker 237286000 # number of demand (read+write) miss cycles
2825system.l2c.demand_miss_latency::cpu1.inst 6184697999 # number of demand (read+write) miss cycles
2826system.l2c.demand_miss_latency::cpu1.data 20872620000 # number of demand (read+write) miss cycles
2827system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of demand (read+write) miss cycles
2828system.l2c.demand_miss_latency::total 132818886820 # number of demand (read+write) miss cycles
2829system.l2c.overall_miss_latency::cpu0.dtb.walker 219387000 # number of overall miss cycles
2830system.l2c.overall_miss_latency::cpu0.itb.walker 170599500 # number of overall miss cycles
2831system.l2c.overall_miss_latency::cpu0.inst 8581562500 # number of overall miss cycles
2832system.l2c.overall_miss_latency::cpu0.data 25110475500 # number of overall miss cycles
2833system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 38998929895 # number of overall miss cycles
2834system.l2c.overall_miss_latency::cpu1.dtb.walker 257094000 # number of overall miss cycles
2835system.l2c.overall_miss_latency::cpu1.itb.walker 237286000 # number of overall miss cycles
2836system.l2c.overall_miss_latency::cpu1.inst 6184697999 # number of overall miss cycles
2837system.l2c.overall_miss_latency::cpu1.data 20872620000 # number of overall miss cycles
2838system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32186234426 # number of overall miss cycles
2839system.l2c.overall_miss_latency::total 132818886820 # number of overall miss cycles
2840system.l2c.WritebackDirty_accesses::writebacks 2960473 # number of WritebackDirty accesses(hits+misses)
2841system.l2c.WritebackDirty_accesses::total 2960473 # number of WritebackDirty accesses(hits+misses)
2842system.l2c.UpgradeReq_accesses::cpu0.data 234923 # number of UpgradeReq accesses(hits+misses)
2843system.l2c.UpgradeReq_accesses::cpu1.data 173801 # number of UpgradeReq accesses(hits+misses)
2844system.l2c.UpgradeReq_accesses::total 408724 # number of UpgradeReq accesses(hits+misses)
2845system.l2c.SCUpgradeReq_accesses::cpu0.data 57528 # number of SCUpgradeReq accesses(hits+misses)
2846system.l2c.SCUpgradeReq_accesses::cpu1.data 56416 # number of SCUpgradeReq accesses(hits+misses)
2847system.l2c.SCUpgradeReq_accesses::total 113944 # number of SCUpgradeReq accesses(hits+misses)
2848system.l2c.ReadExReq_accesses::cpu0.data 149530 # number of ReadExReq accesses(hits+misses)
2849system.l2c.ReadExReq_accesses::cpu1.data 105081 # number of ReadExReq accesses(hits+misses)
2850system.l2c.ReadExReq_accesses::total 254611 # number of ReadExReq accesses(hits+misses)
2851system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16283 # number of ReadSharedReq accesses(hits+misses)
2852system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7844 # number of ReadSharedReq accesses(hits+misses)
2853system.l2c.ReadSharedReq_accesses::cpu0.inst 774822 # number of ReadSharedReq accesses(hits+misses)
2854system.l2c.ReadSharedReq_accesses::cpu0.data 833444 # number of ReadSharedReq accesses(hits+misses)
2855system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 600183 # number of ReadSharedReq accesses(hits+misses)
2856system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14936 # number of ReadSharedReq accesses(hits+misses)
2857system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7087 # number of ReadSharedReq accesses(hits+misses)
2858system.l2c.ReadSharedReq_accesses::cpu1.inst 671974 # number of ReadSharedReq accesses(hits+misses)
2859system.l2c.ReadSharedReq_accesses::cpu1.data 699172 # number of ReadSharedReq accesses(hits+misses)
2860system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 526915 # number of ReadSharedReq accesses(hits+misses)
2861system.l2c.ReadSharedReq_accesses::total 4152660 # number of ReadSharedReq accesses(hits+misses)
2862system.l2c.InvalidateReq_accesses::cpu0.data 558815 # number of InvalidateReq accesses(hits+misses)
2863system.l2c.InvalidateReq_accesses::cpu1.data 232894 # number of InvalidateReq accesses(hits+misses)
2864system.l2c.InvalidateReq_accesses::total 791709 # number of InvalidateReq accesses(hits+misses)
2865system.l2c.demand_accesses::cpu0.dtb.walker 16283 # number of demand (read+write) accesses
2866system.l2c.demand_accesses::cpu0.itb.walker 7844 # number of demand (read+write) accesses
2867system.l2c.demand_accesses::cpu0.inst 774822 # number of demand (read+write) accesses
2868system.l2c.demand_accesses::cpu0.data 982974 # number of demand (read+write) accesses
2869system.l2c.demand_accesses::cpu0.l2cache.prefetcher 600183 # number of demand (read+write) accesses
2870system.l2c.demand_accesses::cpu1.dtb.walker 14936 # number of demand (read+write) accesses
2871system.l2c.demand_accesses::cpu1.itb.walker 7087 # number of demand (read+write) accesses
2872system.l2c.demand_accesses::cpu1.inst 671974 # number of demand (read+write) accesses
2873system.l2c.demand_accesses::cpu1.data 804253 # number of demand (read+write) accesses
2874system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526915 # number of demand (read+write) accesses
2875system.l2c.demand_accesses::total 4407271 # number of demand (read+write) accesses
2876system.l2c.overall_accesses::cpu0.dtb.walker 16283 # number of overall (read+write) accesses
2877system.l2c.overall_accesses::cpu0.itb.walker 7844 # number of overall (read+write) accesses
2878system.l2c.overall_accesses::cpu0.inst 774822 # number of overall (read+write) accesses
2879system.l2c.overall_accesses::cpu0.data 982974 # number of overall (read+write) accesses
2880system.l2c.overall_accesses::cpu0.l2cache.prefetcher 600183 # number of overall (read+write) accesses
2881system.l2c.overall_accesses::cpu1.dtb.walker 14936 # number of overall (read+write) accesses
2882system.l2c.overall_accesses::cpu1.itb.walker 7087 # number of overall (read+write) accesses
2883system.l2c.overall_accesses::cpu1.inst 671974 # number of overall (read+write) accesses
2884system.l2c.overall_accesses::cpu1.data 804253 # number of overall (read+write) accesses
2885system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526915 # number of overall (read+write) accesses
2886system.l2c.overall_accesses::total 4407271 # number of overall (read+write) accesses
2887system.l2c.UpgradeReq_miss_rate::cpu0.data 0.085764 # miss rate for UpgradeReq accesses
2888system.l2c.UpgradeReq_miss_rate::cpu1.data 0.129643 # miss rate for UpgradeReq accesses
2889system.l2c.UpgradeReq_miss_rate::total 0.104423 # miss rate for UpgradeReq accesses
2890system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.010986 # miss rate for SCUpgradeReq accesses
2891system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016697 # miss rate for SCUpgradeReq accesses
2892system.l2c.SCUpgradeReq_miss_rate::total 0.013814 # miss rate for SCUpgradeReq accesses
2893system.l2c.ReadExReq_miss_rate::cpu0.data 0.550940 # miss rate for ReadExReq accesses
2894system.l2c.ReadExReq_miss_rate::cpu1.data 0.508646 # miss rate for ReadExReq accesses
2895system.l2c.ReadExReq_miss_rate::total 0.533484 # miss rate for ReadExReq accesses
2896system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for ReadSharedReq accesses
2897system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.206272 # miss rate for ReadSharedReq accesses
2898system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102622 # miss rate for ReadSharedReq accesses
2899system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.176963 # miss rate for ReadSharedReq accesses
2900system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for ReadSharedReq accesses
2901system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for ReadSharedReq accesses
2902system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.339072 # miss rate for ReadSharedReq accesses
2903system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.082904 # miss rate for ReadSharedReq accesses
2904system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.198698 # miss rate for ReadSharedReq accesses
2905system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for ReadSharedReq accesses
2906system.l2c.ReadSharedReq_miss_rate::total 0.226040 # miss rate for ReadSharedReq accesses
2907system.l2c.InvalidateReq_miss_rate::cpu0.data 0.755318 # miss rate for InvalidateReq accesses
2908system.l2c.InvalidateReq_miss_rate::cpu1.data 0.473091 # miss rate for InvalidateReq accesses
2909system.l2c.InvalidateReq_miss_rate::total 0.672296 # miss rate for InvalidateReq accesses
2910system.l2c.demand_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for demand accesses
2911system.l2c.demand_miss_rate::cpu0.itb.walker 0.206272 # miss rate for demand accesses
2912system.l2c.demand_miss_rate::cpu0.inst 0.102622 # miss rate for demand accesses
2913system.l2c.demand_miss_rate::cpu0.data 0.233853 # miss rate for demand accesses
2914system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for demand accesses
2915system.l2c.demand_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for demand accesses
2916system.l2c.demand_miss_rate::cpu1.itb.walker 0.339072 # miss rate for demand accesses
2917system.l2c.demand_miss_rate::cpu1.inst 0.082904 # miss rate for demand accesses
2918system.l2c.demand_miss_rate::cpu1.data 0.239195 # miss rate for demand accesses
2919system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for demand accesses
2920system.l2c.demand_miss_rate::total 0.243801 # miss rate for demand accesses
2921system.l2c.overall_miss_rate::cpu0.dtb.walker 0.127741 # miss rate for overall accesses
2922system.l2c.overall_miss_rate::cpu0.itb.walker 0.206272 # miss rate for overall accesses
2923system.l2c.overall_miss_rate::cpu0.inst 0.102622 # miss rate for overall accesses
2924system.l2c.overall_miss_rate::cpu0.data 0.233853 # miss rate for overall accesses
2925system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.453070 # miss rate for overall accesses
2926system.l2c.overall_miss_rate::cpu1.dtb.walker 0.173741 # miss rate for overall accesses
2927system.l2c.overall_miss_rate::cpu1.itb.walker 0.339072 # miss rate for overall accesses
2928system.l2c.overall_miss_rate::cpu1.inst 0.082904 # miss rate for overall accesses
2929system.l2c.overall_miss_rate::cpu1.data 0.239195 # miss rate for overall accesses
2930system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448668 # miss rate for overall accesses
2931system.l2c.overall_miss_rate::total 0.243801 # miss rate for overall accesses
2932system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7248.287671 # average UpgradeReq miss latency
2933system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5849.036925 # average UpgradeReq miss latency
2934system.l2c.UpgradeReq_avg_miss_latency::total 6509.582943 # average UpgradeReq miss latency
2935system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16379.746835 # average SCUpgradeReq miss latency
2936system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9075.902335 # average SCUpgradeReq miss latency
2937system.l2c.SCUpgradeReq_avg_miss_latency::total 12008.576874 # average SCUpgradeReq miss latency
2938system.l2c.ReadExReq_avg_miss_latency::cpu0.data 105738.832512 # average ReadExReq miss latency
2939system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106148.721211 # average ReadExReq miss latency
2940system.l2c.ReadExReq_avg_miss_latency::total 105900.122211 # average ReadExReq miss latency
2941system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average ReadSharedReq miss latency
2942system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 105438.504326 # average ReadSharedReq miss latency
2943system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 107925.176698 # average ReadSharedReq miss latency
2944system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111191.336303 # average ReadSharedReq miss latency
2945system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average ReadSharedReq miss latency
2946system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average ReadSharedReq miss latency
2947system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 98745.734499 # average ReadSharedReq miss latency
2948system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111017.932453 # average ReadSharedReq miss latency
2949system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 109405.696640 # average ReadSharedReq miss latency
2950system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average ReadSharedReq miss latency
2951system.l2c.ReadSharedReq_avg_miss_latency::total 126172.931743 # average ReadSharedReq miss latency
2952system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
2953system.l2c.demand_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
2954system.l2c.demand_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
2955system.l2c.demand_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
2956system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
2957system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
2958system.l2c.demand_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
2959system.l2c.demand_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
2960system.l2c.demand_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
2961system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
2962system.l2c.demand_avg_miss_latency::total 123610.175933 # average overall miss latency
2963system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 105474.519231 # average overall miss latency
2964system.l2c.overall_avg_miss_latency::cpu0.itb.walker 105438.504326 # average overall miss latency
2965system.l2c.overall_avg_miss_latency::cpu0.inst 107925.176698 # average overall miss latency
2966system.l2c.overall_avg_miss_latency::cpu0.data 109237.248283 # average overall miss latency
2967system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143417.964126 # average overall miss latency
2968system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 99072.832370 # average overall miss latency
2969system.l2c.overall_avg_miss_latency::cpu1.itb.walker 98745.734499 # average overall miss latency
2970system.l2c.overall_avg_miss_latency::cpu1.inst 111017.932453 # average overall miss latency
2971system.l2c.overall_avg_miss_latency::cpu1.data 108500.777136 # average overall miss latency
2972system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136145.824737 # average overall miss latency
2973system.l2c.overall_avg_miss_latency::total 123610.175933 # average overall miss latency
2974system.l2c.blocked_cycles::no_mshrs 1362 # number of cycles access was blocked
2975system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2976system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked
2977system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2978system.l2c.avg_blocked_cycles::no_mshrs 104.769231 # average number of cycles each access was blocked
2979system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2980system.l2c.writebacks::writebacks 1205906 # number of writebacks
2981system.l2c.writebacks::total 1205906 # number of writebacks
2982system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits
2983system.l2c.ReadSharedReq_mshr_hits::cpu0.data 38 # number of ReadSharedReq MSHR hits
2984system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 160 # number of ReadSharedReq MSHR hits
2985system.l2c.ReadSharedReq_mshr_hits::cpu1.data 11 # number of ReadSharedReq MSHR hits
2986system.l2c.ReadSharedReq_mshr_hits::total 380 # number of ReadSharedReq MSHR hits
2987system.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits
2988system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
2989system.l2c.demand_mshr_hits::cpu1.inst 160 # number of demand (read+write) MSHR hits
2990system.l2c.demand_mshr_hits::cpu1.data 11 # number of demand (read+write) MSHR hits
2991system.l2c.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits
2992system.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits
2993system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
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2995system.l2c.overall_mshr_hits::cpu1.data 11 # number of overall MSHR hits
2996system.l2c.overall_mshr_hits::total 380 # number of overall MSHR hits
2997system.l2c.CleanEvict_mshr_misses::writebacks 74973 # number of CleanEvict MSHR misses
2998system.l2c.CleanEvict_mshr_misses::total 74973 # number of CleanEvict MSHR misses
2999system.l2c.UpgradeReq_mshr_misses::cpu0.data 20148 # number of UpgradeReq MSHR misses
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3002system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 632 # number of SCUpgradeReq MSHR misses
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3009system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1618 # number of ReadSharedReq MSHR misses
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3013system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2595 # number of ReadSharedReq MSHR misses
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3018system.l2c.ReadSharedReq_mshr_misses::total 938287 # number of ReadSharedReq MSHR misses
3019system.l2c.InvalidateReq_mshr_misses::cpu0.data 422083 # number of InvalidateReq MSHR misses
3020system.l2c.InvalidateReq_mshr_misses::cpu1.data 110180 # number of InvalidateReq MSHR misses
3021system.l2c.InvalidateReq_mshr_misses::total 532263 # number of InvalidateReq MSHR misses
3022system.l2c.demand_mshr_misses::cpu0.dtb.walker 2080 # number of demand (read+write) MSHR misses
3023system.l2c.demand_mshr_misses::cpu0.itb.walker 1618 # number of demand (read+write) MSHR misses
3024system.l2c.demand_mshr_misses::cpu0.inst 79343 # number of demand (read+write) MSHR misses
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3026system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 271925 # number of demand (read+write) MSHR misses
3027system.l2c.demand_mshr_misses::cpu1.dtb.walker 2595 # number of demand (read+write) MSHR misses
3028system.l2c.demand_mshr_misses::cpu1.itb.walker 2403 # number of demand (read+write) MSHR misses
3029system.l2c.demand_mshr_misses::cpu1.inst 55549 # number of demand (read+write) MSHR misses
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3031system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 236410 # number of demand (read+write) MSHR misses
3032system.l2c.demand_mshr_misses::total 1074118 # number of demand (read+write) MSHR misses
3033system.l2c.overall_mshr_misses::cpu0.dtb.walker 2080 # number of overall MSHR misses
3034system.l2c.overall_mshr_misses::cpu0.itb.walker 1618 # number of overall MSHR misses
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3039system.l2c.overall_mshr_misses::cpu1.itb.walker 2403 # number of overall MSHR misses
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3043system.l2c.overall_mshr_misses::total 1074118 # number of overall MSHR misses
3044system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4283 # number of ReadReq MSHR uncacheable
3045system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32770 # number of ReadReq MSHR uncacheable
3046system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 95 # number of ReadReq MSHR uncacheable
3047system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5328 # number of ReadReq MSHR uncacheable
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3049system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32733 # number of WriteReq MSHR uncacheable
3050system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5266 # number of WriteReq MSHR uncacheable
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3052system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4283 # number of overall MSHR uncacheable misses
3053system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65503 # number of overall MSHR uncacheable misses
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3055system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10594 # number of overall MSHR uncacheable misses
3056system.l2c.overall_mshr_uncacheable_misses::total 80475 # number of overall MSHR uncacheable misses
3057system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 406966500 # number of UpgradeReq MSHR miss cycles
3058system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 461692998 # number of UpgradeReq MSHR miss cycles
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3060system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15287999 # number of SCUpgradeReq MSHR miss cycles
3061system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22938500 # number of SCUpgradeReq MSHR miss cycles
3062system.l2c.SCUpgradeReq_mshr_miss_latency::total 38226499 # number of SCUpgradeReq MSHR miss cycles
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3064system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5139033541 # number of ReadExReq MSHR miss cycles
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3066system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of ReadSharedReq MSHR miss cycles
3067system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154419500 # number of ReadSharedReq MSHR miss cycles
3068system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7774295554 # number of ReadSharedReq MSHR miss cycles
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3070system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36279461370 # number of ReadSharedReq MSHR miss cycles
3071system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of ReadSharedReq MSHR miss cycles
3072system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213255501 # number of ReadSharedReq MSHR miss cycles
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3074system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13808714201 # number of ReadSharedReq MSHR miss cycles
3075system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29821990735 # number of ReadSharedReq MSHR miss cycles
3076system.l2c.ReadSharedReq_mshr_miss_latency::total 109017709147 # number of ReadSharedReq MSHR miss cycles
3077system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8734501501 # number of InvalidateReq MSHR miss cycles
3078system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2122534500 # number of InvalidateReq MSHR miss cycles
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3080system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of demand (read+write) MSHR miss cycles
3081system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154419500 # number of demand (read+write) MSHR miss cycles
3082system.l2c.demand_mshr_miss_latency::cpu0.inst 7774295554 # number of demand (read+write) MSHR miss cycles
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3085system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 231143002 # number of demand (read+write) MSHR miss cycles
3086system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213255501 # number of demand (read+write) MSHR miss cycles
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3090system.l2c.demand_mshr_miss_latency::total 122043861267 # number of demand (read+write) MSHR miss cycles
3091system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 198586501 # number of overall MSHR miss cycles
3092system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154419500 # number of overall MSHR miss cycles
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3103system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5434541500 # number of ReadReq MSHR uncacheable cycles
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3105system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 495854501 # number of ReadReq MSHR uncacheable cycles
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3108system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5434541500 # number of overall MSHR uncacheable cycles
3109system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6865000 # number of overall MSHR uncacheable cycles
3110system.l2c.overall_mshr_uncacheable_latency::cpu1.data 495854501 # number of overall MSHR uncacheable cycles
3111system.l2c.overall_mshr_uncacheable_latency::total 6240868001 # number of overall MSHR uncacheable cycles
3112system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3113system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3114system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.085764 # mshr miss rate for UpgradeReq accesses
3115system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.129643 # mshr miss rate for UpgradeReq accesses
3116system.l2c.UpgradeReq_mshr_miss_rate::total 0.104423 # mshr miss rate for UpgradeReq accesses
3117system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.010986 # mshr miss rate for SCUpgradeReq accesses
3118system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016697 # mshr miss rate for SCUpgradeReq accesses
3119system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013814 # mshr miss rate for SCUpgradeReq accesses
3120system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.550940 # mshr miss rate for ReadExReq accesses
3121system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508646 # mshr miss rate for ReadExReq accesses
3122system.l2c.ReadExReq_mshr_miss_rate::total 0.533484 # mshr miss rate for ReadExReq accesses
3123system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for ReadSharedReq accesses
3124system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for ReadSharedReq accesses
3125system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for ReadSharedReq accesses
3126system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.176918 # mshr miss rate for ReadSharedReq accesses
3127system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for ReadSharedReq accesses
3128system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for ReadSharedReq accesses
3129system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for ReadSharedReq accesses
3130system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for ReadSharedReq accesses
3131system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.198682 # mshr miss rate for ReadSharedReq accesses
3132system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for ReadSharedReq accesses
3133system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225948 # mshr miss rate for ReadSharedReq accesses
3134system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.755318 # mshr miss rate for InvalidateReq accesses
3135system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.473091 # mshr miss rate for InvalidateReq accesses
3136system.l2c.InvalidateReq_mshr_miss_rate::total 0.672296 # mshr miss rate for InvalidateReq accesses
3137system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for demand accesses
3138system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for demand accesses
3139system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for demand accesses
3140system.l2c.demand_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for demand accesses
3141system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for demand accesses
3142system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for demand accesses
3143system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for demand accesses
3144system.l2c.demand_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for demand accesses
3145system.l2c.demand_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for demand accesses
3146system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for demand accesses
3147system.l2c.demand_mshr_miss_rate::total 0.243715 # mshr miss rate for demand accesses
3148system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.127741 # mshr miss rate for overall accesses
3149system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.206272 # mshr miss rate for overall accesses
3150system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102402 # mshr miss rate for overall accesses
3151system.l2c.overall_mshr_miss_rate::cpu0.data 0.233814 # mshr miss rate for overall accesses
3152system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.453070 # mshr miss rate for overall accesses
3153system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.173741 # mshr miss rate for overall accesses
3154system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339072 # mshr miss rate for overall accesses
3155system.l2c.overall_mshr_miss_rate::cpu1.inst 0.082665 # mshr miss rate for overall accesses
3156system.l2c.overall_mshr_miss_rate::cpu1.data 0.239181 # mshr miss rate for overall accesses
3157system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448668 # mshr miss rate for overall accesses
3158system.l2c.overall_mshr_miss_rate::total 0.243715 # mshr miss rate for overall accesses
3159system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20198.853484 # average UpgradeReq mshr miss latency
3160system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20490.546689 # average UpgradeReq mshr miss latency
3161system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20352.846720 # average UpgradeReq mshr miss latency
3162system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24189.871835 # average SCUpgradeReq mshr miss latency
3163system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24350.849257 # average SCUpgradeReq mshr miss latency
3164system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24286.212834 # average SCUpgradeReq mshr miss latency
3165system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 95738.372205 # average ReadExReq mshr miss latency
3166system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 96148.357144 # average ReadExReq mshr miss latency
3167system.l2c.ReadExReq_avg_mshr_miss_latency::total 95899.699774 # average ReadExReq mshr miss latency
3168system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average ReadSharedReq mshr miss latency
3169system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average ReadSharedReq mshr miss latency
3170system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average ReadSharedReq mshr miss latency
3171system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101195.083485 # average ReadSharedReq mshr miss latency
3172system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average ReadSharedReq mshr miss latency
3173system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average ReadSharedReq mshr miss latency
3174system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average ReadSharedReq mshr miss latency
3175system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average ReadSharedReq mshr miss latency
3176system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 99405.485455 # average ReadSharedReq mshr miss latency
3177system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average ReadSharedReq mshr miss latency
3178system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 116188.020453 # average ReadSharedReq mshr miss latency
3179system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20693.800748 # average InvalidateReq mshr miss latency
3180system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19264.244872 # average InvalidateReq mshr miss latency
3181system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20397.878494 # average InvalidateReq mshr miss latency
3182system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
3183system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
3184system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
3185system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
3186system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
3187system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
3188system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
3189system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
3190system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
3191system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
3192system.l2c.demand_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
3193system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 95474.279327 # average overall mshr miss latency
3194system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 95438.504326 # average overall mshr miss latency
3195system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 97983.382958 # average overall mshr miss latency
3196system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99239.164237 # average overall mshr miss latency
3197system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133417.160504 # average overall mshr miss latency
3198system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 89072.447784 # average overall mshr miss latency
3199system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 88745.526841 # average overall mshr miss latency
3200system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101073.404166 # average overall mshr miss latency
3201system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98500.471725 # average overall mshr miss latency
3202system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126145.216932 # average overall mshr miss latency
3203system.l2c.overall_avg_mshr_miss_latency::total 113622.396484 # average overall mshr miss latency
3204system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average ReadReq mshr uncacheable latency
3205system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165838.922795 # average ReadReq mshr uncacheable latency
3206system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average ReadReq mshr uncacheable latency
3207system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93065.784722 # average ReadReq mshr uncacheable latency
3208system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 146926.923463 # average ReadReq mshr uncacheable latency
3209system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70886.528134 # average overall mshr uncacheable latency
3210system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82966.299253 # average overall mshr uncacheable latency
3211system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 72263.157895 # average overall mshr uncacheable latency
3212system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46805.220030 # average overall mshr uncacheable latency
3213system.l2c.overall_avg_mshr_uncacheable_latency::total 77550.394545 # average overall mshr uncacheable latency
3214system.membus.snoop_filter.tot_requests 3927234 # Total number of requests made to the snoop filter.
3215system.membus.snoop_filter.hit_single_requests 2267569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3216system.membus.snoop_filter.hit_multi_requests 3039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3217system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3218system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3219system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3220system.membus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3221system.membus.trans_dist::ReadReq 42476 # Transaction distribution
3222system.membus.trans_dist::ReadResp 989688 # Transaction distribution
3223system.membus.trans_dist::WriteReq 37999 # Transaction distribution
3224system.membus.trans_dist::WriteResp 37999 # Transaction distribution
3225system.membus.trans_dist::WritebackDirty 1312599 # Transaction distribution
3226system.membus.trans_dist::CleanEvict 291937 # Transaction distribution
3227system.membus.trans_dist::UpgradeReq 286456 # Transaction distribution
3228system.membus.trans_dist::SCUpgradeReq 289177 # Transaction distribution
3229system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
3230system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
3231system.membus.trans_dist::ReadExReq 150791 # Transaction distribution
3232system.membus.trans_dist::ReadExResp 135122 # Transaction distribution
3233system.membus.trans_dist::ReadSharedReq 947213 # Transaction distribution
3234system.membus.trans_dist::InvalidateReq 648655 # Transaction distribution
3235system.membus.trans_dist::InvalidateResp 27962 # Transaction distribution
3236system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122162 # Packet count per connected master and slave (bytes)
3237system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 54 # Packet count per connected master and slave (bytes)
3238system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24812 # Packet count per connected master and slave (bytes)
3239system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4782183 # Packet count per connected master and slave (bytes)
3240system.membus.pkt_count_system.l2c.mem_side::total 4929211 # Packet count per connected master and slave (bytes)
3241system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238327 # Packet count per connected master and slave (bytes)
3242system.membus.pkt_count_system.iocache.mem_side::total 238327 # Packet count per connected master and slave (bytes)
3243system.membus.pkt_count::total 5167538 # Packet count per connected master and slave (bytes)
3244system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155269 # Cumulative packet size per connected master and slave (bytes)
3245system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1388 # Cumulative packet size per connected master and slave (bytes)
3246system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49624 # Cumulative packet size per connected master and slave (bytes)
3247system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146129536 # Cumulative packet size per connected master and slave (bytes)
3248system.membus.pkt_size_system.l2c.mem_side::total 146335817 # Cumulative packet size per connected master and slave (bytes)
3249system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281024 # Cumulative packet size per connected master and slave (bytes)
3250system.membus.pkt_size_system.iocache.mem_side::total 7281024 # Cumulative packet size per connected master and slave (bytes)
3251system.membus.pkt_size::total 153616841 # Cumulative packet size per connected master and slave (bytes)
3252system.membus.snoops 586564 # Total snoops (count)
3253system.membus.snoopTraffic 164864 # Total snoop traffic (bytes)
3254system.membus.snoop_fanout::samples 2402773 # Request fanout histogram
3255system.membus.snoop_fanout::mean 0.012913 # Request fanout histogram
3256system.membus.snoop_fanout::stdev 0.112899 # Request fanout histogram
3257system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3258system.membus.snoop_fanout::0 2371746 98.71% 98.71% # Request fanout histogram
3259system.membus.snoop_fanout::1 31027 1.29% 100.00% # Request fanout histogram
3260system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3261system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3262system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3263system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3264system.membus.snoop_fanout::total 2402773 # Request fanout histogram
3265system.membus.reqLayer0.occupancy 103148497 # Layer occupancy (ticks)
3266system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3267system.membus.reqLayer1.occupancy 34812 # Layer occupancy (ticks)
3268system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3269system.membus.reqLayer2.occupancy 20826497 # Layer occupancy (ticks)
3270system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3271system.membus.reqLayer5.occupancy 8952131044 # Layer occupancy (ticks)
3272system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3273system.membus.respLayer2.occupancy 5789704061 # Layer occupancy (ticks)
3274system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3275system.membus.respLayer3.occupancy 78011284 # Layer occupancy (ticks)
3276system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3277system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3278system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3279system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3280system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3281system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3282system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3283system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3284system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3285system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3286system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3287system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3288system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3289system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3290system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3291system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3292system.realview.ethernet.txBytes 966 # Bytes Transmitted
3293system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3294system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3295system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3296system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3297system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3298system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3299system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3326system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3327system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3328system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3329system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3330system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3331system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3332system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3333system.realview.ethernet.droppedPackets 0 # number of packets dropped
3334system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3335system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3336system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3337system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3338system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3339system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3340system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3341system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3342system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3343system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3344system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3345system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3346system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3347system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3348system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3349system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3350system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3351system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3352system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3353system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3354system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3355system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3356system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3357system.toL2Bus.snoop_filter.tot_requests 12820673 # Total number of requests made to the snoop filter.
3358system.toL2Bus.snoop_filter.hit_single_requests 6781255 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3359system.toL2Bus.snoop_filter.hit_multi_requests 2351025 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3360system.toL2Bus.snoop_filter.tot_snoops 247233 # Total number of snoops made to the snoop filter.
3361system.toL2Bus.snoop_filter.hit_single_snoops 222755 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3362system.toL2Bus.snoop_filter.hit_multi_snoops 24478 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3363system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47310816168000 # Cumulative time (in ticks) in various power states
3364system.toL2Bus.trans_dist::ReadReq 42478 # Transaction distribution
3365system.toL2Bus.trans_dist::ReadResp 4925290 # Transaction distribution
3366system.toL2Bus.trans_dist::WriteReq 37999 # Transaction distribution
3367system.toL2Bus.trans_dist::WriteResp 37999 # Transaction distribution
3368system.toL2Bus.trans_dist::WritebackDirty 4166379 # Transaction distribution
3369system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
3370system.toL2Bus.trans_dist::CleanEvict 3160031 # Transaction distribution
3371system.toL2Bus.trans_dist::UpgradeReq 651791 # Transaction distribution
3372system.toL2Bus.trans_dist::SCUpgradeReq 401547 # Transaction distribution
3373system.toL2Bus.trans_dist::UpgradeResp 1053338 # Transaction distribution
3374system.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution
3375system.toL2Bus.trans_dist::UpgradeFailResp 94 # Transaction distribution
3376system.toL2Bus.trans_dist::ReadExReq 305355 # Transaction distribution
3377system.toL2Bus.trans_dist::ReadExResp 305355 # Transaction distribution
3378system.toL2Bus.trans_dist::ReadSharedReq 4883226 # Transaction distribution
3379system.toL2Bus.trans_dist::InvalidateReq 892239 # Transaction distribution
3380system.toL2Bus.trans_dist::InvalidateResp 875311 # Transaction distribution
3381system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10573421 # Packet count per connected master and slave (bytes)
3382system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8142599 # Packet count per connected master and slave (bytes)
3383system.toL2Bus.pkt_count::total 18716020 # Packet count per connected master and slave (bytes)
3384system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267921245 # Cumulative packet size per connected master and slave (bytes)
3385system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 204226604 # Cumulative packet size per connected master and slave (bytes)
3386system.toL2Bus.pkt_size::total 472147849 # Cumulative packet size per connected master and slave (bytes)
3387system.toL2Bus.snoops 3035429 # Total snoops (count)
3388system.toL2Bus.snoopTraffic 127161424 # Total snoop traffic (bytes)
3389system.toL2Bus.snoop_fanout::samples 8824674 # Request fanout histogram
3390system.toL2Bus.snoop_fanout::mean 0.367843 # Request fanout histogram
3391system.toL2Bus.snoop_fanout::stdev 0.487937 # Request fanout histogram
3392system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3393system.toL2Bus.snoop_fanout::0 5603059 63.49% 63.49% # Request fanout histogram
3394system.toL2Bus.snoop_fanout::1 3197137 36.23% 99.72% # Request fanout histogram
3395system.toL2Bus.snoop_fanout::2 24478 0.28% 100.00% # Request fanout histogram
3396system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3397system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3398system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3399system.toL2Bus.snoop_fanout::total 8824674 # Request fanout histogram
3400system.toL2Bus.reqLayer0.occupancy 9845744502 # Layer occupancy (ticks)
3401system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3402system.toL2Bus.snoopLayer0.occupancy 8465131 # Layer occupancy (ticks)
3403system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3404system.toL2Bus.respLayer0.occupancy 4808552711 # Layer occupancy (ticks)
3405system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3406system.toL2Bus.respLayer1.occupancy 4013025600 # Layer occupancy (ticks)
3407system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3408
3409---------- End Simulation Statistics ----------