1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.496138 # Number of seconds simulated
4sim_ticks 47496138032000 # Number of ticks simulated
5final_tick 47496138032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 287392 # Simulator instruction rate (inst/s)
8host_op_rate 338020 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 15163142641 # Simulator tick rate (ticks/s)
10host_mem_usage 759192 # Number of bytes of host memory used
11host_seconds 3132.34 # Real time elapsed on the host
12sim_insts 900209792 # Number of instructions simulated
13sim_ops 1058792792 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 123968 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 99904 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 7981184 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 13323912 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 15275072 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 135168 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 122048 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3081152 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 10821968 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 12736320 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 446656 # Number of bytes read from this memory
27system.physmem.bytes_read::total 64147352 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 7981184 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3081152 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 11062336 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 76613760 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 76634344 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1937 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1561 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 124706 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 208199 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 238673 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2112 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1907 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 48143 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 169106 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 199005 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6979 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1002328 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1197090 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1199664 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2610 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2103 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 168039 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 280526 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 321607 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 2846 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 2570 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 64872 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 227849 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 268155 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9404 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1350580 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 168039 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 64872 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 232910 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1613052 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1613486 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1613052 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2610 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2103 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 168039 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 280960 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 321607 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 2846 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 2570 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 64872 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 227850 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 268155 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9404 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 2964066 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1002328 # Number of read requests accepted
84system.physmem.writeReqs 1199664 # Number of write requests accepted
85system.physmem.readBursts 1002328 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1199664 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 64118976 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 30016 # Total number of bytes read from write queue
89system.physmem.bytesWritten 76632896 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 64147352 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 76634344 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 469 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 52312 # Per bank write bursts
96system.physmem.perBankRdBursts::1 66235 # Per bank write bursts
97system.physmem.perBankRdBursts::2 59334 # Per bank write bursts
98system.physmem.perBankRdBursts::3 65978 # Per bank write bursts
99system.physmem.perBankRdBursts::4 61446 # Per bank write bursts
100system.physmem.perBankRdBursts::5 69476 # Per bank write bursts
101system.physmem.perBankRdBursts::6 59128 # Per bank write bursts
102system.physmem.perBankRdBursts::7 60480 # Per bank write bursts
103system.physmem.perBankRdBursts::8 57677 # Per bank write bursts
104system.physmem.perBankRdBursts::9 110303 # Per bank write bursts
105system.physmem.perBankRdBursts::10 51521 # Per bank write bursts
106system.physmem.perBankRdBursts::11 60498 # Per bank write bursts
107system.physmem.perBankRdBursts::12 54125 # Per bank write bursts
108system.physmem.perBankRdBursts::13 57278 # Per bank write bursts
109system.physmem.perBankRdBursts::14 58648 # Per bank write bursts
110system.physmem.perBankRdBursts::15 57420 # Per bank write bursts
111system.physmem.perBankWrBursts::0 71344 # Per bank write bursts
112system.physmem.perBankWrBursts::1 78863 # Per bank write bursts
113system.physmem.perBankWrBursts::2 73221 # Per bank write bursts
114system.physmem.perBankWrBursts::3 79189 # Per bank write bursts
115system.physmem.perBankWrBursts::4 75543 # Per bank write bursts
116system.physmem.perBankWrBursts::5 82829 # Per bank write bursts
117system.physmem.perBankWrBursts::6 74512 # Per bank write bursts
118system.physmem.perBankWrBursts::7 77237 # Per bank write bursts
119system.physmem.perBankWrBursts::8 71961 # Per bank write bursts
120system.physmem.perBankWrBursts::9 73593 # Per bank write bursts
121system.physmem.perBankWrBursts::10 69363 # Per bank write bursts
122system.physmem.perBankWrBursts::11 76682 # Per bank write bursts
123system.physmem.perBankWrBursts::12 71227 # Per bank write bursts
124system.physmem.perBankWrBursts::13 74509 # Per bank write bursts
125system.physmem.perBankWrBursts::14 73049 # Per bank write bursts
126system.physmem.perBankWrBursts::15 74267 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 57 # Number of times write queue was full causing retry
129system.physmem.totGap 47496135919500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1002298 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1197090 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 675393 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 118123 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 43619 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 33801 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 29137 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 27086 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 24475 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 22026 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 18598 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 3546 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 1664 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 1196 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 985 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 727 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 426 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 352 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 286 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 223 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 119 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::19 69 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see

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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 31163 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 38080 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 51935 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 55190 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 60170 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 62406 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 65836 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 70016 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 72724 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 73495 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 74816 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 77871 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 75261 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 76182 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 84001 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 74766 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 69103 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 66691 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 3873 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 2118 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 1475 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 1059 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 826 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 727 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 636 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 578 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 535 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 498 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 445 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 421 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 456 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 364 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 377 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 296 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 346 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 303 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 301 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 234 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 209 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 168 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 220 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 155 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 143 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 87 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 167 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 993836 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 141.624332 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 96.550200 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 190.035765 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 676204 68.04% 68.04% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 192250 19.34% 87.38% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 44807 4.51% 91.89% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 21137 2.13% 94.02% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 15251 1.53% 95.55% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 9933 1.00% 96.55% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 5714 0.57% 97.13% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 4523 0.46% 97.58% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 24017 2.42% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 993836 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 62276 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 16.086984 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 158.174793 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 62273 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 62276 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 62276 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 19.227134 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 18.463029 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 8.016188 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 49891 80.11% 80.11% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 5512 8.85% 88.96% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 3034 4.87% 93.84% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 1650 2.65% 96.49% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 463 0.74% 97.23% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 302 0.48% 97.71% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 265 0.43% 98.14% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 82 0.13% 98.27% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 283 0.45% 98.73% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 77 0.12% 98.85% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 32 0.05% 98.90% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 49 0.08% 98.98% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 248 0.40% 99.38% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 39 0.06% 99.44% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 31 0.05% 99.49% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 106 0.17% 99.66% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 143 0.23% 99.89% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 4 0.01% 99.90% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.90% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::100-103 3 0.00% 99.91% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::104-107 4 0.01% 99.91% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::112-115 5 0.01% 99.92% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::116-119 2 0.00% 99.93% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::128-131 12 0.02% 99.95% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::132-135 5 0.01% 99.96% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::140-143 5 0.01% 99.96% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::total 62276 # Writes before turning the bus around for reads
304system.physmem.totQLat 32552700191 # Total ticks spent queuing
305system.physmem.totMemAccLat 51337556441 # Total ticks spent from burst creation until serviced by the DRAM
306system.physmem.totBusLat 5009295000 # Total ticks spent in databus transfers
307system.physmem.avgQLat 32492.30 # Average queueing delay per DRAM burst
308system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
309system.physmem.avgMemAccLat 51242.30 # Average memory access latency per DRAM burst
310system.physmem.avgRdBW 1.35 # Average DRAM read bandwidth in MiByte/s
311system.physmem.avgWrBW 1.61 # Average achieved write bandwidth in MiByte/s
312system.physmem.avgRdBWSys 1.35 # Average system read bandwidth in MiByte/s
313system.physmem.avgWrBWSys 1.61 # Average system write bandwidth in MiByte/s
314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
315system.physmem.busUtil 0.02 # Data bus utilization in percentage
316system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
317system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
318system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
319system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing
320system.physmem.readRowHits 748874 # Number of row buffer hits during reads
321system.physmem.writeRowHits 456536 # Number of row buffer hits during writes
322system.physmem.readRowHitRate 74.75 # Row buffer hit rate for reads
323system.physmem.writeRowHitRate 38.13 # Row buffer hit rate for writes
324system.physmem.avgGap 21569622.38 # Average gap between requests
325system.physmem.pageHitRate 54.81 # Row buffer hit rate, read and write combined
326system.physmem_0.actEnergy 3877765920 # Energy for activate commands per rank (pJ)
327system.physmem_0.preEnergy 2115844500 # Energy for precharge commands per rank (pJ)
328system.physmem_0.readEnergy 3856171800 # Energy for read commands per rank (pJ)
329system.physmem_0.writeEnergy 3970542240 # Energy for write commands per rank (pJ)
330system.physmem_0.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
331system.physmem_0.actBackEnergy 1199773763640 # Energy for active background per rank (pJ)
332system.physmem_0.preBackEnergy 27445246701750 # Energy for precharge background per rank (pJ)
333system.physmem_0.totalEnergy 31761057298410 # Total energy per rank (pJ)
334system.physmem_0.averagePower 668.708277 # Core power per rank (mW)
335system.physmem_0.memoryStateTime::IDLE 45657180846254 # Time in different power states
336system.physmem_0.memoryStateTime::REF 1586000260000 # Time in different power states
337system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
338system.physmem_0.memoryStateTime::ACT 252951953746 # Time in different power states
339system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
340system.physmem_1.actEnergy 3635634240 # Energy for activate commands per rank (pJ)
341system.physmem_1.preEnergy 1983729000 # Energy for precharge commands per rank (pJ)
342system.physmem_1.readEnergy 3958266000 # Energy for read commands per rank (pJ)
343system.physmem_1.writeEnergy 3788538480 # Energy for write commands per rank (pJ)
344system.physmem_1.refreshEnergy 3102216508560 # Energy for refresh commands per rank (pJ)
345system.physmem_1.actBackEnergy 1194664304160 # Energy for active background per rank (pJ)
346system.physmem_1.preBackEnergy 27449728675500 # Energy for precharge background per rank (pJ)
347system.physmem_1.totalEnergy 31759975655940 # Total energy per rank (pJ)
348system.physmem_1.averagePower 668.685504 # Core power per rank (mW)
349system.physmem_1.memoryStateTime::IDLE 45664625089280 # Time in different power states
350system.physmem_1.memoryStateTime::REF 1586000260000 # Time in different power states
351system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
352system.physmem_1.memoryStateTime::ACT 245507696970 # Time in different power states
353system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
354system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
355system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
359system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

378system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
379system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
380system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
381system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
382system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
383system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
384system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
385system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
386system.cpu0.branchPred.lookups 138061860 # Number of BP lookups
387system.cpu0.branchPred.condPredicted 98120507 # Number of conditional branches predicted
388system.cpu0.branchPred.condIncorrect 6229967 # Number of conditional branches incorrect
389system.cpu0.branchPred.BTBLookups 103103324 # Number of BTB lookups
390system.cpu0.branchPred.BTBHits 75422199 # Number of BTB hits
391system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
392system.cpu0.branchPred.BTBHitPct 73.152054 # BTB Hit Percentage
393system.cpu0.branchPred.usedRAS 16055942 # Number of times the RAS was used to get a target.
394system.cpu0.branchPred.RASInCorrect 1103312 # Number of incorrect RAS predictions.
395system.cpu_clk_domain.clock 500 # Clock period in ticks
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

417system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
418system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
419system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
420system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
421system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
422system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
423system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
424system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
425system.cpu0.dtb.walker.walks 287097 # Table walker walks requested
426system.cpu0.dtb.walker.walksLong 287097 # Table walker walks initiated with long descriptors
427system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9253 # Level at which table walker walks with long descriptors terminate
428system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79328 # Level at which table walker walks with long descriptors terminate
429system.cpu0.dtb.walker.walkWaitTime::samples 287097 # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::0 287097 100.00% 100.00% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::total 287097 # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkCompletionTime::samples 88581 # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::mean 23354.082704 # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::gmean 21377.049680 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::stdev 19303.806083 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::0-65535 87487 98.76% 98.76% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::65536-131071 212 0.24% 99.00% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::131072-196607 756 0.85% 99.86% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.89% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::262144-327679 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::total 88581 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walkPageSizes::4K 79328 89.55% 89.55% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::2M 9253 10.45% 100.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::total 88581 # Table walker page sizes translated
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 287097 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 287097 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 88581 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 88581 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin::total 375678 # Table walker requests started/completed, data/inst
460system.cpu0.dtb.inst_hits 0 # ITB inst hits
461system.cpu0.dtb.inst_misses 0 # ITB inst misses
462system.cpu0.dtb.read_hits 87655759 # DTB read hits
463system.cpu0.dtb.read_misses 237615 # DTB read misses
464system.cpu0.dtb.write_hits 78096829 # DTB write hits
465system.cpu0.dtb.write_misses 49482 # DTB write misses
466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
468system.cpu0.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
469system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
470system.cpu0.dtb.flush_entries 36184 # Number of entries that have been flushed from TLB
471system.cpu0.dtb.align_faults 2196 # Number of TLB faults due to alignment restrictions
472system.cpu0.dtb.prefetch_faults 9698 # Number of TLB faults due to prefetch
473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
474system.cpu0.dtb.perms_faults 11726 # Number of TLB faults due to permissions restrictions
475system.cpu0.dtb.read_accesses 87893374 # DTB read accesses
476system.cpu0.dtb.write_accesses 78146311 # DTB write accesses
477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
478system.cpu0.dtb.hits 165752588 # DTB hits
479system.cpu0.dtb.misses 287097 # DTB misses
480system.cpu0.dtb.accesses 166039685 # DTB accesses
481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
510system.cpu0.itb.walker.walks 66101 # Table walker walks requested
511system.cpu0.itb.walker.walksLong 66101 # Table walker walks initiated with long descriptors
512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 650 # Level at which table walker walks with long descriptors terminate
513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56681 # Level at which table walker walks with long descriptors terminate
514system.cpu0.itb.walker.walkWaitTime::samples 66101 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::0 66101 100.00% 100.00% # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::total 66101 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkCompletionTime::samples 57331 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::mean 26460.544906 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::gmean 23886.492389 # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::stdev 21943.926110 # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::0-65535 56305 98.21% 98.21% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::65536-131071 11 0.02% 98.23% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::131072-196607 903 1.58% 99.80% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.88% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::total 57331 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution
532system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution
533system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution
534system.cpu0.itb.walker.walkPageSizes::4K 56681 98.87% 98.87% # Table walker page sizes translated
535system.cpu0.itb.walker.walkPageSizes::2M 650 1.13% 100.00% # Table walker page sizes translated
536system.cpu0.itb.walker.walkPageSizes::total 57331 # Table walker page sizes translated
537system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
538system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66101 # Table walker requests started/completed, data/inst
539system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66101 # Table walker requests started/completed, data/inst
540system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
541system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57331 # Table walker requests started/completed, data/inst
542system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57331 # Table walker requests started/completed, data/inst
543system.cpu0.itb.walker.walkRequestOrigin::total 123432 # Table walker requests started/completed, data/inst
544system.cpu0.itb.inst_hits 246672238 # ITB inst hits
545system.cpu0.itb.inst_misses 66101 # ITB inst misses
546system.cpu0.itb.read_hits 0 # DTB read hits
547system.cpu0.itb.read_misses 0 # DTB read misses
548system.cpu0.itb.write_hits 0 # DTB write hits
549system.cpu0.itb.write_misses 0 # DTB write misses
550system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
551system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
552system.cpu0.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
553system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
554system.cpu0.itb.flush_entries 25870 # Number of entries that have been flushed from TLB
555system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
556system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
557system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
558system.cpu0.itb.perms_faults 211969 # Number of TLB faults due to permissions restrictions
559system.cpu0.itb.read_accesses 0 # DTB read accesses
560system.cpu0.itb.write_accesses 0 # DTB write accesses
561system.cpu0.itb.inst_accesses 246738339 # ITB inst accesses
562system.cpu0.itb.hits 246672238 # DTB hits
563system.cpu0.itb.misses 66101 # DTB misses
564system.cpu0.itb.accesses 246738339 # DTB accesses
565system.cpu0.numCycles 1042581150 # number of cpu cycles simulated
566system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
567system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
568system.cpu0.committedInsts 455270721 # Number of instructions committed
569system.cpu0.committedOps 534899361 # Number of ops (including micro ops) committed
570system.cpu0.discardedOps 47095692 # Number of ops (including micro ops) which were discarded before commit
571system.cpu0.numFetchSuspends 4288 # Number of times Execute suspended instruction fetching
572system.cpu0.quiesceCycles 93950410811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
573system.cpu0.cpi 2.290025 # CPI: cycles per instruction
574system.cpu0.ipc 0.436677 # IPC: instructions per cycle
575system.cpu0.kern.inst.arm 0 # number of arm instructions executed
576system.cpu0.kern.inst.quiesce 13221 # number of quiesce instructions executed
577system.cpu0.tickCycles 736979138 # Number of cycles that the object actually ticked
578system.cpu0.idleCycles 305602012 # Total number of cycles that the object has spent stopped
579system.cpu0.dcache.tags.replacements 5679788 # number of replacements
580system.cpu0.dcache.tags.tagsinuse 503.382728 # Cycle average of tags in use
581system.cpu0.dcache.tags.total_refs 157129733 # Total number of references to valid blocks.
582system.cpu0.dcache.tags.sampled_refs 5680300 # Sample count of references to valid blocks.
583system.cpu0.dcache.tags.avg_refs 27.662224 # Average number of references to valid blocks.
584system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit.
585system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.382728 # Average occupied blocks per requestor
586system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983169 # Average percentage of cache occupancy
587system.cpu0.dcache.tags.occ_percent::total 0.983169 # Average percentage of cache occupancy
588system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
589system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
590system.cpu0.dcache.tags.age_task_id_blocks_1024::1 439 # Occupied blocks per task id
591system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
592system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
593system.cpu0.dcache.tags.tag_accesses 334387337 # Number of tag accesses
594system.cpu0.dcache.tags.data_accesses 334387337 # Number of data accesses
595system.cpu0.dcache.ReadReq_hits::cpu0.data 80268736 # number of ReadReq hits
596system.cpu0.dcache.ReadReq_hits::total 80268736 # number of ReadReq hits
597system.cpu0.dcache.WriteReq_hits::cpu0.data 72233903 # number of WriteReq hits
598system.cpu0.dcache.WriteReq_hits::total 72233903 # number of WriteReq hits
599system.cpu0.dcache.SoftPFReq_hits::cpu0.data 277349 # number of SoftPFReq hits
600system.cpu0.dcache.SoftPFReq_hits::total 277349 # number of SoftPFReq hits
601system.cpu0.dcache.WriteLineReq_hits::cpu0.data 251788 # number of WriteLineReq hits
602system.cpu0.dcache.WriteLineReq_hits::total 251788 # number of WriteLineReq hits
603system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1785654 # number of LoadLockedReq hits
604system.cpu0.dcache.LoadLockedReq_hits::total 1785654 # number of LoadLockedReq hits
605system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1744754 # number of StoreCondReq hits
606system.cpu0.dcache.StoreCondReq_hits::total 1744754 # number of StoreCondReq hits
607system.cpu0.dcache.demand_hits::cpu0.data 152502639 # number of demand (read+write) hits
608system.cpu0.dcache.demand_hits::total 152502639 # number of demand (read+write) hits
609system.cpu0.dcache.overall_hits::cpu0.data 152779988 # number of overall hits
610system.cpu0.dcache.overall_hits::total 152779988 # number of overall hits
611system.cpu0.dcache.ReadReq_misses::cpu0.data 3412741 # number of ReadReq misses
612system.cpu0.dcache.ReadReq_misses::total 3412741 # number of ReadReq misses
613system.cpu0.dcache.WriteReq_misses::cpu0.data 2489296 # number of WriteReq misses
614system.cpu0.dcache.WriteReq_misses::total 2489296 # number of WriteReq misses
615system.cpu0.dcache.SoftPFReq_misses::cpu0.data 686937 # number of SoftPFReq misses
616system.cpu0.dcache.SoftPFReq_misses::total 686937 # number of SoftPFReq misses
617system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801634 # number of WriteLineReq misses
618system.cpu0.dcache.WriteLineReq_misses::total 801634 # number of WriteLineReq misses
619system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 154902 # number of LoadLockedReq misses
620system.cpu0.dcache.LoadLockedReq_misses::total 154902 # number of LoadLockedReq misses
621system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194385 # number of StoreCondReq misses
622system.cpu0.dcache.StoreCondReq_misses::total 194385 # number of StoreCondReq misses
623system.cpu0.dcache.demand_misses::cpu0.data 5902037 # number of demand (read+write) misses
624system.cpu0.dcache.demand_misses::total 5902037 # number of demand (read+write) misses
625system.cpu0.dcache.overall_misses::cpu0.data 6588974 # number of overall misses
626system.cpu0.dcache.overall_misses::total 6588974 # number of overall misses
627system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 58848858500 # number of ReadReq miss cycles
628system.cpu0.dcache.ReadReq_miss_latency::total 58848858500 # number of ReadReq miss cycles
629system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 63605542500 # number of WriteReq miss cycles
630system.cpu0.dcache.WriteReq_miss_latency::total 63605542500 # number of WriteReq miss cycles
631system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 48599001500 # number of WriteLineReq miss cycles
632system.cpu0.dcache.WriteLineReq_miss_latency::total 48599001500 # number of WriteLineReq miss cycles
633system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2502004000 # number of LoadLockedReq miss cycles
634system.cpu0.dcache.LoadLockedReq_miss_latency::total 2502004000 # number of LoadLockedReq miss cycles
635system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5451875000 # number of StoreCondReq miss cycles
636system.cpu0.dcache.StoreCondReq_miss_latency::total 5451875000 # number of StoreCondReq miss cycles
637system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 6380500 # number of StoreCondFailReq miss cycles
638system.cpu0.dcache.StoreCondFailReq_miss_latency::total 6380500 # number of StoreCondFailReq miss cycles
639system.cpu0.dcache.demand_miss_latency::cpu0.data 122454401000 # number of demand (read+write) miss cycles
640system.cpu0.dcache.demand_miss_latency::total 122454401000 # number of demand (read+write) miss cycles
641system.cpu0.dcache.overall_miss_latency::cpu0.data 122454401000 # number of overall miss cycles
642system.cpu0.dcache.overall_miss_latency::total 122454401000 # number of overall miss cycles
643system.cpu0.dcache.ReadReq_accesses::cpu0.data 83681477 # number of ReadReq accesses(hits+misses)
644system.cpu0.dcache.ReadReq_accesses::total 83681477 # number of ReadReq accesses(hits+misses)
645system.cpu0.dcache.WriteReq_accesses::cpu0.data 74723199 # number of WriteReq accesses(hits+misses)
646system.cpu0.dcache.WriteReq_accesses::total 74723199 # number of WriteReq accesses(hits+misses)
647system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 964286 # number of SoftPFReq accesses(hits+misses)
648system.cpu0.dcache.SoftPFReq_accesses::total 964286 # number of SoftPFReq accesses(hits+misses)
649system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1053422 # number of WriteLineReq accesses(hits+misses)
650system.cpu0.dcache.WriteLineReq_accesses::total 1053422 # number of WriteLineReq accesses(hits+misses)
651system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1940556 # number of LoadLockedReq accesses(hits+misses)
652system.cpu0.dcache.LoadLockedReq_accesses::total 1940556 # number of LoadLockedReq accesses(hits+misses)
653system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1939139 # number of StoreCondReq accesses(hits+misses)
654system.cpu0.dcache.StoreCondReq_accesses::total 1939139 # number of StoreCondReq accesses(hits+misses)
655system.cpu0.dcache.demand_accesses::cpu0.data 158404676 # number of demand (read+write) accesses
656system.cpu0.dcache.demand_accesses::total 158404676 # number of demand (read+write) accesses
657system.cpu0.dcache.overall_accesses::cpu0.data 159368962 # number of overall (read+write) accesses
658system.cpu0.dcache.overall_accesses::total 159368962 # number of overall (read+write) accesses
659system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040783 # miss rate for ReadReq accesses
660system.cpu0.dcache.ReadReq_miss_rate::total 0.040783 # miss rate for ReadReq accesses
661system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033314 # miss rate for WriteReq accesses
662system.cpu0.dcache.WriteReq_miss_rate::total 0.033314 # miss rate for WriteReq accesses
663system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.712379 # miss rate for SoftPFReq accesses
664system.cpu0.dcache.SoftPFReq_miss_rate::total 0.712379 # miss rate for SoftPFReq accesses
665system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760981 # miss rate for WriteLineReq accesses
666system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760981 # miss rate for WriteLineReq accesses
667system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079824 # miss rate for LoadLockedReq accesses
668system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079824 # miss rate for LoadLockedReq accesses
669system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100243 # miss rate for StoreCondReq accesses
670system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100243 # miss rate for StoreCondReq accesses
671system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037259 # miss rate for demand accesses
672system.cpu0.dcache.demand_miss_rate::total 0.037259 # miss rate for demand accesses
673system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041344 # miss rate for overall accesses
674system.cpu0.dcache.overall_miss_rate::total 0.041344 # miss rate for overall accesses
675system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17243.868931 # average ReadReq miss latency
676system.cpu0.dcache.ReadReq_avg_miss_latency::total 17243.868931 # average ReadReq miss latency
677system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25551.618811 # average WriteReq miss latency
678system.cpu0.dcache.WriteReq_avg_miss_latency::total 25551.618811 # average WriteReq miss latency
679system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60624.925465 # average WriteLineReq miss latency
680system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60624.925465 # average WriteLineReq miss latency
681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16152.173632 # average LoadLockedReq miss latency
682system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16152.173632 # average LoadLockedReq miss latency
683system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28046.788590 # average StoreCondReq miss latency
684system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28046.788590 # average StoreCondReq miss latency
685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
686system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
687system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20747.819948 # average overall miss latency
688system.cpu0.dcache.demand_avg_miss_latency::total 20747.819948 # average overall miss latency
689system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18584.744909 # average overall miss latency
690system.cpu0.dcache.overall_avg_miss_latency::total 18584.744909 # average overall miss latency
691system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
696system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
697system.cpu0.dcache.fast_writes 0 # number of fast writes performed
698system.cpu0.dcache.cache_copies 0 # number of cache copies performed
699system.cpu0.dcache.writebacks::writebacks 5679821 # number of writebacks
700system.cpu0.dcache.writebacks::total 5679821 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 423726 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 423726 # number of ReadReq MSHR hits
703system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1038452 # number of WriteReq MSHR hits
704system.cpu0.dcache.WriteReq_mshr_hits::total 1038452 # number of WriteReq MSHR hits
705system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 85 # number of WriteLineReq MSHR hits
706system.cpu0.dcache.WriteLineReq_mshr_hits::total 85 # number of WriteLineReq MSHR hits
707system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41327 # number of LoadLockedReq MSHR hits
708system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41327 # number of LoadLockedReq MSHR hits
709system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 43 # number of StoreCondReq MSHR hits
710system.cpu0.dcache.StoreCondReq_mshr_hits::total 43 # number of StoreCondReq MSHR hits
711system.cpu0.dcache.demand_mshr_hits::cpu0.data 1462178 # number of demand (read+write) MSHR hits
712system.cpu0.dcache.demand_mshr_hits::total 1462178 # number of demand (read+write) MSHR hits
713system.cpu0.dcache.overall_mshr_hits::cpu0.data 1462178 # number of overall MSHR hits
714system.cpu0.dcache.overall_mshr_hits::total 1462178 # number of overall MSHR hits
715system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2989015 # number of ReadReq MSHR misses
716system.cpu0.dcache.ReadReq_mshr_misses::total 2989015 # number of ReadReq MSHR misses
717system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1450844 # number of WriteReq MSHR misses
718system.cpu0.dcache.WriteReq_mshr_misses::total 1450844 # number of WriteReq MSHR misses
719system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 685285 # number of SoftPFReq MSHR misses
720system.cpu0.dcache.SoftPFReq_mshr_misses::total 685285 # number of SoftPFReq MSHR misses
721system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801549 # number of WriteLineReq MSHR misses
722system.cpu0.dcache.WriteLineReq_mshr_misses::total 801549 # number of WriteLineReq MSHR misses
723system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113575 # number of LoadLockedReq MSHR misses
724system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113575 # number of LoadLockedReq MSHR misses
725system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194342 # number of StoreCondReq MSHR misses
726system.cpu0.dcache.StoreCondReq_mshr_misses::total 194342 # number of StoreCondReq MSHR misses
727system.cpu0.dcache.demand_mshr_misses::cpu0.data 4439859 # number of demand (read+write) MSHR misses
728system.cpu0.dcache.demand_mshr_misses::total 4439859 # number of demand (read+write) MSHR misses
729system.cpu0.dcache.overall_mshr_misses::cpu0.data 5125144 # number of overall MSHR misses
730system.cpu0.dcache.overall_mshr_misses::total 5125144 # number of overall MSHR misses
731system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
732system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32143 # number of ReadReq MSHR uncacheable
733system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
734system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable
735system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
736system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63696 # number of overall MSHR uncacheable misses
737system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 46000579500 # number of ReadReq MSHR miss cycles
738system.cpu0.dcache.ReadReq_mshr_miss_latency::total 46000579500 # number of ReadReq MSHR miss cycles
739system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36719986000 # number of WriteReq MSHR miss cycles
740system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36719986000 # number of WriteReq MSHR miss cycles
741system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17989395000 # number of SoftPFReq MSHR miss cycles
742system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17989395000 # number of SoftPFReq MSHR miss cycles
743system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 47789065000 # number of WriteLineReq MSHR miss cycles
744system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 47789065000 # number of WriteLineReq MSHR miss cycles
745system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1631247500 # number of LoadLockedReq MSHR miss cycles
746system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1631247500 # number of LoadLockedReq MSHR miss cycles
747system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5254690500 # number of StoreCondReq MSHR miss cycles
748system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5254690500 # number of StoreCondReq MSHR miss cycles
749system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 6005000 # number of StoreCondFailReq MSHR miss cycles
750system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 6005000 # number of StoreCondFailReq MSHR miss cycles
751system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82720565500 # number of demand (read+write) MSHR miss cycles
752system.cpu0.dcache.demand_mshr_miss_latency::total 82720565500 # number of demand (read+write) MSHR miss cycles
753system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 100709960500 # number of overall MSHR miss cycles
754system.cpu0.dcache.overall_mshr_miss_latency::total 100709960500 # number of overall MSHR miss cycles
755system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6124425500 # number of ReadReq MSHR uncacheable cycles
756system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6124425500 # number of ReadReq MSHR uncacheable cycles
757system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5931269500 # number of WriteReq MSHR uncacheable cycles
758system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5931269500 # number of WriteReq MSHR uncacheable cycles
759system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12055695000 # number of overall MSHR uncacheable cycles
760system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12055695000 # number of overall MSHR uncacheable cycles
761system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035719 # mshr miss rate for ReadReq accesses
762system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035719 # mshr miss rate for ReadReq accesses
763system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019416 # mshr miss rate for WriteReq accesses
764system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019416 # mshr miss rate for WriteReq accesses
765system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.710666 # mshr miss rate for SoftPFReq accesses
766system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.710666 # mshr miss rate for SoftPFReq accesses
767system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760900 # mshr miss rate for WriteLineReq accesses
768system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760900 # mshr miss rate for WriteLineReq accesses
769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058527 # mshr miss rate for LoadLockedReq accesses
770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058527 # mshr miss rate for LoadLockedReq accesses
771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100221 # mshr miss rate for StoreCondReq accesses
772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100221 # mshr miss rate for StoreCondReq accesses
773system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028029 # mshr miss rate for demand accesses
774system.cpu0.dcache.demand_mshr_miss_rate::total 0.028029 # mshr miss rate for demand accesses
775system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032159 # mshr miss rate for overall accesses
776system.cpu0.dcache.overall_mshr_miss_rate::total 0.032159 # mshr miss rate for overall accesses
777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15389.879107 # average ReadReq mshr miss latency
778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15389.879107 # average ReadReq mshr miss latency
779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25309.396462 # average WriteReq mshr miss latency
780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25309.396462 # average WriteReq mshr miss latency
781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26250.968575 # average SoftPFReq mshr miss latency
782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26250.968575 # average SoftPFReq mshr miss latency
783system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59620.890301 # average WriteLineReq mshr miss latency
784system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59620.890301 # average WriteLineReq mshr miss latency
785system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14362.733876 # average LoadLockedReq mshr miss latency
786system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14362.733876 # average LoadLockedReq mshr miss latency
787system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27038.367929 # average StoreCondReq mshr miss latency
788system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.367929 # average StoreCondReq mshr miss latency
789system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
790system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
791system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18631.349667 # average overall mshr miss latency
792system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18631.349667 # average overall mshr miss latency
793system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19650.171878 # average overall mshr miss latency
794system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19650.171878 # average overall mshr miss latency
795system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190536.835392 # average ReadReq mshr uncacheable latency
796system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190536.835392 # average ReadReq mshr uncacheable latency
797system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187977.989415 # average WriteReq mshr uncacheable latency
798system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187977.989415 # average WriteReq mshr uncacheable latency
799system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189269.263376 # average overall mshr uncacheable latency
800system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189269.263376 # average overall mshr uncacheable latency
801system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
802system.cpu0.icache.tags.replacements 9549530 # number of replacements
803system.cpu0.icache.tags.tagsinuse 511.897064 # Cycle average of tags in use
804system.cpu0.icache.tags.total_refs 236903550 # Total number of references to valid blocks.
805system.cpu0.icache.tags.sampled_refs 9550042 # Sample count of references to valid blocks.
806system.cpu0.icache.tags.avg_refs 24.806545 # Average number of references to valid blocks.
807system.cpu0.icache.tags.warmup_cycle 33055106000 # Cycle when the warmup percentage was hit.
808system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897064 # Average occupied blocks per requestor
809system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy
810system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy
811system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
812system.cpu0.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
813system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
814system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id
815system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
816system.cpu0.icache.tags.tag_accesses 502457255 # Number of tag accesses
817system.cpu0.icache.tags.data_accesses 502457255 # Number of data accesses
818system.cpu0.icache.ReadReq_hits::cpu0.inst 236903550 # number of ReadReq hits
819system.cpu0.icache.ReadReq_hits::total 236903550 # number of ReadReq hits
820system.cpu0.icache.demand_hits::cpu0.inst 236903550 # number of demand (read+write) hits
821system.cpu0.icache.demand_hits::total 236903550 # number of demand (read+write) hits
822system.cpu0.icache.overall_hits::cpu0.inst 236903550 # number of overall hits
823system.cpu0.icache.overall_hits::total 236903550 # number of overall hits
824system.cpu0.icache.ReadReq_misses::cpu0.inst 9550052 # number of ReadReq misses
825system.cpu0.icache.ReadReq_misses::total 9550052 # number of ReadReq misses
826system.cpu0.icache.demand_misses::cpu0.inst 9550052 # number of demand (read+write) misses
827system.cpu0.icache.demand_misses::total 9550052 # number of demand (read+write) misses
828system.cpu0.icache.overall_misses::cpu0.inst 9550052 # number of overall misses
829system.cpu0.icache.overall_misses::total 9550052 # number of overall misses
830system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101421985500 # number of ReadReq miss cycles
831system.cpu0.icache.ReadReq_miss_latency::total 101421985500 # number of ReadReq miss cycles
832system.cpu0.icache.demand_miss_latency::cpu0.inst 101421985500 # number of demand (read+write) miss cycles
833system.cpu0.icache.demand_miss_latency::total 101421985500 # number of demand (read+write) miss cycles
834system.cpu0.icache.overall_miss_latency::cpu0.inst 101421985500 # number of overall miss cycles
835system.cpu0.icache.overall_miss_latency::total 101421985500 # number of overall miss cycles
836system.cpu0.icache.ReadReq_accesses::cpu0.inst 246453602 # number of ReadReq accesses(hits+misses)
837system.cpu0.icache.ReadReq_accesses::total 246453602 # number of ReadReq accesses(hits+misses)
838system.cpu0.icache.demand_accesses::cpu0.inst 246453602 # number of demand (read+write) accesses
839system.cpu0.icache.demand_accesses::total 246453602 # number of demand (read+write) accesses
840system.cpu0.icache.overall_accesses::cpu0.inst 246453602 # number of overall (read+write) accesses
841system.cpu0.icache.overall_accesses::total 246453602 # number of overall (read+write) accesses
842system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038750 # miss rate for ReadReq accesses
843system.cpu0.icache.ReadReq_miss_rate::total 0.038750 # miss rate for ReadReq accesses
844system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038750 # miss rate for demand accesses
845system.cpu0.icache.demand_miss_rate::total 0.038750 # miss rate for demand accesses
846system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038750 # miss rate for overall accesses
847system.cpu0.icache.overall_miss_rate::total 0.038750 # miss rate for overall accesses
848system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10620.045367 # average ReadReq miss latency
849system.cpu0.icache.ReadReq_avg_miss_latency::total 10620.045367 # average ReadReq miss latency
850system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency
851system.cpu0.icache.demand_avg_miss_latency::total 10620.045367 # average overall miss latency
852system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10620.045367 # average overall miss latency
853system.cpu0.icache.overall_avg_miss_latency::total 10620.045367 # average overall miss latency
854system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
855system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
856system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
857system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
858system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
859system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
860system.cpu0.icache.fast_writes 0 # number of fast writes performed
861system.cpu0.icache.cache_copies 0 # number of cache copies performed
862system.cpu0.icache.writebacks::writebacks 9549530 # number of writebacks
863system.cpu0.icache.writebacks::total 9549530 # number of writebacks
864system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9550052 # number of ReadReq MSHR misses
865system.cpu0.icache.ReadReq_mshr_misses::total 9550052 # number of ReadReq MSHR misses
866system.cpu0.icache.demand_mshr_misses::cpu0.inst 9550052 # number of demand (read+write) MSHR misses
867system.cpu0.icache.demand_mshr_misses::total 9550052 # number of demand (read+write) MSHR misses
868system.cpu0.icache.overall_mshr_misses::cpu0.inst 9550052 # number of overall MSHR misses
869system.cpu0.icache.overall_mshr_misses::total 9550052 # number of overall MSHR misses
870system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
871system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
872system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
873system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses
874system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 96646960000 # number of ReadReq MSHR miss cycles
875system.cpu0.icache.ReadReq_mshr_miss_latency::total 96646960000 # number of ReadReq MSHR miss cycles
876system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 96646960000 # number of demand (read+write) MSHR miss cycles
877system.cpu0.icache.demand_mshr_miss_latency::total 96646960000 # number of demand (read+write) MSHR miss cycles
878system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 96646960000 # number of overall MSHR miss cycles
879system.cpu0.icache.overall_mshr_miss_latency::total 96646960000 # number of overall MSHR miss cycles
880system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles
881system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles
882system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles
883system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles
884system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for ReadReq accesses
885system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038750 # mshr miss rate for ReadReq accesses
886system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for demand accesses
887system.cpu0.icache.demand_mshr_miss_rate::total 0.038750 # mshr miss rate for demand accesses
888system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038750 # mshr miss rate for overall accesses
889system.cpu0.icache.overall_mshr_miss_rate::total 0.038750 # mshr miss rate for overall accesses
890system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average ReadReq mshr miss latency
891system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10120.045420 # average ReadReq mshr miss latency
892system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency
893system.cpu0.icache.demand_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency
894system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10120.045420 # average overall mshr miss latency
895system.cpu0.icache.overall_avg_mshr_miss_latency::total 10120.045420 # average overall mshr miss latency
896system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency
897system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency
898system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency
899system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency
900system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
901system.cpu0.l2cache.prefetcher.num_hwpf_issued 7772165 # number of hwpf issued
902system.cpu0.l2cache.prefetcher.pfIdentified 7773534 # number of prefetch candidates identified
903system.cpu0.l2cache.prefetcher.pfBufferHit 1208 # number of redundant prefetches already in prefetch queue
904system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
905system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
906system.cpu0.l2cache.prefetcher.pfSpanPage 991570 # number of prefetches not generated due to page crossing
907system.cpu0.l2cache.tags.replacements 2865211 # number of replacements
908system.cpu0.l2cache.tags.tagsinuse 16182.470551 # Cycle average of tags in use
909system.cpu0.l2cache.tags.total_refs 23591597 # Total number of references to valid blocks.
910system.cpu0.l2cache.tags.sampled_refs 2881428 # Sample count of references to valid blocks.
911system.cpu0.l2cache.tags.avg_refs 8.187467 # Average number of references to valid blocks.
912system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit.
913system.cpu0.l2cache.tags.occ_blocks::writebacks 15283.265421 # Average occupied blocks per requestor
914system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.779936 # Average occupied blocks per requestor
915system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.474522 # Average occupied blocks per requestor
916system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 783.950672 # Average occupied blocks per requestor
917system.cpu0.l2cache.tags.occ_percent::writebacks 0.932816 # Average percentage of cache occupancy
918system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003710 # Average percentage of cache occupancy
919system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003325 # Average percentage of cache occupancy
920system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.047849 # Average percentage of cache occupancy
921system.cpu0.l2cache.tags.occ_percent::total 0.987700 # Average percentage of cache occupancy
922system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1265 # Occupied blocks per task id
923system.cpu0.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id
924system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14897 # Occupied blocks per task id
925system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id
926system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 535 # Occupied blocks per task id
927system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id
928system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 58 # Occupied blocks per task id
929system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
930system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 45 # Occupied blocks per task id
931system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
932system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
933system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id
934system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5291 # Occupied blocks per task id
935system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7937 # Occupied blocks per task id
936system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 458 # Occupied blocks per task id
937system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.077209 # Percentage of cache occupancy per task id
938system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
939system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909241 # Percentage of cache occupancy per task id
940system.cpu0.l2cache.tags.tag_accesses 513878817 # Number of tag accesses
941system.cpu0.l2cache.tags.data_accesses 513878817 # Number of data accesses
942system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 534301 # number of ReadReq hits
943system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 171000 # number of ReadReq hits
944system.cpu0.l2cache.ReadReq_hits::total 705301 # number of ReadReq hits
945system.cpu0.l2cache.WritebackDirty_hits::writebacks 3781367 # number of WritebackDirty hits
946system.cpu0.l2cache.WritebackDirty_hits::total 3781367 # number of WritebackDirty hits
947system.cpu0.l2cache.WritebackClean_hits::writebacks 11445215 # number of WritebackClean hits
948system.cpu0.l2cache.WritebackClean_hits::total 11445215 # number of WritebackClean hits
949system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 428 # number of UpgradeReq hits
950system.cpu0.l2cache.UpgradeReq_hits::total 428 # number of UpgradeReq hits
951system.cpu0.l2cache.ReadExReq_hits::cpu0.data 897370 # number of ReadExReq hits
952system.cpu0.l2cache.ReadExReq_hits::total 897370 # number of ReadExReq hits
953system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 8796749 # number of ReadCleanReq hits
954system.cpu0.l2cache.ReadCleanReq_hits::total 8796749 # number of ReadCleanReq hits
955system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2760570 # number of ReadSharedReq hits
956system.cpu0.l2cache.ReadSharedReq_hits::total 2760570 # number of ReadSharedReq hits
957system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 203097 # number of InvalidateReq hits
958system.cpu0.l2cache.InvalidateReq_hits::total 203097 # number of InvalidateReq hits
959system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 534301 # number of demand (read+write) hits
960system.cpu0.l2cache.demand_hits::cpu0.itb.walker 171000 # number of demand (read+write) hits
961system.cpu0.l2cache.demand_hits::cpu0.inst 8796749 # number of demand (read+write) hits
962system.cpu0.l2cache.demand_hits::cpu0.data 3657940 # number of demand (read+write) hits
963system.cpu0.l2cache.demand_hits::total 13159990 # number of demand (read+write) hits
964system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 534301 # number of overall hits
965system.cpu0.l2cache.overall_hits::cpu0.itb.walker 171000 # number of overall hits
966system.cpu0.l2cache.overall_hits::cpu0.inst 8796749 # number of overall hits
967system.cpu0.l2cache.overall_hits::cpu0.data 3657940 # number of overall hits
968system.cpu0.l2cache.overall_hits::total 13159990 # number of overall hits
969system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12394 # number of ReadReq misses
970system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8896 # number of ReadReq misses
971system.cpu0.l2cache.ReadReq_misses::total 21290 # number of ReadReq misses
972system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
973system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
974system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
975system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
976system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 263050 # number of UpgradeReq misses
977system.cpu0.l2cache.UpgradeReq_misses::total 263050 # number of UpgradeReq misses
978system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 194335 # number of SCUpgradeReq misses
979system.cpu0.l2cache.SCUpgradeReq_misses::total 194335 # number of SCUpgradeReq misses
980system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses
981system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
982system.cpu0.l2cache.ReadExReq_misses::cpu0.data 298989 # number of ReadExReq misses
983system.cpu0.l2cache.ReadExReq_misses::total 298989 # number of ReadExReq misses
984system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 753302 # number of ReadCleanReq misses
985system.cpu0.l2cache.ReadCleanReq_misses::total 753302 # number of ReadCleanReq misses
986system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1026998 # number of ReadSharedReq misses
987system.cpu0.l2cache.ReadSharedReq_misses::total 1026998 # number of ReadSharedReq misses
988system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 596103 # number of InvalidateReq misses
989system.cpu0.l2cache.InvalidateReq_misses::total 596103 # number of InvalidateReq misses
990system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12394 # number of demand (read+write) misses
991system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8896 # number of demand (read+write) misses
992system.cpu0.l2cache.demand_misses::cpu0.inst 753302 # number of demand (read+write) misses
993system.cpu0.l2cache.demand_misses::cpu0.data 1325987 # number of demand (read+write) misses
994system.cpu0.l2cache.demand_misses::total 2100579 # number of demand (read+write) misses
995system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12394 # number of overall misses
996system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8896 # number of overall misses
997system.cpu0.l2cache.overall_misses::cpu0.inst 753302 # number of overall misses
998system.cpu0.l2cache.overall_misses::cpu0.data 1325987 # number of overall misses
999system.cpu0.l2cache.overall_misses::total 2100579 # number of overall misses
1000system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 543058500 # number of ReadReq miss cycles
1001system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 406297500 # number of ReadReq miss cycles
1002system.cpu0.l2cache.ReadReq_miss_latency::total 949356000 # number of ReadReq miss cycles
1003system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3394715000 # number of UpgradeReq miss cycles
1004system.cpu0.l2cache.UpgradeReq_miss_latency::total 3394715000 # number of UpgradeReq miss cycles
1005system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1886445500 # number of SCUpgradeReq miss cycles
1006system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1886445500 # number of SCUpgradeReq miss cycles
1007system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5898999 # number of SCUpgradeFailReq miss cycles
1008system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5898999 # number of SCUpgradeFailReq miss cycles
1009system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19173654497 # number of ReadExReq miss cycles
1010system.cpu0.l2cache.ReadExReq_miss_latency::total 19173654497 # number of ReadExReq miss cycles
1011system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29218782500 # number of ReadCleanReq miss cycles
1012system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29218782500 # number of ReadCleanReq miss cycles
1013system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41703375488 # number of ReadSharedReq miss cycles
1014system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41703375488 # number of ReadSharedReq miss cycles
1015system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 451954500 # number of InvalidateReq miss cycles
1016system.cpu0.l2cache.InvalidateReq_miss_latency::total 451954500 # number of InvalidateReq miss cycles
1017system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 543058500 # number of demand (read+write) miss cycles
1018system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 406297500 # number of demand (read+write) miss cycles
1019system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29218782500 # number of demand (read+write) miss cycles
1020system.cpu0.l2cache.demand_miss_latency::cpu0.data 60877029985 # number of demand (read+write) miss cycles
1021system.cpu0.l2cache.demand_miss_latency::total 91045168485 # number of demand (read+write) miss cycles
1022system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 543058500 # number of overall miss cycles
1023system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 406297500 # number of overall miss cycles
1024system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29218782500 # number of overall miss cycles
1025system.cpu0.l2cache.overall_miss_latency::cpu0.data 60877029985 # number of overall miss cycles
1026system.cpu0.l2cache.overall_miss_latency::total 91045168485 # number of overall miss cycles
1027system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 546695 # number of ReadReq accesses(hits+misses)
1028system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 179896 # number of ReadReq accesses(hits+misses)
1029system.cpu0.l2cache.ReadReq_accesses::total 726591 # number of ReadReq accesses(hits+misses)
1030system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3781369 # number of WritebackDirty accesses(hits+misses)
1031system.cpu0.l2cache.WritebackDirty_accesses::total 3781369 # number of WritebackDirty accesses(hits+misses)
1032system.cpu0.l2cache.WritebackClean_accesses::writebacks 11445216 # number of WritebackClean accesses(hits+misses)
1033system.cpu0.l2cache.WritebackClean_accesses::total 11445216 # number of WritebackClean accesses(hits+misses)
1034system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 263478 # number of UpgradeReq accesses(hits+misses)
1035system.cpu0.l2cache.UpgradeReq_accesses::total 263478 # number of UpgradeReq accesses(hits+misses)
1036system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194335 # number of SCUpgradeReq accesses(hits+misses)
1037system.cpu0.l2cache.SCUpgradeReq_accesses::total 194335 # number of SCUpgradeReq accesses(hits+misses)
1038system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
1039system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
1040system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196359 # number of ReadExReq accesses(hits+misses)
1041system.cpu0.l2cache.ReadExReq_accesses::total 1196359 # number of ReadExReq accesses(hits+misses)
1042system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9550051 # number of ReadCleanReq accesses(hits+misses)
1043system.cpu0.l2cache.ReadCleanReq_accesses::total 9550051 # number of ReadCleanReq accesses(hits+misses)
1044system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3787568 # number of ReadSharedReq accesses(hits+misses)
1045system.cpu0.l2cache.ReadSharedReq_accesses::total 3787568 # number of ReadSharedReq accesses(hits+misses)
1046system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 799200 # number of InvalidateReq accesses(hits+misses)
1047system.cpu0.l2cache.InvalidateReq_accesses::total 799200 # number of InvalidateReq accesses(hits+misses)
1048system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 546695 # number of demand (read+write) accesses
1049system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 179896 # number of demand (read+write) accesses
1050system.cpu0.l2cache.demand_accesses::cpu0.inst 9550051 # number of demand (read+write) accesses
1051system.cpu0.l2cache.demand_accesses::cpu0.data 4983927 # number of demand (read+write) accesses
1052system.cpu0.l2cache.demand_accesses::total 15260569 # number of demand (read+write) accesses
1053system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 546695 # number of overall (read+write) accesses
1054system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 179896 # number of overall (read+write) accesses
1055system.cpu0.l2cache.overall_accesses::cpu0.inst 9550051 # number of overall (read+write) accesses
1056system.cpu0.l2cache.overall_accesses::cpu0.data 4983927 # number of overall (read+write) accesses
1057system.cpu0.l2cache.overall_accesses::total 15260569 # number of overall (read+write) accesses
1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for ReadReq accesses
1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049451 # miss rate for ReadReq accesses
1060system.cpu0.l2cache.ReadReq_miss_rate::total 0.029301 # miss rate for ReadReq accesses
1061system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
1062system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
1063system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1064system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1065system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998376 # miss rate for UpgradeReq accesses
1066system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998376 # miss rate for UpgradeReq accesses
1067system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1068system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1069system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1070system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1071system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.249916 # miss rate for ReadExReq accesses
1072system.cpu0.l2cache.ReadExReq_miss_rate::total 0.249916 # miss rate for ReadExReq accesses
1073system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.078879 # miss rate for ReadCleanReq accesses
1074system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.078879 # miss rate for ReadCleanReq accesses
1075system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.271150 # miss rate for ReadSharedReq accesses
1076system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.271150 # miss rate for ReadSharedReq accesses
1077system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.745875 # miss rate for InvalidateReq accesses
1078system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.745875 # miss rate for InvalidateReq accesses
1079system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for demand accesses
1080system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049451 # miss rate for demand accesses
1081system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078879 # miss rate for demand accesses
1082system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.266053 # miss rate for demand accesses
1083system.cpu0.l2cache.demand_miss_rate::total 0.137647 # miss rate for demand accesses
1084system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022671 # miss rate for overall accesses
1085system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049451 # miss rate for overall accesses
1086system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078879 # miss rate for overall accesses
1087system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.266053 # miss rate for overall accesses
1088system.cpu0.l2cache.overall_miss_rate::total 0.137647 # miss rate for overall accesses
1089system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average ReadReq miss latency
1090system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45671.931205 # average ReadReq miss latency
1091system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44591.639267 # average ReadReq miss latency
1092system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12905.208135 # average UpgradeReq miss latency
1093system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12905.208135 # average UpgradeReq miss latency
1094system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9707.183472 # average SCUpgradeReq miss latency
1095system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9707.183472 # average SCUpgradeReq miss latency
1096system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842714.142857 # average SCUpgradeFailReq miss latency
1097system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842714.142857 # average SCUpgradeFailReq miss latency
1098system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64128.294007 # average ReadExReq miss latency
1099system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64128.294007 # average ReadExReq miss latency
1100system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38787.607759 # average ReadCleanReq miss latency
1101system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38787.607759 # average ReadCleanReq miss latency
1102system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 40607.065922 # average ReadSharedReq miss latency
1103system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 40607.065922 # average ReadSharedReq miss latency
1104system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 758.181891 # average InvalidateReq miss latency
1105system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 758.181891 # average InvalidateReq miss latency
1106system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average overall miss latency
1107system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45671.931205 # average overall miss latency
1108system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38787.607759 # average overall miss latency
1109system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45910.729129 # average overall miss latency
1110system.cpu0.l2cache.demand_avg_miss_latency::total 43342.891881 # average overall miss latency
1111system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 43816.241730 # average overall miss latency
1112system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45671.931205 # average overall miss latency
1113system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38787.607759 # average overall miss latency
1114system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45910.729129 # average overall miss latency
1115system.cpu0.l2cache.overall_avg_miss_latency::total 43342.891881 # average overall miss latency
1116system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1117system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1118system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1119system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1120system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1121system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1122system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1123system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1124system.cpu0.l2cache.writebacks::writebacks 1676207 # number of writebacks
1125system.cpu0.l2cache.writebacks::total 1676207 # number of writebacks
1126system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits
1127system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
1128system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9778 # number of ReadExReq MSHR hits
1129system.cpu0.l2cache.ReadExReq_mshr_hits::total 9778 # number of ReadExReq MSHR hits
1130system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
1131system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1132system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1426 # number of ReadSharedReq MSHR hits
1133system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1426 # number of ReadSharedReq MSHR hits
1134system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
1135system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
1136system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits
1137system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
1138system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11204 # number of demand (read+write) MSHR hits
1139system.cpu0.l2cache.demand_mshr_hits::total 11215 # number of demand (read+write) MSHR hits
1140system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits
1141system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
1142system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11204 # number of overall MSHR hits
1143system.cpu0.l2cache.overall_mshr_hits::total 11215 # number of overall MSHR hits
1144system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12394 # number of ReadReq MSHR misses
1145system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8894 # number of ReadReq MSHR misses
1146system.cpu0.l2cache.ReadReq_mshr_misses::total 21288 # number of ReadReq MSHR misses
1147system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
1148system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
1149system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
1150system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
1151system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 800672 # number of HardPFReq MSHR misses
1152system.cpu0.l2cache.HardPFReq_mshr_misses::total 800672 # number of HardPFReq MSHR misses
1153system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 263050 # number of UpgradeReq MSHR misses
1154system.cpu0.l2cache.UpgradeReq_mshr_misses::total 263050 # number of UpgradeReq MSHR misses
1155system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 194335 # number of SCUpgradeReq MSHR misses
1156system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 194335 # number of SCUpgradeReq MSHR misses
1157system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses
1158system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
1159system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289211 # number of ReadExReq MSHR misses
1160system.cpu0.l2cache.ReadExReq_mshr_misses::total 289211 # number of ReadExReq MSHR misses
1161system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 753293 # number of ReadCleanReq MSHR misses
1162system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 753293 # number of ReadCleanReq MSHR misses
1163system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1025572 # number of ReadSharedReq MSHR misses
1164system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1025572 # number of ReadSharedReq MSHR misses
1165system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 596100 # number of InvalidateReq MSHR misses
1166system.cpu0.l2cache.InvalidateReq_mshr_misses::total 596100 # number of InvalidateReq MSHR misses
1167system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12394 # number of demand (read+write) MSHR misses
1168system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8894 # number of demand (read+write) MSHR misses
1169system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 753293 # number of demand (read+write) MSHR misses
1170system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1314783 # number of demand (read+write) MSHR misses
1171system.cpu0.l2cache.demand_mshr_misses::total 2089364 # number of demand (read+write) MSHR misses
1172system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12394 # number of overall MSHR misses
1173system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8894 # number of overall MSHR misses
1174system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 753293 # number of overall MSHR misses
1175system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1314783 # number of overall MSHR misses
1176system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 800672 # number of overall MSHR misses
1177system.cpu0.l2cache.overall_mshr_misses::total 2890036 # number of overall MSHR misses
1178system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
1179system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
1180system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84452 # number of ReadReq MSHR uncacheable
1181system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
1182system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31553 # number of WriteReq MSHR uncacheable
1183system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
1184system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
1185system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 116005 # number of overall MSHR uncacheable misses
1186system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of ReadReq MSHR miss cycles
1187system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 352893500 # number of ReadReq MSHR miss cycles
1188system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 821588000 # number of ReadReq MSHR miss cycles
1189system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47791541037 # number of HardPFReq MSHR miss cycles
1190system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47791541037 # number of HardPFReq MSHR miss cycles
1191system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7826601497 # number of UpgradeReq MSHR miss cycles
1192system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7826601497 # number of UpgradeReq MSHR miss cycles
1193system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3792362000 # number of SCUpgradeReq MSHR miss cycles
1194system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3792362000 # number of SCUpgradeReq MSHR miss cycles
1195system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5478999 # number of SCUpgradeFailReq MSHR miss cycles
1196system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5478999 # number of SCUpgradeFailReq MSHR miss cycles
1197system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16008058497 # number of ReadExReq MSHR miss cycles
1198system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16008058497 # number of ReadExReq MSHR miss cycles
1199system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 24698519500 # number of ReadCleanReq MSHR miss cycles
1200system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 24698519500 # number of ReadCleanReq MSHR miss cycles
1201system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 35410416988 # number of ReadSharedReq MSHR miss cycles
1202system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 35410416988 # number of ReadSharedReq MSHR miss cycles
1203system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 41536789000 # number of InvalidateReq MSHR miss cycles
1204system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 41536789000 # number of InvalidateReq MSHR miss cycles
1205system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of demand (read+write) MSHR miss cycles
1206system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 352893500 # number of demand (read+write) MSHR miss cycles
1207system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 24698519500 # number of demand (read+write) MSHR miss cycles
1208system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 51418475485 # number of demand (read+write) MSHR miss cycles
1209system.cpu0.l2cache.demand_mshr_miss_latency::total 76938582985 # number of demand (read+write) MSHR miss cycles
1210system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 468694500 # number of overall MSHR miss cycles
1211system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 352893500 # number of overall MSHR miss cycles
1212system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24698519500 # number of overall MSHR miss cycles
1213system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 51418475485 # number of overall MSHR miss cycles
1214system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47791541037 # number of overall MSHR miss cycles
1215system.cpu0.l2cache.overall_mshr_miss_latency::total 124730124022 # number of overall MSHR miss cycles
1216system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles
1217system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5867073000 # number of ReadReq MSHR uncacheable cycles
1218system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12863228000 # number of ReadReq MSHR uncacheable cycles
1219system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5694540000 # number of WriteReq MSHR uncacheable cycles
1220system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5694540000 # number of WriteReq MSHR uncacheable cycles
1221system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles
1222system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561613000 # number of overall MSHR uncacheable cycles
1223system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18557768000 # number of overall MSHR uncacheable cycles
1224system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for ReadReq accesses
1225system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for ReadReq accesses
1226system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029298 # mshr miss rate for ReadReq accesses
1227system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
1228system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
1229system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1230system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1231system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1232system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1233system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998376 # mshr miss rate for UpgradeReq accesses
1234system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998376 # mshr miss rate for UpgradeReq accesses
1235system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1236system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1237system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1238system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1239system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.241743 # mshr miss rate for ReadExReq accesses
1240system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.241743 # mshr miss rate for ReadExReq accesses
1241system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for ReadCleanReq accesses
1242system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.078878 # mshr miss rate for ReadCleanReq accesses
1243system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270773 # mshr miss rate for ReadSharedReq accesses
1244system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270773 # mshr miss rate for ReadSharedReq accesses
1245system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.745871 # mshr miss rate for InvalidateReq accesses
1246system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.745871 # mshr miss rate for InvalidateReq accesses
1247system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for demand accesses
1248system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for demand accesses
1249system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for demand accesses
1250system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for demand accesses
1251system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136913 # mshr miss rate for demand accesses
1252system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022671 # mshr miss rate for overall accesses
1253system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049440 # mshr miss rate for overall accesses
1254system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078878 # mshr miss rate for overall accesses
1255system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263805 # mshr miss rate for overall accesses
1256system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1257system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189379 # mshr miss rate for overall accesses
1258system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average ReadReq mshr miss latency
1259system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average ReadReq mshr miss latency
1260system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38593.949643 # average ReadReq mshr miss latency
1261system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average HardPFReq mshr miss latency
1262system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59689.287295 # average HardPFReq mshr miss latency
1263system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29753.284535 # average UpgradeReq mshr miss latency
1264system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29753.284535 # average UpgradeReq mshr miss latency
1265system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19514.559909 # average SCUpgradeReq mshr miss latency
1266system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19514.559909 # average SCUpgradeReq mshr miss latency
1267system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 782714.142857 # average SCUpgradeFailReq mshr miss latency
1268system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782714.142857 # average SCUpgradeFailReq mshr miss latency
1269system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55350.794047 # average ReadExReq mshr miss latency
1270system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55350.794047 # average ReadExReq mshr miss latency
1271system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average ReadCleanReq mshr miss latency
1272system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32787.400786 # average ReadCleanReq mshr miss latency
1273system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 34527.480263 # average ReadSharedReq mshr miss latency
1274system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34527.480263 # average ReadSharedReq mshr miss latency
1275system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69680.907566 # average InvalidateReq mshr miss latency
1276system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 69680.907566 # average InvalidateReq mshr miss latency
1277system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
1278system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
1279system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
1280system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
1281system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36823.924881 # average overall mshr miss latency
1282system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37816.241730 # average overall mshr miss latency
1283system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39677.704070 # average overall mshr miss latency
1284system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32787.400786 # average overall mshr miss latency
1285system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39107.955826 # average overall mshr miss latency
1286system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59689.287295 # average overall mshr miss latency
1287system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43158.674848 # average overall mshr miss latency
1288system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency
1289system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182530.348754 # average ReadReq mshr uncacheable latency
1290system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152314.071899 # average ReadReq mshr uncacheable latency
1291system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180475.390613 # average WriteReq mshr uncacheable latency
1292system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 180475.390613 # average WriteReq mshr uncacheable latency
1293system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency
1294system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181512.386963 # average overall mshr uncacheable latency
1295system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159973.863196 # average overall mshr uncacheable latency
1296system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1297system.cpu0.toL2Bus.snoop_filter.tot_requests 31336515 # Total number of requests made to the snoop filter.
1298system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16003499 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1299system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2764 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1300system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238925 # Total number of snoops made to the snoop filter.
1301system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238443 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1302system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 482 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1303system.cpu0.toL2Bus.trans_dist::ReadReq 888197 # Transaction distribution
1304system.cpu0.toL2Bus.trans_dist::ReadResp 14329408 # Transaction distribution
1305system.cpu0.toL2Bus.trans_dist::WriteReq 31554 # Transaction distribution
1306system.cpu0.toL2Bus.trans_dist::WriteResp 31553 # Transaction distribution
1307system.cpu0.toL2Bus.trans_dist::WritebackDirty 5463883 # Transaction distribution
1308system.cpu0.toL2Bus.trans_dist::WritebackClean 11447979 # Transaction distribution
1309system.cpu0.toL2Bus.trans_dist::CleanEvict 3030252 # Transaction distribution
1310system.cpu0.toL2Bus.trans_dist::HardPFReq 1046563 # Transaction distribution
1311system.cpu0.toL2Bus.trans_dist::UpgradeReq 472775 # Transaction distribution
1312system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352055 # Transaction distribution
1313system.cpu0.toL2Bus.trans_dist::UpgradeResp 529438 # Transaction distribution
1314system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
1315system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
1316system.cpu0.toL2Bus.trans_dist::ReadExReq 1230630 # Transaction distribution
1317system.cpu0.toL2Bus.trans_dist::ReadExResp 1206068 # Transaction distribution
1318system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9550052 # Transaction distribution
1319system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4850843 # Transaction distribution
1320system.cpu0.toL2Bus.trans_dist::InvalidateReq 854414 # Transaction distribution
1321system.cpu0.toL2Bus.trans_dist::InvalidateResp 799200 # Transaction distribution
1322system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28754250 # Packet count per connected master and slave (bytes)
1323system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18474160 # Packet count per connected master and slave (bytes)
1324system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377323 # Packet count per connected master and slave (bytes)
1325system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1153011 # Packet count per connected master and slave (bytes)
1326system.cpu0.toL2Bus.pkt_count::total 48758744 # Packet count per connected master and slave (bytes)
1327system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1225720896 # Cumulative packet size per connected master and slave (bytes)
1328system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 689935275 # Cumulative packet size per connected master and slave (bytes)
1329system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes)
1330system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4373560 # Cumulative packet size per connected master and slave (bytes)
1331system.cpu0.toL2Bus.pkt_size::total 1921468899 # Cumulative packet size per connected master and slave (bytes)
1332system.cpu0.toL2Bus.snoops 7541383 # Total snoops (count)
1333system.cpu0.toL2Bus.snoop_fanout::samples 23989921 # Request fanout histogram
1334system.cpu0.toL2Bus.snoop_fanout::mean 0.106643 # Request fanout histogram
1335system.cpu0.toL2Bus.snoop_fanout::stdev 0.308724 # Request fanout histogram
1336system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1337system.cpu0.toL2Bus.snoop_fanout::0 21432051 89.34% 89.34% # Request fanout histogram
1338system.cpu0.toL2Bus.snoop_fanout::1 2557388 10.66% 100.00% # Request fanout histogram
1339system.cpu0.toL2Bus.snoop_fanout::2 482 0.00% 100.00% # Request fanout histogram
1340system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1341system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1342system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1343system.cpu0.toL2Bus.snoop_fanout::total 23989921 # Request fanout histogram
1344system.cpu0.toL2Bus.reqLayer0.occupancy 31215182485 # Layer occupancy (ticks)
1345system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1346system.cpu0.toL2Bus.snoopLayer0.occupancy 206081920 # Layer occupancy (ticks)
1347system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1348system.cpu0.toL2Bus.respLayer0.occupancy 14406948660 # Layer occupancy (ticks)
1349system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1350system.cpu0.toL2Bus.respLayer1.occupancy 8156637515 # Layer occupancy (ticks)
1351system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1352system.cpu0.toL2Bus.respLayer2.occupancy 197502349 # Layer occupancy (ticks)
1353system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1354system.cpu0.toL2Bus.respLayer3.occupancy 606443243 # Layer occupancy (ticks)
1355system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1356system.cpu1.branchPred.lookups 134798362 # Number of BP lookups
1357system.cpu1.branchPred.condPredicted 95816419 # Number of conditional branches predicted
1358system.cpu1.branchPred.condIncorrect 6051956 # Number of conditional branches incorrect
1359system.cpu1.branchPred.BTBLookups 100961028 # Number of BTB lookups
1360system.cpu1.branchPred.BTBHits 73848042 # Number of BTB hits
1361system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1362system.cpu1.branchPred.BTBHitPct 73.145097 # BTB Hit Percentage
1363system.cpu1.branchPred.usedRAS 15861028 # Number of times the RAS was used to get a target.
1364system.cpu1.branchPred.RASInCorrect 1023147 # Number of incorrect RAS predictions.
1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1367system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1368system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1369system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1370system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1371system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1372system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1386system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1387system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1388system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1389system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1390system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1391system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1392system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1393system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1394system.cpu1.dtb.walker.walks 282723 # Table walker walks requested
1395system.cpu1.dtb.walker.walksLong 282723 # Table walker walks initiated with long descriptors
1396system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10766 # Level at which table walker walks with long descriptors terminate
1397system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86594 # Level at which table walker walks with long descriptors terminate
1398system.cpu1.dtb.walker.walkWaitTime::samples 282723 # Table walker wait (enqueue to first request) latency
1399system.cpu1.dtb.walker.walkWaitTime::0 282723 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1400system.cpu1.dtb.walker.walkWaitTime::total 282723 # Table walker wait (enqueue to first request) latency
1401system.cpu1.dtb.walker.walkCompletionTime::samples 97360 # Table walker service (enqueue to completion) latency
1402system.cpu1.dtb.walker.walkCompletionTime::mean 23363.804437 # Table walker service (enqueue to completion) latency
1403system.cpu1.dtb.walker.walkCompletionTime::gmean 21328.911362 # Table walker service (enqueue to completion) latency
1404system.cpu1.dtb.walker.walkCompletionTime::stdev 20585.456118 # Table walker service (enqueue to completion) latency
1405system.cpu1.dtb.walker.walkCompletionTime::0-65535 96095 98.70% 98.70% # Table walker service (enqueue to completion) latency
1406system.cpu1.dtb.walker.walkCompletionTime::65536-131071 182 0.19% 98.89% # Table walker service (enqueue to completion) latency
1407system.cpu1.dtb.walker.walkCompletionTime::131072-196607 912 0.94% 99.82% # Table walker service (enqueue to completion) latency
1408system.cpu1.dtb.walker.walkCompletionTime::196608-262143 29 0.03% 99.85% # Table walker service (enqueue to completion) latency
1409system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.04% 99.90% # Table walker service (enqueue to completion) latency
1410system.cpu1.dtb.walker.walkCompletionTime::327680-393215 31 0.03% 99.93% # Table walker service (enqueue to completion) latency
1411system.cpu1.dtb.walker.walkCompletionTime::393216-458751 49 0.05% 99.98% # Table walker service (enqueue to completion) latency
1412system.cpu1.dtb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
1413system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1414system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1415system.cpu1.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1416system.cpu1.dtb.walker.walkCompletionTime::total 97360 # Table walker service (enqueue to completion) latency
1417system.cpu1.dtb.walker.walksPending::samples 1788277352 # Table walker pending requests distribution
1418system.cpu1.dtb.walker.walksPending::0 1788277352 100.00% 100.00% # Table walker pending requests distribution
1419system.cpu1.dtb.walker.walksPending::total 1788277352 # Table walker pending requests distribution
1420system.cpu1.dtb.walker.walkPageSizes::4K 86594 88.94% 88.94% # Table walker page sizes translated
1421system.cpu1.dtb.walker.walkPageSizes::2M 10766 11.06% 100.00% # Table walker page sizes translated
1422system.cpu1.dtb.walker.walkPageSizes::total 97360 # Table walker page sizes translated
1423system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 282723 # Table walker requests started/completed, data/inst
1424system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1425system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 282723 # Table walker requests started/completed, data/inst
1426system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97360 # Table walker requests started/completed, data/inst
1427system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1428system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97360 # Table walker requests started/completed, data/inst
1429system.cpu1.dtb.walker.walkRequestOrigin::total 380083 # Table walker requests started/completed, data/inst
1430system.cpu1.dtb.inst_hits 0 # ITB inst hits
1431system.cpu1.dtb.inst_misses 0 # ITB inst misses
1432system.cpu1.dtb.read_hits 88221750 # DTB read hits
1433system.cpu1.dtb.read_misses 234611 # DTB read misses
1434system.cpu1.dtb.write_hits 76459163 # DTB write hits
1435system.cpu1.dtb.write_misses 48112 # DTB write misses
1436system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1437system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1438system.cpu1.dtb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
1439system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
1440system.cpu1.dtb.flush_entries 39871 # Number of entries that have been flushed from TLB
1441system.cpu1.dtb.align_faults 1240 # Number of TLB faults due to alignment restrictions
1442system.cpu1.dtb.prefetch_faults 8073 # Number of TLB faults due to prefetch
1443system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1444system.cpu1.dtb.perms_faults 11018 # Number of TLB faults due to permissions restrictions
1445system.cpu1.dtb.read_accesses 88456361 # DTB read accesses
1446system.cpu1.dtb.write_accesses 76507275 # DTB write accesses
1447system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1448system.cpu1.dtb.hits 164680913 # DTB hits
1449system.cpu1.dtb.misses 282723 # DTB misses
1450system.cpu1.dtb.accesses 164963636 # DTB accesses
1451system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1452system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1453system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1454system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1455system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1456system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1457system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1458system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1472system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1473system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1474system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1475system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1476system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1477system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1478system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1479system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1480system.cpu1.itb.walker.walks 64693 # Table walker walks requested
1481system.cpu1.itb.walker.walksLong 64693 # Table walker walks initiated with long descriptors
1482system.cpu1.itb.walker.walksLongTerminationLevel::Level2 526 # Level at which table walker walks with long descriptors terminate
1483system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55247 # Level at which table walker walks with long descriptors terminate
1484system.cpu1.itb.walker.walkWaitTime::samples 64693 # Table walker wait (enqueue to first request) latency
1485system.cpu1.itb.walker.walkWaitTime::0 64693 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1486system.cpu1.itb.walker.walkWaitTime::total 64693 # Table walker wait (enqueue to first request) latency
1487system.cpu1.itb.walker.walkCompletionTime::samples 55773 # Table walker service (enqueue to completion) latency
1488system.cpu1.itb.walker.walkCompletionTime::mean 26679.495455 # Table walker service (enqueue to completion) latency
1489system.cpu1.itb.walker.walkCompletionTime::gmean 23706.173761 # Table walker service (enqueue to completion) latency
1490system.cpu1.itb.walker.walkCompletionTime::stdev 24561.580376 # Table walker service (enqueue to completion) latency
1491system.cpu1.itb.walker.walkCompletionTime::0-65535 54531 97.77% 97.77% # Table walker service (enqueue to completion) latency
1492system.cpu1.itb.walker.walkCompletionTime::65536-131071 9 0.02% 97.79% # Table walker service (enqueue to completion) latency
1493system.cpu1.itb.walker.walkCompletionTime::131072-196607 1101 1.97% 99.76% # Table walker service (enqueue to completion) latency
1494system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.06% 99.83% # Table walker service (enqueue to completion) latency
1495system.cpu1.itb.walker.walkCompletionTime::262144-327679 52 0.09% 99.92% # Table walker service (enqueue to completion) latency
1496system.cpu1.itb.walker.walkCompletionTime::327680-393215 31 0.06% 99.97% # Table walker service (enqueue to completion) latency
1497system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1498system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
1499system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1500system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1501system.cpu1.itb.walker.walkCompletionTime::total 55773 # Table walker service (enqueue to completion) latency
1502system.cpu1.itb.walker.walksPending::samples 1787261852 # Table walker pending requests distribution
1503system.cpu1.itb.walker.walksPending::0 1787261852 100.00% 100.00% # Table walker pending requests distribution
1504system.cpu1.itb.walker.walksPending::total 1787261852 # Table walker pending requests distribution
1505system.cpu1.itb.walker.walkPageSizes::4K 55247 99.06% 99.06% # Table walker page sizes translated
1506system.cpu1.itb.walker.walkPageSizes::2M 526 0.94% 100.00% # Table walker page sizes translated
1507system.cpu1.itb.walker.walkPageSizes::total 55773 # Table walker page sizes translated
1508system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1509system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64693 # Table walker requests started/completed, data/inst
1510system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64693 # Table walker requests started/completed, data/inst
1511system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1512system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55773 # Table walker requests started/completed, data/inst
1513system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55773 # Table walker requests started/completed, data/inst
1514system.cpu1.itb.walker.walkRequestOrigin::total 120466 # Table walker requests started/completed, data/inst
1515system.cpu1.itb.inst_hits 241355329 # ITB inst hits
1516system.cpu1.itb.inst_misses 64693 # ITB inst misses
1517system.cpu1.itb.read_hits 0 # DTB read hits
1518system.cpu1.itb.read_misses 0 # DTB read misses
1519system.cpu1.itb.write_hits 0 # DTB write hits
1520system.cpu1.itb.write_misses 0 # DTB write misses
1521system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1522system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1523system.cpu1.itb.flush_tlb_mva_asid 42183 # Number of times TLB was flushed by MVA & ASID
1524system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
1525system.cpu1.itb.flush_entries 28782 # Number of entries that have been flushed from TLB
1526system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1527system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1528system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1529system.cpu1.itb.perms_faults 214506 # Number of TLB faults due to permissions restrictions
1530system.cpu1.itb.read_accesses 0 # DTB read accesses
1531system.cpu1.itb.write_accesses 0 # DTB write accesses
1532system.cpu1.itb.inst_accesses 241420022 # ITB inst accesses
1533system.cpu1.itb.hits 241355329 # DTB hits
1534system.cpu1.itb.misses 64693 # DTB misses
1535system.cpu1.itb.accesses 241420022 # DTB accesses
1536system.cpu1.numCycles 943222184 # number of cpu cycles simulated
1537system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1538system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1539system.cpu1.committedInsts 444939071 # Number of instructions committed
1540system.cpu1.committedOps 523893431 # Number of ops (including micro ops) committed
1541system.cpu1.discardedOps 46484386 # Number of ops (including micro ops) which were discarded before commit
1542system.cpu1.numFetchSuspends 5697 # Number of times Execute suspended instruction fetching
1543system.cpu1.quiesceCycles 94049904755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1544system.cpu1.cpi 2.119891 # CPI: cycles per instruction
1545system.cpu1.ipc 0.471722 # IPC: instructions per cycle
1546system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1547system.cpu1.kern.inst.quiesce 5760 # number of quiesce instructions executed
1548system.cpu1.tickCycles 722277565 # Number of cycles that the object actually ticked
1549system.cpu1.idleCycles 220944619 # Total number of cycles that the object has spent stopped
1550system.cpu1.dcache.tags.replacements 5315264 # number of replacements
1551system.cpu1.dcache.tags.tagsinuse 430.485039 # Cycle average of tags in use
1552system.cpu1.dcache.tags.total_refs 156623393 # Total number of references to valid blocks.
1553system.cpu1.dcache.tags.sampled_refs 5315774 # Sample count of references to valid blocks.
1554system.cpu1.dcache.tags.avg_refs 29.463892 # Average number of references to valid blocks.
1555system.cpu1.dcache.tags.warmup_cycle 8391021559000 # Cycle when the warmup percentage was hit.
1556system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.485039 # Average occupied blocks per requestor
1557system.cpu1.dcache.tags.occ_percent::cpu1.data 0.840791 # Average percentage of cache occupancy
1558system.cpu1.dcache.tags.occ_percent::total 0.840791 # Average percentage of cache occupancy
1559system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
1560system.cpu1.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
1561system.cpu1.dcache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id
1562system.cpu1.dcache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id
1563system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
1564system.cpu1.dcache.tags.tag_accesses 332053228 # Number of tag accesses
1565system.cpu1.dcache.tags.data_accesses 332053228 # Number of data accesses
1566system.cpu1.dcache.ReadReq_hits::cpu1.data 80890555 # number of ReadReq hits
1567system.cpu1.dcache.ReadReq_hits::total 80890555 # number of ReadReq hits
1568system.cpu1.dcache.WriteReq_hits::cpu1.data 71395384 # number of WriteReq hits
1569system.cpu1.dcache.WriteReq_hits::total 71395384 # number of WriteReq hits
1570system.cpu1.dcache.SoftPFReq_hits::cpu1.data 230003 # number of SoftPFReq hits
1571system.cpu1.dcache.SoftPFReq_hits::total 230003 # number of SoftPFReq hits
1572system.cpu1.dcache.WriteLineReq_hits::cpu1.data 70856 # number of WriteLineReq hits
1573system.cpu1.dcache.WriteLineReq_hits::total 70856 # number of WriteLineReq hits
1574system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1784180 # number of LoadLockedReq hits
1575system.cpu1.dcache.LoadLockedReq_hits::total 1784180 # number of LoadLockedReq hits
1576system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762697 # number of StoreCondReq hits
1577system.cpu1.dcache.StoreCondReq_hits::total 1762697 # number of StoreCondReq hits
1578system.cpu1.dcache.demand_hits::cpu1.data 152285939 # number of demand (read+write) hits
1579system.cpu1.dcache.demand_hits::total 152285939 # number of demand (read+write) hits
1580system.cpu1.dcache.overall_hits::cpu1.data 152515942 # number of overall hits
1581system.cpu1.dcache.overall_hits::total 152515942 # number of overall hits
1582system.cpu1.dcache.ReadReq_misses::cpu1.data 3470383 # number of ReadReq misses
1583system.cpu1.dcache.ReadReq_misses::total 3470383 # number of ReadReq misses
1584system.cpu1.dcache.WriteReq_misses::cpu1.data 2256465 # number of WriteReq misses
1585system.cpu1.dcache.WriteReq_misses::total 2256465 # number of WriteReq misses
1586system.cpu1.dcache.SoftPFReq_misses::cpu1.data 629037 # number of SoftPFReq misses
1587system.cpu1.dcache.SoftPFReq_misses::total 629037 # number of SoftPFReq misses
1588system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454847 # number of WriteLineReq misses
1589system.cpu1.dcache.WriteLineReq_misses::total 454847 # number of WriteLineReq misses
1590system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178965 # number of LoadLockedReq misses
1591system.cpu1.dcache.LoadLockedReq_misses::total 178965 # number of LoadLockedReq misses
1592system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198846 # number of StoreCondReq misses
1593system.cpu1.dcache.StoreCondReq_misses::total 198846 # number of StoreCondReq misses
1594system.cpu1.dcache.demand_misses::cpu1.data 5726848 # number of demand (read+write) misses
1595system.cpu1.dcache.demand_misses::total 5726848 # number of demand (read+write) misses
1596system.cpu1.dcache.overall_misses::cpu1.data 6355885 # number of overall misses
1597system.cpu1.dcache.overall_misses::total 6355885 # number of overall misses
1598system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 57691506500 # number of ReadReq miss cycles
1599system.cpu1.dcache.ReadReq_miss_latency::total 57691506500 # number of ReadReq miss cycles
1600system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 50161466000 # number of WriteReq miss cycles
1601system.cpu1.dcache.WriteReq_miss_latency::total 50161466000 # number of WriteReq miss cycles
1602system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17158564500 # number of WriteLineReq miss cycles
1603system.cpu1.dcache.WriteLineReq_miss_latency::total 17158564500 # number of WriteLineReq miss cycles
1604system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2980004000 # number of LoadLockedReq miss cycles
1605system.cpu1.dcache.LoadLockedReq_miss_latency::total 2980004000 # number of LoadLockedReq miss cycles
1606system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5546868500 # number of StoreCondReq miss cycles
1607system.cpu1.dcache.StoreCondReq_miss_latency::total 5546868500 # number of StoreCondReq miss cycles
1608system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5779500 # number of StoreCondFailReq miss cycles
1609system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5779500 # number of StoreCondFailReq miss cycles
1610system.cpu1.dcache.demand_miss_latency::cpu1.data 107852972500 # number of demand (read+write) miss cycles
1611system.cpu1.dcache.demand_miss_latency::total 107852972500 # number of demand (read+write) miss cycles
1612system.cpu1.dcache.overall_miss_latency::cpu1.data 107852972500 # number of overall miss cycles
1613system.cpu1.dcache.overall_miss_latency::total 107852972500 # number of overall miss cycles
1614system.cpu1.dcache.ReadReq_accesses::cpu1.data 84360938 # number of ReadReq accesses(hits+misses)
1615system.cpu1.dcache.ReadReq_accesses::total 84360938 # number of ReadReq accesses(hits+misses)
1616system.cpu1.dcache.WriteReq_accesses::cpu1.data 73651849 # number of WriteReq accesses(hits+misses)
1617system.cpu1.dcache.WriteReq_accesses::total 73651849 # number of WriteReq accesses(hits+misses)
1618system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 859040 # number of SoftPFReq accesses(hits+misses)
1619system.cpu1.dcache.SoftPFReq_accesses::total 859040 # number of SoftPFReq accesses(hits+misses)
1620system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 525703 # number of WriteLineReq accesses(hits+misses)
1621system.cpu1.dcache.WriteLineReq_accesses::total 525703 # number of WriteLineReq accesses(hits+misses)
1622system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1963145 # number of LoadLockedReq accesses(hits+misses)
1623system.cpu1.dcache.LoadLockedReq_accesses::total 1963145 # number of LoadLockedReq accesses(hits+misses)
1624system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1961543 # number of StoreCondReq accesses(hits+misses)
1625system.cpu1.dcache.StoreCondReq_accesses::total 1961543 # number of StoreCondReq accesses(hits+misses)
1626system.cpu1.dcache.demand_accesses::cpu1.data 158012787 # number of demand (read+write) accesses
1627system.cpu1.dcache.demand_accesses::total 158012787 # number of demand (read+write) accesses
1628system.cpu1.dcache.overall_accesses::cpu1.data 158871827 # number of overall (read+write) accesses
1629system.cpu1.dcache.overall_accesses::total 158871827 # number of overall (read+write) accesses
1630system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041137 # miss rate for ReadReq accesses
1631system.cpu1.dcache.ReadReq_miss_rate::total 0.041137 # miss rate for ReadReq accesses
1632system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030637 # miss rate for WriteReq accesses
1633system.cpu1.dcache.WriteReq_miss_rate::total 0.030637 # miss rate for WriteReq accesses
1634system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732256 # miss rate for SoftPFReq accesses
1635system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732256 # miss rate for SoftPFReq accesses
1636system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.865217 # miss rate for WriteLineReq accesses
1637system.cpu1.dcache.WriteLineReq_miss_rate::total 0.865217 # miss rate for WriteLineReq accesses
1638system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091162 # miss rate for LoadLockedReq accesses
1639system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091162 # miss rate for LoadLockedReq accesses
1640system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101372 # miss rate for StoreCondReq accesses
1641system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101372 # miss rate for StoreCondReq accesses
1642system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036243 # miss rate for demand accesses
1643system.cpu1.dcache.demand_miss_rate::total 0.036243 # miss rate for demand accesses
1644system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040006 # miss rate for overall accesses
1645system.cpu1.dcache.overall_miss_rate::total 0.040006 # miss rate for overall accesses
1646system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16623.959517 # average ReadReq miss latency
1647system.cpu1.dcache.ReadReq_avg_miss_latency::total 16623.959517 # average ReadReq miss latency
1648system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22230.110372 # average WriteReq miss latency
1649system.cpu1.dcache.WriteReq_avg_miss_latency::total 22230.110372 # average WriteReq miss latency
1650system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 37723.815921 # average WriteLineReq miss latency
1651system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 37723.815921 # average WriteLineReq miss latency
1652system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16651.322884 # average LoadLockedReq miss latency
1653system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16651.322884 # average LoadLockedReq miss latency
1654system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27895.298372 # average StoreCondReq miss latency
1655system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27895.298372 # average StoreCondReq miss latency
1656system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1657system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1658system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18832.868010 # average overall miss latency
1659system.cpu1.dcache.demand_avg_miss_latency::total 18832.868010 # average overall miss latency
1660system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16968.993696 # average overall miss latency
1661system.cpu1.dcache.overall_avg_miss_latency::total 16968.993696 # average overall miss latency
1662system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1663system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1664system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1665system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1666system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1667system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1668system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1669system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1670system.cpu1.dcache.writebacks::writebacks 5315289 # number of writebacks
1671system.cpu1.dcache.writebacks::total 5315289 # number of writebacks
1672system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 392143 # number of ReadReq MSHR hits
1673system.cpu1.dcache.ReadReq_mshr_hits::total 392143 # number of ReadReq MSHR hits
1674system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 920496 # number of WriteReq MSHR hits
1675system.cpu1.dcache.WriteReq_mshr_hits::total 920496 # number of WriteReq MSHR hits
1676system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 60 # number of WriteLineReq MSHR hits
1677system.cpu1.dcache.WriteLineReq_mshr_hits::total 60 # number of WriteLineReq MSHR hits
1678system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44592 # number of LoadLockedReq MSHR hits
1679system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44592 # number of LoadLockedReq MSHR hits
1680system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 44 # number of StoreCondReq MSHR hits
1681system.cpu1.dcache.StoreCondReq_mshr_hits::total 44 # number of StoreCondReq MSHR hits
1682system.cpu1.dcache.demand_mshr_hits::cpu1.data 1312639 # number of demand (read+write) MSHR hits
1683system.cpu1.dcache.demand_mshr_hits::total 1312639 # number of demand (read+write) MSHR hits
1684system.cpu1.dcache.overall_mshr_hits::cpu1.data 1312639 # number of overall MSHR hits
1685system.cpu1.dcache.overall_mshr_hits::total 1312639 # number of overall MSHR hits
1686system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3078240 # number of ReadReq MSHR misses
1687system.cpu1.dcache.ReadReq_mshr_misses::total 3078240 # number of ReadReq MSHR misses
1688system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335969 # number of WriteReq MSHR misses
1689system.cpu1.dcache.WriteReq_mshr_misses::total 1335969 # number of WriteReq MSHR misses
1690system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628734 # number of SoftPFReq MSHR misses
1691system.cpu1.dcache.SoftPFReq_mshr_misses::total 628734 # number of SoftPFReq MSHR misses
1692system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454787 # number of WriteLineReq MSHR misses
1693system.cpu1.dcache.WriteLineReq_mshr_misses::total 454787 # number of WriteLineReq MSHR misses
1694system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 134373 # number of LoadLockedReq MSHR misses
1695system.cpu1.dcache.LoadLockedReq_mshr_misses::total 134373 # number of LoadLockedReq MSHR misses
1696system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198802 # number of StoreCondReq MSHR misses
1697system.cpu1.dcache.StoreCondReq_mshr_misses::total 198802 # number of StoreCondReq MSHR misses
1698system.cpu1.dcache.demand_mshr_misses::cpu1.data 4414209 # number of demand (read+write) MSHR misses
1699system.cpu1.dcache.demand_mshr_misses::total 4414209 # number of demand (read+write) MSHR misses
1700system.cpu1.dcache.overall_mshr_misses::cpu1.data 5042943 # number of overall MSHR misses
1701system.cpu1.dcache.overall_mshr_misses::total 5042943 # number of overall MSHR misses
1702system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable
1703system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6731 # number of ReadReq MSHR uncacheable
1704system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
1705system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable
1706system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses
1707system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13933 # number of overall MSHR uncacheable misses
1708system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46218671000 # number of ReadReq MSHR miss cycles
1709system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46218671000 # number of ReadReq MSHR miss cycles
1710system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29907223500 # number of WriteReq MSHR miss cycles
1711system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29907223500 # number of WriteReq MSHR miss cycles
1712system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14916352500 # number of SoftPFReq MSHR miss cycles
1713system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14916352500 # number of SoftPFReq MSHR miss cycles
1714system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16698306500 # number of WriteLineReq MSHR miss cycles
1715system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16698306500 # number of WriteLineReq MSHR miss cycles
1716system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1935752000 # number of LoadLockedReq MSHR miss cycles
1717system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1935752000 # number of LoadLockedReq MSHR miss cycles
1718system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344630000 # number of StoreCondReq MSHR miss cycles
1719system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344630000 # number of StoreCondReq MSHR miss cycles
1720system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5479500 # number of StoreCondFailReq MSHR miss cycles
1721system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5479500 # number of StoreCondFailReq MSHR miss cycles
1722system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76125894500 # number of demand (read+write) MSHR miss cycles
1723system.cpu1.dcache.demand_mshr_miss_latency::total 76125894500 # number of demand (read+write) MSHR miss cycles
1724system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91042247000 # number of overall MSHR miss cycles
1725system.cpu1.dcache.overall_mshr_miss_latency::total 91042247000 # number of overall MSHR miss cycles
1726system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 839317500 # number of ReadReq MSHR uncacheable cycles
1727system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 839317500 # number of ReadReq MSHR uncacheable cycles
1728system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1016449500 # number of WriteReq MSHR uncacheable cycles
1729system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1016449500 # number of WriteReq MSHR uncacheable cycles
1730system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1855767000 # number of overall MSHR uncacheable cycles
1731system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1855767000 # number of overall MSHR uncacheable cycles
1732system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036489 # mshr miss rate for ReadReq accesses
1733system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses
1734system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018139 # mshr miss rate for WriteReq accesses
1735system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018139 # mshr miss rate for WriteReq accesses
1736system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.731903 # mshr miss rate for SoftPFReq accesses
1737system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.731903 # mshr miss rate for SoftPFReq accesses
1738system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.865103 # mshr miss rate for WriteLineReq accesses
1739system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.865103 # mshr miss rate for WriteLineReq accesses
1740system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068448 # mshr miss rate for LoadLockedReq accesses
1741system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068448 # mshr miss rate for LoadLockedReq accesses
1742system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101350 # mshr miss rate for StoreCondReq accesses
1743system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101350 # mshr miss rate for StoreCondReq accesses
1744system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027936 # mshr miss rate for demand accesses
1745system.cpu1.dcache.demand_mshr_miss_rate::total 0.027936 # mshr miss rate for demand accesses
1746system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031742 # mshr miss rate for overall accesses
1747system.cpu1.dcache.overall_mshr_miss_rate::total 0.031742 # mshr miss rate for overall accesses
1748system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15014.641808 # average ReadReq mshr miss latency
1749system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15014.641808 # average ReadReq mshr miss latency
1750system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22386.165772 # average WriteReq mshr miss latency
1751system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22386.165772 # average WriteReq mshr miss latency
1752system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23724.424796 # average SoftPFReq mshr miss latency
1753system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23724.424796 # average SoftPFReq mshr miss latency
1754system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 36716.763012 # average WriteLineReq mshr miss latency
1755system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 36716.763012 # average WriteLineReq mshr miss latency
1756system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14405.810691 # average LoadLockedReq mshr miss latency
1757system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14405.810691 # average LoadLockedReq mshr miss latency
1758system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26884.186276 # average StoreCondReq mshr miss latency
1759system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26884.186276 # average StoreCondReq mshr miss latency
1760system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1761system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1762system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17245.647975 # average overall mshr miss latency
1763system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17245.647975 # average overall mshr miss latency
1764system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18053.396003 # average overall mshr miss latency
1765system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18053.396003 # average overall mshr miss latency
1766system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 124694.324766 # average ReadReq mshr uncacheable latency
1767system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 124694.324766 # average ReadReq mshr uncacheable latency
1768system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 141134.337684 # average WriteReq mshr uncacheable latency
1769system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 141134.337684 # average WriteReq mshr uncacheable latency
1770system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 133192.205555 # average overall mshr uncacheable latency
1771system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 133192.205555 # average overall mshr uncacheable latency
1772system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1773system.cpu1.icache.tags.replacements 9419212 # number of replacements
1774system.cpu1.icache.tags.tagsinuse 506.776997 # Cycle average of tags in use
1775system.cpu1.icache.tags.total_refs 231714815 # Total number of references to valid blocks.
1776system.cpu1.icache.tags.sampled_refs 9419724 # Sample count of references to valid blocks.
1777system.cpu1.icache.tags.avg_refs 24.598896 # Average number of references to valid blocks.
1778system.cpu1.icache.tags.warmup_cycle 8379179578000 # Cycle when the warmup percentage was hit.
1779system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.776997 # Average occupied blocks per requestor
1780system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989799 # Average percentage of cache occupancy
1781system.cpu1.icache.tags.occ_percent::total 0.989799 # Average percentage of cache occupancy
1782system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1783system.cpu1.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id
1784system.cpu1.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
1785system.cpu1.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id
1786system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1787system.cpu1.icache.tags.tag_accesses 491688802 # Number of tag accesses
1788system.cpu1.icache.tags.data_accesses 491688802 # Number of data accesses
1789system.cpu1.icache.ReadReq_hits::cpu1.inst 231714815 # number of ReadReq hits
1790system.cpu1.icache.ReadReq_hits::total 231714815 # number of ReadReq hits
1791system.cpu1.icache.demand_hits::cpu1.inst 231714815 # number of demand (read+write) hits
1792system.cpu1.icache.demand_hits::total 231714815 # number of demand (read+write) hits
1793system.cpu1.icache.overall_hits::cpu1.inst 231714815 # number of overall hits
1794system.cpu1.icache.overall_hits::total 231714815 # number of overall hits
1795system.cpu1.icache.ReadReq_misses::cpu1.inst 9419724 # number of ReadReq misses
1796system.cpu1.icache.ReadReq_misses::total 9419724 # number of ReadReq misses
1797system.cpu1.icache.demand_misses::cpu1.inst 9419724 # number of demand (read+write) misses
1798system.cpu1.icache.demand_misses::total 9419724 # number of demand (read+write) misses
1799system.cpu1.icache.overall_misses::cpu1.inst 9419724 # number of overall misses
1800system.cpu1.icache.overall_misses::total 9419724 # number of overall misses
1801system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 96182532500 # number of ReadReq miss cycles
1802system.cpu1.icache.ReadReq_miss_latency::total 96182532500 # number of ReadReq miss cycles
1803system.cpu1.icache.demand_miss_latency::cpu1.inst 96182532500 # number of demand (read+write) miss cycles
1804system.cpu1.icache.demand_miss_latency::total 96182532500 # number of demand (read+write) miss cycles
1805system.cpu1.icache.overall_miss_latency::cpu1.inst 96182532500 # number of overall miss cycles
1806system.cpu1.icache.overall_miss_latency::total 96182532500 # number of overall miss cycles
1807system.cpu1.icache.ReadReq_accesses::cpu1.inst 241134539 # number of ReadReq accesses(hits+misses)
1808system.cpu1.icache.ReadReq_accesses::total 241134539 # number of ReadReq accesses(hits+misses)
1809system.cpu1.icache.demand_accesses::cpu1.inst 241134539 # number of demand (read+write) accesses
1810system.cpu1.icache.demand_accesses::total 241134539 # number of demand (read+write) accesses
1811system.cpu1.icache.overall_accesses::cpu1.inst 241134539 # number of overall (read+write) accesses
1812system.cpu1.icache.overall_accesses::total 241134539 # number of overall (read+write) accesses
1813system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039064 # miss rate for ReadReq accesses
1814system.cpu1.icache.ReadReq_miss_rate::total 0.039064 # miss rate for ReadReq accesses
1815system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039064 # miss rate for demand accesses
1816system.cpu1.icache.demand_miss_rate::total 0.039064 # miss rate for demand accesses
1817system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039064 # miss rate for overall accesses
1818system.cpu1.icache.overall_miss_rate::total 0.039064 # miss rate for overall accesses
1819system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10210.759094 # average ReadReq miss latency
1820system.cpu1.icache.ReadReq_avg_miss_latency::total 10210.759094 # average ReadReq miss latency
1821system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency
1822system.cpu1.icache.demand_avg_miss_latency::total 10210.759094 # average overall miss latency
1823system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10210.759094 # average overall miss latency
1824system.cpu1.icache.overall_avg_miss_latency::total 10210.759094 # average overall miss latency
1825system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1826system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1827system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1828system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1829system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1830system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1831system.cpu1.icache.fast_writes 0 # number of fast writes performed
1832system.cpu1.icache.cache_copies 0 # number of cache copies performed
1833system.cpu1.icache.writebacks::writebacks 9419212 # number of writebacks
1834system.cpu1.icache.writebacks::total 9419212 # number of writebacks
1835system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9419724 # number of ReadReq MSHR misses
1836system.cpu1.icache.ReadReq_mshr_misses::total 9419724 # number of ReadReq MSHR misses
1837system.cpu1.icache.demand_mshr_misses::cpu1.inst 9419724 # number of demand (read+write) MSHR misses
1838system.cpu1.icache.demand_mshr_misses::total 9419724 # number of demand (read+write) MSHR misses
1839system.cpu1.icache.overall_mshr_misses::cpu1.inst 9419724 # number of overall MSHR misses
1840system.cpu1.icache.overall_mshr_misses::total 9419724 # number of overall MSHR misses
1841system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
1842system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable
1843system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
1844system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses
1845system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 91472670500 # number of ReadReq MSHR miss cycles
1846system.cpu1.icache.ReadReq_mshr_miss_latency::total 91472670500 # number of ReadReq MSHR miss cycles
1847system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 91472670500 # number of demand (read+write) MSHR miss cycles
1848system.cpu1.icache.demand_mshr_miss_latency::total 91472670500 # number of demand (read+write) MSHR miss cycles
1849system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 91472670500 # number of overall MSHR miss cycles
1850system.cpu1.icache.overall_mshr_miss_latency::total 91472670500 # number of overall MSHR miss cycles
1851system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13081000 # number of ReadReq MSHR uncacheable cycles
1852system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13081000 # number of ReadReq MSHR uncacheable cycles
1853system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13081000 # number of overall MSHR uncacheable cycles
1854system.cpu1.icache.overall_mshr_uncacheable_latency::total 13081000 # number of overall MSHR uncacheable cycles
1855system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for ReadReq accesses
1856system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039064 # mshr miss rate for ReadReq accesses
1857system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for demand accesses
1858system.cpu1.icache.demand_mshr_miss_rate::total 0.039064 # mshr miss rate for demand accesses
1859system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039064 # mshr miss rate for overall accesses
1860system.cpu1.icache.overall_mshr_miss_rate::total 0.039064 # mshr miss rate for overall accesses
1861system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average ReadReq mshr miss latency
1862system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9710.759094 # average ReadReq mshr miss latency
1863system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
1864system.cpu1.icache.demand_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency
1865system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9710.759094 # average overall mshr miss latency
1866system.cpu1.icache.overall_avg_mshr_miss_latency::total 9710.759094 # average overall mshr miss latency
1867system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average ReadReq mshr uncacheable latency
1868system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140655.913978 # average ReadReq mshr uncacheable latency
1869system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140655.913978 # average overall mshr uncacheable latency
1870system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140655.913978 # average overall mshr uncacheable latency
1871system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1872system.cpu1.l2cache.prefetcher.num_hwpf_issued 7256046 # number of hwpf issued
1873system.cpu1.l2cache.prefetcher.pfIdentified 7256259 # number of prefetch candidates identified
1874system.cpu1.l2cache.prefetcher.pfBufferHit 183 # number of redundant prefetches already in prefetch queue
1875system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1876system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1877system.cpu1.l2cache.prefetcher.pfSpanPage 925773 # number of prefetches not generated due to page crossing
1878system.cpu1.l2cache.tags.replacements 2304751 # number of replacements
1879system.cpu1.l2cache.tags.tagsinuse 13454.881705 # Cycle average of tags in use
1880system.cpu1.l2cache.tags.total_refs 23669466 # Total number of references to valid blocks.
1881system.cpu1.l2cache.tags.sampled_refs 2320587 # Sample count of references to valid blocks.
1882system.cpu1.l2cache.tags.avg_refs 10.199775 # Average number of references to valid blocks.
1883system.cpu1.l2cache.tags.warmup_cycle 9853632359500 # Cycle when the warmup percentage was hit.
1884system.cpu1.l2cache.tags.occ_blocks::writebacks 12618.151234 # Average occupied blocks per requestor
1885system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.761915 # Average occupied blocks per requestor
1886system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 57.964405 # Average occupied blocks per requestor
1887system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 717.004151 # Average occupied blocks per requestor
1888system.cpu1.l2cache.tags.occ_percent::writebacks 0.770151 # Average percentage of cache occupancy
1889system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003770 # Average percentage of cache occupancy
1890system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003538 # Average percentage of cache occupancy
1891system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.043762 # Average percentage of cache occupancy
1892system.cpu1.l2cache.tags.occ_percent::total 0.821221 # Average percentage of cache occupancy
1893system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1043 # Occupied blocks per task id
1894system.cpu1.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id
1895system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14722 # Occupied blocks per task id
1896system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
1897system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 319 # Occupied blocks per task id
1898system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 650 # Occupied blocks per task id
1899system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 71 # Occupied blocks per task id
1900system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
1901system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id
1902system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
1903system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
1904system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
1905system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5507 # Occupied blocks per task id
1906system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8143 # Occupied blocks per task id
1907system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 659 # Occupied blocks per task id
1908system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063660 # Percentage of cache occupancy per task id
1909system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id
1910system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898560 # Percentage of cache occupancy per task id
1911system.cpu1.l2cache.tags.tag_accesses 496871809 # Number of tag accesses
1912system.cpu1.l2cache.tags.data_accesses 496871809 # Number of data accesses
1913system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 551874 # number of ReadReq hits
1914system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166024 # number of ReadReq hits
1915system.cpu1.l2cache.ReadReq_hits::total 717898 # number of ReadReq hits
1916system.cpu1.l2cache.WritebackDirty_hits::writebacks 3295376 # number of WritebackDirty hits
1917system.cpu1.l2cache.WritebackDirty_hits::total 3295376 # number of WritebackDirty hits
1918system.cpu1.l2cache.WritebackClean_hits::writebacks 11437109 # number of WritebackClean hits
1919system.cpu1.l2cache.WritebackClean_hits::total 11437109 # number of WritebackClean hits
1920system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 567 # number of UpgradeReq hits
1921system.cpu1.l2cache.UpgradeReq_hits::total 567 # number of UpgradeReq hits
1922system.cpu1.l2cache.ReadExReq_hits::cpu1.data 865133 # number of ReadExReq hits
1923system.cpu1.l2cache.ReadExReq_hits::total 865133 # number of ReadExReq hits
1924system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8732847 # number of ReadCleanReq hits
1925system.cpu1.l2cache.ReadCleanReq_hits::total 8732847 # number of ReadCleanReq hits
1926system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2873391 # number of ReadSharedReq hits
1927system.cpu1.l2cache.ReadSharedReq_hits::total 2873391 # number of ReadSharedReq hits
1928system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191011 # number of InvalidateReq hits
1929system.cpu1.l2cache.InvalidateReq_hits::total 191011 # number of InvalidateReq hits
1930system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 551874 # number of demand (read+write) hits
1931system.cpu1.l2cache.demand_hits::cpu1.itb.walker 166024 # number of demand (read+write) hits
1932system.cpu1.l2cache.demand_hits::cpu1.inst 8732847 # number of demand (read+write) hits
1933system.cpu1.l2cache.demand_hits::cpu1.data 3738524 # number of demand (read+write) hits
1934system.cpu1.l2cache.demand_hits::total 13189269 # number of demand (read+write) hits
1935system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 551874 # number of overall hits
1936system.cpu1.l2cache.overall_hits::cpu1.itb.walker 166024 # number of overall hits
1937system.cpu1.l2cache.overall_hits::cpu1.inst 8732847 # number of overall hits
1938system.cpu1.l2cache.overall_hits::cpu1.data 3738524 # number of overall hits
1939system.cpu1.l2cache.overall_hits::total 13189269 # number of overall hits
1940system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11967 # number of ReadReq misses
1941system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8433 # number of ReadReq misses
1942system.cpu1.l2cache.ReadReq_misses::total 20400 # number of ReadReq misses
1943system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
1944system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
1945system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 222957 # number of UpgradeReq misses
1946system.cpu1.l2cache.UpgradeReq_misses::total 222957 # number of UpgradeReq misses
1947system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 198797 # number of SCUpgradeReq misses
1948system.cpu1.l2cache.SCUpgradeReq_misses::total 198797 # number of SCUpgradeReq misses
1949system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
1950system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1951system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249481 # number of ReadExReq misses
1952system.cpu1.l2cache.ReadExReq_misses::total 249481 # number of ReadExReq misses
1953system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 686877 # number of ReadCleanReq misses
1954system.cpu1.l2cache.ReadCleanReq_misses::total 686877 # number of ReadCleanReq misses
1955system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 967667 # number of ReadSharedReq misses
1956system.cpu1.l2cache.ReadSharedReq_misses::total 967667 # number of ReadSharedReq misses
1957system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 262059 # number of InvalidateReq misses
1958system.cpu1.l2cache.InvalidateReq_misses::total 262059 # number of InvalidateReq misses
1959system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11967 # number of demand (read+write) misses
1960system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8433 # number of demand (read+write) misses
1961system.cpu1.l2cache.demand_misses::cpu1.inst 686877 # number of demand (read+write) misses
1962system.cpu1.l2cache.demand_misses::cpu1.data 1217148 # number of demand (read+write) misses
1963system.cpu1.l2cache.demand_misses::total 1924425 # number of demand (read+write) misses
1964system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11967 # number of overall misses
1965system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8433 # number of overall misses
1966system.cpu1.l2cache.overall_misses::cpu1.inst 686877 # number of overall misses
1967system.cpu1.l2cache.overall_misses::cpu1.data 1217148 # number of overall misses
1968system.cpu1.l2cache.overall_misses::total 1924425 # number of overall misses
1969system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 548385000 # number of ReadReq miss cycles
1970system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 436726500 # number of ReadReq miss cycles
1971system.cpu1.l2cache.ReadReq_miss_latency::total 985111500 # number of ReadReq miss cycles
1972system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3348912000 # number of UpgradeReq miss cycles
1973system.cpu1.l2cache.UpgradeReq_miss_latency::total 3348912000 # number of UpgradeReq miss cycles
1974system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1915512500 # number of SCUpgradeReq miss cycles
1975system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1915512500 # number of SCUpgradeReq miss cycles
1976system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5381000 # number of SCUpgradeFailReq miss cycles
1977system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5381000 # number of SCUpgradeFailReq miss cycles
1978system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13948272999 # number of ReadExReq miss cycles
1979system.cpu1.l2cache.ReadExReq_miss_latency::total 13948272999 # number of ReadExReq miss cycles
1980system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24574911500 # number of ReadCleanReq miss cycles
1981system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24574911500 # number of ReadCleanReq miss cycles
1982system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38337752989 # number of ReadSharedReq miss cycles
1983system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38337752989 # number of ReadSharedReq miss cycles
1984system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 401272000 # number of InvalidateReq miss cycles
1985system.cpu1.l2cache.InvalidateReq_miss_latency::total 401272000 # number of InvalidateReq miss cycles
1986system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 548385000 # number of demand (read+write) miss cycles
1987system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 436726500 # number of demand (read+write) miss cycles
1988system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24574911500 # number of demand (read+write) miss cycles
1989system.cpu1.l2cache.demand_miss_latency::cpu1.data 52286025988 # number of demand (read+write) miss cycles
1990system.cpu1.l2cache.demand_miss_latency::total 77846048988 # number of demand (read+write) miss cycles
1991system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 548385000 # number of overall miss cycles
1992system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 436726500 # number of overall miss cycles
1993system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24574911500 # number of overall miss cycles
1994system.cpu1.l2cache.overall_miss_latency::cpu1.data 52286025988 # number of overall miss cycles
1995system.cpu1.l2cache.overall_miss_latency::total 77846048988 # number of overall miss cycles
1996system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 563841 # number of ReadReq accesses(hits+misses)
1997system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174457 # number of ReadReq accesses(hits+misses)
1998system.cpu1.l2cache.ReadReq_accesses::total 738298 # number of ReadReq accesses(hits+misses)
1999system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3295377 # number of WritebackDirty accesses(hits+misses)
2000system.cpu1.l2cache.WritebackDirty_accesses::total 3295377 # number of WritebackDirty accesses(hits+misses)
2001system.cpu1.l2cache.WritebackClean_accesses::writebacks 11437109 # number of WritebackClean accesses(hits+misses)
2002system.cpu1.l2cache.WritebackClean_accesses::total 11437109 # number of WritebackClean accesses(hits+misses)
2003system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 223524 # number of UpgradeReq accesses(hits+misses)
2004system.cpu1.l2cache.UpgradeReq_accesses::total 223524 # number of UpgradeReq accesses(hits+misses)
2005system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198797 # number of SCUpgradeReq accesses(hits+misses)
2006system.cpu1.l2cache.SCUpgradeReq_accesses::total 198797 # number of SCUpgradeReq accesses(hits+misses)
2007system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
2008system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
2009system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1114614 # number of ReadExReq accesses(hits+misses)
2010system.cpu1.l2cache.ReadExReq_accesses::total 1114614 # number of ReadExReq accesses(hits+misses)
2011system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 9419724 # number of ReadCleanReq accesses(hits+misses)
2012system.cpu1.l2cache.ReadCleanReq_accesses::total 9419724 # number of ReadCleanReq accesses(hits+misses)
2013system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3841058 # number of ReadSharedReq accesses(hits+misses)
2014system.cpu1.l2cache.ReadSharedReq_accesses::total 3841058 # number of ReadSharedReq accesses(hits+misses)
2015system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 453070 # number of InvalidateReq accesses(hits+misses)
2016system.cpu1.l2cache.InvalidateReq_accesses::total 453070 # number of InvalidateReq accesses(hits+misses)
2017system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 563841 # number of demand (read+write) accesses
2018system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174457 # number of demand (read+write) accesses
2019system.cpu1.l2cache.demand_accesses::cpu1.inst 9419724 # number of demand (read+write) accesses
2020system.cpu1.l2cache.demand_accesses::cpu1.data 4955672 # number of demand (read+write) accesses
2021system.cpu1.l2cache.demand_accesses::total 15113694 # number of demand (read+write) accesses
2022system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 563841 # number of overall (read+write) accesses
2023system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174457 # number of overall (read+write) accesses
2024system.cpu1.l2cache.overall_accesses::cpu1.inst 9419724 # number of overall (read+write) accesses
2025system.cpu1.l2cache.overall_accesses::cpu1.data 4955672 # number of overall (read+write) accesses
2026system.cpu1.l2cache.overall_accesses::total 15113694 # number of overall (read+write) accesses
2027system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for ReadReq accesses
2028system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048339 # miss rate for ReadReq accesses
2029system.cpu1.l2cache.ReadReq_miss_rate::total 0.027631 # miss rate for ReadReq accesses
2030system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
2031system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
2032system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997463 # miss rate for UpgradeReq accesses
2033system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997463 # miss rate for UpgradeReq accesses
2034system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2035system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2036system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2037system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2038system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.223827 # miss rate for ReadExReq accesses
2039system.cpu1.l2cache.ReadExReq_miss_rate::total 0.223827 # miss rate for ReadExReq accesses
2040system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.072919 # miss rate for ReadCleanReq accesses
2041system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.072919 # miss rate for ReadCleanReq accesses
2042system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.251927 # miss rate for ReadSharedReq accesses
2043system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.251927 # miss rate for ReadSharedReq accesses
2044system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.578407 # miss rate for InvalidateReq accesses
2045system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.578407 # miss rate for InvalidateReq accesses
2046system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for demand accesses
2047system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048339 # miss rate for demand accesses
2048system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.072919 # miss rate for demand accesses
2049system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245607 # miss rate for demand accesses
2050system.cpu1.l2cache.demand_miss_rate::total 0.127330 # miss rate for demand accesses
2051system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021224 # miss rate for overall accesses
2052system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048339 # miss rate for overall accesses
2053system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.072919 # miss rate for overall accesses
2054system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245607 # miss rate for overall accesses
2055system.cpu1.l2cache.overall_miss_rate::total 0.127330 # miss rate for overall accesses
2056system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average ReadReq miss latency
2057system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 51787.797937 # average ReadReq miss latency
2058system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48289.779412 # average ReadReq miss latency
2059system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15020.438919 # average UpgradeReq miss latency
2060system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15020.438919 # average UpgradeReq miss latency
2061system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9635.520154 # average SCUpgradeReq miss latency
2062system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9635.520154 # average SCUpgradeReq miss latency
2063system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1076200 # average SCUpgradeFailReq miss latency
2064system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1076200 # average SCUpgradeFailReq miss latency
2065system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 55909.159411 # average ReadExReq miss latency
2066system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 55909.159411 # average ReadExReq miss latency
2067system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35777.746962 # average ReadCleanReq miss latency
2068system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35777.746962 # average ReadCleanReq miss latency
2069system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39618.745900 # average ReadSharedReq miss latency
2070system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39618.745900 # average ReadSharedReq miss latency
2071system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1531.227701 # average InvalidateReq miss latency
2072system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1531.227701 # average InvalidateReq miss latency
2073system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average overall miss latency
2074system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 51787.797937 # average overall miss latency
2075system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35777.746962 # average overall miss latency
2076system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42957.821060 # average overall miss latency
2077system.cpu1.l2cache.demand_avg_miss_latency::total 40451.588910 # average overall miss latency
2078system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 45824.768112 # average overall miss latency
2079system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 51787.797937 # average overall miss latency
2080system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35777.746962 # average overall miss latency
2081system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42957.821060 # average overall miss latency
2082system.cpu1.l2cache.overall_avg_miss_latency::total 40451.588910 # average overall miss latency
2083system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2084system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2085system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2086system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2087system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2088system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2089system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2090system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2091system.cpu1.l2cache.writebacks::writebacks 1133493 # number of writebacks
2092system.cpu1.l2cache.writebacks::total 1133493 # number of writebacks
2093system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits
2094system.cpu1.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
2095system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6803 # number of ReadExReq MSHR hits
2096system.cpu1.l2cache.ReadExReq_mshr_hits::total 6803 # number of ReadExReq MSHR hits
2097system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
2098system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2099system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 882 # number of ReadSharedReq MSHR hits
2100system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 882 # number of ReadSharedReq MSHR hits
2101system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
2102system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
2103system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits
2104system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2105system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7685 # number of demand (read+write) MSHR hits
2106system.cpu1.l2cache.demand_mshr_hits::total 7687 # number of demand (read+write) MSHR hits
2107system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits
2108system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2109system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7685 # number of overall MSHR hits
2110system.cpu1.l2cache.overall_mshr_hits::total 7687 # number of overall MSHR hits
2111system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11967 # number of ReadReq MSHR misses
2112system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8432 # number of ReadReq MSHR misses
2113system.cpu1.l2cache.ReadReq_mshr_misses::total 20399 # number of ReadReq MSHR misses
2114system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
2115system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
2116system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 726483 # number of HardPFReq MSHR misses
2117system.cpu1.l2cache.HardPFReq_mshr_misses::total 726483 # number of HardPFReq MSHR misses
2118system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 222957 # number of UpgradeReq MSHR misses
2119system.cpu1.l2cache.UpgradeReq_mshr_misses::total 222957 # number of UpgradeReq MSHR misses
2120system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 198797 # number of SCUpgradeReq MSHR misses
2121system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 198797 # number of SCUpgradeReq MSHR misses
2122system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
2123system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
2124system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 242678 # number of ReadExReq MSHR misses
2125system.cpu1.l2cache.ReadExReq_mshr_misses::total 242678 # number of ReadExReq MSHR misses
2126system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 686876 # number of ReadCleanReq MSHR misses
2127system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 686876 # number of ReadCleanReq MSHR misses
2128system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966785 # number of ReadSharedReq MSHR misses
2129system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966785 # number of ReadSharedReq MSHR misses
2130system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 262056 # number of InvalidateReq MSHR misses
2131system.cpu1.l2cache.InvalidateReq_mshr_misses::total 262056 # number of InvalidateReq MSHR misses
2132system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11967 # number of demand (read+write) MSHR misses
2133system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8432 # number of demand (read+write) MSHR misses
2134system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 686876 # number of demand (read+write) MSHR misses
2135system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1209463 # number of demand (read+write) MSHR misses
2136system.cpu1.l2cache.demand_mshr_misses::total 1916738 # number of demand (read+write) MSHR misses
2137system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11967 # number of overall MSHR misses
2138system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8432 # number of overall MSHR misses
2139system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 686876 # number of overall MSHR misses
2140system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1209463 # number of overall MSHR misses
2141system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 726483 # number of overall MSHR misses
2142system.cpu1.l2cache.overall_mshr_misses::total 2643221 # number of overall MSHR misses
2143system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
2144system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6731 # number of ReadReq MSHR uncacheable
2145system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6824 # number of ReadReq MSHR uncacheable
2146system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
2147system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7202 # number of WriteReq MSHR uncacheable
2148system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
2149system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13933 # number of overall MSHR uncacheable misses
2150system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14026 # number of overall MSHR uncacheable misses
2151system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of ReadReq MSHR miss cycles
2152system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 386118000 # number of ReadReq MSHR miss cycles
2153system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 862701000 # number of ReadReq MSHR miss cycles
2154system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38725078481 # number of HardPFReq MSHR miss cycles
2155system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38725078481 # number of HardPFReq MSHR miss cycles
2156system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7000085492 # number of UpgradeReq MSHR miss cycles
2157system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7000085492 # number of UpgradeReq MSHR miss cycles
2158system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3849189999 # number of SCUpgradeReq MSHR miss cycles
2159system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3849189999 # number of SCUpgradeReq MSHR miss cycles
2160system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4991000 # number of SCUpgradeFailReq MSHR miss cycles
2161system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4991000 # number of SCUpgradeFailReq MSHR miss cycles
2162system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11472999499 # number of ReadExReq MSHR miss cycles
2163system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11472999499 # number of ReadExReq MSHR miss cycles
2164system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20453639500 # number of ReadCleanReq MSHR miss cycles
2165system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20453639500 # number of ReadCleanReq MSHR miss cycles
2166system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 32473658989 # number of ReadSharedReq MSHR miss cycles
2167system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 32473658989 # number of ReadSharedReq MSHR miss cycles
2168system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13075073000 # number of InvalidateReq MSHR miss cycles
2169system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13075073000 # number of InvalidateReq MSHR miss cycles
2170system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of demand (read+write) MSHR miss cycles
2171system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 386118000 # number of demand (read+write) MSHR miss cycles
2172system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20453639500 # number of demand (read+write) MSHR miss cycles
2173system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43946658488 # number of demand (read+write) MSHR miss cycles
2174system.cpu1.l2cache.demand_mshr_miss_latency::total 65262998988 # number of demand (read+write) MSHR miss cycles
2175system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 476583000 # number of overall MSHR miss cycles
2176system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 386118000 # number of overall MSHR miss cycles
2177system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20453639500 # number of overall MSHR miss cycles
2178system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43946658488 # number of overall MSHR miss cycles
2179system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38725078481 # number of overall MSHR miss cycles
2180system.cpu1.l2cache.overall_mshr_miss_latency::total 103988077469 # number of overall MSHR miss cycles
2181system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12337000 # number of ReadReq MSHR uncacheable cycles
2182system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 785396000 # number of ReadReq MSHR uncacheable cycles
2183system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 797733000 # number of ReadReq MSHR uncacheable cycles
2184system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 962364500 # number of WriteReq MSHR uncacheable cycles
2185system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 962364500 # number of WriteReq MSHR uncacheable cycles
2186system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12337000 # number of overall MSHR uncacheable cycles
2187system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1747760500 # number of overall MSHR uncacheable cycles
2188system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1760097500 # number of overall MSHR uncacheable cycles
2189system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for ReadReq accesses
2190system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for ReadReq accesses
2191system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027630 # mshr miss rate for ReadReq accesses
2192system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
2193system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
2194system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2195system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2196system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997463 # mshr miss rate for UpgradeReq accesses
2197system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997463 # mshr miss rate for UpgradeReq accesses
2198system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2199system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2200system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2201system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2202system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217724 # mshr miss rate for ReadExReq accesses
2203system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217724 # mshr miss rate for ReadExReq accesses
2204system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for ReadCleanReq accesses
2205system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.072919 # mshr miss rate for ReadCleanReq accesses
2206system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251698 # mshr miss rate for ReadSharedReq accesses
2207system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251698 # mshr miss rate for ReadSharedReq accesses
2208system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.578401 # mshr miss rate for InvalidateReq accesses
2209system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.578401 # mshr miss rate for InvalidateReq accesses
2210system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for demand accesses
2211system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for demand accesses
2212system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for demand accesses
2213system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for demand accesses
2214system.cpu1.l2cache.demand_mshr_miss_rate::total 0.126821 # mshr miss rate for demand accesses
2215system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021224 # mshr miss rate for overall accesses
2216system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048333 # mshr miss rate for overall accesses
2217system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.072919 # mshr miss rate for overall accesses
2218system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.244056 # mshr miss rate for overall accesses
2219system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2220system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174889 # mshr miss rate for overall accesses
2221system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average ReadReq mshr miss latency
2222system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average ReadReq mshr miss latency
2223system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42291.337811 # average ReadReq mshr miss latency
2224system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average HardPFReq mshr miss latency
2225system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53304.865332 # average HardPFReq mshr miss latency
2226system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31396.571949 # average UpgradeReq mshr miss latency
2227system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31396.571949 # average UpgradeReq mshr miss latency
2228system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19362.414921 # average SCUpgradeReq mshr miss latency
2229system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19362.414921 # average SCUpgradeReq mshr miss latency
2230system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 998200 # average SCUpgradeFailReq mshr miss latency
2231system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 998200 # average SCUpgradeFailReq mshr miss latency
2232system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47276.636115 # average ReadExReq mshr miss latency
2233system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47276.636115 # average ReadExReq mshr miss latency
2234system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average ReadCleanReq mshr miss latency
2235system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29777.775756 # average ReadCleanReq mshr miss latency
2236system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33589.328536 # average ReadSharedReq mshr miss latency
2237system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33589.328536 # average ReadSharedReq mshr miss latency
2238system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 49894.194371 # average InvalidateReq mshr miss latency
2239system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 49894.194371 # average InvalidateReq mshr miss latency
2240system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency
2241system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency
2242system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency
2243system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency
2244system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34048.993127 # average overall mshr miss latency
2245system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 39824.768112 # average overall mshr miss latency
2246system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 45791.982922 # average overall mshr miss latency
2247system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29777.775756 # average overall mshr miss latency
2248system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36335.678304 # average overall mshr miss latency
2249system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53304.865332 # average overall mshr miss latency
2250system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39341.423766 # average overall mshr miss latency
2251system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average ReadReq mshr uncacheable latency
2252system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116683.405140 # average ReadReq mshr uncacheable latency
2253system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116901.084408 # average ReadReq mshr uncacheable latency
2254system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133624.618162 # average WriteReq mshr uncacheable latency
2255system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 133624.618162 # average WriteReq mshr uncacheable latency
2256system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132655.913978 # average overall mshr uncacheable latency
2257system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 125440.357425 # average overall mshr uncacheable latency
2258system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 125488.200485 # average overall mshr uncacheable latency
2259system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2260system.cpu1.toL2Bus.snoop_filter.tot_requests 30305906 # Total number of requests made to the snoop filter.
2261system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15477606 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2262system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2263system.cpu1.toL2Bus.snoop_filter.tot_snoops 2090955 # Total number of snoops made to the snoop filter.
2264system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2090626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2265system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 329 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2266system.cpu1.toL2Bus.trans_dist::ReadReq 826390 # Transaction distribution
2267system.cpu1.toL2Bus.trans_dist::ReadResp 14176907 # Transaction distribution
2268system.cpu1.toL2Bus.trans_dist::WriteReq 7202 # Transaction distribution
2269system.cpu1.toL2Bus.trans_dist::WriteResp 7202 # Transaction distribution
2270system.cpu1.toL2Bus.trans_dist::WritebackDirty 4434109 # Transaction distribution
2271system.cpu1.toL2Bus.trans_dist::WritebackClean 11439122 # Transaction distribution
2272system.cpu1.toL2Bus.trans_dist::CleanEvict 2886028 # Transaction distribution
2273system.cpu1.toL2Bus.trans_dist::HardPFReq 940232 # Transaction distribution
2274system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
2275system.cpu1.toL2Bus.trans_dist::UpgradeReq 438079 # Transaction distribution
2276system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353355 # Transaction distribution
2277system.cpu1.toL2Bus.trans_dist::UpgradeResp 486110 # Transaction distribution
2278system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
2279system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
2280system.cpu1.toL2Bus.trans_dist::ReadExReq 1143505 # Transaction distribution
2281system.cpu1.toL2Bus.trans_dist::ReadExResp 1120857 # Transaction distribution
2282system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9419724 # Transaction distribution
2283system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4894979 # Transaction distribution
2284system.cpu1.toL2Bus.trans_dist::InvalidateReq 500608 # Transaction distribution
2285system.cpu1.toL2Bus.trans_dist::InvalidateResp 453070 # Transaction distribution
2286system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 28258846 # Packet count per connected master and slave (bytes)
2287system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17165188 # Packet count per connected master and slave (bytes)
2288system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 367696 # Packet count per connected master and slave (bytes)
2289system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1190168 # Packet count per connected master and slave (bytes)
2290system.cpu1.toL2Bus.pkt_count::total 46981898 # Packet count per connected master and slave (bytes)
2291system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1205697856 # Cumulative packet size per connected master and slave (bytes)
2292system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 663528133 # Cumulative packet size per connected master and slave (bytes)
2293system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395656 # Cumulative packet size per connected master and slave (bytes)
2294system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4510728 # Cumulative packet size per connected master and slave (bytes)
2295system.cpu1.toL2Bus.pkt_size::total 1875132373 # Cumulative packet size per connected master and slave (bytes)
2296system.cpu1.toL2Bus.snoops 6705692 # Total snoops (count)
2297system.cpu1.toL2Bus.snoop_fanout::samples 22548909 # Request fanout histogram
2298system.cpu1.toL2Bus.snoop_fanout::mean 0.107052 # Request fanout histogram
2299system.cpu1.toL2Bus.snoop_fanout::stdev 0.309227 # Request fanout histogram
2300system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2301system.cpu1.toL2Bus.snoop_fanout::0 20135326 89.30% 89.30% # Request fanout histogram
2302system.cpu1.toL2Bus.snoop_fanout::1 2413254 10.70% 100.00% # Request fanout histogram
2303system.cpu1.toL2Bus.snoop_fanout::2 329 0.00% 100.00% # Request fanout histogram
2304system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2305system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2306system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2307system.cpu1.toL2Bus.snoop_fanout::total 22548909 # Request fanout histogram
2308system.cpu1.toL2Bus.reqLayer0.occupancy 30147553476 # Layer occupancy (ticks)
2309system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2310system.cpu1.toL2Bus.snoopLayer0.occupancy 176219861 # Layer occupancy (ticks)
2311system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2312system.cpu1.toL2Bus.respLayer0.occupancy 14133264904 # Layer occupancy (ticks)
2313system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2314system.cpu1.toL2Bus.respLayer1.occupancy 7885730738 # Layer occupancy (ticks)
2315system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2316system.cpu1.toL2Bus.respLayer2.occupancy 193298381 # Layer occupancy (ticks)
2317system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2318system.cpu1.toL2Bus.respLayer3.occupancy 626482687 # Layer occupancy (ticks)
2319system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2320system.iobus.trans_dist::ReadReq 40387 # Transaction distribution
2321system.iobus.trans_dist::ReadResp 40387 # Transaction distribution
2322system.iobus.trans_dist::WriteReq 136979 # Transaction distribution
2323system.iobus.trans_dist::WriteResp 136979 # Transaction distribution
2324system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47868 # Packet count per connected master and slave (bytes)
2325system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2326system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2327system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2328system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2329system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2330system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2331system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2332system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2333system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2334system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2335system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
2336system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2337system.iobus.pkt_count_system.bridge.master::total 122958 # Packet count per connected master and slave (bytes)
2338system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231694 # Packet count per connected master and slave (bytes)
2339system.iobus.pkt_count_system.realview.ide.dma::total 231694 # Packet count per connected master and slave (bytes)
2340system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2341system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2342system.iobus.pkt_count::total 354732 # Packet count per connected master and slave (bytes)
2343system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47888 # Cumulative packet size per connected master and slave (bytes)
2344system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2345system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2346system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2347system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2348system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2349system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2350system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2351system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2352system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2353system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2354system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
2355system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2356system.iobus.pkt_size_system.bridge.master::total 155996 # Cumulative packet size per connected master and slave (bytes)
2357system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355128 # Cumulative packet size per connected master and slave (bytes)
2358system.iobus.pkt_size_system.realview.ide.dma::total 7355128 # Cumulative packet size per connected master and slave (bytes)
2359system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2360system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2361system.iobus.pkt_size::total 7513210 # Cumulative packet size per connected master and slave (bytes)
2362system.iobus.reqLayer0.occupancy 47188500 # Layer occupancy (ticks)
2363system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2364system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
2365system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2366system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks)
2367system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2368system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
2369system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2370system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks)
2371system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2372system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
2373system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2374system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
2375system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2376system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks)
2377system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2378system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
2379system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2380system.iobus.reqLayer16.occupancy 15000 # Layer occupancy (ticks)
2381system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2382system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks)
2383system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2384system.iobus.reqLayer23.occupancy 26264003 # Layer occupancy (ticks)
2385system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2386system.iobus.reqLayer24.occupancy 36399000 # Layer occupancy (ticks)
2387system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2388system.iobus.reqLayer25.occupancy 568799211 # Layer occupancy (ticks)
2389system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2390system.iobus.respLayer0.occupancy 92966000 # Layer occupancy (ticks)
2391system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2392system.iobus.respLayer3.occupancy 148134000 # Layer occupancy (ticks)
2393system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2394system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
2395system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2396system.iocache.tags.replacements 115828 # number of replacements
2397system.iocache.tags.tagsinuse 11.305227 # Cycle average of tags in use
2398system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2399system.iocache.tags.sampled_refs 115844 # Sample count of references to valid blocks.
2400system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2401system.iocache.tags.warmup_cycle 9138950806000 # Cycle when the warmup percentage was hit.
2402system.iocache.tags.occ_blocks::realview.ethernet 3.834041 # Average occupied blocks per requestor
2403system.iocache.tags.occ_blocks::realview.ide 7.471186 # Average occupied blocks per requestor
2404system.iocache.tags.occ_percent::realview.ethernet 0.239628 # Average percentage of cache occupancy
2405system.iocache.tags.occ_percent::realview.ide 0.466949 # Average percentage of cache occupancy
2406system.iocache.tags.occ_percent::total 0.706577 # Average percentage of cache occupancy
2407system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2408system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2409system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2410system.iocache.tags.tag_accesses 1042980 # Number of tag accesses
2411system.iocache.tags.data_accesses 1042980 # Number of data accesses
2412system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2413system.iocache.ReadReq_misses::realview.ide 8863 # number of ReadReq misses
2414system.iocache.ReadReq_misses::total 8900 # number of ReadReq misses
2415system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2416system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2417system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses
2418system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses
2419system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2420system.iocache.demand_misses::realview.ide 8863 # number of demand (read+write) misses
2421system.iocache.demand_misses::total 8903 # number of demand (read+write) misses
2422system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2423system.iocache.overall_misses::realview.ide 8863 # number of overall misses
2424system.iocache.overall_misses::total 8903 # number of overall misses
2425system.iocache.ReadReq_miss_latency::realview.ethernet 5197000 # number of ReadReq miss cycles
2426system.iocache.ReadReq_miss_latency::realview.ide 1710789963 # number of ReadReq miss cycles
2427system.iocache.ReadReq_miss_latency::total 1715986963 # number of ReadReq miss cycles
2428system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2429system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2430system.iocache.WriteLineReq_miss_latency::realview.ide 13562248248 # number of WriteLineReq miss cycles
2431system.iocache.WriteLineReq_miss_latency::total 13562248248 # number of WriteLineReq miss cycles
2432system.iocache.demand_miss_latency::realview.ethernet 5566000 # number of demand (read+write) miss cycles
2433system.iocache.demand_miss_latency::realview.ide 1710789963 # number of demand (read+write) miss cycles
2434system.iocache.demand_miss_latency::total 1716355963 # number of demand (read+write) miss cycles
2435system.iocache.overall_miss_latency::realview.ethernet 5566000 # number of overall miss cycles
2436system.iocache.overall_miss_latency::realview.ide 1710789963 # number of overall miss cycles
2437system.iocache.overall_miss_latency::total 1716355963 # number of overall miss cycles
2438system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2439system.iocache.ReadReq_accesses::realview.ide 8863 # number of ReadReq accesses(hits+misses)
2440system.iocache.ReadReq_accesses::total 8900 # number of ReadReq accesses(hits+misses)
2441system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2442system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2443system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses)
2444system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses)
2445system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2446system.iocache.demand_accesses::realview.ide 8863 # number of demand (read+write) accesses
2447system.iocache.demand_accesses::total 8903 # number of demand (read+write) accesses
2448system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2449system.iocache.overall_accesses::realview.ide 8863 # number of overall (read+write) accesses
2450system.iocache.overall_accesses::total 8903 # number of overall (read+write) accesses
2451system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2452system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2453system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2454system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2455system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2456system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2457system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2458system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2459system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2460system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2461system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2462system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2463system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2464system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140459.459459 # average ReadReq miss latency
2465system.iocache.ReadReq_avg_miss_latency::realview.ide 193026.059235 # average ReadReq miss latency
2466system.iocache.ReadReq_avg_miss_latency::total 192807.523933 # average ReadReq miss latency
2467system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2468system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2469system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.939729 # average WriteLineReq miss latency
2470system.iocache.WriteLineReq_avg_miss_latency::total 126768.939729 # average WriteLineReq miss latency
2471system.iocache.demand_avg_miss_latency::realview.ethernet 139150 # average overall miss latency
2472system.iocache.demand_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency
2473system.iocache.demand_avg_miss_latency::total 192784.001236 # average overall miss latency
2474system.iocache.overall_avg_miss_latency::realview.ethernet 139150 # average overall miss latency
2475system.iocache.overall_avg_miss_latency::realview.ide 193026.059235 # average overall miss latency
2476system.iocache.overall_avg_miss_latency::total 192784.001236 # average overall miss latency
2477system.iocache.blocked_cycles::no_mshrs 35587 # number of cycles access was blocked
2478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2479system.iocache.blocked::no_mshrs 3530 # number of cycles access was blocked
2480system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2481system.iocache.avg_blocked_cycles::no_mshrs 10.081303 # average number of cycles each access was blocked
2482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2483system.iocache.fast_writes 0 # number of fast writes performed
2484system.iocache.cache_copies 0 # number of cache copies performed
2485system.iocache.writebacks::writebacks 106950 # number of writebacks
2486system.iocache.writebacks::total 106950 # number of writebacks
2487system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2488system.iocache.ReadReq_mshr_misses::realview.ide 8863 # number of ReadReq MSHR misses
2489system.iocache.ReadReq_mshr_misses::total 8900 # number of ReadReq MSHR misses
2490system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2491system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2492system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses
2493system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses
2494system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2495system.iocache.demand_mshr_misses::realview.ide 8863 # number of demand (read+write) MSHR misses
2496system.iocache.demand_mshr_misses::total 8903 # number of demand (read+write) MSHR misses
2497system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2498system.iocache.overall_mshr_misses::realview.ide 8863 # number of overall MSHR misses
2499system.iocache.overall_mshr_misses::total 8903 # number of overall MSHR misses
2500system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3347000 # number of ReadReq MSHR miss cycles
2501system.iocache.ReadReq_mshr_miss_latency::realview.ide 1267639963 # number of ReadReq MSHR miss cycles
2502system.iocache.ReadReq_mshr_miss_latency::total 1270986963 # number of ReadReq MSHR miss cycles
2503system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
2504system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
2505system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8206832286 # number of WriteLineReq MSHR miss cycles
2506system.iocache.WriteLineReq_mshr_miss_latency::total 8206832286 # number of WriteLineReq MSHR miss cycles
2507system.iocache.demand_mshr_miss_latency::realview.ethernet 3566000 # number of demand (read+write) MSHR miss cycles
2508system.iocache.demand_mshr_miss_latency::realview.ide 1267639963 # number of demand (read+write) MSHR miss cycles
2509system.iocache.demand_mshr_miss_latency::total 1271205963 # number of demand (read+write) MSHR miss cycles
2510system.iocache.overall_mshr_miss_latency::realview.ethernet 3566000 # number of overall MSHR miss cycles
2511system.iocache.overall_mshr_miss_latency::realview.ide 1267639963 # number of overall MSHR miss cycles
2512system.iocache.overall_mshr_miss_latency::total 1271205963 # number of overall MSHR miss cycles
2513system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2514system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2515system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2516system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2517system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2518system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2519system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2520system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2521system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2522system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2523system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2524system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2525system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2526system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90459.459459 # average ReadReq mshr miss latency
2527system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143026.059235 # average ReadReq mshr miss latency
2528system.iocache.ReadReq_avg_mshr_miss_latency::total 142807.523933 # average ReadReq mshr miss latency
2529system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
2530system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
2531system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76710.837938 # average WriteLineReq mshr miss latency
2532system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76710.837938 # average WriteLineReq mshr miss latency
2533system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency
2534system.iocache.demand_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency
2535system.iocache.demand_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency
2536system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89150 # average overall mshr miss latency
2537system.iocache.overall_avg_mshr_miss_latency::realview.ide 143026.059235 # average overall mshr miss latency
2538system.iocache.overall_avg_mshr_miss_latency::total 142784.001236 # average overall mshr miss latency
2539system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2540system.l2c.tags.replacements 1399797 # number of replacements
2541system.l2c.tags.tagsinuse 63464.709741 # Cycle average of tags in use
2542system.l2c.tags.total_refs 6644913 # Total number of references to valid blocks.
2543system.l2c.tags.sampled_refs 1460922 # Sample count of references to valid blocks.
2544system.l2c.tags.avg_refs 4.548438 # Average number of references to valid blocks.
2545system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit.
2546system.l2c.tags.occ_blocks::writebacks 21707.053985 # Average occupied blocks per requestor
2547system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.735345 # Average occupied blocks per requestor
2548system.l2c.tags.occ_blocks::cpu0.itb.walker 115.995716 # Average occupied blocks per requestor
2549system.l2c.tags.occ_blocks::cpu0.inst 4966.190479 # Average occupied blocks per requestor
2550system.l2c.tags.occ_blocks::cpu0.data 4993.948919 # Average occupied blocks per requestor
2551system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 6019.423287 # Average occupied blocks per requestor
2552system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.036337 # Average occupied blocks per requestor
2553system.l2c.tags.occ_blocks::cpu1.itb.walker 317.216521 # Average occupied blocks per requestor
2554system.l2c.tags.occ_blocks::cpu1.inst 3872.812023 # Average occupied blocks per requestor
2555system.l2c.tags.occ_blocks::cpu1.data 8822.287754 # Average occupied blocks per requestor
2556system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12306.009376 # Average occupied blocks per requestor
2557system.l2c.tags.occ_percent::writebacks 0.331223 # Average percentage of cache occupancy
2558system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001568 # Average percentage of cache occupancy
2559system.l2c.tags.occ_percent::cpu0.itb.walker 0.001770 # Average percentage of cache occupancy
2560system.l2c.tags.occ_percent::cpu0.inst 0.075778 # Average percentage of cache occupancy
2561system.l2c.tags.occ_percent::cpu0.data 0.076202 # Average percentage of cache occupancy
2562system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.091849 # Average percentage of cache occupancy
2563system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003678 # Average percentage of cache occupancy
2564system.l2c.tags.occ_percent::cpu1.itb.walker 0.004840 # Average percentage of cache occupancy
2565system.l2c.tags.occ_percent::cpu1.inst 0.059094 # Average percentage of cache occupancy
2566system.l2c.tags.occ_percent::cpu1.data 0.134617 # Average percentage of cache occupancy
2567system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.187775 # Average percentage of cache occupancy
2568system.l2c.tags.occ_percent::total 0.968395 # Average percentage of cache occupancy
2569system.l2c.tags.occ_task_id_blocks::1022 10216 # Occupied blocks per task id
2570system.l2c.tags.occ_task_id_blocks::1023 187 # Occupied blocks per task id
2571system.l2c.tags.occ_task_id_blocks::1024 50722 # Occupied blocks per task id
2572system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
2573system.l2c.tags.age_task_id_blocks_1022::2 140 # Occupied blocks per task id
2574system.l2c.tags.age_task_id_blocks_1022::3 3377 # Occupied blocks per task id
2575system.l2c.tags.age_task_id_blocks_1022::4 6697 # Occupied blocks per task id
2576system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
2577system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
2578system.l2c.tags.age_task_id_blocks_1023::4 176 # Occupied blocks per task id
2579system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
2580system.l2c.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id
2581system.l2c.tags.age_task_id_blocks_1024::2 2228 # Occupied blocks per task id
2582system.l2c.tags.age_task_id_blocks_1024::3 13666 # Occupied blocks per task id
2583system.l2c.tags.age_task_id_blocks_1024::4 34520 # Occupied blocks per task id
2584system.l2c.tags.occ_task_id_percent::1022 0.155884 # Percentage of cache occupancy per task id
2585system.l2c.tags.occ_task_id_percent::1023 0.002853 # Percentage of cache occupancy per task id
2586system.l2c.tags.occ_task_id_percent::1024 0.773956 # Percentage of cache occupancy per task id
2587system.l2c.tags.tag_accesses 81151228 # Number of tag accesses
2588system.l2c.tags.data_accesses 81151228 # Number of data accesses
2589system.l2c.WritebackDirty_hits::writebacks 2809703 # number of WritebackDirty hits
2590system.l2c.WritebackDirty_hits::total 2809703 # number of WritebackDirty hits
2591system.l2c.UpgradeReq_hits::cpu0.data 181902 # number of UpgradeReq hits
2592system.l2c.UpgradeReq_hits::cpu1.data 125777 # number of UpgradeReq hits
2593system.l2c.UpgradeReq_hits::total 307679 # number of UpgradeReq hits
2594system.l2c.SCUpgradeReq_hits::cpu0.data 42034 # number of SCUpgradeReq hits
2595system.l2c.SCUpgradeReq_hits::cpu1.data 42908 # number of SCUpgradeReq hits
2596system.l2c.SCUpgradeReq_hits::total 84942 # number of SCUpgradeReq hits
2597system.l2c.ReadExReq_hits::cpu0.data 62506 # number of ReadExReq hits
2598system.l2c.ReadExReq_hits::cpu1.data 50661 # number of ReadExReq hits
2599system.l2c.ReadExReq_hits::total 113167 # number of ReadExReq hits
2600system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7522 # number of ReadSharedReq hits
2601system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5409 # number of ReadSharedReq hits
2602system.l2c.ReadSharedReq_hits::cpu0.inst 680705 # number of ReadSharedReq hits
2603system.l2c.ReadSharedReq_hits::cpu0.data 645150 # number of ReadSharedReq hits
2604system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 332678 # number of ReadSharedReq hits
2605system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6067 # number of ReadSharedReq hits
2606system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4079 # number of ReadSharedReq hits
2607system.l2c.ReadSharedReq_hits::cpu1.inst 638595 # number of ReadSharedReq hits
2608system.l2c.ReadSharedReq_hits::cpu1.data 567372 # number of ReadSharedReq hits
2609system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 305148 # number of ReadSharedReq hits
2610system.l2c.ReadSharedReq_hits::total 3192725 # number of ReadSharedReq hits
2611system.l2c.InvalidateReq_hits::cpu0.data 139615 # number of InvalidateReq hits
2612system.l2c.InvalidateReq_hits::cpu1.data 131240 # number of InvalidateReq hits
2613system.l2c.InvalidateReq_hits::total 270855 # number of InvalidateReq hits
2614system.l2c.demand_hits::cpu0.dtb.walker 7522 # number of demand (read+write) hits
2615system.l2c.demand_hits::cpu0.itb.walker 5409 # number of demand (read+write) hits
2616system.l2c.demand_hits::cpu0.inst 680705 # number of demand (read+write) hits
2617system.l2c.demand_hits::cpu0.data 707656 # number of demand (read+write) hits
2618system.l2c.demand_hits::cpu0.l2cache.prefetcher 332678 # number of demand (read+write) hits
2619system.l2c.demand_hits::cpu1.dtb.walker 6067 # number of demand (read+write) hits
2620system.l2c.demand_hits::cpu1.itb.walker 4079 # number of demand (read+write) hits
2621system.l2c.demand_hits::cpu1.inst 638595 # number of demand (read+write) hits
2622system.l2c.demand_hits::cpu1.data 618033 # number of demand (read+write) hits
2623system.l2c.demand_hits::cpu1.l2cache.prefetcher 305148 # number of demand (read+write) hits
2624system.l2c.demand_hits::total 3305892 # number of demand (read+write) hits
2625system.l2c.overall_hits::cpu0.dtb.walker 7522 # number of overall hits
2626system.l2c.overall_hits::cpu0.itb.walker 5409 # number of overall hits
2627system.l2c.overall_hits::cpu0.inst 680705 # number of overall hits
2628system.l2c.overall_hits::cpu0.data 707656 # number of overall hits
2629system.l2c.overall_hits::cpu0.l2cache.prefetcher 332678 # number of overall hits
2630system.l2c.overall_hits::cpu1.dtb.walker 6067 # number of overall hits
2631system.l2c.overall_hits::cpu1.itb.walker 4079 # number of overall hits
2632system.l2c.overall_hits::cpu1.inst 638595 # number of overall hits
2633system.l2c.overall_hits::cpu1.data 618033 # number of overall hits
2634system.l2c.overall_hits::cpu1.l2cache.prefetcher 305148 # number of overall hits
2635system.l2c.overall_hits::total 3305892 # number of overall hits
2636system.l2c.UpgradeReq_misses::cpu0.data 64206 # number of UpgradeReq misses
2637system.l2c.UpgradeReq_misses::cpu1.data 62132 # number of UpgradeReq misses
2638system.l2c.UpgradeReq_misses::total 126338 # number of UpgradeReq misses
2639system.l2c.SCUpgradeReq_misses::cpu0.data 12168 # number of SCUpgradeReq misses
2640system.l2c.SCUpgradeReq_misses::cpu1.data 12142 # number of SCUpgradeReq misses
2641system.l2c.SCUpgradeReq_misses::total 24310 # number of SCUpgradeReq misses
2642system.l2c.ReadExReq_misses::cpu0.data 79720 # number of ReadExReq misses
2643system.l2c.ReadExReq_misses::cpu1.data 52688 # number of ReadExReq misses
2644system.l2c.ReadExReq_misses::total 132408 # number of ReadExReq misses
2645system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1937 # number of ReadSharedReq misses
2646system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1561 # number of ReadSharedReq misses
2647system.l2c.ReadSharedReq_misses::cpu0.inst 72587 # number of ReadSharedReq misses
2648system.l2c.ReadSharedReq_misses::cpu0.data 131602 # number of ReadSharedReq misses
2649system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 238730 # number of ReadSharedReq misses
2650system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2112 # number of ReadSharedReq misses
2651system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1907 # number of ReadSharedReq misses
2652system.l2c.ReadSharedReq_misses::cpu1.inst 48281 # number of ReadSharedReq misses
2653system.l2c.ReadSharedReq_misses::cpu1.data 118892 # number of ReadSharedReq misses
2654system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 199183 # number of ReadSharedReq misses
2655system.l2c.ReadSharedReq_misses::total 816792 # number of ReadSharedReq misses
2656system.l2c.InvalidateReq_misses::cpu0.data 443932 # number of InvalidateReq misses
2657system.l2c.InvalidateReq_misses::cpu1.data 119113 # number of InvalidateReq misses
2658system.l2c.InvalidateReq_misses::total 563045 # number of InvalidateReq misses
2659system.l2c.demand_misses::cpu0.dtb.walker 1937 # number of demand (read+write) misses
2660system.l2c.demand_misses::cpu0.itb.walker 1561 # number of demand (read+write) misses
2661system.l2c.demand_misses::cpu0.inst 72587 # number of demand (read+write) misses
2662system.l2c.demand_misses::cpu0.data 211322 # number of demand (read+write) misses
2663system.l2c.demand_misses::cpu0.l2cache.prefetcher 238730 # number of demand (read+write) misses
2664system.l2c.demand_misses::cpu1.dtb.walker 2112 # number of demand (read+write) misses
2665system.l2c.demand_misses::cpu1.itb.walker 1907 # number of demand (read+write) misses
2666system.l2c.demand_misses::cpu1.inst 48281 # number of demand (read+write) misses
2667system.l2c.demand_misses::cpu1.data 171580 # number of demand (read+write) misses
2668system.l2c.demand_misses::cpu1.l2cache.prefetcher 199183 # number of demand (read+write) misses
2669system.l2c.demand_misses::total 949200 # number of demand (read+write) misses
2670system.l2c.overall_misses::cpu0.dtb.walker 1937 # number of overall misses
2671system.l2c.overall_misses::cpu0.itb.walker 1561 # number of overall misses
2672system.l2c.overall_misses::cpu0.inst 72587 # number of overall misses
2673system.l2c.overall_misses::cpu0.data 211322 # number of overall misses
2674system.l2c.overall_misses::cpu0.l2cache.prefetcher 238730 # number of overall misses
2675system.l2c.overall_misses::cpu1.dtb.walker 2112 # number of overall misses
2676system.l2c.overall_misses::cpu1.itb.walker 1907 # number of overall misses
2677system.l2c.overall_misses::cpu1.inst 48281 # number of overall misses
2678system.l2c.overall_misses::cpu1.data 171580 # number of overall misses
2679system.l2c.overall_misses::cpu1.l2cache.prefetcher 199183 # number of overall misses
2680system.l2c.overall_misses::total 949200 # number of overall misses
2681system.l2c.UpgradeReq_miss_latency::cpu0.data 1150609000 # number of UpgradeReq miss cycles
2682system.l2c.UpgradeReq_miss_latency::cpu1.data 1077871000 # number of UpgradeReq miss cycles
2683system.l2c.UpgradeReq_miss_latency::total 2228480000 # number of UpgradeReq miss cycles
2684system.l2c.SCUpgradeReq_miss_latency::cpu0.data 192622500 # number of SCUpgradeReq miss cycles
2685system.l2c.SCUpgradeReq_miss_latency::cpu1.data 197330500 # number of SCUpgradeReq miss cycles
2686system.l2c.SCUpgradeReq_miss_latency::total 389953000 # number of SCUpgradeReq miss cycles
2687system.l2c.ReadExReq_miss_latency::cpu0.data 11022660500 # number of ReadExReq miss cycles
2688system.l2c.ReadExReq_miss_latency::cpu1.data 7093820500 # number of ReadExReq miss cycles
2689system.l2c.ReadExReq_miss_latency::total 18116481000 # number of ReadExReq miss cycles
2690system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 272199000 # number of ReadSharedReq miss cycles
2691system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 220485500 # number of ReadSharedReq miss cycles
2692system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9769762500 # number of ReadSharedReq miss cycles
2693system.l2c.ReadSharedReq_miss_latency::cpu0.data 18492608500 # number of ReadSharedReq miss cycles
2694system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of ReadSharedReq miss cycles
2695system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 294211000 # number of ReadSharedReq miss cycles
2696system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 267576500 # number of ReadSharedReq miss cycles
2697system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6491475500 # number of ReadSharedReq miss cycles
2698system.l2c.ReadSharedReq_miss_latency::cpu1.data 16608783999 # number of ReadSharedReq miss cycles
2699system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of ReadSharedReq miss cycles
2700system.l2c.ReadSharedReq_miss_latency::total 127469272889 # number of ReadSharedReq miss cycles
2701system.l2c.InvalidateReq_miss_latency::cpu0.data 140111000 # number of InvalidateReq miss cycles
2702system.l2c.InvalidateReq_miss_latency::cpu1.data 126265000 # number of InvalidateReq miss cycles
2703system.l2c.InvalidateReq_miss_latency::total 266376000 # number of InvalidateReq miss cycles
2704system.l2c.demand_miss_latency::cpu0.dtb.walker 272199000 # number of demand (read+write) miss cycles
2705system.l2c.demand_miss_latency::cpu0.itb.walker 220485500 # number of demand (read+write) miss cycles
2706system.l2c.demand_miss_latency::cpu0.inst 9769762500 # number of demand (read+write) miss cycles
2707system.l2c.demand_miss_latency::cpu0.data 29515269000 # number of demand (read+write) miss cycles
2708system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of demand (read+write) miss cycles
2709system.l2c.demand_miss_latency::cpu1.dtb.walker 294211000 # number of demand (read+write) miss cycles
2710system.l2c.demand_miss_latency::cpu1.itb.walker 267576500 # number of demand (read+write) miss cycles
2711system.l2c.demand_miss_latency::cpu1.inst 6491475500 # number of demand (read+write) miss cycles
2712system.l2c.demand_miss_latency::cpu1.data 23702604499 # number of demand (read+write) miss cycles
2713system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of demand (read+write) miss cycles
2714system.l2c.demand_miss_latency::total 145585753889 # number of demand (read+write) miss cycles
2715system.l2c.overall_miss_latency::cpu0.dtb.walker 272199000 # number of overall miss cycles
2716system.l2c.overall_miss_latency::cpu0.itb.walker 220485500 # number of overall miss cycles
2717system.l2c.overall_miss_latency::cpu0.inst 9769762500 # number of overall miss cycles
2718system.l2c.overall_miss_latency::cpu0.data 29515269000 # number of overall miss cycles
2719system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 41827968898 # number of overall miss cycles
2720system.l2c.overall_miss_latency::cpu1.dtb.walker 294211000 # number of overall miss cycles
2721system.l2c.overall_miss_latency::cpu1.itb.walker 267576500 # number of overall miss cycles
2722system.l2c.overall_miss_latency::cpu1.inst 6491475500 # number of overall miss cycles
2723system.l2c.overall_miss_latency::cpu1.data 23702604499 # number of overall miss cycles
2724system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33224201492 # number of overall miss cycles
2725system.l2c.overall_miss_latency::total 145585753889 # number of overall miss cycles
2726system.l2c.WritebackDirty_accesses::writebacks 2809703 # number of WritebackDirty accesses(hits+misses)
2727system.l2c.WritebackDirty_accesses::total 2809703 # number of WritebackDirty accesses(hits+misses)
2728system.l2c.UpgradeReq_accesses::cpu0.data 246108 # number of UpgradeReq accesses(hits+misses)
2729system.l2c.UpgradeReq_accesses::cpu1.data 187909 # number of UpgradeReq accesses(hits+misses)
2730system.l2c.UpgradeReq_accesses::total 434017 # number of UpgradeReq accesses(hits+misses)
2731system.l2c.SCUpgradeReq_accesses::cpu0.data 54202 # number of SCUpgradeReq accesses(hits+misses)
2732system.l2c.SCUpgradeReq_accesses::cpu1.data 55050 # number of SCUpgradeReq accesses(hits+misses)
2733system.l2c.SCUpgradeReq_accesses::total 109252 # number of SCUpgradeReq accesses(hits+misses)
2734system.l2c.ReadExReq_accesses::cpu0.data 142226 # number of ReadExReq accesses(hits+misses)
2735system.l2c.ReadExReq_accesses::cpu1.data 103349 # number of ReadExReq accesses(hits+misses)
2736system.l2c.ReadExReq_accesses::total 245575 # number of ReadExReq accesses(hits+misses)
2737system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9459 # number of ReadSharedReq accesses(hits+misses)
2738system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6970 # number of ReadSharedReq accesses(hits+misses)
2739system.l2c.ReadSharedReq_accesses::cpu0.inst 753292 # number of ReadSharedReq accesses(hits+misses)
2740system.l2c.ReadSharedReq_accesses::cpu0.data 776752 # number of ReadSharedReq accesses(hits+misses)
2741system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 571408 # number of ReadSharedReq accesses(hits+misses)
2742system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8179 # number of ReadSharedReq accesses(hits+misses)
2743system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5986 # number of ReadSharedReq accesses(hits+misses)
2744system.l2c.ReadSharedReq_accesses::cpu1.inst 686876 # number of ReadSharedReq accesses(hits+misses)
2745system.l2c.ReadSharedReq_accesses::cpu1.data 686264 # number of ReadSharedReq accesses(hits+misses)
2746system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 504331 # number of ReadSharedReq accesses(hits+misses)
2747system.l2c.ReadSharedReq_accesses::total 4009517 # number of ReadSharedReq accesses(hits+misses)
2748system.l2c.InvalidateReq_accesses::cpu0.data 583547 # number of InvalidateReq accesses(hits+misses)
2749system.l2c.InvalidateReq_accesses::cpu1.data 250353 # number of InvalidateReq accesses(hits+misses)
2750system.l2c.InvalidateReq_accesses::total 833900 # number of InvalidateReq accesses(hits+misses)
2751system.l2c.demand_accesses::cpu0.dtb.walker 9459 # number of demand (read+write) accesses
2752system.l2c.demand_accesses::cpu0.itb.walker 6970 # number of demand (read+write) accesses
2753system.l2c.demand_accesses::cpu0.inst 753292 # number of demand (read+write) accesses
2754system.l2c.demand_accesses::cpu0.data 918978 # number of demand (read+write) accesses
2755system.l2c.demand_accesses::cpu0.l2cache.prefetcher 571408 # number of demand (read+write) accesses
2756system.l2c.demand_accesses::cpu1.dtb.walker 8179 # number of demand (read+write) accesses
2757system.l2c.demand_accesses::cpu1.itb.walker 5986 # number of demand (read+write) accesses
2758system.l2c.demand_accesses::cpu1.inst 686876 # number of demand (read+write) accesses
2759system.l2c.demand_accesses::cpu1.data 789613 # number of demand (read+write) accesses
2760system.l2c.demand_accesses::cpu1.l2cache.prefetcher 504331 # number of demand (read+write) accesses
2761system.l2c.demand_accesses::total 4255092 # number of demand (read+write) accesses
2762system.l2c.overall_accesses::cpu0.dtb.walker 9459 # number of overall (read+write) accesses
2763system.l2c.overall_accesses::cpu0.itb.walker 6970 # number of overall (read+write) accesses
2764system.l2c.overall_accesses::cpu0.inst 753292 # number of overall (read+write) accesses
2765system.l2c.overall_accesses::cpu0.data 918978 # number of overall (read+write) accesses
2766system.l2c.overall_accesses::cpu0.l2cache.prefetcher 571408 # number of overall (read+write) accesses
2767system.l2c.overall_accesses::cpu1.dtb.walker 8179 # number of overall (read+write) accesses
2768system.l2c.overall_accesses::cpu1.itb.walker 5986 # number of overall (read+write) accesses
2769system.l2c.overall_accesses::cpu1.inst 686876 # number of overall (read+write) accesses
2770system.l2c.overall_accesses::cpu1.data 789613 # number of overall (read+write) accesses
2771system.l2c.overall_accesses::cpu1.l2cache.prefetcher 504331 # number of overall (read+write) accesses
2772system.l2c.overall_accesses::total 4255092 # number of overall (read+write) accesses
2773system.l2c.UpgradeReq_miss_rate::cpu0.data 0.260885 # miss rate for UpgradeReq accesses
2774system.l2c.UpgradeReq_miss_rate::cpu1.data 0.330649 # miss rate for UpgradeReq accesses
2775system.l2c.UpgradeReq_miss_rate::total 0.291090 # miss rate for UpgradeReq accesses
2776system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.224494 # miss rate for SCUpgradeReq accesses
2777system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.220563 # miss rate for SCUpgradeReq accesses
2778system.l2c.SCUpgradeReq_miss_rate::total 0.222513 # miss rate for SCUpgradeReq accesses
2779system.l2c.ReadExReq_miss_rate::cpu0.data 0.560516 # miss rate for ReadExReq accesses
2780system.l2c.ReadExReq_miss_rate::cpu1.data 0.509807 # miss rate for ReadExReq accesses
2781system.l2c.ReadExReq_miss_rate::total 0.539175 # miss rate for ReadExReq accesses
2782system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for ReadSharedReq accesses
2783system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.223960 # miss rate for ReadSharedReq accesses
2784system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.096360 # miss rate for ReadSharedReq accesses
2785system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.169426 # miss rate for ReadSharedReq accesses
2786system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for ReadSharedReq accesses
2787system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for ReadSharedReq accesses
2788system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.318577 # miss rate for ReadSharedReq accesses
2789system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070291 # miss rate for ReadSharedReq accesses
2790system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.173245 # miss rate for ReadSharedReq accesses
2791system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for ReadSharedReq accesses
2792system.l2c.ReadSharedReq_miss_rate::total 0.203713 # miss rate for ReadSharedReq accesses
2793system.l2c.InvalidateReq_miss_rate::cpu0.data 0.760748 # miss rate for InvalidateReq accesses
2794system.l2c.InvalidateReq_miss_rate::cpu1.data 0.475780 # miss rate for InvalidateReq accesses
2795system.l2c.InvalidateReq_miss_rate::total 0.675195 # miss rate for InvalidateReq accesses
2796system.l2c.demand_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for demand accesses
2797system.l2c.demand_miss_rate::cpu0.itb.walker 0.223960 # miss rate for demand accesses
2798system.l2c.demand_miss_rate::cpu0.inst 0.096360 # miss rate for demand accesses
2799system.l2c.demand_miss_rate::cpu0.data 0.229953 # miss rate for demand accesses
2800system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for demand accesses
2801system.l2c.demand_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for demand accesses
2802system.l2c.demand_miss_rate::cpu1.itb.walker 0.318577 # miss rate for demand accesses
2803system.l2c.demand_miss_rate::cpu1.inst 0.070291 # miss rate for demand accesses
2804system.l2c.demand_miss_rate::cpu1.data 0.217296 # miss rate for demand accesses
2805system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for demand accesses
2806system.l2c.demand_miss_rate::total 0.223074 # miss rate for demand accesses
2807system.l2c.overall_miss_rate::cpu0.dtb.walker 0.204779 # miss rate for overall accesses
2808system.l2c.overall_miss_rate::cpu0.itb.walker 0.223960 # miss rate for overall accesses
2809system.l2c.overall_miss_rate::cpu0.inst 0.096360 # miss rate for overall accesses
2810system.l2c.overall_miss_rate::cpu0.data 0.229953 # miss rate for overall accesses
2811system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.417793 # miss rate for overall accesses
2812system.l2c.overall_miss_rate::cpu1.dtb.walker 0.258222 # miss rate for overall accesses
2813system.l2c.overall_miss_rate::cpu1.itb.walker 0.318577 # miss rate for overall accesses
2814system.l2c.overall_miss_rate::cpu1.inst 0.070291 # miss rate for overall accesses
2815system.l2c.overall_miss_rate::cpu1.data 0.217296 # miss rate for overall accesses
2816system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.394945 # miss rate for overall accesses
2817system.l2c.overall_miss_rate::total 0.223074 # miss rate for overall accesses
2818system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17920.583746 # average UpgradeReq miss latency
2819system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17348.081504 # average UpgradeReq miss latency
2820system.l2c.UpgradeReq_avg_miss_latency::total 17639.031804 # average UpgradeReq miss latency
2821system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15830.251479 # average SCUpgradeReq miss latency
2822system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 16251.894251 # average SCUpgradeReq miss latency
2823system.l2c.SCUpgradeReq_avg_miss_latency::total 16040.847388 # average SCUpgradeReq miss latency
2824system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138267.191420 # average ReadExReq miss latency
2825system.l2c.ReadExReq_avg_miss_latency::cpu1.data 134638.257288 # average ReadExReq miss latency
2826system.l2c.ReadExReq_avg_miss_latency::total 136823.160232 # average ReadExReq miss latency
2827system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average ReadSharedReq miss latency
2828system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141246.316464 # average ReadSharedReq miss latency
2829system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134593.832229 # average ReadSharedReq miss latency
2830system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140519.205635 # average ReadSharedReq miss latency
2831system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average ReadSharedReq miss latency
2832system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average ReadSharedReq miss latency
2833system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140312.794966 # average ReadSharedReq miss latency
2834system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134451.968683 # average ReadSharedReq miss latency
2835system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139696.396721 # average ReadSharedReq miss latency
2836system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average ReadSharedReq miss latency
2837system.l2c.ReadSharedReq_avg_miss_latency::total 156060.873379 # average ReadSharedReq miss latency
2838system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 315.613653 # average InvalidateReq miss latency
2839system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1060.043824 # average InvalidateReq miss latency
2840system.l2c.InvalidateReq_avg_miss_latency::total 473.098953 # average InvalidateReq miss latency
2841system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average overall miss latency
2842system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141246.316464 # average overall miss latency
2843system.l2c.demand_avg_miss_latency::cpu0.inst 134593.832229 # average overall miss latency
2844system.l2c.demand_avg_miss_latency::cpu0.data 139669.646322 # average overall miss latency
2845system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average overall miss latency
2846system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average overall miss latency
2847system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140312.794966 # average overall miss latency
2848system.l2c.demand_avg_miss_latency::cpu1.inst 134451.968683 # average overall miss latency
2849system.l2c.demand_avg_miss_latency::cpu1.data 138143.166447 # average overall miss latency
2850system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average overall miss latency
2851system.l2c.demand_avg_miss_latency::total 153377.321838 # average overall miss latency
2852system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140526.071244 # average overall miss latency
2853system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141246.316464 # average overall miss latency
2854system.l2c.overall_avg_miss_latency::cpu0.inst 134593.832229 # average overall miss latency
2855system.l2c.overall_avg_miss_latency::cpu0.data 139669.646322 # average overall miss latency
2856system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 175210.358556 # average overall miss latency
2857system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139304.450758 # average overall miss latency
2858system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140312.794966 # average overall miss latency
2859system.l2c.overall_avg_miss_latency::cpu1.inst 134451.968683 # average overall miss latency
2860system.l2c.overall_avg_miss_latency::cpu1.data 138143.166447 # average overall miss latency
2861system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 166802.395245 # average overall miss latency
2862system.l2c.overall_avg_miss_latency::total 153377.321838 # average overall miss latency
2863system.l2c.blocked_cycles::no_mshrs 1015 # number of cycles access was blocked
2864system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2865system.l2c.blocked::no_mshrs 9 # number of cycles access was blocked
2866system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2867system.l2c.avg_blocked_cycles::no_mshrs 112.777778 # average number of cycles each access was blocked
2868system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2869system.l2c.fast_writes 0 # number of fast writes performed
2870system.l2c.cache_copies 0 # number of cache copies performed
2871system.l2c.writebacks::writebacks 1090140 # number of writebacks
2872system.l2c.writebacks::total 1090140 # number of writebacks
2873system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 179 # number of ReadSharedReq MSHR hits
2874system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits
2875system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 207 # number of ReadSharedReq MSHR hits
2876system.l2c.ReadSharedReq_mshr_hits::cpu1.data 18 # number of ReadSharedReq MSHR hits
2877system.l2c.ReadSharedReq_mshr_hits::total 427 # number of ReadSharedReq MSHR hits
2878system.l2c.demand_mshr_hits::cpu0.inst 179 # number of demand (read+write) MSHR hits
2879system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits
2880system.l2c.demand_mshr_hits::cpu1.inst 207 # number of demand (read+write) MSHR hits
2881system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits
2882system.l2c.demand_mshr_hits::total 427 # number of demand (read+write) MSHR hits
2883system.l2c.overall_mshr_hits::cpu0.inst 179 # number of overall MSHR hits
2884system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits
2885system.l2c.overall_mshr_hits::cpu1.inst 207 # number of overall MSHR hits
2886system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits
2887system.l2c.overall_mshr_hits::total 427 # number of overall MSHR hits
2888system.l2c.CleanEvict_mshr_misses::writebacks 54511 # number of CleanEvict MSHR misses
2889system.l2c.CleanEvict_mshr_misses::total 54511 # number of CleanEvict MSHR misses
2890system.l2c.UpgradeReq_mshr_misses::cpu0.data 64206 # number of UpgradeReq MSHR misses
2891system.l2c.UpgradeReq_mshr_misses::cpu1.data 62132 # number of UpgradeReq MSHR misses
2892system.l2c.UpgradeReq_mshr_misses::total 126338 # number of UpgradeReq MSHR misses
2893system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12168 # number of SCUpgradeReq MSHR misses
2894system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12142 # number of SCUpgradeReq MSHR misses
2895system.l2c.SCUpgradeReq_mshr_misses::total 24310 # number of SCUpgradeReq MSHR misses
2896system.l2c.ReadExReq_mshr_misses::cpu0.data 79720 # number of ReadExReq MSHR misses
2897system.l2c.ReadExReq_mshr_misses::cpu1.data 52688 # number of ReadExReq MSHR misses
2898system.l2c.ReadExReq_mshr_misses::total 132408 # number of ReadExReq MSHR misses
2899system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1937 # number of ReadSharedReq MSHR misses
2900system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1561 # number of ReadSharedReq MSHR misses
2901system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 72408 # number of ReadSharedReq MSHR misses
2902system.l2c.ReadSharedReq_mshr_misses::cpu0.data 131579 # number of ReadSharedReq MSHR misses
2903system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of ReadSharedReq MSHR misses
2904system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2112 # number of ReadSharedReq MSHR misses
2905system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1907 # number of ReadSharedReq MSHR misses
2906system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 48074 # number of ReadSharedReq MSHR misses
2907system.l2c.ReadSharedReq_mshr_misses::cpu1.data 118874 # number of ReadSharedReq MSHR misses
2908system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of ReadSharedReq MSHR misses
2909system.l2c.ReadSharedReq_mshr_misses::total 816365 # number of ReadSharedReq MSHR misses
2910system.l2c.InvalidateReq_mshr_misses::cpu0.data 443932 # number of InvalidateReq MSHR misses
2911system.l2c.InvalidateReq_mshr_misses::cpu1.data 119113 # number of InvalidateReq MSHR misses
2912system.l2c.InvalidateReq_mshr_misses::total 563045 # number of InvalidateReq MSHR misses
2913system.l2c.demand_mshr_misses::cpu0.dtb.walker 1937 # number of demand (read+write) MSHR misses
2914system.l2c.demand_mshr_misses::cpu0.itb.walker 1561 # number of demand (read+write) MSHR misses
2915system.l2c.demand_mshr_misses::cpu0.inst 72408 # number of demand (read+write) MSHR misses
2916system.l2c.demand_mshr_misses::cpu0.data 211299 # number of demand (read+write) MSHR misses
2917system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of demand (read+write) MSHR misses
2918system.l2c.demand_mshr_misses::cpu1.dtb.walker 2112 # number of demand (read+write) MSHR misses
2919system.l2c.demand_mshr_misses::cpu1.itb.walker 1907 # number of demand (read+write) MSHR misses
2920system.l2c.demand_mshr_misses::cpu1.inst 48074 # number of demand (read+write) MSHR misses
2921system.l2c.demand_mshr_misses::cpu1.data 171562 # number of demand (read+write) MSHR misses
2922system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of demand (read+write) MSHR misses
2923system.l2c.demand_mshr_misses::total 948773 # number of demand (read+write) MSHR misses
2924system.l2c.overall_mshr_misses::cpu0.dtb.walker 1937 # number of overall MSHR misses
2925system.l2c.overall_mshr_misses::cpu0.itb.walker 1561 # number of overall MSHR misses
2926system.l2c.overall_mshr_misses::cpu0.inst 72408 # number of overall MSHR misses
2927system.l2c.overall_mshr_misses::cpu0.data 211299 # number of overall MSHR misses
2928system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 238730 # number of overall MSHR misses
2929system.l2c.overall_mshr_misses::cpu1.dtb.walker 2112 # number of overall MSHR misses
2930system.l2c.overall_mshr_misses::cpu1.itb.walker 1907 # number of overall MSHR misses
2931system.l2c.overall_mshr_misses::cpu1.inst 48074 # number of overall MSHR misses
2932system.l2c.overall_mshr_misses::cpu1.data 171562 # number of overall MSHR misses
2933system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 199183 # number of overall MSHR misses
2934system.l2c.overall_mshr_misses::total 948773 # number of overall MSHR misses
2935system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable
2936system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32143 # number of ReadReq MSHR uncacheable
2937system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable
2938system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6729 # number of ReadReq MSHR uncacheable
2939system.l2c.ReadReq_mshr_uncacheable::total 91274 # number of ReadReq MSHR uncacheable
2940system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31553 # number of WriteReq MSHR uncacheable
2941system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7202 # number of WriteReq MSHR uncacheable
2942system.l2c.WriteReq_mshr_uncacheable::total 38755 # number of WriteReq MSHR uncacheable
2943system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses
2944system.l2c.overall_mshr_uncacheable_misses::cpu0.data 63696 # number of overall MSHR uncacheable misses
2945system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses
2946system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13931 # number of overall MSHR uncacheable misses
2947system.l2c.overall_mshr_uncacheable_misses::total 130029 # number of overall MSHR uncacheable misses
2948system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4544765997 # number of UpgradeReq MSHR miss cycles
2949system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4377476492 # number of UpgradeReq MSHR miss cycles
2950system.l2c.UpgradeReq_mshr_miss_latency::total 8922242489 # number of UpgradeReq MSHR miss cycles
2951system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 896994500 # number of SCUpgradeReq MSHR miss cycles
2952system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 892131500 # number of SCUpgradeReq MSHR miss cycles
2953system.l2c.SCUpgradeReq_mshr_miss_latency::total 1789126000 # number of SCUpgradeReq MSHR miss cycles
2954system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10225195953 # number of ReadExReq MSHR miss cycles
2955system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6566674837 # number of ReadExReq MSHR miss cycles
2956system.l2c.ReadExReq_mshr_miss_latency::total 16791870790 # number of ReadExReq MSHR miss cycles
2957system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of ReadSharedReq MSHR miss cycles
2958system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 204866519 # number of ReadSharedReq MSHR miss cycles
2959system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9025630028 # number of ReadSharedReq MSHR miss cycles
2960system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17172972916 # number of ReadSharedReq MSHR miss cycles
2961system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of ReadSharedReq MSHR miss cycles
2962system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of ReadSharedReq MSHR miss cycles
2963system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 248503510 # number of ReadSharedReq MSHR miss cycles
2964system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5986913295 # number of ReadSharedReq MSHR miss cycles
2965system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 15417511413 # number of ReadSharedReq MSHR miss cycles
2966system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of ReadSharedReq MSHR miss cycles
2967system.l2c.ReadSharedReq_mshr_miss_latency::total 119251773144 # number of ReadSharedReq MSHR miss cycles
2968system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 31065864000 # number of InvalidateReq MSHR miss cycles
2969system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 8291731997 # number of InvalidateReq MSHR miss cycles
2970system.l2c.InvalidateReq_mshr_miss_latency::total 39357595997 # number of InvalidateReq MSHR miss cycles
2971system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of demand (read+write) MSHR miss cycles
2972system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 204866519 # number of demand (read+write) MSHR miss cycles
2973system.l2c.demand_mshr_miss_latency::cpu0.inst 9025630028 # number of demand (read+write) MSHR miss cycles
2974system.l2c.demand_mshr_miss_latency::cpu0.data 27398168869 # number of demand (read+write) MSHR miss cycles
2975system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of demand (read+write) MSHR miss cycles
2976system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of demand (read+write) MSHR miss cycles
2977system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 248503510 # number of demand (read+write) MSHR miss cycles
2978system.l2c.demand_mshr_miss_latency::cpu1.inst 5986913295 # number of demand (read+write) MSHR miss cycles
2979system.l2c.demand_mshr_miss_latency::cpu1.data 21984186250 # number of demand (read+write) MSHR miss cycles
2980system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of demand (read+write) MSHR miss cycles
2981system.l2c.demand_mshr_miss_latency::total 136043643934 # number of demand (read+write) MSHR miss cycles
2982system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 252817523 # number of overall MSHR miss cycles
2983system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 204866519 # number of overall MSHR miss cycles
2984system.l2c.overall_mshr_miss_latency::cpu0.inst 9025630028 # number of overall MSHR miss cycles
2985system.l2c.overall_mshr_miss_latency::cpu0.data 27398168869 # number of overall MSHR miss cycles
2986system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39438396932 # number of overall MSHR miss cycles
2987system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 273086509 # number of overall MSHR miss cycles
2988system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 248503510 # number of overall MSHR miss cycles
2989system.l2c.overall_mshr_miss_latency::cpu1.inst 5986913295 # number of overall MSHR miss cycles
2990system.l2c.overall_mshr_miss_latency::cpu1.data 21984186250 # number of overall MSHR miss cycles
2991system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 31231074499 # number of overall MSHR miss cycles
2992system.l2c.overall_mshr_miss_latency::total 136043643934 # number of overall MSHR miss cycles
2993system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles
2994system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5288332558 # number of ReadReq MSHR uncacheable cycles
2995system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10383500 # number of ReadReq MSHR uncacheable cycles
2996system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 664180522 # number of ReadReq MSHR uncacheable cycles
2997system.l2c.ReadReq_mshr_uncacheable_latency::total 11860562580 # number of ReadReq MSHR uncacheable cycles
2998system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5157955518 # number of WriteReq MSHR uncacheable cycles
2999system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 839811556 # number of WriteReq MSHR uncacheable cycles
3000system.l2c.WriteReq_mshr_uncacheable_latency::total 5997767074 # number of WriteReq MSHR uncacheable cycles
3001system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles
3002system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10446288076 # number of overall MSHR uncacheable cycles
3003system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10383500 # number of overall MSHR uncacheable cycles
3004system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1503992078 # number of overall MSHR uncacheable cycles
3005system.l2c.overall_mshr_uncacheable_latency::total 17858329654 # number of overall MSHR uncacheable cycles
3006system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3007system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3008system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.260885 # mshr miss rate for UpgradeReq accesses
3009system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.330649 # mshr miss rate for UpgradeReq accesses
3010system.l2c.UpgradeReq_mshr_miss_rate::total 0.291090 # mshr miss rate for UpgradeReq accesses
3011system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224494 # mshr miss rate for SCUpgradeReq accesses
3012system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220563 # mshr miss rate for SCUpgradeReq accesses
3013system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222513 # mshr miss rate for SCUpgradeReq accesses
3014system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.560516 # mshr miss rate for ReadExReq accesses
3015system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.509807 # mshr miss rate for ReadExReq accesses
3016system.l2c.ReadExReq_mshr_miss_rate::total 0.539175 # mshr miss rate for ReadExReq accesses
3017system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for ReadSharedReq accesses
3018system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for ReadSharedReq accesses
3019system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for ReadSharedReq accesses
3020system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.169396 # mshr miss rate for ReadSharedReq accesses
3021system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for ReadSharedReq accesses
3022system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for ReadSharedReq accesses
3023system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for ReadSharedReq accesses
3024system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for ReadSharedReq accesses
3025system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.173219 # mshr miss rate for ReadSharedReq accesses
3026system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for ReadSharedReq accesses
3027system.l2c.ReadSharedReq_mshr_miss_rate::total 0.203607 # mshr miss rate for ReadSharedReq accesses
3028system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.760748 # mshr miss rate for InvalidateReq accesses
3029system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.475780 # mshr miss rate for InvalidateReq accesses
3030system.l2c.InvalidateReq_mshr_miss_rate::total 0.675195 # mshr miss rate for InvalidateReq accesses
3031system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for demand accesses
3032system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for demand accesses
3033system.l2c.demand_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for demand accesses
3034system.l2c.demand_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for demand accesses
3035system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for demand accesses
3036system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for demand accesses
3037system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for demand accesses
3038system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for demand accesses
3039system.l2c.demand_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for demand accesses
3040system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for demand accesses
3041system.l2c.demand_mshr_miss_rate::total 0.222974 # mshr miss rate for demand accesses
3042system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.204779 # mshr miss rate for overall accesses
3043system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.223960 # mshr miss rate for overall accesses
3044system.l2c.overall_mshr_miss_rate::cpu0.inst 0.096122 # mshr miss rate for overall accesses
3045system.l2c.overall_mshr_miss_rate::cpu0.data 0.229928 # mshr miss rate for overall accesses
3046system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.417793 # mshr miss rate for overall accesses
3047system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.258222 # mshr miss rate for overall accesses
3048system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.318577 # mshr miss rate for overall accesses
3049system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069989 # mshr miss rate for overall accesses
3050system.l2c.overall_mshr_miss_rate::cpu1.data 0.217274 # mshr miss rate for overall accesses
3051system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.394945 # mshr miss rate for overall accesses
3052system.l2c.overall_mshr_miss_rate::total 0.222974 # mshr miss rate for overall accesses
3053system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70784.132277 # average UpgradeReq mshr miss latency
3054system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70454.459731 # average UpgradeReq mshr miss latency
3055system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70622.002003 # average UpgradeReq mshr miss latency
3056system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73717.496713 # average SCUpgradeReq mshr miss latency
3057system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73474.839400 # average SCUpgradeReq mshr miss latency
3058system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73596.297820 # average SCUpgradeReq mshr miss latency
3059system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128263.872968 # average ReadExReq mshr miss latency
3060system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 124633.215096 # average ReadExReq mshr miss latency
3061system.l2c.ReadExReq_avg_mshr_miss_latency::total 126819.155867 # average ReadExReq mshr miss latency
3062system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average ReadSharedReq mshr miss latency
3063system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average ReadSharedReq mshr miss latency
3064system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average ReadSharedReq mshr miss latency
3065system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130514.541956 # average ReadSharedReq mshr miss latency
3066system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average ReadSharedReq mshr miss latency
3067system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average ReadSharedReq mshr miss latency
3068system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average ReadSharedReq mshr miss latency
3069system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average ReadSharedReq mshr miss latency
3070system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129696.244873 # average ReadSharedReq mshr miss latency
3071system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average ReadSharedReq mshr miss latency
3072system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146076.538245 # average ReadSharedReq mshr miss latency
3073system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69978.879648 # average InvalidateReq mshr miss latency
3074system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69612.317690 # average InvalidateReq mshr miss latency
3075system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69901.332925 # average InvalidateReq mshr miss latency
3076system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency
3077system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency
3078system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency
3079system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency
3080system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency
3081system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency
3082system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency
3083system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency
3084system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency
3085system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency
3086system.l2c.demand_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency
3087system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130520.146102 # average overall mshr miss latency
3088system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131240.563101 # average overall mshr miss latency
3089system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124649.624738 # average overall mshr miss latency
3090system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129665.397702 # average overall mshr miss latency
3091system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 165200.841671 # average overall mshr miss latency
3092system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129302.324337 # average overall mshr miss latency
3093system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130311.227058 # average overall mshr miss latency
3094system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124535.368286 # average overall mshr miss latency
3095system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128141.349774 # average overall mshr miss latency
3096system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156795.883680 # average overall mshr miss latency
3097system.l2c.overall_avg_mshr_miss_latency::total 143389.033978 # average overall mshr miss latency
3098system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency
3099system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164525.170581 # average ReadReq mshr uncacheable latency
3100system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average ReadReq mshr uncacheable latency
3101system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 98704.194085 # average ReadReq mshr uncacheable latency
3102system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129944.590793 # average ReadReq mshr uncacheable latency
3103system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163469.575571 # average WriteReq mshr uncacheable latency
3104system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116608.102749 # average WriteReq mshr uncacheable latency
3105system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154761.116604 # average WriteReq mshr uncacheable latency
3106system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency
3107system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164002.261932 # average overall mshr uncacheable latency
3108system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111650.537634 # average overall mshr uncacheable latency
3109system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 107960.094609 # average overall mshr uncacheable latency
3110system.l2c.overall_avg_mshr_uncacheable_latency::total 137341.128933 # average overall mshr uncacheable latency
3111system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3112system.membus.trans_dist::ReadReq 91274 # Transaction distribution
3113system.membus.trans_dist::ReadResp 916539 # Transaction distribution
3114system.membus.trans_dist::WriteReq 38755 # Transaction distribution
3115system.membus.trans_dist::WriteResp 38755 # Transaction distribution
3116system.membus.trans_dist::WritebackDirty 1197090 # Transaction distribution
3117system.membus.trans_dist::CleanEvict 262945 # Transaction distribution
3118system.membus.trans_dist::UpgradeReq 440993 # Transaction distribution
3119system.membus.trans_dist::SCUpgradeReq 308067 # Transaction distribution
3120system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3121system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
3122system.membus.trans_dist::ReadExReq 144406 # Transaction distribution
3123system.membus.trans_dist::ReadExResp 127298 # Transaction distribution
3124system.membus.trans_dist::ReadSharedReq 825265 # Transaction distribution
3125system.membus.trans_dist::InvalidateReq 666679 # Transaction distribution
3126system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122958 # Packet count per connected master and slave (bytes)
3127system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3128system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27076 # Packet count per connected master and slave (bytes)
3129system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4666640 # Packet count per connected master and slave (bytes)
3130system.membus.pkt_count_system.l2c.mem_side::total 4816726 # Packet count per connected master and slave (bytes)
3131system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238694 # Packet count per connected master and slave (bytes)
3132system.membus.pkt_count_system.iocache.mem_side::total 238694 # Packet count per connected master and slave (bytes)
3133system.membus.pkt_count::total 5055420 # Packet count per connected master and slave (bytes)
3134system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155996 # Cumulative packet size per connected master and slave (bytes)
3135system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3136system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54152 # Cumulative packet size per connected master and slave (bytes)
3137system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 133490240 # Cumulative packet size per connected master and slave (bytes)
3138system.membus.pkt_size_system.l2c.mem_side::total 133701712 # Cumulative packet size per connected master and slave (bytes)
3139system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7291456 # Cumulative packet size per connected master and slave (bytes)
3140system.membus.pkt_size_system.iocache.mem_side::total 7291456 # Cumulative packet size per connected master and slave (bytes)
3141system.membus.pkt_size::total 140993168 # Cumulative packet size per connected master and slave (bytes)
3142system.membus.snoops 609728 # Total snoops (count)
3143system.membus.snoop_fanout::samples 3975535 # Request fanout histogram
3144system.membus.snoop_fanout::mean 1 # Request fanout histogram
3145system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3146system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3147system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3148system.membus.snoop_fanout::1 3975535 100.00% 100.00% # Request fanout histogram
3149system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3150system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3151system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3152system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3153system.membus.snoop_fanout::total 3975535 # Request fanout histogram
3154system.membus.reqLayer0.occupancy 110272997 # Layer occupancy (ticks)
3155system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3156system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
3157system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3158system.membus.reqLayer2.occupancy 22907496 # Layer occupancy (ticks)
3159system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3160system.membus.reqLayer5.occupancy 8443265855 # Layer occupancy (ticks)
3161system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3162system.membus.respLayer2.occupancy 5364054651 # Layer occupancy (ticks)
3163system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3164system.membus.respLayer3.occupancy 45386996 # Layer occupancy (ticks)
3165system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3166system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3167system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3168system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3169system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3170system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3171system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3172system.realview.ethernet.txBytes 966 # Bytes Transmitted

--- 37 unchanged lines hidden (view full) ---

3210system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3211system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3212system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3213system.realview.ethernet.droppedPackets 0 # number of packets dropped
3214system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3215system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3216system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3217system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3218system.toL2Bus.snoop_filter.tot_requests 12590063 # Total number of requests made to the snoop filter.
3219system.toL2Bus.snoop_filter.hit_single_requests 6816351 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3220system.toL2Bus.snoop_filter.hit_multi_requests 2112405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3221system.toL2Bus.snoop_filter.tot_snoops 136080 # Total number of snoops made to the snoop filter.
3222system.toL2Bus.snoop_filter.hit_single_snoops 123352 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3223system.toL2Bus.snoop_filter.hit_multi_snoops 12728 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3224system.toL2Bus.trans_dist::ReadReq 91276 # Transaction distribution
3225system.toL2Bus.trans_dist::ReadResp 4889046 # Transaction distribution
3226system.toL2Bus.trans_dist::WriteReq 38755 # Transaction distribution
3227system.toL2Bus.trans_dist::WriteResp 38755 # Transaction distribution
3228system.toL2Bus.trans_dist::WritebackDirty 4006843 # Transaction distribution
3229system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
3230system.toL2Bus.trans_dist::CleanEvict 3033326 # Transaction distribution
3231system.toL2Bus.trans_dist::UpgradeReq 740212 # Transaction distribution
3232system.toL2Bus.trans_dist::SCUpgradeReq 393009 # Transaction distribution
3233system.toL2Bus.trans_dist::UpgradeResp 1133221 # Transaction distribution
3234system.toL2Bus.trans_dist::SCUpgradeFailReq 135 # Transaction distribution
3235system.toL2Bus.trans_dist::UpgradeFailResp 135 # Transaction distribution
3236system.toL2Bus.trans_dist::ReadExReq 301958 # Transaction distribution
3237system.toL2Bus.trans_dist::ReadExResp 301958 # Transaction distribution
3238system.toL2Bus.trans_dist::ReadSharedReq 4804997 # Transaction distribution
3239system.toL2Bus.trans_dist::InvalidateReq 940884 # Transaction distribution
3240system.toL2Bus.trans_dist::InvalidateResp 833900 # Transaction distribution
3241system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10292862 # Packet count per connected master and slave (bytes)
3242system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8190937 # Packet count per connected master and slave (bytes)
3243system.toL2Bus.pkt_count::total 18483799 # Packet count per connected master and slave (bytes)
3244system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255537947 # Cumulative packet size per connected master and slave (bytes)
3245system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 200300853 # Cumulative packet size per connected master and slave (bytes)
3246system.toL2Bus.pkt_size::total 455838800 # Cumulative packet size per connected master and slave (bytes)
3247system.toL2Bus.snoops 3066288 # Total snoops (count)
3248system.toL2Bus.snoop_fanout::samples 8826957 # Request fanout histogram
3249system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
3250system.toL2Bus.snoop_fanout::stdev 0.482240 # Request fanout histogram
3251system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3252system.toL2Bus.snoop_fanout::0 5684742 64.40% 64.40% # Request fanout histogram
3253system.toL2Bus.snoop_fanout::1 3129487 35.45% 99.86% # Request fanout histogram
3254system.toL2Bus.snoop_fanout::2 12728 0.14% 100.00% # Request fanout histogram
3255system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3256system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3257system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3258system.toL2Bus.snoop_fanout::total 8826957 # Request fanout histogram
3259system.toL2Bus.reqLayer0.occupancy 9586281743 # Layer occupancy (ticks)
3260system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3261system.toL2Bus.snoopLayer0.occupancy 2585661 # Layer occupancy (ticks)
3262system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3263system.toL2Bus.respLayer0.occupancy 4723415116 # Layer occupancy (ticks)
3264system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3265system.toL2Bus.respLayer1.occupancy 4064152578 # Layer occupancy (ticks)
3266system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3267
3268---------- End Simulation Statistics ----------