1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.477179 # Number of seconds simulated
4sim_ticks 47477179149500 # Number of ticks simulated
5final_tick 47477179149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 181000 # Simulator instruction rate (inst/s)
8host_op_rate 212908 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9614368962 # Simulator tick rate (ticks/s)
10host_mem_usage 772236 # Number of bytes of host memory used
11host_seconds 4938.15 # Real time elapsed on the host
12sim_insts 893806699 # Number of instructions simulated
13sim_ops 1051369194 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 125376 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 108736 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 7965248 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 14333320 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 15086080 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 149568 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3627008 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 11510096 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14847104 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 436288 # Number of bytes read from this memory
27system.physmem.bytes_read::total 68325080 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 7965248 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3627008 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 11592256 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 80335616 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 80356200 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 1959 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1699 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 124457 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 223971 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 235720 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2337 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 56672 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 179858 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 231986 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6817 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1067605 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1255244 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1257818 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2641 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2290 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 167770 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 301899 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 317754 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 3150 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 2870 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 76395 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 242434 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 312721 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9189 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1439114 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 167770 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 76395 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 244165 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1692089 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1692523 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1692089 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2641 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2290 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 167770 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 302333 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 317754 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 3150 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 2870 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 76395 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 242434 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 312721 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9189 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3131637 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1067605 # Number of read requests accepted
84system.physmem.writeReqs 1929186 # Number of write requests accepted
85system.physmem.readBursts 1067605 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1929186 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 68309056 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 17664 # Total number of bytes read from write queue
89system.physmem.bytesWritten 120257344 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 68325080 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 123323752 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 276 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 50133 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 117648 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 62386 # Per bank write bursts
96system.physmem.perBankRdBursts::1 65796 # Per bank write bursts
97system.physmem.perBankRdBursts::2 60427 # Per bank write bursts
98system.physmem.perBankRdBursts::3 63507 # Per bank write bursts
99system.physmem.perBankRdBursts::4 66319 # Per bank write bursts
100system.physmem.perBankRdBursts::5 73621 # Per bank write bursts
101system.physmem.perBankRdBursts::6 69221 # Per bank write bursts
102system.physmem.perBankRdBursts::7 63591 # Per bank write bursts
103system.physmem.perBankRdBursts::8 61143 # Per bank write bursts
104system.physmem.perBankRdBursts::9 115825 # Per bank write bursts
105system.physmem.perBankRdBursts::10 59973 # Per bank write bursts
106system.physmem.perBankRdBursts::11 66407 # Per bank write bursts
107system.physmem.perBankRdBursts::12 58867 # Per bank write bursts
108system.physmem.perBankRdBursts::13 61123 # Per bank write bursts
109system.physmem.perBankRdBursts::14 58743 # Per bank write bursts
110system.physmem.perBankRdBursts::15 60380 # Per bank write bursts
111system.physmem.perBankWrBursts::0 115877 # Per bank write bursts
112system.physmem.perBankWrBursts::1 122877 # Per bank write bursts
113system.physmem.perBankWrBursts::2 115996 # Per bank write bursts
114system.physmem.perBankWrBursts::3 119851 # Per bank write bursts
115system.physmem.perBankWrBursts::4 119313 # Per bank write bursts
116system.physmem.perBankWrBursts::5 126432 # Per bank write bursts
117system.physmem.perBankWrBursts::6 119028 # Per bank write bursts
118system.physmem.perBankWrBursts::7 120185 # Per bank write bursts
119system.physmem.perBankWrBursts::8 118113 # Per bank write bursts
120system.physmem.perBankWrBursts::9 119452 # Per bank write bursts
121system.physmem.perBankWrBursts::10 113141 # Per bank write bursts
122system.physmem.perBankWrBursts::11 117109 # Per bank write bursts
123system.physmem.perBankWrBursts::12 112676 # Per bank write bursts
124system.physmem.perBankWrBursts::13 113553 # Per bank write bursts
125system.physmem.perBankWrBursts::14 112771 # Per bank write bursts
126system.physmem.perBankWrBursts::15 112647 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 226 # Number of times write queue was full causing retry
129system.physmem.totGap 47477177227000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1067575 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1926612 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 704225 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 128672 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 50762 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 38076 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 32557 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 29624 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 27261 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 24554 # What read queue length does an incoming req see
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161system.physmem.rdQLenPdf::17 190 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 103 # What read queue length does an incoming req see
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164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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192system.physmem.wrQLenPdf::16 65288 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::18 105702 # What write queue length does an incoming req see
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197system.physmem.wrQLenPdf::21 108444 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 104050 # What write queue length does an incoming req see
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203system.physmem.wrQLenPdf::27 104741 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 100206 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 114790 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 102548 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 96204 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 91928 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 7498 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 6040 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 6647 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 7551 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 7971 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 7109 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 6845 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 7426 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 5746 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 5672 # What write queue length does an incoming req see
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221system.physmem.wrQLenPdf::45 4631 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 3871 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 3873 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 3174 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 2570 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 1610 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 1389 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 919 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 1025 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 778 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 627 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 635 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 623 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 556 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 443 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 391 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 338 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 256 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 704 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1080190 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 174.567156 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 106.861850 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 244.135229 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 694007 64.25% 64.25% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 206792 19.14% 83.39% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 51978 4.81% 88.20% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 24974 2.31% 90.52% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 18580 1.72% 92.24% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11712 1.08% 93.32% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 8387 0.78% 94.10% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7821 0.72% 94.82% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 55939 5.18% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1080190 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 83578 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 12.770071 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 136.461901 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 83575 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 83578 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 83578 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 22.482244 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 19.955849 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 20.755182 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::0-31 75860 90.77% 90.77% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::32-63 5202 6.22% 96.99% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::64-95 1276 1.53% 98.52% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::96-127 755 0.90% 99.42% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::128-159 241 0.29% 99.71% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::160-191 100 0.12% 99.83% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::192-223 48 0.06% 99.89% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::224-255 8 0.01% 99.89% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::256-287 9 0.01% 99.91% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::288-319 10 0.01% 99.92% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::320-351 17 0.02% 99.94% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::352-383 25 0.03% 99.97% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::384-415 5 0.01% 99.97% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::448-479 5 0.01% 99.98% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::480-511 2 0.00% 99.98% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::512-543 5 0.01% 99.99% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::544-575 3 0.00% 99.99% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::672-703 3 0.00% 100.00% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::total 83578 # Writes before turning the bus around for reads
289system.physmem.totQLat 40962619238 # Total ticks spent queuing
290system.physmem.totMemAccLat 60975037988 # Total ticks spent from burst creation until serviced by the DRAM
291system.physmem.totBusLat 5336645000 # Total ticks spent in databus transfers
292system.physmem.avgQLat 38378.62 # Average queueing delay per DRAM burst
293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
294system.physmem.avgMemAccLat 57128.62 # Average memory access latency per DRAM burst
295system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
296system.physmem.avgWrBW 2.53 # Average achieved write bandwidth in MiByte/s
297system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
298system.physmem.avgWrBWSys 2.60 # Average system write bandwidth in MiByte/s
299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
300system.physmem.busUtil 0.03 # Data bus utilization in percentage
301system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
303system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing
304system.physmem.avgWrQLen 23.74 # Average write queue length when enqueuing
305system.physmem.readRowHits 799066 # Number of row buffer hits during reads
306system.physmem.writeRowHits 1067089 # Number of row buffer hits during writes
307system.physmem.readRowHitRate 74.87 # Row buffer hit rate for reads
308system.physmem.writeRowHitRate 56.79 # Row buffer hit rate for writes
309system.physmem.avgGap 15842672.12 # Average gap between requests
310system.physmem.pageHitRate 63.34 # Row buffer hit rate, read and write combined
311system.physmem_0.actEnergy 4225820760 # Energy for activate commands per rank (pJ)
312system.physmem_0.preEnergy 2305755375 # Energy for precharge commands per rank (pJ)
313system.physmem_0.readEnergy 4093954800 # Energy for read commands per rank (pJ)
314system.physmem_0.writeEnergy 6217942320 # Energy for write commands per rank (pJ)
315system.physmem_0.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ)
316system.physmem_0.actBackEnergy 1196990920755 # Energy for active background per rank (pJ)
317system.physmem_0.preBackEnergy 27436312080750 # Energy for precharge background per rank (pJ)
318system.physmem_0.totalEnergy 31751124639720 # Total energy per rank (pJ)
319system.physmem_0.averagePower 668.766110 # Core power per rank (mW)
320system.physmem_0.memoryStateTime::IDLE 45642284556030 # Time in different power states
321system.physmem_0.memoryStateTime::REF 1585367160000 # Time in different power states
322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
323system.physmem_0.memoryStateTime::ACT 249523460470 # Time in different power states
324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
325system.physmem_1.actEnergy 3940415640 # Energy for activate commands per rank (pJ)
326system.physmem_1.preEnergy 2150028375 # Energy for precharge commands per rank (pJ)
327system.physmem_1.readEnergy 4231125600 # Energy for read commands per rank (pJ)
328system.physmem_1.writeEnergy 5958113760 # Energy for write commands per rank (pJ)
329system.physmem_1.refreshEnergy 3100978164960 # Energy for refresh commands per rank (pJ)
330system.physmem_1.actBackEnergy 1192295919105 # Energy for active background per rank (pJ)
331system.physmem_1.preBackEnergy 27440430503250 # Energy for precharge background per rank (pJ)
332system.physmem_1.totalEnergy 31749984270690 # Total energy per rank (pJ)
333system.physmem_1.averagePower 668.742090 # Core power per rank (mW)
334system.physmem_1.memoryStateTime::IDLE 45649112064952 # Time in different power states
335system.physmem_1.memoryStateTime::REF 1585367160000 # Time in different power states
336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
337system.physmem_1.memoryStateTime::ACT 242698243548 # Time in different power states
338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
339system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
340system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
341system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
342system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
343system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
344system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
345system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory

--- 14 unchanged lines hidden (view full) ---

360system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s)
361system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
362system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
363system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
364system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
365system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
366system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
367system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
368system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
369system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
370system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
371system.cpu0.branchPred.lookups 146228375 # Number of BP lookups
372system.cpu0.branchPred.condPredicted 102974776 # Number of conditional branches predicted
373system.cpu0.branchPred.condIncorrect 6711039 # Number of conditional branches incorrect
374system.cpu0.branchPred.BTBLookups 109409110 # Number of BTB lookups
375system.cpu0.branchPred.BTBHits 78811291 # Number of BTB hits
376system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
377system.cpu0.branchPred.BTBHitPct 72.033573 # BTB Hit Percentage
378system.cpu0.branchPred.usedRAS 17518133 # Number of times the RAS was used to get a target.
379system.cpu0.branchPred.RASInCorrect 1190785 # Number of incorrect RAS predictions.
380system.cpu_clk_domain.clock 500 # Clock period in ticks
381system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
382system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

402system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
403system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
404system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
405system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
406system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
407system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
408system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
409system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
410system.cpu0.dtb.walker.walks 302414 # Table walker walks requested
411system.cpu0.dtb.walker.walksLong 302414 # Table walker walks initiated with long descriptors
412system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9161 # Level at which table walker walks with long descriptors terminate
413system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 80364 # Level at which table walker walks with long descriptors terminate
414system.cpu0.dtb.walker.walkWaitTime::samples 302414 # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::0 302414 100.00% 100.00% # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkWaitTime::total 302414 # Table walker wait (enqueue to first request) latency
417system.cpu0.dtb.walker.walkCompletionTime::samples 89525 # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walkCompletionTime::mean 18873.046300 # Table walker service (enqueue to completion) latency
419system.cpu0.dtb.walker.walkCompletionTime::gmean 17079.714221 # Table walker service (enqueue to completion) latency
420system.cpu0.dtb.walker.walkCompletionTime::stdev 14739.219535 # Table walker service (enqueue to completion) latency
421system.cpu0.dtb.walker.walkCompletionTime::0-65535 88579 98.94% 98.94% # Table walker service (enqueue to completion) latency
422system.cpu0.dtb.walker.walkCompletionTime::65536-131071 783 0.87% 99.82% # Table walker service (enqueue to completion) latency
423system.cpu0.dtb.walker.walkCompletionTime::131072-196607 49 0.05% 99.87% # Table walker service (enqueue to completion) latency
424system.cpu0.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.92% # Table walker service (enqueue to completion) latency
425system.cpu0.dtb.walker.walkCompletionTime::262144-327679 44 0.05% 99.97% # Table walker service (enqueue to completion) latency
426system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::total 89525 # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
433system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
434system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
435system.cpu0.dtb.walker.walkPageSizes::4K 80364 89.77% 89.77% # Table walker page sizes translated
436system.cpu0.dtb.walker.walkPageSizes::2M 9161 10.23% 100.00% # Table walker page sizes translated
437system.cpu0.dtb.walker.walkPageSizes::total 89525 # Table walker page sizes translated
438system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302414 # Table walker requests started/completed, data/inst
439system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
440system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302414 # Table walker requests started/completed, data/inst
441system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89525 # Table walker requests started/completed, data/inst
442system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
443system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89525 # Table walker requests started/completed, data/inst
444system.cpu0.dtb.walker.walkRequestOrigin::total 391939 # Table walker requests started/completed, data/inst
445system.cpu0.dtb.inst_hits 0 # ITB inst hits
446system.cpu0.dtb.inst_misses 0 # ITB inst misses
447system.cpu0.dtb.read_hits 94852147 # DTB read hits
448system.cpu0.dtb.read_misses 252189 # DTB read misses
449system.cpu0.dtb.write_hits 83443537 # DTB write hits
450system.cpu0.dtb.write_misses 50225 # DTB write misses
451system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
452system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
453system.cpu0.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID
454system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
455system.cpu0.dtb.flush_entries 36113 # Number of entries that have been flushed from TLB
456system.cpu0.dtb.align_faults 2068 # Number of TLB faults due to alignment restrictions
457system.cpu0.dtb.prefetch_faults 9574 # Number of TLB faults due to prefetch
458system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
459system.cpu0.dtb.perms_faults 10663 # Number of TLB faults due to permissions restrictions
460system.cpu0.dtb.read_accesses 95104336 # DTB read accesses
461system.cpu0.dtb.write_accesses 83493762 # DTB write accesses
462system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
463system.cpu0.dtb.hits 178295684 # DTB hits
464system.cpu0.dtb.misses 302414 # DTB misses
465system.cpu0.dtb.accesses 178598098 # DTB accesses
466system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
467system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
468system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
469system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
470system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
471system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
472system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

487system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
488system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
489system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
490system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
491system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
492system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
493system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
494system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
495system.cpu0.itb.walker.walks 66598 # Table walker walks requested
496system.cpu0.itb.walker.walksLong 66598 # Table walker walks initiated with long descriptors
497system.cpu0.itb.walker.walksLongTerminationLevel::Level2 516 # Level at which table walker walks with long descriptors terminate
498system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54284 # Level at which table walker walks with long descriptors terminate
499system.cpu0.itb.walker.walkWaitTime::samples 66598 # Table walker wait (enqueue to first request) latency
500system.cpu0.itb.walker.walkWaitTime::0 66598 100.00% 100.00% # Table walker wait (enqueue to first request) latency
501system.cpu0.itb.walker.walkWaitTime::total 66598 # Table walker wait (enqueue to first request) latency
502system.cpu0.itb.walker.walkCompletionTime::samples 54800 # Table walker service (enqueue to completion) latency
503system.cpu0.itb.walker.walkCompletionTime::mean 21262.637080 # Table walker service (enqueue to completion) latency
504system.cpu0.itb.walker.walkCompletionTime::gmean 19017.155066 # Table walker service (enqueue to completion) latency
505system.cpu0.itb.walker.walkCompletionTime::stdev 16721.874177 # Table walker service (enqueue to completion) latency
506system.cpu0.itb.walker.walkCompletionTime::0-65535 53728 98.04% 98.04% # Table walker service (enqueue to completion) latency
507system.cpu0.itb.walker.walkCompletionTime::65536-131071 946 1.73% 99.77% # Table walker service (enqueue to completion) latency
508system.cpu0.itb.walker.walkCompletionTime::131072-196607 48 0.09% 99.86% # Table walker service (enqueue to completion) latency
509system.cpu0.itb.walker.walkCompletionTime::196608-262143 54 0.10% 99.96% # Table walker service (enqueue to completion) latency
510system.cpu0.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.98% # Table walker service (enqueue to completion) latency
511system.cpu0.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
512system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
513system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
514system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
515system.cpu0.itb.walker.walkCompletionTime::total 54800 # Table walker service (enqueue to completion) latency
516system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
517system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
518system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
519system.cpu0.itb.walker.walkPageSizes::4K 54284 99.06% 99.06% # Table walker page sizes translated
520system.cpu0.itb.walker.walkPageSizes::2M 516 0.94% 100.00% # Table walker page sizes translated
521system.cpu0.itb.walker.walkPageSizes::total 54800 # Table walker page sizes translated
522system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
523system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66598 # Table walker requests started/completed, data/inst
524system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66598 # Table walker requests started/completed, data/inst
525system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
526system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54800 # Table walker requests started/completed, data/inst
527system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54800 # Table walker requests started/completed, data/inst
528system.cpu0.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst
529system.cpu0.itb.inst_hits 261387859 # ITB inst hits
530system.cpu0.itb.inst_misses 66598 # ITB inst misses
531system.cpu0.itb.read_hits 0 # DTB read hits
532system.cpu0.itb.read_misses 0 # DTB read misses
533system.cpu0.itb.write_hits 0 # DTB write hits
534system.cpu0.itb.write_misses 0 # DTB write misses
535system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
536system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
537system.cpu0.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID
538system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
539system.cpu0.itb.flush_entries 25865 # Number of entries that have been flushed from TLB
540system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
541system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
542system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
543system.cpu0.itb.perms_faults 223375 # Number of TLB faults due to permissions restrictions
544system.cpu0.itb.read_accesses 0 # DTB read accesses
545system.cpu0.itb.write_accesses 0 # DTB write accesses
546system.cpu0.itb.inst_accesses 261454457 # ITB inst accesses
547system.cpu0.itb.hits 261387859 # DTB hits
548system.cpu0.itb.misses 66598 # DTB misses
549system.cpu0.itb.accesses 261454457 # DTB accesses
550system.cpu0.numCycles 1029830596 # number of cpu cycles simulated
551system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
552system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
553system.cpu0.committedInsts 487755400 # Number of instructions committed
554system.cpu0.committedOps 573075495 # Number of ops (including micro ops) committed
555system.cpu0.discardedOps 47715438 # Number of ops (including micro ops) which were discarded before commit
556system.cpu0.numFetchSuspends 4391 # Number of times Execute suspended instruction fetching
557system.cpu0.quiesceCycles 93925247519 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
558system.cpu0.cpi 2.111367 # CPI: cycles per instruction
559system.cpu0.ipc 0.473627 # IPC: instructions per cycle
560system.cpu0.kern.inst.arm 0 # number of arm instructions executed
561system.cpu0.kern.inst.quiesce 13314 # number of quiesce instructions executed
562system.cpu0.tickCycles 777849504 # Number of cycles that the object actually ticked
563system.cpu0.idleCycles 251981092 # Total number of cycles that the object has spent stopped
564system.cpu0.dcache.tags.replacements 5902107 # number of replacements
565system.cpu0.dcache.tags.tagsinuse 475.000126 # Cycle average of tags in use
566system.cpu0.dcache.tags.total_refs 169363182 # Total number of references to valid blocks.
567system.cpu0.dcache.tags.sampled_refs 5902609 # Sample count of references to valid blocks.
568system.cpu0.dcache.tags.avg_refs 28.692936 # Average number of references to valid blocks.
569system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit.
570system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.000126 # Average occupied blocks per requestor
571system.cpu0.dcache.tags.occ_percent::cpu0.data 0.927735 # Average percentage of cache occupancy
572system.cpu0.dcache.tags.occ_percent::total 0.927735 # Average percentage of cache occupancy
573system.cpu0.dcache.tags.occ_task_id_blocks::1024 502 # Occupied blocks per task id
574system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
575system.cpu0.dcache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
576system.cpu0.dcache.tags.age_task_id_blocks_1024::2 153 # Occupied blocks per task id
577system.cpu0.dcache.tags.occ_task_id_percent::1024 0.980469 # Percentage of cache occupancy per task id
578system.cpu0.dcache.tags.tag_accesses 359562725 # Number of tag accesses
579system.cpu0.dcache.tags.data_accesses 359562725 # Number of data accesses
580system.cpu0.dcache.ReadReq_hits::cpu0.data 86974547 # number of ReadReq hits
581system.cpu0.dcache.ReadReq_hits::total 86974547 # number of ReadReq hits
582system.cpu0.dcache.WriteReq_hits::cpu0.data 77401946 # number of WriteReq hits
583system.cpu0.dcache.WriteReq_hits::total 77401946 # number of WriteReq hits
584system.cpu0.dcache.SoftPFReq_hits::cpu0.data 298185 # number of SoftPFReq hits
585system.cpu0.dcache.SoftPFReq_hits::total 298185 # number of SoftPFReq hits
586system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 275916 # number of WriteInvalidateReq hits
587system.cpu0.dcache.WriteInvalidateReq_hits::total 275916 # number of WriteInvalidateReq hits
588system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1961524 # number of LoadLockedReq hits
589system.cpu0.dcache.LoadLockedReq_hits::total 1961524 # number of LoadLockedReq hits
590system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1923644 # number of StoreCondReq hits
591system.cpu0.dcache.StoreCondReq_hits::total 1923644 # number of StoreCondReq hits
592system.cpu0.dcache.demand_hits::cpu0.data 164376493 # number of demand (read+write) hits
593system.cpu0.dcache.demand_hits::total 164376493 # number of demand (read+write) hits
594system.cpu0.dcache.overall_hits::cpu0.data 164674678 # number of overall hits
595system.cpu0.dcache.overall_hits::total 164674678 # number of overall hits
596system.cpu0.dcache.ReadReq_misses::cpu0.data 3650210 # number of ReadReq misses
597system.cpu0.dcache.ReadReq_misses::total 3650210 # number of ReadReq misses
598system.cpu0.dcache.WriteReq_misses::cpu0.data 2435892 # number of WriteReq misses
599system.cpu0.dcache.WriteReq_misses::total 2435892 # number of WriteReq misses
600system.cpu0.dcache.SoftPFReq_misses::cpu0.data 670224 # number of SoftPFReq misses
601system.cpu0.dcache.SoftPFReq_misses::total 670224 # number of SoftPFReq misses
602system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 817849 # number of WriteInvalidateReq misses
603system.cpu0.dcache.WriteInvalidateReq_misses::total 817849 # number of WriteInvalidateReq misses
604system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 165967 # number of LoadLockedReq misses
605system.cpu0.dcache.LoadLockedReq_misses::total 165967 # number of LoadLockedReq misses
606system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202383 # number of StoreCondReq misses
607system.cpu0.dcache.StoreCondReq_misses::total 202383 # number of StoreCondReq misses
608system.cpu0.dcache.demand_misses::cpu0.data 6086102 # number of demand (read+write) misses
609system.cpu0.dcache.demand_misses::total 6086102 # number of demand (read+write) misses
610system.cpu0.dcache.overall_misses::cpu0.data 6756326 # number of overall misses
611system.cpu0.dcache.overall_misses::total 6756326 # number of overall misses
612system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 55969500387 # number of ReadReq miss cycles
613system.cpu0.dcache.ReadReq_miss_latency::total 55969500387 # number of ReadReq miss cycles
614system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47032436273 # number of WriteReq miss cycles
615system.cpu0.dcache.WriteReq_miss_latency::total 47032436273 # number of WriteReq miss cycles
616system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 33507618312 # number of WriteInvalidateReq miss cycles
617system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 33507618312 # number of WriteInvalidateReq miss cycles
618system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2441854002 # number of LoadLockedReq miss cycles
619system.cpu0.dcache.LoadLockedReq_miss_latency::total 2441854002 # number of LoadLockedReq miss cycles
620system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4283229947 # number of StoreCondReq miss cycles
621system.cpu0.dcache.StoreCondReq_miss_latency::total 4283229947 # number of StoreCondReq miss cycles
622system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1855000 # number of StoreCondFailReq miss cycles
623system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1855000 # number of StoreCondFailReq miss cycles
624system.cpu0.dcache.demand_miss_latency::cpu0.data 103001936660 # number of demand (read+write) miss cycles
625system.cpu0.dcache.demand_miss_latency::total 103001936660 # number of demand (read+write) miss cycles
626system.cpu0.dcache.overall_miss_latency::cpu0.data 103001936660 # number of overall miss cycles
627system.cpu0.dcache.overall_miss_latency::total 103001936660 # number of overall miss cycles
628system.cpu0.dcache.ReadReq_accesses::cpu0.data 90624757 # number of ReadReq accesses(hits+misses)
629system.cpu0.dcache.ReadReq_accesses::total 90624757 # number of ReadReq accesses(hits+misses)
630system.cpu0.dcache.WriteReq_accesses::cpu0.data 79837838 # number of WriteReq accesses(hits+misses)
631system.cpu0.dcache.WriteReq_accesses::total 79837838 # number of WriteReq accesses(hits+misses)
632system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 968409 # number of SoftPFReq accesses(hits+misses)
633system.cpu0.dcache.SoftPFReq_accesses::total 968409 # number of SoftPFReq accesses(hits+misses)
634system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093765 # number of WriteInvalidateReq accesses(hits+misses)
635system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093765 # number of WriteInvalidateReq accesses(hits+misses)
636system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2127491 # number of LoadLockedReq accesses(hits+misses)
637system.cpu0.dcache.LoadLockedReq_accesses::total 2127491 # number of LoadLockedReq accesses(hits+misses)
638system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2126027 # number of StoreCondReq accesses(hits+misses)
639system.cpu0.dcache.StoreCondReq_accesses::total 2126027 # number of StoreCondReq accesses(hits+misses)
640system.cpu0.dcache.demand_accesses::cpu0.data 170462595 # number of demand (read+write) accesses
641system.cpu0.dcache.demand_accesses::total 170462595 # number of demand (read+write) accesses
642system.cpu0.dcache.overall_accesses::cpu0.data 171431004 # number of overall (read+write) accesses
643system.cpu0.dcache.overall_accesses::total 171431004 # number of overall (read+write) accesses
644system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040278 # miss rate for ReadReq accesses
645system.cpu0.dcache.ReadReq_miss_rate::total 0.040278 # miss rate for ReadReq accesses
646system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030510 # miss rate for WriteReq accesses
647system.cpu0.dcache.WriteReq_miss_rate::total 0.030510 # miss rate for WriteReq accesses
648system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.692088 # miss rate for SoftPFReq accesses
649system.cpu0.dcache.SoftPFReq_miss_rate::total 0.692088 # miss rate for SoftPFReq accesses
650system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.747737 # miss rate for WriteInvalidateReq accesses
651system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.747737 # miss rate for WriteInvalidateReq accesses
652system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078011 # miss rate for LoadLockedReq accesses
653system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078011 # miss rate for LoadLockedReq accesses
654system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095193 # miss rate for StoreCondReq accesses
655system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095193 # miss rate for StoreCondReq accesses
656system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035703 # miss rate for demand accesses
657system.cpu0.dcache.demand_miss_rate::total 0.035703 # miss rate for demand accesses
658system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039411 # miss rate for overall accesses
659system.cpu0.dcache.overall_miss_rate::total 0.039411 # miss rate for overall accesses
660system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15333.227509 # average ReadReq miss latency
661system.cpu0.dcache.ReadReq_avg_miss_latency::total 15333.227509 # average ReadReq miss latency
662system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19308.095873 # average WriteReq miss latency
663system.cpu0.dcache.WriteReq_avg_miss_latency::total 19308.095873 # average WriteReq miss latency
664system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40970.421572 # average WriteInvalidateReq miss latency
665system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40970.421572 # average WriteInvalidateReq miss latency
666system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14712.888719 # average LoadLockedReq miss latency
667system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14712.888719 # average LoadLockedReq miss latency
668system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21163.980903 # average StoreCondReq miss latency
669system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21163.980903 # average StoreCondReq miss latency
670system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
671system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
672system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16924.122642 # average overall miss latency
673system.cpu0.dcache.demand_avg_miss_latency::total 16924.122642 # average overall miss latency
674system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15245.258541 # average overall miss latency
675system.cpu0.dcache.overall_avg_miss_latency::total 15245.258541 # average overall miss latency
676system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
677system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
678system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
679system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
680system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
681system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
682system.cpu0.dcache.fast_writes 0 # number of fast writes performed
683system.cpu0.dcache.cache_copies 0 # number of cache copies performed
684system.cpu0.dcache.writebacks::writebacks 3966592 # number of writebacks
685system.cpu0.dcache.writebacks::total 3966592 # number of writebacks
686system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 443574 # number of ReadReq MSHR hits
687system.cpu0.dcache.ReadReq_mshr_hits::total 443574 # number of ReadReq MSHR hits
688system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1010368 # number of WriteReq MSHR hits
689system.cpu0.dcache.WriteReq_mshr_hits::total 1010368 # number of WriteReq MSHR hits
690system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 102 # number of WriteInvalidateReq MSHR hits
691system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 102 # number of WriteInvalidateReq MSHR hits
692system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43626 # number of LoadLockedReq MSHR hits
693system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43626 # number of LoadLockedReq MSHR hits
694system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 27 # number of StoreCondReq MSHR hits
695system.cpu0.dcache.StoreCondReq_mshr_hits::total 27 # number of StoreCondReq MSHR hits
696system.cpu0.dcache.demand_mshr_hits::cpu0.data 1453942 # number of demand (read+write) MSHR hits
697system.cpu0.dcache.demand_mshr_hits::total 1453942 # number of demand (read+write) MSHR hits
698system.cpu0.dcache.overall_mshr_hits::cpu0.data 1453942 # number of overall MSHR hits
699system.cpu0.dcache.overall_mshr_hits::total 1453942 # number of overall MSHR hits
700system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3206636 # number of ReadReq MSHR misses
701system.cpu0.dcache.ReadReq_mshr_misses::total 3206636 # number of ReadReq MSHR misses
702system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1425524 # number of WriteReq MSHR misses
703system.cpu0.dcache.WriteReq_mshr_misses::total 1425524 # number of WriteReq MSHR misses
704system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 664815 # number of SoftPFReq MSHR misses
705system.cpu0.dcache.SoftPFReq_mshr_misses::total 664815 # number of SoftPFReq MSHR misses
706system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 817747 # number of WriteInvalidateReq MSHR misses
707system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 817747 # number of WriteInvalidateReq MSHR misses
708system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122341 # number of LoadLockedReq MSHR misses
709system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122341 # number of LoadLockedReq MSHR misses
710system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202356 # number of StoreCondReq MSHR misses
711system.cpu0.dcache.StoreCondReq_mshr_misses::total 202356 # number of StoreCondReq MSHR misses
712system.cpu0.dcache.demand_mshr_misses::cpu0.data 4632160 # number of demand (read+write) MSHR misses
713system.cpu0.dcache.demand_mshr_misses::total 4632160 # number of demand (read+write) MSHR misses
714system.cpu0.dcache.overall_mshr_misses::cpu0.data 5296975 # number of overall MSHR misses
715system.cpu0.dcache.overall_mshr_misses::total 5296975 # number of overall MSHR misses
716system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable
717system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31604 # number of ReadReq MSHR uncacheable
718system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable
719system.cpu0.dcache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable
720system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses
721system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62581 # number of overall MSHR uncacheable misses
722system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42580313466 # number of ReadReq MSHR miss cycles
723system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42580313466 # number of ReadReq MSHR miss cycles
724system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25667045166 # number of WriteReq MSHR miss cycles
725system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25667045166 # number of WriteReq MSHR miss cycles
726system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14837829930 # number of SoftPFReq MSHR miss cycles
727system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14837829930 # number of SoftPFReq MSHR miss cycles
728system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 32271814438 # number of WriteInvalidateReq MSHR miss cycles
729system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 32271814438 # number of WriteInvalidateReq MSHR miss cycles
730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1568491891 # number of LoadLockedReq MSHR miss cycles
731system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1568491891 # number of LoadLockedReq MSHR miss cycles
732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3969414040 # number of StoreCondReq MSHR miss cycles
733system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3969414040 # number of StoreCondReq MSHR miss cycles
734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1696000 # number of StoreCondFailReq MSHR miss cycles
735system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1696000 # number of StoreCondFailReq MSHR miss cycles
736system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 68247358632 # number of demand (read+write) MSHR miss cycles
737system.cpu0.dcache.demand_mshr_miss_latency::total 68247358632 # number of demand (read+write) MSHR miss cycles
738system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 83085188562 # number of overall MSHR miss cycles
739system.cpu0.dcache.overall_mshr_miss_latency::total 83085188562 # number of overall MSHR miss cycles
740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5612600750 # number of ReadReq MSHR uncacheable cycles
741system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5612600750 # number of ReadReq MSHR uncacheable cycles
742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5285393252 # number of WriteReq MSHR uncacheable cycles
743system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5285393252 # number of WriteReq MSHR uncacheable cycles
744system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10897994002 # number of overall MSHR uncacheable cycles
745system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10897994002 # number of overall MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035384 # mshr miss rate for ReadReq accesses
747system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035384 # mshr miss rate for ReadReq accesses
748system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017855 # mshr miss rate for WriteReq accesses
749system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017855 # mshr miss rate for WriteReq accesses
750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.686502 # mshr miss rate for SoftPFReq accesses
751system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.686502 # mshr miss rate for SoftPFReq accesses
752system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747644 # mshr miss rate for WriteInvalidateReq accesses
753system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.747644 # mshr miss rate for WriteInvalidateReq accesses
754system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057505 # mshr miss rate for LoadLockedReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057505 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095180 # mshr miss rate for StoreCondReq accesses
757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095180 # mshr miss rate for StoreCondReq accesses
758system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027174 # mshr miss rate for demand accesses
759system.cpu0.dcache.demand_mshr_miss_rate::total 0.027174 # mshr miss rate for demand accesses
760system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030899 # mshr miss rate for overall accesses
761system.cpu0.dcache.overall_mshr_miss_rate::total 0.030899 # mshr miss rate for overall accesses
762system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13278.811024 # average ReadReq mshr miss latency
763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13278.811024 # average ReadReq mshr miss latency
764system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18005.340609 # average WriteReq mshr miss latency
765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18005.340609 # average WriteReq mshr miss latency
766system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22318.735182 # average SoftPFReq mshr miss latency
767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22318.735182 # average SoftPFReq mshr miss latency
768system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39464.301842 # average WriteInvalidateReq mshr miss latency
769system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39464.301842 # average WriteInvalidateReq mshr miss latency
770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12820.656125 # average LoadLockedReq mshr miss latency
771system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12820.656125 # average LoadLockedReq mshr miss latency
772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19615.993793 # average StoreCondReq mshr miss latency
773system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19615.993793 # average StoreCondReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
775system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14733.376790 # average overall mshr miss latency
777system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14733.376790 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15685.403190 # average overall mshr miss latency
779system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15685.403190 # average overall mshr miss latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177591.467852 # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177591.467852 # average ReadReq mshr uncacheable latency
782system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170623.147884 # average WriteReq mshr uncacheable latency
783system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170623.147884 # average WriteReq mshr uncacheable latency
784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174142.215720 # average overall mshr uncacheable latency
785system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174142.215720 # average overall mshr uncacheable latency
786system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
787system.cpu0.icache.tags.replacements 10289736 # number of replacements
788system.cpu0.icache.tags.tagsinuse 511.930282 # Cycle average of tags in use
789system.cpu0.icache.tags.total_refs 250868144 # Total number of references to valid blocks.
790system.cpu0.icache.tags.sampled_refs 10290248 # Sample count of references to valid blocks.
791system.cpu0.icache.tags.avg_refs 24.379213 # Average number of references to valid blocks.
792system.cpu0.icache.tags.warmup_cycle 24018555250 # Cycle when the warmup percentage was hit.
793system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930282 # Average occupied blocks per requestor
794system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
795system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
796system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
797system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id
798system.cpu0.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id
799system.cpu0.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id
800system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
801system.cpu0.icache.tags.tag_accesses 532607059 # Number of tag accesses
802system.cpu0.icache.tags.data_accesses 532607059 # Number of data accesses
803system.cpu0.icache.ReadReq_hits::cpu0.inst 250868144 # number of ReadReq hits
804system.cpu0.icache.ReadReq_hits::total 250868144 # number of ReadReq hits
805system.cpu0.icache.demand_hits::cpu0.inst 250868144 # number of demand (read+write) hits
806system.cpu0.icache.demand_hits::total 250868144 # number of demand (read+write) hits
807system.cpu0.icache.overall_hits::cpu0.inst 250868144 # number of overall hits
808system.cpu0.icache.overall_hits::total 250868144 # number of overall hits
809system.cpu0.icache.ReadReq_misses::cpu0.inst 10290257 # number of ReadReq misses
810system.cpu0.icache.ReadReq_misses::total 10290257 # number of ReadReq misses
811system.cpu0.icache.demand_misses::cpu0.inst 10290257 # number of demand (read+write) misses
812system.cpu0.icache.demand_misses::total 10290257 # number of demand (read+write) misses
813system.cpu0.icache.overall_misses::cpu0.inst 10290257 # number of overall misses
814system.cpu0.icache.overall_misses::total 10290257 # number of overall misses
815system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 101454150461 # number of ReadReq miss cycles
816system.cpu0.icache.ReadReq_miss_latency::total 101454150461 # number of ReadReq miss cycles
817system.cpu0.icache.demand_miss_latency::cpu0.inst 101454150461 # number of demand (read+write) miss cycles
818system.cpu0.icache.demand_miss_latency::total 101454150461 # number of demand (read+write) miss cycles
819system.cpu0.icache.overall_miss_latency::cpu0.inst 101454150461 # number of overall miss cycles
820system.cpu0.icache.overall_miss_latency::total 101454150461 # number of overall miss cycles
821system.cpu0.icache.ReadReq_accesses::cpu0.inst 261158401 # number of ReadReq accesses(hits+misses)
822system.cpu0.icache.ReadReq_accesses::total 261158401 # number of ReadReq accesses(hits+misses)
823system.cpu0.icache.demand_accesses::cpu0.inst 261158401 # number of demand (read+write) accesses
824system.cpu0.icache.demand_accesses::total 261158401 # number of demand (read+write) accesses
825system.cpu0.icache.overall_accesses::cpu0.inst 261158401 # number of overall (read+write) accesses
826system.cpu0.icache.overall_accesses::total 261158401 # number of overall (read+write) accesses
827system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039402 # miss rate for ReadReq accesses
828system.cpu0.icache.ReadReq_miss_rate::total 0.039402 # miss rate for ReadReq accesses
829system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039402 # miss rate for demand accesses
830system.cpu0.icache.demand_miss_rate::total 0.039402 # miss rate for demand accesses
831system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039402 # miss rate for overall accesses
832system.cpu0.icache.overall_miss_rate::total 0.039402 # miss rate for overall accesses
833system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.243599 # average ReadReq miss latency
834system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.243599 # average ReadReq miss latency
835system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency
836system.cpu0.icache.demand_avg_miss_latency::total 9859.243599 # average overall miss latency
837system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.243599 # average overall miss latency
838system.cpu0.icache.overall_avg_miss_latency::total 9859.243599 # average overall miss latency
839system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
840system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
841system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
842system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
843system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
844system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
845system.cpu0.icache.fast_writes 0 # number of fast writes performed
846system.cpu0.icache.cache_copies 0 # number of cache copies performed
847system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10290257 # number of ReadReq MSHR misses
848system.cpu0.icache.ReadReq_mshr_misses::total 10290257 # number of ReadReq MSHR misses
849system.cpu0.icache.demand_mshr_misses::cpu0.inst 10290257 # number of demand (read+write) MSHR misses
850system.cpu0.icache.demand_mshr_misses::total 10290257 # number of demand (read+write) MSHR misses
851system.cpu0.icache.overall_mshr_misses::cpu0.inst 10290257 # number of overall MSHR misses
852system.cpu0.icache.overall_mshr_misses::total 10290257 # number of overall MSHR misses
853system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable
854system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable
855system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses
856system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses
857system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 91134485035 # number of ReadReq MSHR miss cycles
858system.cpu0.icache.ReadReq_mshr_miss_latency::total 91134485035 # number of ReadReq MSHR miss cycles
859system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 91134485035 # number of demand (read+write) MSHR miss cycles
860system.cpu0.icache.demand_mshr_miss_latency::total 91134485035 # number of demand (read+write) MSHR miss cycles
861system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 91134485035 # number of overall MSHR miss cycles
862system.cpu0.icache.overall_mshr_miss_latency::total 91134485035 # number of overall MSHR miss cycles
863system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles
864system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles
865system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles
866system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles
867system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for ReadReq accesses
868system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.039402 # mshr miss rate for ReadReq accesses
869system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for demand accesses
870system.cpu0.icache.demand_mshr_miss_rate::total 0.039402 # mshr miss rate for demand accesses
871system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.039402 # mshr miss rate for overall accesses
872system.cpu0.icache.overall_mshr_miss_rate::total 0.039402 # mshr miss rate for overall accesses
873system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average ReadReq mshr miss latency
874system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8856.385709 # average ReadReq mshr miss latency
875system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency
876system.cpu0.icache.demand_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency
877system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8856.385709 # average overall mshr miss latency
878system.cpu0.icache.overall_avg_mshr_miss_latency::total 8856.385709 # average overall mshr miss latency
879system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency
880system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency
881system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency
882system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency
883system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
884system.cpu0.l2cache.prefetcher.num_hwpf_issued 8031555 # number of hwpf issued
885system.cpu0.l2cache.prefetcher.pfIdentified 8035489 # number of prefetch candidates identified
886system.cpu0.l2cache.prefetcher.pfBufferHit 3395 # number of redundant prefetches already in prefetch queue
887system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
888system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
889system.cpu0.l2cache.prefetcher.pfSpanPage 1023103 # number of prefetches not generated due to page crossing
890system.cpu0.l2cache.tags.replacements 2858654 # number of replacements
891system.cpu0.l2cache.tags.tagsinuse 16072.506631 # Cycle average of tags in use
892system.cpu0.l2cache.tags.total_refs 16359356 # Total number of references to valid blocks.
893system.cpu0.l2cache.tags.sampled_refs 2874620 # Sample count of references to valid blocks.
894system.cpu0.l2cache.tags.avg_refs 5.690963 # Average number of references to valid blocks.
895system.cpu0.l2cache.tags.warmup_cycle 5820437500 # Cycle when the warmup percentage was hit.
896system.cpu0.l2cache.tags.occ_blocks::writebacks 7531.283903 # Average occupied blocks per requestor
897system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 82.699151 # Average occupied blocks per requestor
898system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.479413 # Average occupied blocks per requestor
899system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4176.151665 # Average occupied blocks per requestor
900system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3206.986567 # Average occupied blocks per requestor
901system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 995.905932 # Average occupied blocks per requestor
902system.cpu0.l2cache.tags.occ_percent::writebacks 0.459673 # Average percentage of cache occupancy
903system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005048 # Average percentage of cache occupancy
904system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004851 # Average percentage of cache occupancy
905system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254892 # Average percentage of cache occupancy
906system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.195739 # Average percentage of cache occupancy
907system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060785 # Average percentage of cache occupancy
908system.cpu0.l2cache.tags.occ_percent::total 0.980988 # Average percentage of cache occupancy
909system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1379 # Occupied blocks per task id
910system.cpu0.l2cache.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id
911system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14509 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 349 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 790 # Occupied blocks per task id
914system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 240 # Occupied blocks per task id
915system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
916system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 40 # Occupied blocks per task id
918system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
919system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id
920system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 671 # Occupied blocks per task id
921system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4595 # Occupied blocks per task id
922system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6778 # Occupied blocks per task id
923system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2297 # Occupied blocks per task id
924system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084167 # Percentage of cache occupancy per task id
925system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004761 # Percentage of cache occupancy per task id
926system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.885559 # Percentage of cache occupancy per task id
927system.cpu0.l2cache.tags.tag_accesses 347615506 # Number of tag accesses
928system.cpu0.l2cache.tags.data_accesses 347615506 # Number of data accesses
929system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 522089 # number of ReadReq hits
930system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157285 # number of ReadReq hits
931system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9486915 # number of ReadReq hits
932system.cpu0.l2cache.ReadReq_hits::cpu0.data 2945564 # number of ReadReq hits
933system.cpu0.l2cache.ReadReq_hits::total 13111853 # number of ReadReq hits
934system.cpu0.l2cache.Writeback_hits::writebacks 3966591 # number of Writeback hits
935system.cpu0.l2cache.Writeback_hits::total 3966591 # number of Writeback hits
936system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 220070 # number of WriteInvalidateReq hits
937system.cpu0.l2cache.WriteInvalidateReq_hits::total 220070 # number of WriteInvalidateReq hits
938system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 104135 # number of UpgradeReq hits
939system.cpu0.l2cache.UpgradeReq_hits::total 104135 # number of UpgradeReq hits
940system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36121 # number of SCUpgradeReq hits
941system.cpu0.l2cache.SCUpgradeReq_hits::total 36121 # number of SCUpgradeReq hits
942system.cpu0.l2cache.ReadExReq_hits::cpu0.data 927424 # number of ReadExReq hits
943system.cpu0.l2cache.ReadExReq_hits::total 927424 # number of ReadExReq hits
944system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 522089 # number of demand (read+write) hits
945system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157285 # number of demand (read+write) hits
946system.cpu0.l2cache.demand_hits::cpu0.inst 9486915 # number of demand (read+write) hits
947system.cpu0.l2cache.demand_hits::cpu0.data 3872988 # number of demand (read+write) hits
948system.cpu0.l2cache.demand_hits::total 14039277 # number of demand (read+write) hits
949system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 522089 # number of overall hits
950system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157285 # number of overall hits
951system.cpu0.l2cache.overall_hits::cpu0.inst 9486915 # number of overall hits
952system.cpu0.l2cache.overall_hits::cpu0.data 3872988 # number of overall hits
953system.cpu0.l2cache.overall_hits::total 14039277 # number of overall hits
954system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12017 # number of ReadReq misses
955system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8240 # number of ReadReq misses
956system.cpu0.l2cache.ReadReq_misses::cpu0.inst 803341 # number of ReadReq misses
957system.cpu0.l2cache.ReadReq_misses::cpu0.data 1047943 # number of ReadReq misses
958system.cpu0.l2cache.ReadReq_misses::total 1871541 # number of ReadReq misses
959system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 596217 # number of WriteInvalidateReq misses
960system.cpu0.l2cache.WriteInvalidateReq_misses::total 596217 # number of WriteInvalidateReq misses
961system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136954 # number of UpgradeReq misses
962system.cpu0.l2cache.UpgradeReq_misses::total 136954 # number of UpgradeReq misses
963system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 166233 # number of SCUpgradeReq misses
964system.cpu0.l2cache.SCUpgradeReq_misses::total 166233 # number of SCUpgradeReq misses
965system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
966system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
967system.cpu0.l2cache.ReadExReq_misses::cpu0.data 268888 # number of ReadExReq misses
968system.cpu0.l2cache.ReadExReq_misses::total 268888 # number of ReadExReq misses
969system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12017 # number of demand (read+write) misses
970system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8240 # number of demand (read+write) misses
971system.cpu0.l2cache.demand_misses::cpu0.inst 803341 # number of demand (read+write) misses
972system.cpu0.l2cache.demand_misses::cpu0.data 1316831 # number of demand (read+write) misses
973system.cpu0.l2cache.demand_misses::total 2140429 # number of demand (read+write) misses
974system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12017 # number of overall misses
975system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8240 # number of overall misses
976system.cpu0.l2cache.overall_misses::cpu0.inst 803341 # number of overall misses
977system.cpu0.l2cache.overall_misses::cpu0.data 1316831 # number of overall misses
978system.cpu0.l2cache.overall_misses::total 2140429 # number of overall misses
979system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 431373212 # number of ReadReq miss cycles
980system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 321871478 # number of ReadReq miss cycles
981system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 24275854446 # number of ReadReq miss cycles
982system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 35706676401 # number of ReadReq miss cycles
983system.cpu0.l2cache.ReadReq_miss_latency::total 60735775537 # number of ReadReq miss cycles
984system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 217330162 # number of WriteInvalidateReq miss cycles
985system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 217330162 # number of WriteInvalidateReq miss cycles
986system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2999502703 # number of UpgradeReq miss cycles
987system.cpu0.l2cache.UpgradeReq_miss_latency::total 2999502703 # number of UpgradeReq miss cycles
988system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3447611393 # number of SCUpgradeReq miss cycles
989system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3447611393 # number of SCUpgradeReq miss cycles
990system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1659499 # number of SCUpgradeFailReq miss cycles
991system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1659499 # number of SCUpgradeFailReq miss cycles
992system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13657276886 # number of ReadExReq miss cycles
993system.cpu0.l2cache.ReadExReq_miss_latency::total 13657276886 # number of ReadExReq miss cycles
994system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 431373212 # number of demand (read+write) miss cycles
995system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 321871478 # number of demand (read+write) miss cycles
996system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24275854446 # number of demand (read+write) miss cycles
997system.cpu0.l2cache.demand_miss_latency::cpu0.data 49363953287 # number of demand (read+write) miss cycles
998system.cpu0.l2cache.demand_miss_latency::total 74393052423 # number of demand (read+write) miss cycles
999system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 431373212 # number of overall miss cycles
1000system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 321871478 # number of overall miss cycles
1001system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24275854446 # number of overall miss cycles
1002system.cpu0.l2cache.overall_miss_latency::cpu0.data 49363953287 # number of overall miss cycles
1003system.cpu0.l2cache.overall_miss_latency::total 74393052423 # number of overall miss cycles
1004system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 534106 # number of ReadReq accesses(hits+misses)
1005system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165525 # number of ReadReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 10290256 # number of ReadReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3993507 # number of ReadReq accesses(hits+misses)
1008system.cpu0.l2cache.ReadReq_accesses::total 14983394 # number of ReadReq accesses(hits+misses)
1009system.cpu0.l2cache.Writeback_accesses::writebacks 3966591 # number of Writeback accesses(hits+misses)
1010system.cpu0.l2cache.Writeback_accesses::total 3966591 # number of Writeback accesses(hits+misses)
1011system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 816287 # number of WriteInvalidateReq accesses(hits+misses)
1012system.cpu0.l2cache.WriteInvalidateReq_accesses::total 816287 # number of WriteInvalidateReq accesses(hits+misses)
1013system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241089 # number of UpgradeReq accesses(hits+misses)
1014system.cpu0.l2cache.UpgradeReq_accesses::total 241089 # number of UpgradeReq accesses(hits+misses)
1015system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202354 # number of SCUpgradeReq accesses(hits+misses)
1016system.cpu0.l2cache.SCUpgradeReq_accesses::total 202354 # number of SCUpgradeReq accesses(hits+misses)
1017system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1018system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1019system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196312 # number of ReadExReq accesses(hits+misses)
1020system.cpu0.l2cache.ReadExReq_accesses::total 1196312 # number of ReadExReq accesses(hits+misses)
1021system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 534106 # number of demand (read+write) accesses
1022system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165525 # number of demand (read+write) accesses
1023system.cpu0.l2cache.demand_accesses::cpu0.inst 10290256 # number of demand (read+write) accesses
1024system.cpu0.l2cache.demand_accesses::cpu0.data 5189819 # number of demand (read+write) accesses
1025system.cpu0.l2cache.demand_accesses::total 16179706 # number of demand (read+write) accesses
1026system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 534106 # number of overall (read+write) accesses
1027system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165525 # number of overall (read+write) accesses
1028system.cpu0.l2cache.overall_accesses::cpu0.inst 10290256 # number of overall (read+write) accesses
1029system.cpu0.l2cache.overall_accesses::cpu0.data 5189819 # number of overall (read+write) accesses
1030system.cpu0.l2cache.overall_accesses::total 16179706 # number of overall (read+write) accesses
1031system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for ReadReq accesses
1032system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049781 # miss rate for ReadReq accesses
1033system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078068 # miss rate for ReadReq accesses
1034system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.262412 # miss rate for ReadReq accesses
1035system.cpu0.l2cache.ReadReq_miss_rate::total 0.124908 # miss rate for ReadReq accesses
1036system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.730401 # miss rate for WriteInvalidateReq accesses
1037system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.730401 # miss rate for WriteInvalidateReq accesses
1038system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.568064 # miss rate for UpgradeReq accesses
1039system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.568064 # miss rate for UpgradeReq accesses
1040system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.821496 # miss rate for SCUpgradeReq accesses
1041system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.821496 # miss rate for SCUpgradeReq accesses
1042system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1043system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1044system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.224764 # miss rate for ReadExReq accesses
1045system.cpu0.l2cache.ReadExReq_miss_rate::total 0.224764 # miss rate for ReadExReq accesses
1046system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for demand accesses
1047system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049781 # miss rate for demand accesses
1048system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078068 # miss rate for demand accesses
1049system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253734 # miss rate for demand accesses
1050system.cpu0.l2cache.demand_miss_rate::total 0.132291 # miss rate for demand accesses
1051system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022499 # miss rate for overall accesses
1052system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049781 # miss rate for overall accesses
1053system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078068 # miss rate for overall accesses
1054system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253734 # miss rate for overall accesses
1055system.cpu0.l2cache.overall_miss_rate::total 0.132291 # miss rate for overall accesses
1056system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average ReadReq miss latency
1057system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39062.072573 # average ReadReq miss latency
1058system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30218.617556 # average ReadReq miss latency
1059system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34073.109321 # average ReadReq miss latency
1060system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32452.281589 # average ReadReq miss latency
1061system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 364.515205 # average WriteInvalidateReq miss latency
1062system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 364.515205 # average WriteInvalidateReq miss latency
1063system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21901.534114 # average UpgradeReq miss latency
1064system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21901.534114 # average UpgradeReq miss latency
1065system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20739.632883 # average SCUpgradeReq miss latency
1066system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20739.632883 # average SCUpgradeReq miss latency
1067system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 829749.500000 # average SCUpgradeFailReq miss latency
1068system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 829749.500000 # average SCUpgradeFailReq miss latency
1069system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50791.693516 # average ReadExReq miss latency
1070system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50791.693516 # average ReadExReq miss latency
1071system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average overall miss latency
1072system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39062.072573 # average overall miss latency
1073system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30218.617556 # average overall miss latency
1074system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37486.931343 # average overall miss latency
1075system.cpu0.l2cache.demand_avg_miss_latency::total 34756.141139 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35896.913706 # average overall miss latency
1077system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39062.072573 # average overall miss latency
1078system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30218.617556 # average overall miss latency
1079system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37486.931343 # average overall miss latency
1080system.cpu0.l2cache.overall_avg_miss_latency::total 34756.141139 # average overall miss latency
1081system.cpu0.l2cache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
1082system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1083system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1084system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1085system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked
1086system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1087system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1088system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1089system.cpu0.l2cache.writebacks::writebacks 1439553 # number of writebacks
1090system.cpu0.l2cache.writebacks::total 1439553 # number of writebacks
1091system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits
1092system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 11 # number of ReadReq MSHR hits
1093system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 1023 # number of ReadReq MSHR hits
1094system.cpu0.l2cache.ReadReq_mshr_hits::total 1037 # number of ReadReq MSHR hits
1095system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 27 # number of WriteInvalidateReq MSHR hits
1096system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 27 # number of WriteInvalidateReq MSHR hits
1097system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 8712 # number of ReadExReq MSHR hits
1098system.cpu0.l2cache.ReadExReq_mshr_hits::total 8712 # number of ReadExReq MSHR hits
1099system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits
1100system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
1101system.cpu0.l2cache.demand_mshr_hits::cpu0.data 9735 # number of demand (read+write) MSHR hits
1102system.cpu0.l2cache.demand_mshr_hits::total 9749 # number of demand (read+write) MSHR hits
1103system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits
1104system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
1105system.cpu0.l2cache.overall_mshr_hits::cpu0.data 9735 # number of overall MSHR hits
1106system.cpu0.l2cache.overall_mshr_hits::total 9749 # number of overall MSHR hits
1107system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12017 # number of ReadReq MSHR misses
1108system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses
1109system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 803330 # number of ReadReq MSHR misses
1110system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1046920 # number of ReadReq MSHR misses
1111system.cpu0.l2cache.ReadReq_mshr_misses::total 1870504 # number of ReadReq MSHR misses
1112system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 757617 # number of HardPFReq MSHR misses
1113system.cpu0.l2cache.HardPFReq_mshr_misses::total 757617 # number of HardPFReq MSHR misses
1114system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 596190 # number of WriteInvalidateReq MSHR misses
1115system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 596190 # number of WriteInvalidateReq MSHR misses
1116system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 136954 # number of UpgradeReq MSHR misses
1117system.cpu0.l2cache.UpgradeReq_mshr_misses::total 136954 # number of UpgradeReq MSHR misses
1118system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 166233 # number of SCUpgradeReq MSHR misses
1119system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 166233 # number of SCUpgradeReq MSHR misses
1120system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
1121system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1122system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 260176 # number of ReadExReq MSHR misses
1123system.cpu0.l2cache.ReadExReq_mshr_misses::total 260176 # number of ReadExReq MSHR misses
1124system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12017 # number of demand (read+write) MSHR misses
1125system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses
1126system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 803330 # number of demand (read+write) MSHR misses
1127system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1307096 # number of demand (read+write) MSHR misses
1128system.cpu0.l2cache.demand_mshr_misses::total 2130680 # number of demand (read+write) MSHR misses
1129system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12017 # number of overall MSHR misses
1130system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses
1131system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 803330 # number of overall MSHR misses
1132system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1307096 # number of overall MSHR misses
1133system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 757617 # number of overall MSHR misses
1134system.cpu0.l2cache.overall_mshr_misses::total 2888297 # number of overall MSHR misses
1135system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable
1136system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31604 # number of ReadReq MSHR uncacheable
1137system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83911 # number of ReadReq MSHR uncacheable
1138system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable
1139system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 30977 # number of WriteReq MSHR uncacheable
1140system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses
1141system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62581 # number of overall MSHR uncacheable misses
1142system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 114888 # number of overall MSHR uncacheable misses
1143system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of ReadReq MSHR miss cycles
1144system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 267790036 # number of ReadReq MSHR miss cycles
1145system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 19027435054 # number of ReadReq MSHR miss cycles
1146system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 28762264327 # number of ReadReq MSHR miss cycles
1147system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48410165203 # number of ReadReq MSHR miss cycles
1148system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36487468285 # number of HardPFReq MSHR miss cycles
1149system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36487468285 # number of HardPFReq MSHR miss cycles
1150system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 26018290315 # number of WriteInvalidateReq MSHR miss cycles
1151system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 26018290315 # number of WriteInvalidateReq MSHR miss cycles
1152system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2786437286 # number of UpgradeReq MSHR miss cycles
1153system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2786437286 # number of UpgradeReq MSHR miss cycles
1154system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2450969244 # number of SCUpgradeReq MSHR miss cycles
1155system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2450969244 # number of SCUpgradeReq MSHR miss cycles
1156system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1425499 # number of SCUpgradeFailReq MSHR miss cycles
1157system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1425499 # number of SCUpgradeFailReq MSHR miss cycles
1158system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10771329997 # number of ReadExReq MSHR miss cycles
1159system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10771329997 # number of ReadExReq MSHR miss cycles
1160system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of demand (read+write) MSHR miss cycles
1161system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 267790036 # number of demand (read+write) MSHR miss cycles
1162system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19027435054 # number of demand (read+write) MSHR miss cycles
1163system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39533594324 # number of demand (read+write) MSHR miss cycles
1164system.cpu0.l2cache.demand_mshr_miss_latency::total 59181495200 # number of demand (read+write) MSHR miss cycles
1165system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 352675786 # number of overall MSHR miss cycles
1166system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 267790036 # number of overall MSHR miss cycles
1167system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19027435054 # number of overall MSHR miss cycles
1168system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39533594324 # number of overall MSHR miss cycles
1169system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36487468285 # number of overall MSHR miss cycles
1170system.cpu0.l2cache.overall_mshr_miss_latency::total 95668963485 # number of overall MSHR miss cycles
1171system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles
1172system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5359743750 # number of ReadReq MSHR uncacheable cycles
1173system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9750814500 # number of ReadReq MSHR uncacheable cycles
1174system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5053047499 # number of WriteReq MSHR uncacheable cycles
1175system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5053047499 # number of WriteReq MSHR uncacheable cycles
1176system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles
1177system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10412791249 # number of overall MSHR uncacheable cycles
1178system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14803861999 # number of overall MSHR uncacheable cycles
1179system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for ReadReq accesses
1180system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for ReadReq accesses
1181system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for ReadReq accesses
1182system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.262156 # mshr miss rate for ReadReq accesses
1183system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.124838 # mshr miss rate for ReadReq accesses
1184system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1185system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1186system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.730368 # mshr miss rate for WriteInvalidateReq accesses
1187system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.730368 # mshr miss rate for WriteInvalidateReq accesses
1188system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.568064 # mshr miss rate for UpgradeReq accesses
1189system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.568064 # mshr miss rate for UpgradeReq accesses
1190system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.821496 # mshr miss rate for SCUpgradeReq accesses
1191system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.821496 # mshr miss rate for SCUpgradeReq accesses
1192system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1193system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1194system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.217482 # mshr miss rate for ReadExReq accesses
1195system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.217482 # mshr miss rate for ReadExReq accesses
1196system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for demand accesses
1197system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for demand accesses
1198system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for demand accesses
1199system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for demand accesses
1200system.cpu0.l2cache.demand_mshr_miss_rate::total 0.131688 # mshr miss rate for demand accesses
1201system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022499 # mshr miss rate for overall accesses
1202system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049763 # mshr miss rate for overall accesses
1203system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078067 # mshr miss rate for overall accesses
1204system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251858 # mshr miss rate for overall accesses
1205system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1206system.cpu0.l2cache.overall_mshr_miss_rate::total 0.178514 # mshr miss rate for overall accesses
1207system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average ReadReq mshr miss latency
1208system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average ReadReq mshr miss latency
1209system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average ReadReq mshr miss latency
1210system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27473.220807 # average ReadReq mshr miss latency
1211system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25880.813515 # average ReadReq mshr miss latency
1212system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average HardPFReq mshr miss latency
1213system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48160.836260 # average HardPFReq mshr miss latency
1214system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43640.937143 # average WriteInvalidateReq mshr miss latency
1215system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43640.937143 # average WriteInvalidateReq mshr miss latency
1216system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20345.789725 # average UpgradeReq mshr miss latency
1217system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20345.789725 # average UpgradeReq mshr miss latency
1218system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14744.179820 # average SCUpgradeReq mshr miss latency
1219system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14744.179820 # average SCUpgradeReq mshr miss latency
1220system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 712749.500000 # average SCUpgradeFailReq mshr miss latency
1221system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 712749.500000 # average SCUpgradeFailReq mshr miss latency
1222system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41400.167567 # average ReadExReq mshr miss latency
1223system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41400.167567 # average ReadExReq mshr miss latency
1224system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency
1225system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency
1226system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency
1227system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency
1228system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27775.872116 # average overall mshr miss latency
1229system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29348.072397 # average overall mshr miss latency
1230system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 32510.627170 # average overall mshr miss latency
1231system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23685.702083 # average overall mshr miss latency
1232system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30245.364016 # average overall mshr miss latency
1233system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48160.836260 # average overall mshr miss latency
1234system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33122.966054 # average overall mshr miss latency
1235system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency
1236system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169590.676813 # average ReadReq mshr uncacheable latency
1237system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 116204.246166 # average ReadReq mshr uncacheable latency
1238system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163122.558640 # average WriteReq mshr uncacheable latency
1239system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163122.558640 # average WriteReq mshr uncacheable latency
1240system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency
1241system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 166389.019814 # average overall mshr uncacheable latency
1242system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 128854.728074 # average overall mshr uncacheable latency
1243system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1244system.cpu0.toL2Bus.trans_dist::ReadReq 17664917 # Transaction distribution
1245system.cpu0.toL2Bus.trans_dist::ReadResp 15307376 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution
1247system.cpu0.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution
1248system.cpu0.toL2Bus.trans_dist::Writeback 3966591 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::HardPFReq 1103078 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
1251system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166462 # Transaction distribution
1252system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 816287 # Transaction distribution
1253system.cpu0.toL2Bus.trans_dist::UpgradeReq 481802 # Transaction distribution
1254system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368927 # Transaction distribution
1255system.cpu0.toL2Bus.trans_dist::UpgradeResp 516230 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
1257system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution
1258system.cpu0.toL2Bus.trans_dist::ReadExReq 1338230 # Transaction distribution
1259system.cpu0.toL2Bus.trans_dist::ReadExResp 1206066 # Transaction distribution
1260system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20685127 # Packet count per connected master and slave (bytes)
1261system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17177406 # Packet count per connected master and slave (bytes)
1262system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 364539 # Packet count per connected master and slave (bytes)
1263system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170846 # Packet count per connected master and slave (bytes)
1264system.cpu0.toL2Bus.pkt_count::total 39397918 # Packet count per connected master and slave (bytes)
1265system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 661924032 # Cumulative packet size per connected master and slave (bytes)
1266system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645723507 # Cumulative packet size per connected master and slave (bytes)
1267system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1324200 # Cumulative packet size per connected master and slave (bytes)
1268system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4272848 # Cumulative packet size per connected master and slave (bytes)
1269system.cpu0.toL2Bus.pkt_size::total 1313244587 # Cumulative packet size per connected master and slave (bytes)
1270system.cpu0.toL2Bus.snoops 4794163 # Total snoops (count)
1271system.cpu0.toL2Bus.snoop_fanout::samples 26128529 # Request fanout histogram
1272system.cpu0.toL2Bus.snoop_fanout::mean 1.203121 # Request fanout histogram
1273system.cpu0.toL2Bus.snoop_fanout::stdev 0.402322 # Request fanout histogram
1274system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1275system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1276system.cpu0.toL2Bus.snoop_fanout::1 20821287 79.69% 79.69% # Request fanout histogram
1277system.cpu0.toL2Bus.snoop_fanout::2 5307242 20.31% 100.00% # Request fanout histogram
1278system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1279system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1280system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1281system.cpu0.toL2Bus.snoop_fanout::total 26128529 # Request fanout histogram
1282system.cpu0.toL2Bus.reqLayer0.occupancy 15626998682 # Layer occupancy (ticks)
1283system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1284system.cpu0.toL2Bus.snoopLayer0.occupancy 207003480 # Layer occupancy (ticks)
1285system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1286system.cpu0.toL2Bus.respLayer0.occupancy 15540735463 # Layer occupancy (ticks)
1287system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1288system.cpu0.toL2Bus.respLayer1.occupancy 8534595583 # Layer occupancy (ticks)
1289system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1290system.cpu0.toL2Bus.respLayer2.occupancy 199309237 # Layer occupancy (ticks)
1291system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1292system.cpu0.toL2Bus.respLayer3.occupancy 637104704 # Layer occupancy (ticks)
1293system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1294system.cpu1.branchPred.lookups 125576312 # Number of BP lookups
1295system.cpu1.branchPred.condPredicted 90437850 # Number of conditional branches predicted
1296system.cpu1.branchPred.condIncorrect 5588126 # Number of conditional branches incorrect
1297system.cpu1.branchPred.BTBLookups 96414800 # Number of BTB lookups
1298system.cpu1.branchPred.BTBHits 70448335 # Number of BTB hits
1299system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1300system.cpu1.branchPred.BTBHitPct 73.067968 # BTB Hit Percentage
1301system.cpu1.branchPred.usedRAS 14240452 # Number of times the RAS was used to get a target.
1302system.cpu1.branchPred.RASInCorrect 921306 # Number of incorrect RAS predictions.
1303system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1304system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1305system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1306system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1307system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1308system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1310system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1324system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1325system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1326system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1327system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1328system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1329system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1330system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1331system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1332system.cpu1.dtb.walker.walks 267188 # Table walker walks requested
1333system.cpu1.dtb.walker.walksLong 267188 # Table walker walks initiated with long descriptors
1334system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10577 # Level at which table walker walks with long descriptors terminate
1335system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85745 # Level at which table walker walks with long descriptors terminate
1336system.cpu1.dtb.walker.walkWaitTime::samples 267188 # Table walker wait (enqueue to first request) latency
1337system.cpu1.dtb.walker.walkWaitTime::0 267188 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1338system.cpu1.dtb.walker.walkWaitTime::total 267188 # Table walker wait (enqueue to first request) latency
1339system.cpu1.dtb.walker.walkCompletionTime::samples 96322 # Table walker service (enqueue to completion) latency
1340system.cpu1.dtb.walker.walkCompletionTime::mean 19417.832759 # Table walker service (enqueue to completion) latency
1341system.cpu1.dtb.walker.walkCompletionTime::gmean 17582.202051 # Table walker service (enqueue to completion) latency
1342system.cpu1.dtb.walker.walkCompletionTime::stdev 14852.958051 # Table walker service (enqueue to completion) latency
1343system.cpu1.dtb.walker.walkCompletionTime::0-32767 91721 95.22% 95.22% # Table walker service (enqueue to completion) latency
1344system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3398 3.53% 98.75% # Table walker service (enqueue to completion) latency
1345system.cpu1.dtb.walker.walkCompletionTime::65536-98303 602 0.62% 99.38% # Table walker service (enqueue to completion) latency
1346system.cpu1.dtb.walker.walkCompletionTime::98304-131071 416 0.43% 99.81% # Table walker service (enqueue to completion) latency
1347system.cpu1.dtb.walker.walkCompletionTime::131072-163839 24 0.02% 99.83% # Table walker service (enqueue to completion) latency
1348system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.02% 99.86% # Table walker service (enqueue to completion) latency
1349system.cpu1.dtb.walker.walkCompletionTime::196608-229375 36 0.04% 99.90% # Table walker service (enqueue to completion) latency
1350system.cpu1.dtb.walker.walkCompletionTime::229376-262143 19 0.02% 99.91% # Table walker service (enqueue to completion) latency
1351system.cpu1.dtb.walker.walkCompletionTime::262144-294911 31 0.03% 99.95% # Table walker service (enqueue to completion) latency
1352system.cpu1.dtb.walker.walkCompletionTime::294912-327679 34 0.04% 99.98% # Table walker service (enqueue to completion) latency
1353system.cpu1.dtb.walker.walkCompletionTime::327680-360447 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
1354system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
1355system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1356system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1357system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1358system.cpu1.dtb.walker.walkCompletionTime::total 96322 # Table walker service (enqueue to completion) latency
1359system.cpu1.dtb.walker.walksPending::samples 1244507444 # Table walker pending requests distribution
1360system.cpu1.dtb.walker.walksPending::0 1244507444 100.00% 100.00% # Table walker pending requests distribution
1361system.cpu1.dtb.walker.walksPending::total 1244507444 # Table walker pending requests distribution
1362system.cpu1.dtb.walker.walkPageSizes::4K 85745 89.02% 89.02% # Table walker page sizes translated
1363system.cpu1.dtb.walker.walkPageSizes::2M 10577 10.98% 100.00% # Table walker page sizes translated
1364system.cpu1.dtb.walker.walkPageSizes::total 96322 # Table walker page sizes translated
1365system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 267188 # Table walker requests started/completed, data/inst
1366system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1367system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 267188 # Table walker requests started/completed, data/inst
1368system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 96322 # Table walker requests started/completed, data/inst
1369system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1370system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 96322 # Table walker requests started/completed, data/inst
1371system.cpu1.dtb.walker.walkRequestOrigin::total 363510 # Table walker requests started/completed, data/inst
1372system.cpu1.dtb.inst_hits 0 # ITB inst hits
1373system.cpu1.dtb.inst_misses 0 # ITB inst misses
1374system.cpu1.dtb.read_hits 79480191 # DTB read hits
1375system.cpu1.dtb.read_misses 220503 # DTB read misses
1376system.cpu1.dtb.write_hits 69950509 # DTB write hits
1377system.cpu1.dtb.write_misses 46685 # DTB write misses
1378system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1379system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1380system.cpu1.dtb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID
1381system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
1382system.cpu1.dtb.flush_entries 40279 # Number of entries that have been flushed from TLB
1383system.cpu1.dtb.align_faults 1007 # Number of TLB faults due to alignment restrictions
1384system.cpu1.dtb.prefetch_faults 7671 # Number of TLB faults due to prefetch
1385system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1386system.cpu1.dtb.perms_faults 12807 # Number of TLB faults due to permissions restrictions
1387system.cpu1.dtb.read_accesses 79700694 # DTB read accesses
1388system.cpu1.dtb.write_accesses 69997194 # DTB write accesses
1389system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1390system.cpu1.dtb.hits 149430700 # DTB hits
1391system.cpu1.dtb.misses 267188 # DTB misses
1392system.cpu1.dtb.accesses 149697888 # DTB accesses
1393system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1394system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1395system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1396system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1397system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1398system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1399system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1400system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1414system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1415system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1416system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1417system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1418system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1419system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1420system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1421system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1422system.cpu1.itb.walker.walks 64917 # Table walker walks requested
1423system.cpu1.itb.walker.walksLong 64917 # Table walker walks initiated with long descriptors
1424system.cpu1.itb.walker.walksLongTerminationLevel::Level2 645 # Level at which table walker walks with long descriptors terminate
1425system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55496 # Level at which table walker walks with long descriptors terminate
1426system.cpu1.itb.walker.walkWaitTime::samples 64917 # Table walker wait (enqueue to first request) latency
1427system.cpu1.itb.walker.walkWaitTime::0 64917 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1428system.cpu1.itb.walker.walkWaitTime::total 64917 # Table walker wait (enqueue to first request) latency
1429system.cpu1.itb.walker.walkCompletionTime::samples 56141 # Table walker service (enqueue to completion) latency
1430system.cpu1.itb.walker.walkCompletionTime::mean 22418.994977 # Table walker service (enqueue to completion) latency
1431system.cpu1.itb.walker.walkCompletionTime::gmean 19682.840516 # Table walker service (enqueue to completion) latency
1432system.cpu1.itb.walker.walkCompletionTime::stdev 19289.014659 # Table walker service (enqueue to completion) latency
1433system.cpu1.itb.walker.walkCompletionTime::0-65535 54677 97.39% 97.39% # Table walker service (enqueue to completion) latency
1434system.cpu1.itb.walker.walkCompletionTime::65536-131071 1297 2.31% 99.70% # Table walker service (enqueue to completion) latency
1435system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.79% # Table walker service (enqueue to completion) latency
1436system.cpu1.itb.walker.walkCompletionTime::196608-262143 81 0.14% 99.93% # Table walker service (enqueue to completion) latency
1437system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.96% # Table walker service (enqueue to completion) latency
1438system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.99% # Table walker service (enqueue to completion) latency
1439system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1440system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
1441system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1442system.cpu1.itb.walker.walkCompletionTime::total 56141 # Table walker service (enqueue to completion) latency
1443system.cpu1.itb.walker.walksPending::samples 1243919944 # Table walker pending requests distribution
1444system.cpu1.itb.walker.walksPending::0 1243919944 100.00% 100.00% # Table walker pending requests distribution
1445system.cpu1.itb.walker.walksPending::total 1243919944 # Table walker pending requests distribution
1446system.cpu1.itb.walker.walkPageSizes::4K 55496 98.85% 98.85% # Table walker page sizes translated
1447system.cpu1.itb.walker.walkPageSizes::2M 645 1.15% 100.00% # Table walker page sizes translated
1448system.cpu1.itb.walker.walkPageSizes::total 56141 # Table walker page sizes translated
1449system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1450system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64917 # Table walker requests started/completed, data/inst
1451system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64917 # Table walker requests started/completed, data/inst
1452system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1453system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56141 # Table walker requests started/completed, data/inst
1454system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56141 # Table walker requests started/completed, data/inst
1455system.cpu1.itb.walker.walkRequestOrigin::total 121058 # Table walker requests started/completed, data/inst
1456system.cpu1.itb.inst_hits 225481249 # ITB inst hits
1457system.cpu1.itb.inst_misses 64917 # ITB inst misses
1458system.cpu1.itb.read_hits 0 # DTB read hits
1459system.cpu1.itb.read_misses 0 # DTB read misses
1460system.cpu1.itb.write_hits 0 # DTB write hits
1461system.cpu1.itb.write_misses 0 # DTB write misses
1462system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1463system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1464system.cpu1.itb.flush_tlb_mva_asid 43363 # Number of times TLB was flushed by MVA & ASID
1465system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
1466system.cpu1.itb.flush_entries 28543 # Number of entries that have been flushed from TLB
1467system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1468system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1469system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1470system.cpu1.itb.perms_faults 202570 # Number of TLB faults due to permissions restrictions
1471system.cpu1.itb.read_accesses 0 # DTB read accesses
1472system.cpu1.itb.write_accesses 0 # DTB write accesses
1473system.cpu1.itb.inst_accesses 225546166 # ITB inst accesses
1474system.cpu1.itb.hits 225481249 # DTB hits
1475system.cpu1.itb.misses 64917 # DTB misses
1476system.cpu1.itb.accesses 225546166 # DTB accesses
1477system.cpu1.numCycles 849119079 # number of cpu cycles simulated
1478system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1479system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1480system.cpu1.committedInsts 406051299 # Number of instructions committed
1481system.cpu1.committedOps 478293699 # Number of ops (including micro ops) committed
1482system.cpu1.discardedOps 46606937 # Number of ops (including micro ops) which were discarded before commit
1483system.cpu1.numFetchSuspends 5644 # Number of times Execute suspended instruction fetching
1484system.cpu1.quiesceCycles 94106060514 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1485system.cpu1.cpi 2.091162 # CPI: cycles per instruction
1486system.cpu1.ipc 0.478203 # IPC: instructions per cycle
1487system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1488system.cpu1.kern.inst.quiesce 5757 # number of quiesce instructions executed
1489system.cpu1.tickCycles 666946808 # Number of cycles that the object actually ticked
1490system.cpu1.idleCycles 182172271 # Total number of cycles that the object has spent stopped
1491system.cpu1.dcache.tags.replacements 5052284 # number of replacements
1492system.cpu1.dcache.tags.tagsinuse 457.990994 # Cycle average of tags in use
1493system.cpu1.dcache.tags.total_refs 141727438 # Total number of references to valid blocks.
1494system.cpu1.dcache.tags.sampled_refs 5052796 # Sample count of references to valid blocks.
1495system.cpu1.dcache.tags.avg_refs 28.049309 # Average number of references to valid blocks.
1496system.cpu1.dcache.tags.warmup_cycle 8380007678500 # Cycle when the warmup percentage was hit.
1497system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.990994 # Average occupied blocks per requestor
1498system.cpu1.dcache.tags.occ_percent::cpu1.data 0.894514 # Average percentage of cache occupancy
1499system.cpu1.dcache.tags.occ_percent::total 0.894514 # Average percentage of cache occupancy
1500system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1501system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
1502system.cpu1.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
1503system.cpu1.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
1504system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1505system.cpu1.dcache.tags.tag_accesses 301466109 # Number of tag accesses
1506system.cpu1.dcache.tags.data_accesses 301466109 # Number of data accesses
1507system.cpu1.dcache.ReadReq_hits::cpu1.data 72704936 # number of ReadReq hits
1508system.cpu1.dcache.ReadReq_hits::total 72704936 # number of ReadReq hits
1509system.cpu1.dcache.WriteReq_hits::cpu1.data 65165576 # number of WriteReq hits
1510system.cpu1.dcache.WriteReq_hits::total 65165576 # number of WriteReq hits
1511system.cpu1.dcache.SoftPFReq_hits::cpu1.data 206723 # number of SoftPFReq hits
1512system.cpu1.dcache.SoftPFReq_hits::total 206723 # number of SoftPFReq hits
1513system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 46881 # number of WriteInvalidateReq hits
1514system.cpu1.dcache.WriteInvalidateReq_hits::total 46881 # number of WriteInvalidateReq hits
1515system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1586345 # number of LoadLockedReq hits
1516system.cpu1.dcache.LoadLockedReq_hits::total 1586345 # number of LoadLockedReq hits
1517system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1544117 # number of StoreCondReq hits
1518system.cpu1.dcache.StoreCondReq_hits::total 1544117 # number of StoreCondReq hits
1519system.cpu1.dcache.demand_hits::cpu1.data 137870512 # number of demand (read+write) hits
1520system.cpu1.dcache.demand_hits::total 137870512 # number of demand (read+write) hits
1521system.cpu1.dcache.overall_hits::cpu1.data 138077235 # number of overall hits
1522system.cpu1.dcache.overall_hits::total 138077235 # number of overall hits
1523system.cpu1.dcache.ReadReq_misses::cpu1.data 3207186 # number of ReadReq misses
1524system.cpu1.dcache.ReadReq_misses::total 3207186 # number of ReadReq misses
1525system.cpu1.dcache.WriteReq_misses::cpu1.data 2249159 # number of WriteReq misses
1526system.cpu1.dcache.WriteReq_misses::total 2249159 # number of WriteReq misses
1527system.cpu1.dcache.SoftPFReq_misses::cpu1.data 660232 # number of SoftPFReq misses
1528system.cpu1.dcache.SoftPFReq_misses::total 660232 # number of SoftPFReq misses
1529system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 426407 # number of WriteInvalidateReq misses
1530system.cpu1.dcache.WriteInvalidateReq_misses::total 426407 # number of WriteInvalidateReq misses
1531system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160976 # number of LoadLockedReq misses
1532system.cpu1.dcache.LoadLockedReq_misses::total 160976 # number of LoadLockedReq misses
1533system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201965 # number of StoreCondReq misses
1534system.cpu1.dcache.StoreCondReq_misses::total 201965 # number of StoreCondReq misses
1535system.cpu1.dcache.demand_misses::cpu1.data 5456345 # number of demand (read+write) misses
1536system.cpu1.dcache.demand_misses::total 5456345 # number of demand (read+write) misses
1537system.cpu1.dcache.overall_misses::cpu1.data 6116577 # number of overall misses
1538system.cpu1.dcache.overall_misses::total 6116577 # number of overall misses
1539system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 49733165026 # number of ReadReq miss cycles
1540system.cpu1.dcache.ReadReq_miss_latency::total 49733165026 # number of ReadReq miss cycles
1541system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39916128019 # number of WriteReq miss cycles
1542system.cpu1.dcache.WriteReq_miss_latency::total 39916128019 # number of WriteReq miss cycles
1543system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12105984043 # number of WriteInvalidateReq miss cycles
1544system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12105984043 # number of WriteInvalidateReq miss cycles
1545system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2535632453 # number of LoadLockedReq miss cycles
1546system.cpu1.dcache.LoadLockedReq_miss_latency::total 2535632453 # number of LoadLockedReq miss cycles
1547system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4276755567 # number of StoreCondReq miss cycles
1548system.cpu1.dcache.StoreCondReq_miss_latency::total 4276755567 # number of StoreCondReq miss cycles
1549system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1256500 # number of StoreCondFailReq miss cycles
1550system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1256500 # number of StoreCondFailReq miss cycles
1551system.cpu1.dcache.demand_miss_latency::cpu1.data 89649293045 # number of demand (read+write) miss cycles
1552system.cpu1.dcache.demand_miss_latency::total 89649293045 # number of demand (read+write) miss cycles
1553system.cpu1.dcache.overall_miss_latency::cpu1.data 89649293045 # number of overall miss cycles
1554system.cpu1.dcache.overall_miss_latency::total 89649293045 # number of overall miss cycles
1555system.cpu1.dcache.ReadReq_accesses::cpu1.data 75912122 # number of ReadReq accesses(hits+misses)
1556system.cpu1.dcache.ReadReq_accesses::total 75912122 # number of ReadReq accesses(hits+misses)
1557system.cpu1.dcache.WriteReq_accesses::cpu1.data 67414735 # number of WriteReq accesses(hits+misses)
1558system.cpu1.dcache.WriteReq_accesses::total 67414735 # number of WriteReq accesses(hits+misses)
1559system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 866955 # number of SoftPFReq accesses(hits+misses)
1560system.cpu1.dcache.SoftPFReq_accesses::total 866955 # number of SoftPFReq accesses(hits+misses)
1561system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 473288 # number of WriteInvalidateReq accesses(hits+misses)
1562system.cpu1.dcache.WriteInvalidateReq_accesses::total 473288 # number of WriteInvalidateReq accesses(hits+misses)
1563system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1747321 # number of LoadLockedReq accesses(hits+misses)
1564system.cpu1.dcache.LoadLockedReq_accesses::total 1747321 # number of LoadLockedReq accesses(hits+misses)
1565system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1746082 # number of StoreCondReq accesses(hits+misses)
1566system.cpu1.dcache.StoreCondReq_accesses::total 1746082 # number of StoreCondReq accesses(hits+misses)
1567system.cpu1.dcache.demand_accesses::cpu1.data 143326857 # number of demand (read+write) accesses
1568system.cpu1.dcache.demand_accesses::total 143326857 # number of demand (read+write) accesses
1569system.cpu1.dcache.overall_accesses::cpu1.data 144193812 # number of overall (read+write) accesses
1570system.cpu1.dcache.overall_accesses::total 144193812 # number of overall (read+write) accesses
1571system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.042249 # miss rate for ReadReq accesses
1572system.cpu1.dcache.ReadReq_miss_rate::total 0.042249 # miss rate for ReadReq accesses
1573system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033363 # miss rate for WriteReq accesses
1574system.cpu1.dcache.WriteReq_miss_rate::total 0.033363 # miss rate for WriteReq accesses
1575system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.761553 # miss rate for SoftPFReq accesses
1576system.cpu1.dcache.SoftPFReq_miss_rate::total 0.761553 # miss rate for SoftPFReq accesses
1577system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.900946 # miss rate for WriteInvalidateReq accesses
1578system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.900946 # miss rate for WriteInvalidateReq accesses
1579system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092127 # miss rate for LoadLockedReq accesses
1580system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092127 # miss rate for LoadLockedReq accesses
1581system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.115668 # miss rate for StoreCondReq accesses
1582system.cpu1.dcache.StoreCondReq_miss_rate::total 0.115668 # miss rate for StoreCondReq accesses
1583system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038069 # miss rate for demand accesses
1584system.cpu1.dcache.demand_miss_rate::total 0.038069 # miss rate for demand accesses
1585system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042419 # miss rate for overall accesses
1586system.cpu1.dcache.overall_miss_rate::total 0.042419 # miss rate for overall accesses
1587system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15506.791632 # average ReadReq miss latency
1588system.cpu1.dcache.ReadReq_avg_miss_latency::total 15506.791632 # average ReadReq miss latency
1589system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17747.134826 # average WriteReq miss latency
1590system.cpu1.dcache.WriteReq_avg_miss_latency::total 17747.134826 # average WriteReq miss latency
1591system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28390.678490 # average WriteInvalidateReq miss latency
1592system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 28390.678490 # average WriteInvalidateReq miss latency
1593system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15751.617962 # average LoadLockedReq miss latency
1594system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15751.617962 # average LoadLockedReq miss latency
1595system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21175.726324 # average StoreCondReq miss latency
1596system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21175.726324 # average StoreCondReq miss latency
1597system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1598system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1599system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16430.283101 # average overall miss latency
1600system.cpu1.dcache.demand_avg_miss_latency::total 16430.283101 # average overall miss latency
1601system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14656.775030 # average overall miss latency
1602system.cpu1.dcache.overall_avg_miss_latency::total 14656.775030 # average overall miss latency
1603system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1604system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1605system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1606system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1607system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1608system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1609system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1610system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1611system.cpu1.dcache.writebacks::writebacks 3294639 # number of writebacks
1612system.cpu1.dcache.writebacks::total 3294639 # number of writebacks
1613system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 376716 # number of ReadReq MSHR hits
1614system.cpu1.dcache.ReadReq_mshr_hits::total 376716 # number of ReadReq MSHR hits
1615system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 934861 # number of WriteReq MSHR hits
1616system.cpu1.dcache.WriteReq_mshr_hits::total 934861 # number of WriteReq MSHR hits
1617system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 50 # number of WriteInvalidateReq MSHR hits
1618system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 50 # number of WriteInvalidateReq MSHR hits
1619system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39920 # number of LoadLockedReq MSHR hits
1620system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39920 # number of LoadLockedReq MSHR hits
1621system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 26 # number of StoreCondReq MSHR hits
1622system.cpu1.dcache.StoreCondReq_mshr_hits::total 26 # number of StoreCondReq MSHR hits
1623system.cpu1.dcache.demand_mshr_hits::cpu1.data 1311577 # number of demand (read+write) MSHR hits
1624system.cpu1.dcache.demand_mshr_hits::total 1311577 # number of demand (read+write) MSHR hits
1625system.cpu1.dcache.overall_mshr_hits::cpu1.data 1311577 # number of overall MSHR hits
1626system.cpu1.dcache.overall_mshr_hits::total 1311577 # number of overall MSHR hits
1627system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2830470 # number of ReadReq MSHR misses
1628system.cpu1.dcache.ReadReq_mshr_misses::total 2830470 # number of ReadReq MSHR misses
1629system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1314298 # number of WriteReq MSHR misses
1630system.cpu1.dcache.WriteReq_mshr_misses::total 1314298 # number of WriteReq MSHR misses
1631system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659943 # number of SoftPFReq MSHR misses
1632system.cpu1.dcache.SoftPFReq_mshr_misses::total 659943 # number of SoftPFReq MSHR misses
1633system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 426357 # number of WriteInvalidateReq MSHR misses
1634system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 426357 # number of WriteInvalidateReq MSHR misses
1635system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 121056 # number of LoadLockedReq MSHR misses
1636system.cpu1.dcache.LoadLockedReq_mshr_misses::total 121056 # number of LoadLockedReq MSHR misses
1637system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 201939 # number of StoreCondReq MSHR misses
1638system.cpu1.dcache.StoreCondReq_mshr_misses::total 201939 # number of StoreCondReq MSHR misses
1639system.cpu1.dcache.demand_mshr_misses::cpu1.data 4144768 # number of demand (read+write) MSHR misses
1640system.cpu1.dcache.demand_mshr_misses::total 4144768 # number of demand (read+write) MSHR misses
1641system.cpu1.dcache.overall_mshr_misses::cpu1.data 4804711 # number of overall MSHR misses
1642system.cpu1.dcache.overall_mshr_misses::total 4804711 # number of overall MSHR misses
1643system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable
1644system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7026 # number of ReadReq MSHR uncacheable
1645system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable
1646system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable
1647system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses
1648system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14541 # number of overall MSHR uncacheable misses
1649system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38398702439 # number of ReadReq MSHR miss cycles
1650system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38398702439 # number of ReadReq MSHR miss cycles
1651system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21764603493 # number of WriteReq MSHR miss cycles
1652system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21764603493 # number of WriteReq MSHR miss cycles
1653system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13372610673 # number of SoftPFReq MSHR miss cycles
1654system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13372610673 # number of SoftPFReq MSHR miss cycles
1655system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11459992206 # number of WriteInvalidateReq MSHR miss cycles
1656system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11459992206 # number of WriteInvalidateReq MSHR miss cycles
1657system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1620200910 # number of LoadLockedReq MSHR miss cycles
1658system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1620200910 # number of LoadLockedReq MSHR miss cycles
1659system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3963729421 # number of StoreCondReq MSHR miss cycles
1660system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3963729421 # number of StoreCondReq MSHR miss cycles
1661system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1148000 # number of StoreCondFailReq MSHR miss cycles
1662system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1148000 # number of StoreCondFailReq MSHR miss cycles
1663system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60163305932 # number of demand (read+write) MSHR miss cycles
1664system.cpu1.dcache.demand_mshr_miss_latency::total 60163305932 # number of demand (read+write) MSHR miss cycles
1665system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73535916605 # number of overall MSHR miss cycles
1666system.cpu1.dcache.overall_mshr_miss_latency::total 73535916605 # number of overall MSHR miss cycles
1667system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 828088750 # number of ReadReq MSHR uncacheable cycles
1668system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 828088750 # number of ReadReq MSHR uncacheable cycles
1669system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 987688750 # number of WriteReq MSHR uncacheable cycles
1670system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 987688750 # number of WriteReq MSHR uncacheable cycles
1671system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1815777500 # number of overall MSHR uncacheable cycles
1672system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1815777500 # number of overall MSHR uncacheable cycles
1673system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037286 # mshr miss rate for ReadReq accesses
1674system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037286 # mshr miss rate for ReadReq accesses
1675system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019496 # mshr miss rate for WriteReq accesses
1676system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019496 # mshr miss rate for WriteReq accesses
1677system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761219 # mshr miss rate for SoftPFReq accesses
1678system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.761219 # mshr miss rate for SoftPFReq accesses
1679system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.900841 # mshr miss rate for WriteInvalidateReq accesses
1680system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.900841 # mshr miss rate for WriteInvalidateReq accesses
1681system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069281 # mshr miss rate for LoadLockedReq accesses
1682system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069281 # mshr miss rate for LoadLockedReq accesses
1683system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.115653 # mshr miss rate for StoreCondReq accesses
1684system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.115653 # mshr miss rate for StoreCondReq accesses
1685system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028918 # mshr miss rate for demand accesses
1686system.cpu1.dcache.demand_mshr_miss_rate::total 0.028918 # mshr miss rate for demand accesses
1687system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for overall accesses
1688system.cpu1.dcache.overall_mshr_miss_rate::total 0.033321 # mshr miss rate for overall accesses
1689system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13566.193049 # average ReadReq mshr miss latency
1690system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13566.193049 # average ReadReq mshr miss latency
1691system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16559.869598 # average WriteReq mshr miss latency
1692system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16559.869598 # average WriteReq mshr miss latency
1693system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20263.281333 # average SoftPFReq mshr miss latency
1694system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20263.281333 # average SoftPFReq mshr miss latency
1695system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26878.864909 # average WriteInvalidateReq mshr miss latency
1696system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26878.864909 # average WriteInvalidateReq mshr miss latency
1697system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13383.895966 # average LoadLockedReq mshr miss latency
1698system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13383.895966 # average LoadLockedReq mshr miss latency
1699system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19628.350249 # average StoreCondReq mshr miss latency
1700system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19628.350249 # average StoreCondReq mshr miss latency
1701system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1702system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1703system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14515.482153 # average overall mshr miss latency
1704system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14515.482153 # average overall mshr miss latency
1705system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15304.961444 # average overall mshr miss latency
1706system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15304.961444 # average overall mshr miss latency
1707system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117860.624822 # average ReadReq mshr uncacheable latency
1708system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 117860.624822 # average ReadReq mshr uncacheable latency
1709system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 131428.975383 # average WriteReq mshr uncacheable latency
1710system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 131428.975383 # average WriteReq mshr uncacheable latency
1711system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124872.945465 # average overall mshr uncacheable latency
1712system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124872.945465 # average overall mshr uncacheable latency
1713system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1714system.cpu1.icache.tags.replacements 8512500 # number of replacements
1715system.cpu1.icache.tags.tagsinuse 507.044267 # Cycle average of tags in use
1716system.cpu1.icache.tags.total_refs 216759728 # Total number of references to valid blocks.
1717system.cpu1.icache.tags.sampled_refs 8513012 # Sample count of references to valid blocks.
1718system.cpu1.icache.tags.avg_refs 25.462166 # Average number of references to valid blocks.
1719system.cpu1.icache.tags.warmup_cycle 8369990866500 # Cycle when the warmup percentage was hit.
1720system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.044267 # Average occupied blocks per requestor
1721system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990321 # Average percentage of cache occupancy
1722system.cpu1.icache.tags.occ_percent::total 0.990321 # Average percentage of cache occupancy
1723system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1724system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id
1725system.cpu1.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
1726system.cpu1.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
1727system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1728system.cpu1.icache.tags.tag_accesses 459058494 # Number of tag accesses
1729system.cpu1.icache.tags.data_accesses 459058494 # Number of data accesses
1730system.cpu1.icache.ReadReq_hits::cpu1.inst 216759728 # number of ReadReq hits
1731system.cpu1.icache.ReadReq_hits::total 216759728 # number of ReadReq hits
1732system.cpu1.icache.demand_hits::cpu1.inst 216759728 # number of demand (read+write) hits
1733system.cpu1.icache.demand_hits::total 216759728 # number of demand (read+write) hits
1734system.cpu1.icache.overall_hits::cpu1.inst 216759728 # number of overall hits
1735system.cpu1.icache.overall_hits::total 216759728 # number of overall hits
1736system.cpu1.icache.ReadReq_misses::cpu1.inst 8513013 # number of ReadReq misses
1737system.cpu1.icache.ReadReq_misses::total 8513013 # number of ReadReq misses
1738system.cpu1.icache.demand_misses::cpu1.inst 8513013 # number of demand (read+write) misses
1739system.cpu1.icache.demand_misses::total 8513013 # number of demand (read+write) misses
1740system.cpu1.icache.overall_misses::cpu1.inst 8513013 # number of overall misses
1741system.cpu1.icache.overall_misses::total 8513013 # number of overall misses
1742system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85304905568 # number of ReadReq miss cycles
1743system.cpu1.icache.ReadReq_miss_latency::total 85304905568 # number of ReadReq miss cycles
1744system.cpu1.icache.demand_miss_latency::cpu1.inst 85304905568 # number of demand (read+write) miss cycles
1745system.cpu1.icache.demand_miss_latency::total 85304905568 # number of demand (read+write) miss cycles
1746system.cpu1.icache.overall_miss_latency::cpu1.inst 85304905568 # number of overall miss cycles
1747system.cpu1.icache.overall_miss_latency::total 85304905568 # number of overall miss cycles
1748system.cpu1.icache.ReadReq_accesses::cpu1.inst 225272741 # number of ReadReq accesses(hits+misses)
1749system.cpu1.icache.ReadReq_accesses::total 225272741 # number of ReadReq accesses(hits+misses)
1750system.cpu1.icache.demand_accesses::cpu1.inst 225272741 # number of demand (read+write) accesses
1751system.cpu1.icache.demand_accesses::total 225272741 # number of demand (read+write) accesses
1752system.cpu1.icache.overall_accesses::cpu1.inst 225272741 # number of overall (read+write) accesses
1753system.cpu1.icache.overall_accesses::total 225272741 # number of overall (read+write) accesses
1754system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037790 # miss rate for ReadReq accesses
1755system.cpu1.icache.ReadReq_miss_rate::total 0.037790 # miss rate for ReadReq accesses
1756system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037790 # miss rate for demand accesses
1757system.cpu1.icache.demand_miss_rate::total 0.037790 # miss rate for demand accesses
1758system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037790 # miss rate for overall accesses
1759system.cpu1.icache.overall_miss_rate::total 0.037790 # miss rate for overall accesses
1760system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10020.530401 # average ReadReq miss latency
1761system.cpu1.icache.ReadReq_avg_miss_latency::total 10020.530401 # average ReadReq miss latency
1762system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency
1763system.cpu1.icache.demand_avg_miss_latency::total 10020.530401 # average overall miss latency
1764system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10020.530401 # average overall miss latency
1765system.cpu1.icache.overall_avg_miss_latency::total 10020.530401 # average overall miss latency
1766system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1767system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1768system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1769system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1770system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1771system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1772system.cpu1.icache.fast_writes 0 # number of fast writes performed
1773system.cpu1.icache.cache_copies 0 # number of cache copies performed
1774system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513013 # number of ReadReq MSHR misses
1775system.cpu1.icache.ReadReq_mshr_misses::total 8513013 # number of ReadReq MSHR misses
1776system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513013 # number of demand (read+write) MSHR misses
1777system.cpu1.icache.demand_mshr_misses::total 8513013 # number of demand (read+write) MSHR misses
1778system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513013 # number of overall MSHR misses
1779system.cpu1.icache.overall_mshr_misses::total 8513013 # number of overall MSHR misses
1780system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable
1781system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable
1782system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses
1783system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses
1784system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 76768195856 # number of ReadReq MSHR miss cycles
1785system.cpu1.icache.ReadReq_mshr_miss_latency::total 76768195856 # number of ReadReq MSHR miss cycles
1786system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 76768195856 # number of demand (read+write) MSHR miss cycles
1787system.cpu1.icache.demand_mshr_miss_latency::total 76768195856 # number of demand (read+write) MSHR miss cycles
1788system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 76768195856 # number of overall MSHR miss cycles
1789system.cpu1.icache.overall_mshr_miss_latency::total 76768195856 # number of overall MSHR miss cycles
1790system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8107000 # number of ReadReq MSHR uncacheable cycles
1791system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8107000 # number of ReadReq MSHR uncacheable cycles
1792system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8107000 # number of overall MSHR uncacheable cycles
1793system.cpu1.icache.overall_mshr_uncacheable_latency::total 8107000 # number of overall MSHR uncacheable cycles
1794system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for ReadReq accesses
1795system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037790 # mshr miss rate for ReadReq accesses
1796system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for demand accesses
1797system.cpu1.icache.demand_mshr_miss_rate::total 0.037790 # mshr miss rate for demand accesses
1798system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037790 # mshr miss rate for overall accesses
1799system.cpu1.icache.overall_mshr_miss_rate::total 0.037790 # mshr miss rate for overall accesses
1800system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average ReadReq mshr miss latency
1801system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9017.746814 # average ReadReq mshr miss latency
1802system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency
1803system.cpu1.icache.demand_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency
1804system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9017.746814 # average overall mshr miss latency
1805system.cpu1.icache.overall_avg_mshr_miss_latency::total 9017.746814 # average overall mshr miss latency
1806system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average ReadReq mshr uncacheable latency
1807system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90077.777778 # average ReadReq mshr uncacheable latency
1808system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90077.777778 # average overall mshr uncacheable latency
1809system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90077.777778 # average overall mshr uncacheable latency
1810system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1811system.cpu1.l2cache.prefetcher.num_hwpf_issued 7158191 # number of hwpf issued
1812system.cpu1.l2cache.prefetcher.pfIdentified 7159863 # number of prefetch candidates identified
1813system.cpu1.l2cache.prefetcher.pfBufferHit 1351 # number of redundant prefetches already in prefetch queue
1814system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1815system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1816system.cpu1.l2cache.prefetcher.pfSpanPage 847001 # number of prefetches not generated due to page crossing
1817system.cpu1.l2cache.tags.replacements 2383886 # number of replacements
1818system.cpu1.l2cache.tags.tagsinuse 13587.340153 # Cycle average of tags in use
1819system.cpu1.l2cache.tags.total_refs 13938188 # Total number of references to valid blocks.
1820system.cpu1.l2cache.tags.sampled_refs 2400056 # Sample count of references to valid blocks.
1821system.cpu1.l2cache.tags.avg_refs 5.807443 # Average number of references to valid blocks.
1822system.cpu1.l2cache.tags.warmup_cycle 10048790087250 # Cycle when the warmup percentage was hit.
1823system.cpu1.l2cache.tags.occ_blocks::writebacks 4939.758457 # Average occupied blocks per requestor
1824system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 75.017087 # Average occupied blocks per requestor
1825system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 74.049784 # Average occupied blocks per requestor
1826system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4551.314512 # Average occupied blocks per requestor
1827system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3187.549823 # Average occupied blocks per requestor
1828system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 759.650489 # Average occupied blocks per requestor
1829system.cpu1.l2cache.tags.occ_percent::writebacks 0.301499 # Average percentage of cache occupancy
1830system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004579 # Average percentage of cache occupancy
1831system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004520 # Average percentage of cache occupancy
1832system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.277790 # Average percentage of cache occupancy
1833system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.194553 # Average percentage of cache occupancy
1834system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046365 # Average percentage of cache occupancy
1835system.cpu1.l2cache.tags.occ_percent::total 0.829305 # Average percentage of cache occupancy
1836system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1323 # Occupied blocks per task id
1837system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id
1838system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14780 # Occupied blocks per task id
1839system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 42 # Occupied blocks per task id
1840system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id
1841system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 433 # Occupied blocks per task id
1842system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 562 # Occupied blocks per task id
1843system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
1844system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
1845system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
1846system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
1847system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
1848system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1093 # Occupied blocks per task id
1849system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4947 # Occupied blocks per task id
1850system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2638 # Occupied blocks per task id
1851system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5915 # Occupied blocks per task id
1852system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080750 # Percentage of cache occupancy per task id
1853system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id
1854system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.902100 # Percentage of cache occupancy per task id
1855system.cpu1.l2cache.tags.tag_accesses 292928618 # Number of tag accesses
1856system.cpu1.l2cache.tags.data_accesses 292928618 # Number of data accesses
1857system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 489959 # number of ReadReq hits
1858system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155192 # number of ReadReq hits
1859system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7753793 # number of ReadReq hits
1860system.cpu1.l2cache.ReadReq_hits::cpu1.data 2612837 # number of ReadReq hits
1861system.cpu1.l2cache.ReadReq_hits::total 11011781 # number of ReadReq hits
1862system.cpu1.l2cache.Writeback_hits::writebacks 3294638 # number of Writeback hits
1863system.cpu1.l2cache.Writeback_hits::total 3294638 # number of Writeback hits
1864system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 173190 # number of WriteInvalidateReq hits
1865system.cpu1.l2cache.WriteInvalidateReq_hits::total 173190 # number of WriteInvalidateReq hits
1866system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70896 # number of UpgradeReq hits
1867system.cpu1.l2cache.UpgradeReq_hits::total 70896 # number of UpgradeReq hits
1868system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35338 # number of SCUpgradeReq hits
1869system.cpu1.l2cache.SCUpgradeReq_hits::total 35338 # number of SCUpgradeReq hits
1870system.cpu1.l2cache.ReadExReq_hits::cpu1.data 862674 # number of ReadExReq hits
1871system.cpu1.l2cache.ReadExReq_hits::total 862674 # number of ReadExReq hits
1872system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 489959 # number of demand (read+write) hits
1873system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155192 # number of demand (read+write) hits
1874system.cpu1.l2cache.demand_hits::cpu1.inst 7753793 # number of demand (read+write) hits
1875system.cpu1.l2cache.demand_hits::cpu1.data 3475511 # number of demand (read+write) hits
1876system.cpu1.l2cache.demand_hits::total 11874455 # number of demand (read+write) hits
1877system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 489959 # number of overall hits
1878system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155192 # number of overall hits
1879system.cpu1.l2cache.overall_hits::cpu1.inst 7753793 # number of overall hits
1880system.cpu1.l2cache.overall_hits::cpu1.data 3475511 # number of overall hits
1881system.cpu1.l2cache.overall_hits::total 11874455 # number of overall hits
1882system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11727 # number of ReadReq misses
1883system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8782 # number of ReadReq misses
1884system.cpu1.l2cache.ReadReq_misses::cpu1.inst 759220 # number of ReadReq misses
1885system.cpu1.l2cache.ReadReq_misses::cpu1.data 998421 # number of ReadReq misses
1886system.cpu1.l2cache.ReadReq_misses::total 1778150 # number of ReadReq misses
1887system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 251764 # number of WriteInvalidateReq misses
1888system.cpu1.l2cache.WriteInvalidateReq_misses::total 251764 # number of WriteInvalidateReq misses
1889system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 136318 # number of UpgradeReq misses
1890system.cpu1.l2cache.UpgradeReq_misses::total 136318 # number of UpgradeReq misses
1891system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166600 # number of SCUpgradeReq misses
1892system.cpu1.l2cache.SCUpgradeReq_misses::total 166600 # number of SCUpgradeReq misses
1893system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
1894system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1895system.cpu1.l2cache.ReadExReq_misses::cpu1.data 246181 # number of ReadExReq misses
1896system.cpu1.l2cache.ReadExReq_misses::total 246181 # number of ReadExReq misses
1897system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11727 # number of demand (read+write) misses
1898system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8782 # number of demand (read+write) misses
1899system.cpu1.l2cache.demand_misses::cpu1.inst 759220 # number of demand (read+write) misses
1900system.cpu1.l2cache.demand_misses::cpu1.data 1244602 # number of demand (read+write) misses
1901system.cpu1.l2cache.demand_misses::total 2024331 # number of demand (read+write) misses
1902system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11727 # number of overall misses
1903system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8782 # number of overall misses
1904system.cpu1.l2cache.overall_misses::cpu1.inst 759220 # number of overall misses
1905system.cpu1.l2cache.overall_misses::cpu1.data 1244602 # number of overall misses
1906system.cpu1.l2cache.overall_misses::total 2024331 # number of overall misses
1907system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 449146209 # number of ReadReq miss cycles
1908system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 373707270 # number of ReadReq miss cycles
1909system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22071218543 # number of ReadReq miss cycles
1910system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 32673719778 # number of ReadReq miss cycles
1911system.cpu1.l2cache.ReadReq_miss_latency::total 55567791800 # number of ReadReq miss cycles
1912system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 216255594 # number of WriteInvalidateReq miss cycles
1913system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 216255594 # number of WriteInvalidateReq miss cycles
1914system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2967566092 # number of UpgradeReq miss cycles
1915system.cpu1.l2cache.UpgradeReq_miss_latency::total 2967566092 # number of UpgradeReq miss cycles
1916system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3447328545 # number of SCUpgradeReq miss cycles
1917system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3447328545 # number of SCUpgradeReq miss cycles
1918system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1119500 # number of SCUpgradeFailReq miss cycles
1919system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1119500 # number of SCUpgradeFailReq miss cycles
1920system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10839077173 # number of ReadExReq miss cycles
1921system.cpu1.l2cache.ReadExReq_miss_latency::total 10839077173 # number of ReadExReq miss cycles
1922system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 449146209 # number of demand (read+write) miss cycles
1923system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 373707270 # number of demand (read+write) miss cycles
1924system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22071218543 # number of demand (read+write) miss cycles
1925system.cpu1.l2cache.demand_miss_latency::cpu1.data 43512796951 # number of demand (read+write) miss cycles
1926system.cpu1.l2cache.demand_miss_latency::total 66406868973 # number of demand (read+write) miss cycles
1927system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449146209 # number of overall miss cycles
1928system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 373707270 # number of overall miss cycles
1929system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22071218543 # number of overall miss cycles
1930system.cpu1.l2cache.overall_miss_latency::cpu1.data 43512796951 # number of overall miss cycles
1931system.cpu1.l2cache.overall_miss_latency::total 66406868973 # number of overall miss cycles
1932system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 501686 # number of ReadReq accesses(hits+misses)
1933system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 163974 # number of ReadReq accesses(hits+misses)
1934system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513013 # number of ReadReq accesses(hits+misses)
1935system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3611258 # number of ReadReq accesses(hits+misses)
1936system.cpu1.l2cache.ReadReq_accesses::total 12789931 # number of ReadReq accesses(hits+misses)
1937system.cpu1.l2cache.Writeback_accesses::writebacks 3294638 # number of Writeback accesses(hits+misses)
1938system.cpu1.l2cache.Writeback_accesses::total 3294638 # number of Writeback accesses(hits+misses)
1939system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 424954 # number of WriteInvalidateReq accesses(hits+misses)
1940system.cpu1.l2cache.WriteInvalidateReq_accesses::total 424954 # number of WriteInvalidateReq accesses(hits+misses)
1941system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 207214 # number of UpgradeReq accesses(hits+misses)
1942system.cpu1.l2cache.UpgradeReq_accesses::total 207214 # number of UpgradeReq accesses(hits+misses)
1943system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 201938 # number of SCUpgradeReq accesses(hits+misses)
1944system.cpu1.l2cache.SCUpgradeReq_accesses::total 201938 # number of SCUpgradeReq accesses(hits+misses)
1945system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1946system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1947system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1108855 # number of ReadExReq accesses(hits+misses)
1948system.cpu1.l2cache.ReadExReq_accesses::total 1108855 # number of ReadExReq accesses(hits+misses)
1949system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 501686 # number of demand (read+write) accesses
1950system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 163974 # number of demand (read+write) accesses
1951system.cpu1.l2cache.demand_accesses::cpu1.inst 8513013 # number of demand (read+write) accesses
1952system.cpu1.l2cache.demand_accesses::cpu1.data 4720113 # number of demand (read+write) accesses
1953system.cpu1.l2cache.demand_accesses::total 13898786 # number of demand (read+write) accesses
1954system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 501686 # number of overall (read+write) accesses
1955system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163974 # number of overall (read+write) accesses
1956system.cpu1.l2cache.overall_accesses::cpu1.inst 8513013 # number of overall (read+write) accesses
1957system.cpu1.l2cache.overall_accesses::cpu1.data 4720113 # number of overall (read+write) accesses
1958system.cpu1.l2cache.overall_accesses::total 13898786 # number of overall (read+write) accesses
1959system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for ReadReq accesses
1960system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053557 # miss rate for ReadReq accesses
1961system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.089183 # miss rate for ReadReq accesses
1962system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.276475 # miss rate for ReadReq accesses
1963system.cpu1.l2cache.ReadReq_miss_rate::total 0.139027 # miss rate for ReadReq accesses
1964system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.592450 # miss rate for WriteInvalidateReq accesses
1965system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.592450 # miss rate for WriteInvalidateReq accesses
1966system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.657861 # miss rate for UpgradeReq accesses
1967system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.657861 # miss rate for UpgradeReq accesses
1968system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825006 # miss rate for SCUpgradeReq accesses
1969system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825006 # miss rate for SCUpgradeReq accesses
1970system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1971system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1972system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.222014 # miss rate for ReadExReq accesses
1973system.cpu1.l2cache.ReadExReq_miss_rate::total 0.222014 # miss rate for ReadExReq accesses
1974system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for demand accesses
1975system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053557 # miss rate for demand accesses
1976system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.089183 # miss rate for demand accesses
1977system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.263681 # miss rate for demand accesses
1978system.cpu1.l2cache.demand_miss_rate::total 0.145648 # miss rate for demand accesses
1979system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023375 # miss rate for overall accesses
1980system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053557 # miss rate for overall accesses
1981system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.089183 # miss rate for overall accesses
1982system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.263681 # miss rate for overall accesses
1983system.cpu1.l2cache.overall_miss_rate::total 0.145648 # miss rate for overall accesses
1984system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average ReadReq miss latency
1985system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42553.777044 # average ReadReq miss latency
1986system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29070.912967 # average ReadReq miss latency
1987system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32725.393174 # average ReadReq miss latency
1988system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31250.339848 # average ReadReq miss latency
1989system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 858.961543 # average WriteInvalidateReq miss latency
1990system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 858.961543 # average WriteInvalidateReq miss latency
1991system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21769.436846 # average UpgradeReq miss latency
1992system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21769.436846 # average UpgradeReq miss latency
1993system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20692.248169 # average SCUpgradeReq miss latency
1994system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20692.248169 # average SCUpgradeReq miss latency
1995system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1119500 # average SCUpgradeFailReq miss latency
1996system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1119500 # average SCUpgradeFailReq miss latency
1997system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44028.894078 # average ReadExReq miss latency
1998system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44028.894078 # average ReadExReq miss latency
1999system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average overall miss latency
2000system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42553.777044 # average overall miss latency
2001system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29070.912967 # average overall miss latency
2002system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34961.214068 # average overall miss latency
2003system.cpu1.l2cache.demand_avg_miss_latency::total 32804.353129 # average overall miss latency
2004system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38300.179841 # average overall miss latency
2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42553.777044 # average overall miss latency
2006system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29070.912967 # average overall miss latency
2007system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34961.214068 # average overall miss latency
2008system.cpu1.l2cache.overall_avg_miss_latency::total 32804.353129 # average overall miss latency
2009system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2010system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2011system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2012system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2013system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2014system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2015system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2016system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2017system.cpu1.l2cache.writebacks::writebacks 1051021 # number of writebacks
2018system.cpu1.l2cache.writebacks::total 1051021 # number of writebacks
2019system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits
2020system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 699 # number of ReadReq MSHR hits
2021system.cpu1.l2cache.ReadReq_mshr_hits::total 701 # number of ReadReq MSHR hits
2022system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 6 # number of WriteInvalidateReq MSHR hits
2023system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits
2024system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 8312 # number of ReadExReq MSHR hits
2025system.cpu1.l2cache.ReadExReq_mshr_hits::total 8312 # number of ReadExReq MSHR hits
2026system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
2027system.cpu1.l2cache.demand_mshr_hits::cpu1.data 9011 # number of demand (read+write) MSHR hits
2028system.cpu1.l2cache.demand_mshr_hits::total 9013 # number of demand (read+write) MSHR hits
2029system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
2030system.cpu1.l2cache.overall_mshr_hits::cpu1.data 9011 # number of overall MSHR hits
2031system.cpu1.l2cache.overall_mshr_hits::total 9013 # number of overall MSHR hits
2032system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11727 # number of ReadReq MSHR misses
2033system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8782 # number of ReadReq MSHR misses
2034system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 759218 # number of ReadReq MSHR misses
2035system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 997722 # number of ReadReq MSHR misses
2036system.cpu1.l2cache.ReadReq_mshr_misses::total 1777449 # number of ReadReq MSHR misses
2037system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 732693 # number of HardPFReq MSHR misses
2038system.cpu1.l2cache.HardPFReq_mshr_misses::total 732693 # number of HardPFReq MSHR misses
2039system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 251758 # number of WriteInvalidateReq MSHR misses
2040system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 251758 # number of WriteInvalidateReq MSHR misses
2041system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 136318 # number of UpgradeReq MSHR misses
2042system.cpu1.l2cache.UpgradeReq_mshr_misses::total 136318 # number of UpgradeReq MSHR misses
2043system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 166600 # number of SCUpgradeReq MSHR misses
2044system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 166600 # number of SCUpgradeReq MSHR misses
2045system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2046system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2047system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237869 # number of ReadExReq MSHR misses
2048system.cpu1.l2cache.ReadExReq_mshr_misses::total 237869 # number of ReadExReq MSHR misses
2049system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11727 # number of demand (read+write) MSHR misses
2050system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8782 # number of demand (read+write) MSHR misses
2051system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 759218 # number of demand (read+write) MSHR misses
2052system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1235591 # number of demand (read+write) MSHR misses
2053system.cpu1.l2cache.demand_mshr_misses::total 2015318 # number of demand (read+write) MSHR misses
2054system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11727 # number of overall MSHR misses
2055system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8782 # number of overall MSHR misses
2056system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 759218 # number of overall MSHR misses
2057system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1235591 # number of overall MSHR misses
2058system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 732693 # number of overall MSHR misses
2059system.cpu1.l2cache.overall_mshr_misses::total 2748011 # number of overall MSHR misses
2060system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable
2061system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7026 # number of ReadReq MSHR uncacheable
2062system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7116 # number of ReadReq MSHR uncacheable
2063system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable
2064system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7515 # number of WriteReq MSHR uncacheable
2065system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses
2066system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14541 # number of overall MSHR uncacheable misses
2067system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14631 # number of overall MSHR uncacheable misses
2068system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of ReadReq MSHR miss cycles
2069system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 315988754 # number of ReadReq MSHR miss cycles
2070system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 17115860957 # number of ReadReq MSHR miss cycles
2071system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26083443690 # number of ReadReq MSHR miss cycles
2072system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 43887496684 # number of ReadReq MSHR miss cycles
2073system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35590505004 # number of HardPFReq MSHR miss cycles
2074system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35590505004 # number of HardPFReq MSHR miss cycles
2075system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8154289208 # number of WriteInvalidateReq MSHR miss cycles
2076system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8154289208 # number of WriteInvalidateReq MSHR miss cycles
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2662634544 # number of UpgradeReq MSHR miss cycles
2078system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2662634544 # number of UpgradeReq MSHR miss cycles
2079system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2448254099 # number of SCUpgradeReq MSHR miss cycles
2080system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2448254099 # number of SCUpgradeReq MSHR miss cycles
2081system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 937500 # number of SCUpgradeFailReq MSHR miss cycles
2082system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 937500 # number of SCUpgradeFailReq MSHR miss cycles
2083system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8085398810 # number of ReadExReq MSHR miss cycles
2084system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8085398810 # number of ReadExReq MSHR miss cycles
2085system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of demand (read+write) MSHR miss cycles
2086system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 315988754 # number of demand (read+write) MSHR miss cycles
2087system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17115860957 # number of demand (read+write) MSHR miss cycles
2088system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34168842500 # number of demand (read+write) MSHR miss cycles
2089system.cpu1.l2cache.demand_mshr_miss_latency::total 51972895494 # number of demand (read+write) MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 372203283 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 315988754 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17115860957 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34168842500 # number of overall MSHR miss cycles
2094system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35590505004 # number of overall MSHR miss cycles
2095system.cpu1.l2cache.overall_mshr_miss_latency::total 87563400498 # number of overall MSHR miss cycles
2096system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7349000 # number of ReadReq MSHR uncacheable cycles
2097system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 771832750 # number of ReadReq MSHR uncacheable cycles
2098system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 779181750 # number of ReadReq MSHR uncacheable cycles
2099system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 931317500 # number of WriteReq MSHR uncacheable cycles
2100system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 931317500 # number of WriteReq MSHR uncacheable cycles
2101system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7349000 # number of overall MSHR uncacheable cycles
2102system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1703150250 # number of overall MSHR uncacheable cycles
2103system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1710499250 # number of overall MSHR uncacheable cycles
2104system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for ReadReq accesses
2105system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for ReadReq accesses
2106system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for ReadReq accesses
2107system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.276281 # mshr miss rate for ReadReq accesses
2108system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.138973 # mshr miss rate for ReadReq accesses
2109system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2110system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2111system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.592436 # mshr miss rate for WriteInvalidateReq accesses
2112system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.592436 # mshr miss rate for WriteInvalidateReq accesses
2113system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.657861 # mshr miss rate for UpgradeReq accesses
2114system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.657861 # mshr miss rate for UpgradeReq accesses
2115system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825006 # mshr miss rate for SCUpgradeReq accesses
2116system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825006 # mshr miss rate for SCUpgradeReq accesses
2117system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2118system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2119system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.214518 # mshr miss rate for ReadExReq accesses
2120system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.214518 # mshr miss rate for ReadExReq accesses
2121system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for demand accesses
2122system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for demand accesses
2123system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for demand accesses
2124system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for demand accesses
2125system.cpu1.l2cache.demand_mshr_miss_rate::total 0.145000 # mshr miss rate for demand accesses
2126system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023375 # mshr miss rate for overall accesses
2127system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053557 # mshr miss rate for overall accesses
2128system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.089183 # mshr miss rate for overall accesses
2129system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.261771 # mshr miss rate for overall accesses
2130system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2131system.cpu1.l2cache.overall_mshr_miss_rate::total 0.197716 # mshr miss rate for overall accesses
2132system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average ReadReq mshr miss latency
2133system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average ReadReq mshr miss latency
2134system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average ReadReq mshr miss latency
2135system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26142.997438 # average ReadReq mshr miss latency
2136system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24691.283229 # average ReadReq mshr miss latency
2137system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average HardPFReq mshr miss latency
2138system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48574.921562 # average HardPFReq mshr miss latency
2139system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32389.394609 # average WriteInvalidateReq mshr miss latency
2140system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32389.394609 # average WriteInvalidateReq mshr miss latency
2141system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19532.523541 # average UpgradeReq mshr miss latency
2142system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19532.523541 # average UpgradeReq mshr miss latency
2143system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14695.402755 # average SCUpgradeReq mshr miss latency
2144system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14695.402755 # average SCUpgradeReq mshr miss latency
2145system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 937500 # average SCUpgradeFailReq mshr miss latency
2146system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 937500 # average SCUpgradeFailReq mshr miss latency
2147system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33990.973225 # average ReadExReq mshr miss latency
2148system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33990.973225 # average ReadExReq mshr miss latency
2149system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency
2150system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency
2151system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency
2152system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency
2153system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25788.930330 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31739.002558 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35981.411296 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22544.066338 # average overall mshr miss latency
2157system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27653.845407 # average overall mshr miss latency
2158system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48574.921562 # average overall mshr miss latency
2159system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31864.283112 # average overall mshr miss latency
2160system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average ReadReq mshr uncacheable latency
2161system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 109853.793054 # average ReadReq mshr uncacheable latency
2162system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 109497.154300 # average ReadReq mshr uncacheable latency
2163system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123927.811045 # average WriteReq mshr uncacheable latency
2164system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123927.811045 # average WriteReq mshr uncacheable latency
2165system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81655.555556 # average overall mshr uncacheable latency
2166system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 117127.449969 # average overall mshr uncacheable latency
2167system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116909.250906 # average overall mshr uncacheable latency
2168system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2169system.cpu1.toL2Bus.trans_dist::ReadReq 15573132 # Transaction distribution
2170system.cpu1.toL2Bus.trans_dist::ReadResp 13012901 # Transaction distribution
2171system.cpu1.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution
2172system.cpu1.toL2Bus.trans_dist::WriteResp 7515 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::Writeback 3294638 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::HardPFReq 1065592 # Transaction distribution
2175system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
2176system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1119456 # Transaction distribution
2177system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 424954 # Transaction distribution
2178system.cpu1.toL2Bus.trans_dist::UpgradeReq 452600 # Transaction distribution
2179system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368137 # Transaction distribution
2180system.cpu1.toL2Bus.trans_dist::UpgradeResp 473527 # Transaction distribution
2181system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution
2182system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution
2183system.cpu1.toL2Bus.trans_dist::ReadExReq 1269149 # Transaction distribution
2184system.cpu1.toL2Bus.trans_dist::ReadExResp 1115295 # Transaction distribution
2185system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17026205 # Packet count per connected master and slave (bytes)
2186system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14595450 # Packet count per connected master and slave (bytes)
2187system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 357835 # Packet count per connected master and slave (bytes)
2188system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1096931 # Packet count per connected master and slave (bytes)
2189system.cpu1.toL2Bus.pkt_count::total 33076421 # Packet count per connected master and slave (bytes)
2190system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544838528 # Cumulative packet size per connected master and slave (bytes)
2191system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 546511254 # Cumulative packet size per connected master and slave (bytes)
2192system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1311792 # Cumulative packet size per connected master and slave (bytes)
2193system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4013488 # Cumulative packet size per connected master and slave (bytes)
2194system.cpu1.toL2Bus.pkt_size::total 1096675062 # Cumulative packet size per connected master and slave (bytes)
2195system.cpu1.toL2Bus.snoops 5302361 # Total snoops (count)
2196system.cpu1.toL2Bus.snoop_fanout::samples 23181233 # Request fanout histogram
2197system.cpu1.toL2Bus.snoop_fanout::mean 1.250406 # Request fanout histogram
2198system.cpu1.toL2Bus.snoop_fanout::stdev 0.433247 # Request fanout histogram
2199system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2200system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2201system.cpu1.toL2Bus.snoop_fanout::1 17376502 74.96% 74.96% # Request fanout histogram
2202system.cpu1.toL2Bus.snoop_fanout::2 5804731 25.04% 100.00% # Request fanout histogram
2203system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2204system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2205system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2206system.cpu1.toL2Bus.snoop_fanout::total 23181233 # Request fanout histogram
2207system.cpu1.toL2Bus.reqLayer0.occupancy 12806281931 # Layer occupancy (ticks)
2208system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2209system.cpu1.toL2Bus.snoopLayer0.occupancy 180531485 # Layer occupancy (ticks)
2210system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2211system.cpu1.toL2Bus.respLayer0.occupancy 12781520856 # Layer occupancy (ticks)
2212system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2213system.cpu1.toL2Bus.respLayer1.occupancy 7568960857 # Layer occupancy (ticks)
2214system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2215system.cpu1.toL2Bus.respLayer2.occupancy 194234943 # Layer occupancy (ticks)
2216system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2217system.cpu1.toL2Bus.respLayer3.occupancy 595690418 # Layer occupancy (ticks)
2218system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2219system.iobus.trans_dist::ReadReq 40349 # Transaction distribution
2220system.iobus.trans_dist::ReadResp 40349 # Transaction distribution
2221system.iobus.trans_dist::WriteReq 136610 # Transaction distribution
2222system.iobus.trans_dist::WriteResp 29882 # Transaction distribution
2223system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2224system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47640 # Packet count per connected master and slave (bytes)
2225system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2226system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2227system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2228system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2229system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2230system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2231system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2232system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2233system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2234system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2235system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2236system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2237system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2238system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2239system.iobus.pkt_count_system.bridge.master::total 122574 # Packet count per connected master and slave (bytes)
2240system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes)
2241system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes)
2242system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2243system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2244system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
2245system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47660 # Cumulative packet size per connected master and slave (bytes)
2246system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2247system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2248system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2249system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2250system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2251system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2252system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2253system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2254system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2255system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2256system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2257system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2259system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2260system.iobus.pkt_size_system.bridge.master::total 155681 # Cumulative packet size per connected master and slave (bytes)
2261system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes)
2262system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes)
2263system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2264system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2265system.iobus.pkt_size::total 7496839 # Cumulative packet size per connected master and slave (bytes)
2266system.iobus.reqLayer0.occupancy 36172000 # Layer occupancy (ticks)
2267system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2268system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2269system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2270system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2271system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2272system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2273system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2274system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2275system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2276system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2277system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2278system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2279system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2280system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
2281system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2282system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
2283system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2284system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2285system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2286system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
2287system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2288system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2289system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2290system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2291system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2292system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2293system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2294system.iobus.reqLayer27.occupancy 607512131 # Layer occupancy (ticks)
2295system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2296system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2297system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2298system.iobus.respLayer0.occupancy 92695000 # Layer occupancy (ticks)
2299system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2300system.iobus.respLayer3.occupancy 148588668 # Layer occupancy (ticks)
2301system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2302system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
2303system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2304system.iocache.tags.replacements 115637 # number of replacements
2305system.iocache.tags.tagsinuse 11.310069 # Cycle average of tags in use
2306system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2307system.iocache.tags.sampled_refs 115653 # Sample count of references to valid blocks.
2308system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2309system.iocache.tags.warmup_cycle 9129457632000 # Cycle when the warmup percentage was hit.
2310system.iocache.tags.occ_blocks::realview.ethernet 7.399895 # Average occupied blocks per requestor
2311system.iocache.tags.occ_blocks::realview.ide 3.910174 # Average occupied blocks per requestor
2312system.iocache.tags.occ_percent::realview.ethernet 0.462493 # Average percentage of cache occupancy
2313system.iocache.tags.occ_percent::realview.ide 0.244386 # Average percentage of cache occupancy
2314system.iocache.tags.occ_percent::total 0.706879 # Average percentage of cache occupancy
2315system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2316system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2317system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2318system.iocache.tags.tag_accesses 1041045 # Number of tag accesses
2319system.iocache.tags.data_accesses 1041045 # Number of data accesses
2320system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2321system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses
2322system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses
2323system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2324system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2325system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2326system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2327system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2328system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses
2329system.iocache.demand_misses::total 8944 # number of demand (read+write) misses
2330system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2331system.iocache.overall_misses::realview.ide 8904 # number of overall misses
2332system.iocache.overall_misses::total 8944 # number of overall misses
2333system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
2334system.iocache.ReadReq_miss_latency::realview.ide 1622865167 # number of ReadReq miss cycles
2335system.iocache.ReadReq_miss_latency::total 1628060667 # number of ReadReq miss cycles
2336system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2337system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2338system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19842621296 # number of WriteInvalidateReq miss cycles
2339system.iocache.WriteInvalidateReq_miss_latency::total 19842621296 # number of WriteInvalidateReq miss cycles
2340system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
2341system.iocache.demand_miss_latency::realview.ide 1622865167 # number of demand (read+write) miss cycles
2342system.iocache.demand_miss_latency::total 1628429667 # number of demand (read+write) miss cycles
2343system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
2344system.iocache.overall_miss_latency::realview.ide 1622865167 # number of overall miss cycles
2345system.iocache.overall_miss_latency::total 1628429667 # number of overall miss cycles
2346system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2347system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses)
2348system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses)
2349system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2350system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2351system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
2352system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
2353system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2354system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses
2355system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses
2356system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2357system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses
2358system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses
2359system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2360system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2361system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2362system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2363system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2364system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2365system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2366system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2367system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2368system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2369system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2370system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2371system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2372system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
2373system.iocache.ReadReq_avg_miss_latency::realview.ide 182262.485063 # average ReadReq miss latency
2374system.iocache.ReadReq_avg_miss_latency::total 182089.326362 # average ReadReq miss latency
2375system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2376system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2377system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185917.671989 # average WriteInvalidateReq miss latency
2378system.iocache.WriteInvalidateReq_avg_miss_latency::total 185917.671989 # average WriteInvalidateReq miss latency
2379system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2380system.iocache.demand_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency
2381system.iocache.demand_avg_miss_latency::total 182069.506597 # average overall miss latency
2382system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2383system.iocache.overall_avg_miss_latency::realview.ide 182262.485063 # average overall miss latency
2384system.iocache.overall_avg_miss_latency::total 182069.506597 # average overall miss latency
2385system.iocache.blocked_cycles::no_mshrs 110288 # number of cycles access was blocked
2386system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2387system.iocache.blocked::no_mshrs 16227 # number of cycles access was blocked
2388system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2389system.iocache.avg_blocked_cycles::no_mshrs 6.796574 # average number of cycles each access was blocked
2390system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2391system.iocache.fast_writes 0 # number of fast writes performed
2392system.iocache.cache_copies 0 # number of cache copies performed
2393system.iocache.writebacks::writebacks 106703 # number of writebacks
2394system.iocache.writebacks::total 106703 # number of writebacks
2395system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2396system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses
2397system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses
2398system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2399system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2400system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
2401system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
2402system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2403system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses
2404system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses
2405system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2406system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses
2407system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses
2408system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
2409system.iocache.ReadReq_mshr_miss_latency::realview.ide 1158690425 # number of ReadReq MSHR miss cycles
2410system.iocache.ReadReq_mshr_miss_latency::total 1161960925 # number of ReadReq MSHR miss cycles
2411system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
2412system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
2413system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14292687374 # number of WriteInvalidateReq MSHR miss cycles
2414system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14292687374 # number of WriteInvalidateReq MSHR miss cycles
2415system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
2416system.iocache.demand_mshr_miss_latency::realview.ide 1158690425 # number of demand (read+write) MSHR miss cycles
2417system.iocache.demand_mshr_miss_latency::total 1162173925 # number of demand (read+write) MSHR miss cycles
2418system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
2419system.iocache.overall_mshr_miss_latency::realview.ide 1158690425 # number of overall MSHR miss cycles
2420system.iocache.overall_mshr_miss_latency::total 1162173925 # number of overall MSHR miss cycles
2421system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2422system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2423system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2424system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2425system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2426system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2427system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2428system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2429system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2431system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2432system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2433system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2434system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
2435system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130131.449349 # average ReadReq mshr miss latency
2436system.iocache.ReadReq_avg_mshr_miss_latency::total 129958.721060 # average ReadReq mshr miss latency
2437system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
2438system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
2439system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133916.941890 # average WriteInvalidateReq mshr miss latency
2440system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133916.941890 # average WriteInvalidateReq mshr miss latency
2441system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2442system.iocache.demand_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency
2443system.iocache.demand_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency
2444system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2445system.iocache.overall_avg_mshr_miss_latency::realview.ide 130131.449349 # average overall mshr miss latency
2446system.iocache.overall_avg_mshr_miss_latency::total 129938.945103 # average overall mshr miss latency
2447system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2448system.l2c.tags.replacements 1500558 # number of replacements
2449system.l2c.tags.tagsinuse 64423.791175 # Cycle average of tags in use
2450system.l2c.tags.total_refs 5010724 # Total number of references to valid blocks.
2451system.l2c.tags.sampled_refs 1561220 # Sample count of references to valid blocks.
2452system.l2c.tags.avg_refs 3.209493 # Average number of references to valid blocks.
2453system.l2c.tags.warmup_cycle 8774171000 # Cycle when the warmup percentage was hit.
2454system.l2c.tags.occ_blocks::writebacks 18406.054563 # Average occupied blocks per requestor
2455system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.983954 # Average occupied blocks per requestor
2456system.l2c.tags.occ_blocks::cpu0.itb.walker 204.641755 # Average occupied blocks per requestor
2457system.l2c.tags.occ_blocks::cpu0.inst 4710.197783 # Average occupied blocks per requestor
2458system.l2c.tags.occ_blocks::cpu0.data 8659.570147 # Average occupied blocks per requestor
2459system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11639.948556 # Average occupied blocks per requestor
2460system.l2c.tags.occ_blocks::cpu1.dtb.walker 186.392680 # Average occupied blocks per requestor
2461system.l2c.tags.occ_blocks::cpu1.itb.walker 219.831325 # Average occupied blocks per requestor
2462system.l2c.tags.occ_blocks::cpu1.inst 3870.715230 # Average occupied blocks per requestor
2463system.l2c.tags.occ_blocks::cpu1.data 6776.772016 # Average occupied blocks per requestor
2464system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9585.683167 # Average occupied blocks per requestor
2465system.l2c.tags.occ_percent::writebacks 0.280854 # Average percentage of cache occupancy
2466system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002502 # Average percentage of cache occupancy
2467system.l2c.tags.occ_percent::cpu0.itb.walker 0.003123 # Average percentage of cache occupancy
2468system.l2c.tags.occ_percent::cpu0.inst 0.071872 # Average percentage of cache occupancy
2469system.l2c.tags.occ_percent::cpu0.data 0.132135 # Average percentage of cache occupancy
2470system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177612 # Average percentage of cache occupancy
2471system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002844 # Average percentage of cache occupancy
2472system.l2c.tags.occ_percent::cpu1.itb.walker 0.003354 # Average percentage of cache occupancy
2473system.l2c.tags.occ_percent::cpu1.inst 0.059062 # Average percentage of cache occupancy
2474system.l2c.tags.occ_percent::cpu1.data 0.103405 # Average percentage of cache occupancy
2475system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.146266 # Average percentage of cache occupancy
2476system.l2c.tags.occ_percent::total 0.983029 # Average percentage of cache occupancy
2477system.l2c.tags.occ_task_id_blocks::1022 9890 # Occupied blocks per task id
2478system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id
2479system.l2c.tags.occ_task_id_blocks::1024 50532 # Occupied blocks per task id
2480system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
2481system.l2c.tags.age_task_id_blocks_1022::2 96 # Occupied blocks per task id
2482system.l2c.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id
2483system.l2c.tags.age_task_id_blocks_1022::4 9383 # Occupied blocks per task id
2484system.l2c.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id
2485system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
2486system.l2c.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id
2487system.l2c.tags.age_task_id_blocks_1024::2 1652 # Occupied blocks per task id
2488system.l2c.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id
2489system.l2c.tags.age_task_id_blocks_1024::4 43541 # Occupied blocks per task id
2490system.l2c.tags.occ_task_id_percent::1022 0.150909 # Percentage of cache occupancy per task id
2491system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id
2492system.l2c.tags.occ_task_id_percent::1024 0.771057 # Percentage of cache occupancy per task id
2493system.l2c.tags.tag_accesses 65146304 # Number of tag accesses
2494system.l2c.tags.data_accesses 65146304 # Number of data accesses
2495system.l2c.ReadReq_hits::cpu0.dtb.walker 6273 # number of ReadReq hits
2496system.l2c.ReadReq_hits::cpu0.itb.walker 4042 # number of ReadReq hits
2497system.l2c.ReadReq_hits::cpu0.inst 730934 # number of ReadReq hits
2498system.l2c.ReadReq_hits::cpu0.data 606426 # number of ReadReq hits
2499system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 316069 # number of ReadReq hits
2500system.l2c.ReadReq_hits::cpu1.dtb.walker 6330 # number of ReadReq hits
2501system.l2c.ReadReq_hits::cpu1.itb.walker 4616 # number of ReadReq hits
2502system.l2c.ReadReq_hits::cpu1.inst 702346 # number of ReadReq hits
2503system.l2c.ReadReq_hits::cpu1.data 568034 # number of ReadReq hits
2504system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 305702 # number of ReadReq hits
2505system.l2c.ReadReq_hits::total 3250772 # number of ReadReq hits
2506system.l2c.Writeback_hits::writebacks 2490573 # number of Writeback hits
2507system.l2c.Writeback_hits::total 2490573 # number of Writeback hits
2508system.l2c.WriteInvalidateReq_hits::cpu0.data 135019 # number of WriteInvalidateReq hits
2509system.l2c.WriteInvalidateReq_hits::cpu1.data 128371 # number of WriteInvalidateReq hits
2510system.l2c.WriteInvalidateReq_hits::total 263390 # number of WriteInvalidateReq hits
2511system.l2c.UpgradeReq_hits::cpu0.data 28214 # number of UpgradeReq hits
2512system.l2c.UpgradeReq_hits::cpu1.data 29967 # number of UpgradeReq hits
2513system.l2c.UpgradeReq_hits::total 58181 # number of UpgradeReq hits
2514system.l2c.SCUpgradeReq_hits::cpu0.data 6140 # number of SCUpgradeReq hits
2515system.l2c.SCUpgradeReq_hits::cpu1.data 6184 # number of SCUpgradeReq hits
2516system.l2c.SCUpgradeReq_hits::total 12324 # number of SCUpgradeReq hits
2517system.l2c.ReadExReq_hits::cpu0.data 50287 # number of ReadExReq hits
2518system.l2c.ReadExReq_hits::cpu1.data 53122 # number of ReadExReq hits
2519system.l2c.ReadExReq_hits::total 103409 # number of ReadExReq hits
2520system.l2c.demand_hits::cpu0.dtb.walker 6273 # number of demand (read+write) hits
2521system.l2c.demand_hits::cpu0.itb.walker 4042 # number of demand (read+write) hits
2522system.l2c.demand_hits::cpu0.inst 730934 # number of demand (read+write) hits
2523system.l2c.demand_hits::cpu0.data 656713 # number of demand (read+write) hits
2524system.l2c.demand_hits::cpu0.l2cache.prefetcher 316069 # number of demand (read+write) hits
2525system.l2c.demand_hits::cpu1.dtb.walker 6330 # number of demand (read+write) hits
2526system.l2c.demand_hits::cpu1.itb.walker 4616 # number of demand (read+write) hits
2527system.l2c.demand_hits::cpu1.inst 702346 # number of demand (read+write) hits
2528system.l2c.demand_hits::cpu1.data 621156 # number of demand (read+write) hits
2529system.l2c.demand_hits::cpu1.l2cache.prefetcher 305702 # number of demand (read+write) hits
2530system.l2c.demand_hits::total 3354181 # number of demand (read+write) hits
2531system.l2c.overall_hits::cpu0.dtb.walker 6273 # number of overall hits
2532system.l2c.overall_hits::cpu0.itb.walker 4042 # number of overall hits
2533system.l2c.overall_hits::cpu0.inst 730934 # number of overall hits
2534system.l2c.overall_hits::cpu0.data 656713 # number of overall hits
2535system.l2c.overall_hits::cpu0.l2cache.prefetcher 316069 # number of overall hits
2536system.l2c.overall_hits::cpu1.dtb.walker 6330 # number of overall hits
2537system.l2c.overall_hits::cpu1.itb.walker 4616 # number of overall hits
2538system.l2c.overall_hits::cpu1.inst 702346 # number of overall hits
2539system.l2c.overall_hits::cpu1.data 621156 # number of overall hits
2540system.l2c.overall_hits::cpu1.l2cache.prefetcher 305702 # number of overall hits
2541system.l2c.overall_hits::total 3354181 # number of overall hits
2542system.l2c.ReadReq_misses::cpu0.dtb.walker 1959 # number of ReadReq misses
2543system.l2c.ReadReq_misses::cpu0.itb.walker 1699 # number of ReadReq misses
2544system.l2c.ReadReq_misses::cpu0.inst 72396 # number of ReadReq misses
2545system.l2c.ReadReq_misses::cpu0.data 144803 # number of ReadReq misses
2546system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 235787 # number of ReadReq misses
2547system.l2c.ReadReq_misses::cpu1.dtb.walker 2337 # number of ReadReq misses
2548system.l2c.ReadReq_misses::cpu1.itb.walker 2129 # number of ReadReq misses
2549system.l2c.ReadReq_misses::cpu1.inst 56871 # number of ReadReq misses
2550system.l2c.ReadReq_misses::cpu1.data 125845 # number of ReadReq misses
2551system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 232153 # number of ReadReq misses
2552system.l2c.ReadReq_misses::total 875979 # number of ReadReq misses
2553system.l2c.WriteInvalidateReq_misses::cpu0.data 452629 # number of WriteInvalidateReq misses
2554system.l2c.WriteInvalidateReq_misses::cpu1.data 114950 # number of WriteInvalidateReq misses
2555system.l2c.WriteInvalidateReq_misses::total 567579 # number of WriteInvalidateReq misses
2556system.l2c.UpgradeReq_misses::cpu0.data 49085 # number of UpgradeReq misses
2557system.l2c.UpgradeReq_misses::cpu1.data 42979 # number of UpgradeReq misses
2558system.l2c.UpgradeReq_misses::total 92064 # number of UpgradeReq misses
2559system.l2c.SCUpgradeReq_misses::cpu0.data 9286 # number of SCUpgradeReq misses
2560system.l2c.SCUpgradeReq_misses::cpu1.data 8933 # number of SCUpgradeReq misses
2561system.l2c.SCUpgradeReq_misses::total 18219 # number of SCUpgradeReq misses
2562system.l2c.ReadExReq_misses::cpu0.data 81593 # number of ReadExReq misses
2563system.l2c.ReadExReq_misses::cpu1.data 56532 # number of ReadExReq misses
2564system.l2c.ReadExReq_misses::total 138125 # number of ReadExReq misses
2565system.l2c.demand_misses::cpu0.dtb.walker 1959 # number of demand (read+write) misses
2566system.l2c.demand_misses::cpu0.itb.walker 1699 # number of demand (read+write) misses
2567system.l2c.demand_misses::cpu0.inst 72396 # number of demand (read+write) misses
2568system.l2c.demand_misses::cpu0.data 226396 # number of demand (read+write) misses
2569system.l2c.demand_misses::cpu0.l2cache.prefetcher 235787 # number of demand (read+write) misses
2570system.l2c.demand_misses::cpu1.dtb.walker 2337 # number of demand (read+write) misses
2571system.l2c.demand_misses::cpu1.itb.walker 2129 # number of demand (read+write) misses
2572system.l2c.demand_misses::cpu1.inst 56871 # number of demand (read+write) misses
2573system.l2c.demand_misses::cpu1.data 182377 # number of demand (read+write) misses
2574system.l2c.demand_misses::cpu1.l2cache.prefetcher 232153 # number of demand (read+write) misses
2575system.l2c.demand_misses::total 1014104 # number of demand (read+write) misses
2576system.l2c.overall_misses::cpu0.dtb.walker 1959 # number of overall misses
2577system.l2c.overall_misses::cpu0.itb.walker 1699 # number of overall misses
2578system.l2c.overall_misses::cpu0.inst 72396 # number of overall misses
2579system.l2c.overall_misses::cpu0.data 226396 # number of overall misses
2580system.l2c.overall_misses::cpu0.l2cache.prefetcher 235787 # number of overall misses
2581system.l2c.overall_misses::cpu1.dtb.walker 2337 # number of overall misses
2582system.l2c.overall_misses::cpu1.itb.walker 2129 # number of overall misses
2583system.l2c.overall_misses::cpu1.inst 56871 # number of overall misses
2584system.l2c.overall_misses::cpu1.data 182377 # number of overall misses
2585system.l2c.overall_misses::cpu1.l2cache.prefetcher 232153 # number of overall misses
2586system.l2c.overall_misses::total 1014104 # number of overall misses
2587system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 183693028 # number of ReadReq miss cycles
2588system.l2c.ReadReq_miss_latency::cpu0.itb.walker 155473534 # number of ReadReq miss cycles
2589system.l2c.ReadReq_miss_latency::cpu0.inst 6124405792 # number of ReadReq miss cycles
2590system.l2c.ReadReq_miss_latency::cpu0.data 13529784764 # number of ReadReq miss cycles
2591system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of ReadReq miss cycles
2592system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 209221515 # number of ReadReq miss cycles
2593system.l2c.ReadReq_miss_latency::cpu1.itb.walker 197082496 # number of ReadReq miss cycles
2594system.l2c.ReadReq_miss_latency::cpu1.inst 4800216916 # number of ReadReq miss cycles
2595system.l2c.ReadReq_miss_latency::cpu1.data 11513015623 # number of ReadReq miss cycles
2596system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of ReadReq miss cycles
2597system.l2c.ReadReq_miss_latency::total 98828755334 # number of ReadReq miss cycles
2598system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50831909 # number of WriteInvalidateReq miss cycles
2599system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41081201 # number of WriteInvalidateReq miss cycles
2600system.l2c.WriteInvalidateReq_miss_latency::total 91913110 # number of WriteInvalidateReq miss cycles
2601system.l2c.UpgradeReq_miss_latency::cpu0.data 314052545 # number of UpgradeReq miss cycles
2602system.l2c.UpgradeReq_miss_latency::cpu1.data 253554995 # number of UpgradeReq miss cycles
2603system.l2c.UpgradeReq_miss_latency::total 567607540 # number of UpgradeReq miss cycles
2604system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59571609 # number of SCUpgradeReq miss cycles
2605system.l2c.SCUpgradeReq_miss_latency::cpu1.data 53385310 # number of SCUpgradeReq miss cycles
2606system.l2c.SCUpgradeReq_miss_latency::total 112956919 # number of SCUpgradeReq miss cycles
2607system.l2c.ReadExReq_miss_latency::cpu0.data 7326457212 # number of ReadExReq miss cycles
2608system.l2c.ReadExReq_miss_latency::cpu1.data 4778922810 # number of ReadExReq miss cycles
2609system.l2c.ReadExReq_miss_latency::total 12105380022 # number of ReadExReq miss cycles
2610system.l2c.demand_miss_latency::cpu0.dtb.walker 183693028 # number of demand (read+write) miss cycles
2611system.l2c.demand_miss_latency::cpu0.itb.walker 155473534 # number of demand (read+write) miss cycles
2612system.l2c.demand_miss_latency::cpu0.inst 6124405792 # number of demand (read+write) miss cycles
2613system.l2c.demand_miss_latency::cpu0.data 20856241976 # number of demand (read+write) miss cycles
2614system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of demand (read+write) miss cycles
2615system.l2c.demand_miss_latency::cpu1.dtb.walker 209221515 # number of demand (read+write) miss cycles
2616system.l2c.demand_miss_latency::cpu1.itb.walker 197082496 # number of demand (read+write) miss cycles
2617system.l2c.demand_miss_latency::cpu1.inst 4800216916 # number of demand (read+write) miss cycles
2618system.l2c.demand_miss_latency::cpu1.data 16291938433 # number of demand (read+write) miss cycles
2619system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of demand (read+write) miss cycles
2620system.l2c.demand_miss_latency::total 110934135356 # number of demand (read+write) miss cycles
2621system.l2c.overall_miss_latency::cpu0.dtb.walker 183693028 # number of overall miss cycles
2622system.l2c.overall_miss_latency::cpu0.itb.walker 155473534 # number of overall miss cycles
2623system.l2c.overall_miss_latency::cpu0.inst 6124405792 # number of overall miss cycles
2624system.l2c.overall_miss_latency::cpu0.data 20856241976 # number of overall miss cycles
2625system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 31415388170 # number of overall miss cycles
2626system.l2c.overall_miss_latency::cpu1.dtb.walker 209221515 # number of overall miss cycles
2627system.l2c.overall_miss_latency::cpu1.itb.walker 197082496 # number of overall miss cycles
2628system.l2c.overall_miss_latency::cpu1.inst 4800216916 # number of overall miss cycles
2629system.l2c.overall_miss_latency::cpu1.data 16291938433 # number of overall miss cycles
2630system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30700473496 # number of overall miss cycles
2631system.l2c.overall_miss_latency::total 110934135356 # number of overall miss cycles
2632system.l2c.ReadReq_accesses::cpu0.dtb.walker 8232 # number of ReadReq accesses(hits+misses)
2633system.l2c.ReadReq_accesses::cpu0.itb.walker 5741 # number of ReadReq accesses(hits+misses)
2634system.l2c.ReadReq_accesses::cpu0.inst 803330 # number of ReadReq accesses(hits+misses)
2635system.l2c.ReadReq_accesses::cpu0.data 751229 # number of ReadReq accesses(hits+misses)
2636system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 551856 # number of ReadReq accesses(hits+misses)
2637system.l2c.ReadReq_accesses::cpu1.dtb.walker 8667 # number of ReadReq accesses(hits+misses)
2638system.l2c.ReadReq_accesses::cpu1.itb.walker 6745 # number of ReadReq accesses(hits+misses)
2639system.l2c.ReadReq_accesses::cpu1.inst 759217 # number of ReadReq accesses(hits+misses)
2640system.l2c.ReadReq_accesses::cpu1.data 693879 # number of ReadReq accesses(hits+misses)
2641system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 537855 # number of ReadReq accesses(hits+misses)
2642system.l2c.ReadReq_accesses::total 4126751 # number of ReadReq accesses(hits+misses)
2643system.l2c.Writeback_accesses::writebacks 2490573 # number of Writeback accesses(hits+misses)
2644system.l2c.Writeback_accesses::total 2490573 # number of Writeback accesses(hits+misses)
2645system.l2c.WriteInvalidateReq_accesses::cpu0.data 587648 # number of WriteInvalidateReq accesses(hits+misses)
2646system.l2c.WriteInvalidateReq_accesses::cpu1.data 243321 # number of WriteInvalidateReq accesses(hits+misses)
2647system.l2c.WriteInvalidateReq_accesses::total 830969 # number of WriteInvalidateReq accesses(hits+misses)
2648system.l2c.UpgradeReq_accesses::cpu0.data 77299 # number of UpgradeReq accesses(hits+misses)
2649system.l2c.UpgradeReq_accesses::cpu1.data 72946 # number of UpgradeReq accesses(hits+misses)
2650system.l2c.UpgradeReq_accesses::total 150245 # number of UpgradeReq accesses(hits+misses)
2651system.l2c.SCUpgradeReq_accesses::cpu0.data 15426 # number of SCUpgradeReq accesses(hits+misses)
2652system.l2c.SCUpgradeReq_accesses::cpu1.data 15117 # number of SCUpgradeReq accesses(hits+misses)
2653system.l2c.SCUpgradeReq_accesses::total 30543 # number of SCUpgradeReq accesses(hits+misses)
2654system.l2c.ReadExReq_accesses::cpu0.data 131880 # number of ReadExReq accesses(hits+misses)
2655system.l2c.ReadExReq_accesses::cpu1.data 109654 # number of ReadExReq accesses(hits+misses)
2656system.l2c.ReadExReq_accesses::total 241534 # number of ReadExReq accesses(hits+misses)
2657system.l2c.demand_accesses::cpu0.dtb.walker 8232 # number of demand (read+write) accesses
2658system.l2c.demand_accesses::cpu0.itb.walker 5741 # number of demand (read+write) accesses
2659system.l2c.demand_accesses::cpu0.inst 803330 # number of demand (read+write) accesses
2660system.l2c.demand_accesses::cpu0.data 883109 # number of demand (read+write) accesses
2661system.l2c.demand_accesses::cpu0.l2cache.prefetcher 551856 # number of demand (read+write) accesses
2662system.l2c.demand_accesses::cpu1.dtb.walker 8667 # number of demand (read+write) accesses
2663system.l2c.demand_accesses::cpu1.itb.walker 6745 # number of demand (read+write) accesses
2664system.l2c.demand_accesses::cpu1.inst 759217 # number of demand (read+write) accesses
2665system.l2c.demand_accesses::cpu1.data 803533 # number of demand (read+write) accesses
2666system.l2c.demand_accesses::cpu1.l2cache.prefetcher 537855 # number of demand (read+write) accesses
2667system.l2c.demand_accesses::total 4368285 # number of demand (read+write) accesses
2668system.l2c.overall_accesses::cpu0.dtb.walker 8232 # number of overall (read+write) accesses
2669system.l2c.overall_accesses::cpu0.itb.walker 5741 # number of overall (read+write) accesses
2670system.l2c.overall_accesses::cpu0.inst 803330 # number of overall (read+write) accesses
2671system.l2c.overall_accesses::cpu0.data 883109 # number of overall (read+write) accesses
2672system.l2c.overall_accesses::cpu0.l2cache.prefetcher 551856 # number of overall (read+write) accesses
2673system.l2c.overall_accesses::cpu1.dtb.walker 8667 # number of overall (read+write) accesses
2674system.l2c.overall_accesses::cpu1.itb.walker 6745 # number of overall (read+write) accesses
2675system.l2c.overall_accesses::cpu1.inst 759217 # number of overall (read+write) accesses
2676system.l2c.overall_accesses::cpu1.data 803533 # number of overall (read+write) accesses
2677system.l2c.overall_accesses::cpu1.l2cache.prefetcher 537855 # number of overall (read+write) accesses
2678system.l2c.overall_accesses::total 4368285 # number of overall (read+write) accesses
2679system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.237974 # miss rate for ReadReq accesses
2680system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.295941 # miss rate for ReadReq accesses
2681system.l2c.ReadReq_miss_rate::cpu0.inst 0.090120 # miss rate for ReadReq accesses
2682system.l2c.ReadReq_miss_rate::cpu0.data 0.192755 # miss rate for ReadReq accesses
2683system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.427262 # miss rate for ReadReq accesses
2684system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for ReadReq accesses
2685system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.315641 # miss rate for ReadReq accesses
2686system.l2c.ReadReq_miss_rate::cpu1.inst 0.074907 # miss rate for ReadReq accesses
2687system.l2c.ReadReq_miss_rate::cpu1.data 0.181364 # miss rate for ReadReq accesses
2688system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for ReadReq accesses
2689system.l2c.ReadReq_miss_rate::total 0.212268 # miss rate for ReadReq accesses
2690system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.770238 # miss rate for WriteInvalidateReq accesses
2691system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.472421 # miss rate for WriteInvalidateReq accesses
2692system.l2c.WriteInvalidateReq_miss_rate::total 0.683033 # miss rate for WriteInvalidateReq accesses
2693system.l2c.UpgradeReq_miss_rate::cpu0.data 0.635002 # miss rate for UpgradeReq accesses
2694system.l2c.UpgradeReq_miss_rate::cpu1.data 0.589189 # miss rate for UpgradeReq accesses
2695system.l2c.UpgradeReq_miss_rate::total 0.612759 # miss rate for UpgradeReq accesses
2696system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601971 # miss rate for SCUpgradeReq accesses
2697system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590924 # miss rate for SCUpgradeReq accesses
2698system.l2c.SCUpgradeReq_miss_rate::total 0.596503 # miss rate for SCUpgradeReq accesses
2699system.l2c.ReadExReq_miss_rate::cpu0.data 0.618691 # miss rate for ReadExReq accesses
2700system.l2c.ReadExReq_miss_rate::cpu1.data 0.515549 # miss rate for ReadExReq accesses
2701system.l2c.ReadExReq_miss_rate::total 0.571866 # miss rate for ReadExReq accesses
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2703system.l2c.demand_miss_rate::cpu0.itb.walker 0.295941 # miss rate for demand accesses
2704system.l2c.demand_miss_rate::cpu0.inst 0.090120 # miss rate for demand accesses
2705system.l2c.demand_miss_rate::cpu0.data 0.256362 # miss rate for demand accesses
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2707system.l2c.demand_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for demand accesses
2708system.l2c.demand_miss_rate::cpu1.itb.walker 0.315641 # miss rate for demand accesses
2709system.l2c.demand_miss_rate::cpu1.inst 0.074907 # miss rate for demand accesses
2710system.l2c.demand_miss_rate::cpu1.data 0.226969 # miss rate for demand accesses
2711system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for demand accesses
2712system.l2c.demand_miss_rate::total 0.232152 # miss rate for demand accesses
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2714system.l2c.overall_miss_rate::cpu0.itb.walker 0.295941 # miss rate for overall accesses
2715system.l2c.overall_miss_rate::cpu0.inst 0.090120 # miss rate for overall accesses
2716system.l2c.overall_miss_rate::cpu0.data 0.256362 # miss rate for overall accesses
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2718system.l2c.overall_miss_rate::cpu1.dtb.walker 0.269643 # miss rate for overall accesses
2719system.l2c.overall_miss_rate::cpu1.itb.walker 0.315641 # miss rate for overall accesses
2720system.l2c.overall_miss_rate::cpu1.inst 0.074907 # miss rate for overall accesses
2721system.l2c.overall_miss_rate::cpu1.data 0.226969 # miss rate for overall accesses
2722system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.431627 # miss rate for overall accesses
2723system.l2c.overall_miss_rate::total 0.232152 # miss rate for overall accesses
2724system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average ReadReq miss latency
2725system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91508.848735 # average ReadReq miss latency
2726system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84595.914028 # average ReadReq miss latency
2727system.l2c.ReadReq_avg_miss_latency::cpu0.data 93435.804258 # average ReadReq miss latency
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2729system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average ReadReq miss latency
2730system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 92570.453734 # average ReadReq miss latency
2731system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84405.354504 # average ReadReq miss latency
2732system.l2c.ReadReq_avg_miss_latency::cpu1.data 91485.681775 # average ReadReq miss latency
2733system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545 # average ReadReq miss latency
2734system.l2c.ReadReq_avg_miss_latency::total 112820.918463 # average ReadReq miss latency
2735system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 112.303695 # average WriteInvalidateReq miss latency
2736system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 357.383219 # average WriteInvalidateReq miss latency
2737system.l2c.WriteInvalidateReq_avg_miss_latency::total 161.938884 # average WriteInvalidateReq miss latency
2738system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6398.136804 # average UpgradeReq miss latency
2739system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5899.508946 # average UpgradeReq miss latency
2740system.l2c.UpgradeReq_avg_miss_latency::total 6165.358229 # average UpgradeReq miss latency
2741system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6415.206655 # average SCUpgradeReq miss latency
2742system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5976.190529 # average SCUpgradeReq miss latency
2743system.l2c.SCUpgradeReq_avg_miss_latency::total 6199.951644 # average SCUpgradeReq miss latency
2744system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89792.717660 # average ReadExReq miss latency
2745system.l2c.ReadExReq_avg_miss_latency::cpu1.data 84534.826470 # average ReadExReq miss latency
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2747system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average overall miss latency
2748system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91508.848735 # average overall miss latency
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2752system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average overall miss latency
2753system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92570.453734 # average overall miss latency
2754system.l2c.demand_avg_miss_latency::cpu1.inst 84405.354504 # average overall miss latency
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2757system.l2c.demand_avg_miss_latency::total 109391.280733 # average overall miss latency
2758system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93768.773864 # average overall miss latency
2759system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91508.848735 # average overall miss latency
2760system.l2c.overall_avg_miss_latency::cpu0.inst 84595.914028 # average overall miss latency
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2763system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89525.680359 # average overall miss latency
2764system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92570.453734 # average overall miss latency
2765system.l2c.overall_avg_miss_latency::cpu1.inst 84405.354504 # average overall miss latency
2766system.l2c.overall_avg_miss_latency::cpu1.data 89331.102239 # average overall miss latency
2767system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132242.415545 # average overall miss latency
2768system.l2c.overall_avg_miss_latency::total 109391.280733 # average overall miss latency
2769system.l2c.blocked_cycles::no_mshrs 1791 # number of cycles access was blocked
2770system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2771system.l2c.blocked::no_mshrs 28 # number of cycles access was blocked
2772system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2773system.l2c.avg_blocked_cycles::no_mshrs 63.964286 # average number of cycles each access was blocked
2774system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2775system.l2c.fast_writes 0 # number of fast writes performed
2776system.l2c.cache_copies 0 # number of cache copies performed
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2778system.l2c.writebacks::total 1148541 # number of writebacks
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2809system.l2c.UpgradeReq_mshr_misses::cpu1.data 42979 # number of UpgradeReq MSHR misses
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2841system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable
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2844system.l2c.WriteReq_mshr_uncacheable::cpu0.data 30977 # number of WriteReq MSHR uncacheable
2845system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7515 # number of WriteReq MSHR uncacheable
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2850system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14539 # number of overall MSHR uncacheable misses
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2869system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 165173761 # number of SCUpgradeReq MSHR miss cycles
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2895system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27845565280 # number of overall MSHR miss cycles
2896system.l2c.overall_mshr_miss_latency::total 98308289156 # number of overall MSHR miss cycles
2897system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles
2898system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4742528250 # number of ReadReq MSHR uncacheable cycles
2899system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5282500 # number of ReadReq MSHR uncacheable cycles
2900system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 634028250 # number of ReadReq MSHR uncacheable cycles
2901system.l2c.ReadReq_mshr_uncacheable_latency::total 8569851750 # number of ReadReq MSHR uncacheable cycles
2902system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4479331501 # number of WriteReq MSHR uncacheable cycles
2903system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 791938501 # number of WriteReq MSHR uncacheable cycles
2904system.l2c.WriteReq_mshr_uncacheable_latency::total 5271270002 # number of WriteReq MSHR uncacheable cycles
2905system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles
2906system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9221859751 # number of overall MSHR uncacheable cycles
2907system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5282500 # number of overall MSHR uncacheable cycles
2908system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1425966751 # number of overall MSHR uncacheable cycles
2909system.l2c.overall_mshr_uncacheable_latency::total 13841121752 # number of overall MSHR uncacheable cycles
2910system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for ReadReq accesses
2911system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for ReadReq accesses
2912system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for ReadReq accesses
2913system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.192710 # mshr miss rate for ReadReq accesses
2914system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for ReadReq accesses
2915system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for ReadReq accesses
2916system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for ReadReq accesses
2917system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for ReadReq accesses
2918system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.181320 # mshr miss rate for ReadReq accesses
2919system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for ReadReq accesses
2920system.l2c.ReadReq_mshr_miss_rate::total 0.212132 # mshr miss rate for ReadReq accesses
2921system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770238 # mshr miss rate for WriteInvalidateReq accesses
2922system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.472421 # mshr miss rate for WriteInvalidateReq accesses
2923system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.683033 # mshr miss rate for WriteInvalidateReq accesses
2924system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.635002 # mshr miss rate for UpgradeReq accesses
2925system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.589189 # mshr miss rate for UpgradeReq accesses
2926system.l2c.UpgradeReq_mshr_miss_rate::total 0.612759 # mshr miss rate for UpgradeReq accesses
2927system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601971 # mshr miss rate for SCUpgradeReq accesses
2928system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590924 # mshr miss rate for SCUpgradeReq accesses
2929system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.596503 # mshr miss rate for SCUpgradeReq accesses
2930system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618691 # mshr miss rate for ReadExReq accesses
2931system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.515549 # mshr miss rate for ReadExReq accesses
2932system.l2c.ReadExReq_mshr_miss_rate::total 0.571866 # mshr miss rate for ReadExReq accesses
2933system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for demand accesses
2934system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for demand accesses
2935system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for demand accesses
2936system.l2c.demand_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for demand accesses
2937system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for demand accesses
2938system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for demand accesses
2939system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for demand accesses
2940system.l2c.demand_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for demand accesses
2941system.l2c.demand_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for demand accesses
2942system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for demand accesses
2943system.l2c.demand_mshr_miss_rate::total 0.232022 # mshr miss rate for demand accesses
2944system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.237974 # mshr miss rate for overall accesses
2945system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.295941 # mshr miss rate for overall accesses
2946system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089846 # mshr miss rate for overall accesses
2947system.l2c.overall_mshr_miss_rate::cpu0.data 0.256324 # mshr miss rate for overall accesses
2948system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.427262 # mshr miss rate for overall accesses
2949system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.269643 # mshr miss rate for overall accesses
2950system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315641 # mshr miss rate for overall accesses
2951system.l2c.overall_mshr_miss_rate::cpu1.inst 0.074539 # mshr miss rate for overall accesses
2952system.l2c.overall_mshr_miss_rate::cpu1.data 0.226930 # mshr miss rate for overall accesses
2953system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.431627 # mshr miss rate for overall accesses
2954system.l2c.overall_mshr_miss_rate::total 0.232022 # mshr miss rate for overall accesses
2955system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average ReadReq mshr miss latency
2956system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average ReadReq mshr miss latency
2957system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average ReadReq mshr miss latency
2958system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80918.630618 # average ReadReq mshr miss latency
2959system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average ReadReq mshr miss latency
2960system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average ReadReq mshr miss latency
2961system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average ReadReq mshr miss latency
2962system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average ReadReq mshr miss latency
2963system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 78953.022931 # average ReadReq mshr miss latency
2964system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average ReadReq mshr miss latency
2965system.l2c.ReadReq_avg_mshr_miss_latency::total 100443.793085 # average ReadReq mshr miss latency
2966system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33548.050591 # average WriteInvalidateReq mshr miss latency
2967system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32025.022175 # average WriteInvalidateReq mshr miss latency
2968system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33239.596409 # average WriteInvalidateReq mshr miss latency
2969system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17799.416115 # average UpgradeReq mshr miss latency
2970system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.188394 # average UpgradeReq mshr miss latency
2971system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17801.177159 # average UpgradeReq mshr miss latency
2972system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17787.396188 # average SCUpgradeReq mshr miss latency
2973system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17809.571812 # average SCUpgradeReq mshr miss latency
2974system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17798.269170 # average SCUpgradeReq mshr miss latency
2975system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77295.267829 # average ReadExReq mshr miss latency
2976system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72023.520979 # average ReadExReq mshr miss latency
2977system.l2c.ReadExReq_avg_mshr_miss_latency::total 75137.639645 # average ReadExReq mshr miss latency
2978system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency
2979system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency
2980system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency
2981system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency
2982system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency
2983system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency
2984system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency
2985system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency
2986system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency
2987system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency
2988system.l2c.demand_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency
2989system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81132.451251 # average overall mshr miss latency
2990system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78872.256622 # average overall mshr miss latency
2991system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72093.700926 # average overall mshr miss latency
2992system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79612.576422 # average overall mshr miss latency
2993system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120959.363061 # average overall mshr miss latency
2994system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76912.482242 # average overall mshr miss latency
2995system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79952.090183 # average overall mshr miss latency
2996system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71909.797212 # average overall mshr miss latency
2997system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76804.697197 # average overall mshr miss latency
2998system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119944.886691 # average overall mshr miss latency
2999system.l2c.overall_avg_mshr_miss_latency::total 96995.072864 # average overall mshr miss latency
3000system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency
3001system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150061.012846 # average ReadReq mshr uncacheable latency
3002system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average ReadReq mshr uncacheable latency
3003system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 90265.980923 # average ReadReq mshr uncacheable latency
3004system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94148.330129 # average ReadReq mshr uncacheable latency
3005system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144601.849792 # average WriteReq mshr uncacheable latency
3006system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105381.038057 # average WriteReq mshr uncacheable latency
3007system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136944.559961 # average WriteReq mshr uncacheable latency
3008system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency
3009system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147358.779038 # average overall mshr uncacheable latency
3010system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58694.444444 # average overall mshr uncacheable latency
3011system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 98078.736571 # average overall mshr uncacheable latency
3012system.l2c.overall_avg_mshr_uncacheable_latency::total 106867.220149 # average overall mshr uncacheable latency
3013system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3014system.membus.trans_dist::ReadReq 975380 # Transaction distribution
3015system.membus.trans_dist::ReadResp 975380 # Transaction distribution
3016system.membus.trans_dist::WriteReq 38492 # Transaction distribution
3017system.membus.trans_dist::WriteResp 38492 # Transaction distribution
3018system.membus.trans_dist::Writeback 1255244 # Transaction distribution
3019system.membus.trans_dist::WriteInvalidateReq 671368 # Transaction distribution
3020system.membus.trans_dist::WriteInvalidateResp 671368 # Transaction distribution
3021system.membus.trans_dist::UpgradeReq 435292 # Transaction distribution
3022system.membus.trans_dist::SCUpgradeReq 320448 # Transaction distribution
3023system.membus.trans_dist::UpgradeResp 117663 # Transaction distribution
3024system.membus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution
3025system.membus.trans_dist::ReadExReq 151367 # Transaction distribution
3026system.membus.trans_dist::ReadExResp 133687 # Transaction distribution
3027system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122574 # Packet count per connected master and slave (bytes)
3028system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
3029system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26446 # Packet count per connected master and slave (bytes)
3030system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5296349 # Packet count per connected master and slave (bytes)
3031system.membus.pkt_count_system.l2c.mem_side::total 5445421 # Packet count per connected master and slave (bytes)
3032system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335920 # Packet count per connected master and slave (bytes)
3033system.membus.pkt_count_system.iocache.mem_side::total 335920 # Packet count per connected master and slave (bytes)
3034system.membus.pkt_count::total 5781341 # Packet count per connected master and slave (bytes)
3035system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155681 # Cumulative packet size per connected master and slave (bytes)
3036system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
3037system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52892 # Cumulative packet size per connected master and slave (bytes)
3038system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 177552960 # Cumulative packet size per connected master and slave (bytes)
3039system.membus.pkt_size_system.l2c.mem_side::total 177762857 # Cumulative packet size per connected master and slave (bytes)
3040system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14095872 # Cumulative packet size per connected master and slave (bytes)
3041system.membus.pkt_size_system.iocache.mem_side::total 14095872 # Cumulative packet size per connected master and slave (bytes)
3042system.membus.pkt_size::total 191858729 # Cumulative packet size per connected master and slave (bytes)
3043system.membus.snoops 658635 # Total snoops (count)
3044system.membus.snoop_fanout::samples 3847839 # Request fanout histogram
3045system.membus.snoop_fanout::mean 1 # Request fanout histogram
3046system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3047system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3048system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3049system.membus.snoop_fanout::1 3847839 100.00% 100.00% # Request fanout histogram
3050system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3051system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3052system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3053system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3054system.membus.snoop_fanout::total 3847839 # Request fanout histogram
3055system.membus.reqLayer0.occupancy 109654500 # Layer occupancy (ticks)
3056system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3057system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
3058system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3059system.membus.reqLayer2.occupancy 21898998 # Layer occupancy (ticks)
3060system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3061system.membus.reqLayer5.occupancy 11397821385 # Layer occupancy (ticks)
3062system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3063system.membus.respLayer2.occupancy 6506682845 # Layer occupancy (ticks)
3064system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3065system.membus.respLayer3.occupancy 152058832 # Layer occupancy (ticks)
3066system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3067system.realview.ethernet.txBytes 966 # Bytes Transmitted
3068system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3069system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3070system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3071system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3072system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3073system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3101system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3102system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3103system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3104system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3105system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3106system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3107system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3108system.realview.ethernet.droppedPackets 0 # number of packets dropped
3109system.toL2Bus.trans_dist::ReadReq 5105910 # Transaction distribution
3110system.toL2Bus.trans_dist::ReadResp 5098639 # Transaction distribution
3111system.toL2Bus.trans_dist::WriteReq 38492 # Transaction distribution
3112system.toL2Bus.trans_dist::WriteResp 38492 # Transaction distribution
3113system.toL2Bus.trans_dist::Writeback 2490573 # Transaction distribution
3114system.toL2Bus.trans_dist::WriteInvalidateReq 937823 # Transaction distribution
3115system.toL2Bus.trans_dist::WriteInvalidateResp 830969 # Transaction distribution
3116system.toL2Bus.trans_dist::UpgradeReq 486096 # Transaction distribution
3117system.toL2Bus.trans_dist::SCUpgradeReq 332772 # Transaction distribution
3118system.toL2Bus.trans_dist::UpgradeResp 818868 # Transaction distribution
3119system.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution
3120system.toL2Bus.trans_dist::UpgradeFailResp 64 # Transaction distribution
3121system.toL2Bus.trans_dist::ReadExReq 302211 # Transaction distribution
3122system.toL2Bus.trans_dist::ReadExResp 302211 # Transaction distribution
3123system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8322623 # Packet count per connected master and slave (bytes)
3124system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6766752 # Packet count per connected master and slave (bytes)
3125system.toL2Bus.pkt_count::total 15089375 # Packet count per connected master and slave (bytes)
3126system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 277489443 # Cumulative packet size per connected master and slave (bytes)
3127system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218349254 # Cumulative packet size per connected master and slave (bytes)
3128system.toL2Bus.pkt_size::total 495838697 # Cumulative packet size per connected master and slave (bytes)
3129system.toL2Bus.snoops 1695482 # Total snoops (count)
3130system.toL2Bus.snoop_fanout::samples 9694113 # Request fanout histogram
3131system.toL2Bus.snoop_fanout::mean 1.011945 # Request fanout histogram
3132system.toL2Bus.snoop_fanout::stdev 0.108639 # Request fanout histogram
3133system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3134system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3135system.toL2Bus.snoop_fanout::1 9578315 98.81% 98.81% # Request fanout histogram
3136system.toL2Bus.snoop_fanout::2 115798 1.19% 100.00% # Request fanout histogram
3137system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3138system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3139system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3140system.toL2Bus.snoop_fanout::total 9694113 # Request fanout histogram
3141system.toL2Bus.reqLayer0.occupancy 8435746901 # Layer occupancy (ticks)
3142system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3143system.toL2Bus.snoopLayer0.occupancy 2506500 # Layer occupancy (ticks)
3144system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3145system.toL2Bus.respLayer0.occupancy 4797228870 # Layer occupancy (ticks)
3146system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3147system.toL2Bus.respLayer1.occupancy 4287100444 # Layer occupancy (ticks)
3148system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3149
3150---------- End Simulation Statistics ----------