1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.357291 # Number of seconds simulated
4sim_ticks 47357290872500 # Number of ticks simulated
5final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 179609 # Simulator instruction rate (inst/s)
8host_op_rate 211253 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9509351214 # Simulator tick rate (ticks/s)
10host_mem_usage 764316 # Number of bytes of host memory used
11host_seconds 4980.08 # Real time elapsed on the host
12sim_insts 894465242 # Number of instructions simulated
13sim_ops 1052057457 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory
27system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1077470 # Number of read requests accepted
84system.physmem.writeReqs 1907210 # Number of write requests accepted
85system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue
89system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 58565 # Per bank write bursts
96system.physmem.perBankRdBursts::1 71236 # Per bank write bursts
97system.physmem.perBankRdBursts::2 60619 # Per bank write bursts
98system.physmem.perBankRdBursts::3 68763 # Per bank write bursts
99system.physmem.perBankRdBursts::4 63623 # Per bank write bursts
100system.physmem.perBankRdBursts::5 74242 # Per bank write bursts
101system.physmem.perBankRdBursts::6 69161 # Per bank write bursts
102system.physmem.perBankRdBursts::7 67695 # Per bank write bursts
103system.physmem.perBankRdBursts::8 61029 # Per bank write bursts
104system.physmem.perBankRdBursts::9 112215 # Per bank write bursts
105system.physmem.perBankRdBursts::10 55292 # Per bank write bursts
106system.physmem.perBankRdBursts::11 71140 # Per bank write bursts
107system.physmem.perBankRdBursts::12 63760 # Per bank write bursts
108system.physmem.perBankRdBursts::13 63951 # Per bank write bursts
109system.physmem.perBankRdBursts::14 57537 # Per bank write bursts
110system.physmem.perBankRdBursts::15 58328 # Per bank write bursts
111system.physmem.perBankWrBursts::0 113661 # Per bank write bursts
112system.physmem.perBankWrBursts::1 123588 # Per bank write bursts
113system.physmem.perBankWrBursts::2 119813 # Per bank write bursts
114system.physmem.perBankWrBursts::3 126847 # Per bank write bursts
115system.physmem.perBankWrBursts::4 114977 # Per bank write bursts
116system.physmem.perBankWrBursts::5 123724 # Per bank write bursts
117system.physmem.perBankWrBursts::6 117451 # Per bank write bursts
118system.physmem.perBankWrBursts::7 117840 # Per bank write bursts
119system.physmem.perBankWrBursts::8 112656 # Per bank write bursts
120system.physmem.perBankWrBursts::9 114020 # Per bank write bursts
121system.physmem.perBankWrBursts::10 109420 # Per bank write bursts
122system.physmem.perBankWrBursts::11 118853 # Per bank write bursts
123system.physmem.perBankWrBursts::12 108855 # Per bank write bursts
124system.physmem.perBankWrBursts::13 111956 # Per bank write bursts
125system.physmem.perBankWrBursts::14 111151 # Per bank write bursts
126system.physmem.perBankWrBursts::15 113638 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 260 # Number of times write queue was full causing retry
129system.physmem.totGap 47357288950000 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 37 # Read request sizes (log2)
134system.physmem.readPktSize::4 5 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1077428 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2601 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1904607 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see
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153system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see
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157system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see
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160system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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191system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see
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196system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see
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204system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see
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220system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads
305system.physmem.totQLat 41096385470 # Total ticks spent queuing
306system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM
307system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers
308system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst
309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
310system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst
311system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s
312system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s
313system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s
314system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s
315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
316system.physmem.busUtil 0.03 # Data bus utilization in percentage
317system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
318system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
319system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
320system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing
321system.physmem.readRowHits 809420 # Number of row buffer hits during reads
322system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes
323system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads
324system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes
325system.physmem.avgGap 15866789.39 # Average gap between requests
326system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined
327system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ)
328system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ)
329system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ)
330system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ)
331system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ)
332system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ)
333system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ)
334system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ)
335system.physmem_0.averagePower 668.775859 # Core power per rank (mW)
336system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states
337system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states
338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
339system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states
340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
341system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ)
342system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ)
343system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ)
344system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ)
345system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ)
346system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ)
347system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ)
348system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ)
349system.physmem_1.averagePower 668.740522 # Core power per rank (mW)
350system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states
351system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states
352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
353system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states
354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
355system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
380system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
384system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
385system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
386system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
387system.cpu0.branchPred.lookups 151571686 # Number of BP lookups
388system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted
389system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect
390system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups
391system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits
392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
393system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage
394system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target.
395system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions.
396system.cpu_clk_domain.clock 500 # Clock period in ticks
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

418system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
419system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
420system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
421system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
422system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
423system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
424system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
425system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
426system.cpu0.dtb.walker.walks 310912 # Table walker walks requested
427system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors
428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate
429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate
430system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
449system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated
452system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst
460system.cpu0.dtb.inst_hits 0 # ITB inst hits
461system.cpu0.dtb.inst_misses 0 # ITB inst misses
462system.cpu0.dtb.read_hits 98035121 # DTB read hits
463system.cpu0.dtb.read_misses 261233 # DTB read misses
464system.cpu0.dtb.write_hits 86222704 # DTB write hits
465system.cpu0.dtb.write_misses 49679 # DTB write misses
466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
468system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
469system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
470system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB
471system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions
472system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch
473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
474system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions
475system.cpu0.dtb.read_accesses 98296354 # DTB read accesses
476system.cpu0.dtb.write_accesses 86272383 # DTB write accesses
477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
478system.cpu0.dtb.hits 184257825 # DTB hits
479system.cpu0.dtb.misses 310912 # DTB misses
480system.cpu0.dtb.accesses 184568737 # DTB accesses
481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
510system.cpu0.itb.walker.walks 67664 # Table walker walks requested
511system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors
512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate
513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate
514system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency
518system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency
519system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency
520system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency
521system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency
522system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency
523system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency
524system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency
525system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency
526system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
538system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
539system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
540system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated
541system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated
542system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated
543system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
544system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst
545system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst
546system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
547system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst
548system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst
549system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst
550system.cpu0.itb.inst_hits 272362835 # ITB inst hits
551system.cpu0.itb.inst_misses 67664 # ITB inst misses
552system.cpu0.itb.read_hits 0 # DTB read hits
553system.cpu0.itb.read_misses 0 # DTB read misses
554system.cpu0.itb.write_hits 0 # DTB write hits
555system.cpu0.itb.write_misses 0 # DTB write misses
556system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
557system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
558system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
559system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
560system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB
561system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
562system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
563system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
564system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions
565system.cpu0.itb.read_accesses 0 # DTB read accesses
566system.cpu0.itb.write_accesses 0 # DTB write accesses
567system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses
568system.cpu0.itb.hits 272362835 # DTB hits
569system.cpu0.itb.misses 67664 # DTB misses
570system.cpu0.itb.accesses 272430499 # DTB accesses
571system.cpu0.numCycles 1079786982 # number of cpu cycles simulated
572system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
573system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
574system.cpu0.committedInsts 504924574 # Number of instructions committed
575system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed
576system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit
577system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching
578system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
579system.cpu0.cpi 2.138511 # CPI: cycles per instruction
580system.cpu0.ipc 0.467615 # IPC: instructions per cycle
581system.cpu0.kern.inst.arm 0 # number of arm instructions executed
582system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed
583system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked
584system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped
585system.cpu0.dcache.tags.replacements 6269899 # number of replacements
586system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use
587system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks.
588system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks.
589system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks.
590system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit.
591system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor
592system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy
593system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy
594system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
595system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
596system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
597system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
598system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
599system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses
600system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses
601system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits
602system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits
603system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits
604system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits
605system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits
606system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits
607system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits
608system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits
609system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits
610system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits
611system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits
612system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits
613system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits
614system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits
615system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses
616system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses
617system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses
618system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses
619system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses
620system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses
621system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses
622system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses
623system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses
624system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses
625system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses
626system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses
627system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses
628system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses
629system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles
630system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles
631system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles
632system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles
633system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles
634system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles
635system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles
636system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles
637system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles
638system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles
639system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles
640system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # number of StoreCondFailReq miss cycles
641system.cpu0.dcache.demand_miss_latency::cpu0.data 114869281781 # number of demand (read+write) miss cycles
642system.cpu0.dcache.demand_miss_latency::total 114869281781 # number of demand (read+write) miss cycles
643system.cpu0.dcache.overall_miss_latency::cpu0.data 114869281781 # number of overall miss cycles
644system.cpu0.dcache.overall_miss_latency::total 114869281781 # number of overall miss cycles
645system.cpu0.dcache.ReadReq_accesses::cpu0.data 94789755 # number of ReadReq accesses(hits+misses)
646system.cpu0.dcache.ReadReq_accesses::total 94789755 # number of ReadReq accesses(hits+misses)
647system.cpu0.dcache.WriteReq_accesses::cpu0.data 82605230 # number of WriteReq accesses(hits+misses)
648system.cpu0.dcache.WriteReq_accesses::total 82605230 # number of WriteReq accesses(hits+misses)
649system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1146106 # number of WriteInvalidateReq accesses(hits+misses)
650system.cpu0.dcache.WriteInvalidateReq_accesses::total 1146106 # number of WriteInvalidateReq accesses(hits+misses)
651system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses)
652system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses)
653system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses)
654system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses)
655system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses
656system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses
657system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses
658system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses
659system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses
660system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses
661system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses
662system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses
663system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses
664system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses
665system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses
666system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses
667system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses
668system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses
669system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses
670system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses
671system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses
672system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses
673system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency
674system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency
675system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency
676system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency
677system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency
678system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency
679system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency
680system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency
681system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency
682system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency
683system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
684system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
685system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency
686system.cpu0.dcache.demand_avg_miss_latency::total 16292.988224 # average overall miss latency
687system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency
688system.cpu0.dcache.overall_avg_miss_latency::total 16292.988224 # average overall miss latency
689system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
690system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
691system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
692system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
693system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
694system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
695system.cpu0.dcache.fast_writes 0 # number of fast writes performed
696system.cpu0.dcache.cache_copies 0 # number of cache copies performed
697system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks
698system.cpu0.dcache.writebacks::total 4374601 # number of writebacks
699system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits
700system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits
701system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits
702system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits
703system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits
704system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits
705system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits
706system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits
707system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits
708system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits
709system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits
710system.cpu0.dcache.demand_mshr_hits::total 1476528 # number of demand (read+write) MSHR hits
711system.cpu0.dcache.overall_mshr_hits::cpu0.data 1476528 # number of overall MSHR hits
712system.cpu0.dcache.overall_mshr_hits::total 1476528 # number of overall MSHR hits
713system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 4079154 # number of ReadReq MSHR misses
714system.cpu0.dcache.ReadReq_mshr_misses::total 4079154 # number of ReadReq MSHR misses
715system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1494546 # number of WriteReq MSHR misses
716system.cpu0.dcache.WriteReq_mshr_misses::total 1494546 # number of WriteReq MSHR misses
717system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 864790 # number of WriteInvalidateReq MSHR misses
718system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 864790 # number of WriteInvalidateReq MSHR misses
719system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140704 # number of LoadLockedReq MSHR misses
720system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140704 # number of LoadLockedReq MSHR misses
721system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198425 # number of StoreCondReq MSHR misses
722system.cpu0.dcache.StoreCondReq_mshr_misses::total 198425 # number of StoreCondReq MSHR misses
723system.cpu0.dcache.demand_mshr_misses::cpu0.data 5573700 # number of demand (read+write) MSHR misses
724system.cpu0.dcache.demand_mshr_misses::total 5573700 # number of demand (read+write) MSHR misses
725system.cpu0.dcache.overall_mshr_misses::cpu0.data 5573700 # number of overall MSHR misses
726system.cpu0.dcache.overall_mshr_misses::total 5573700 # number of overall MSHR misses
727system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53839740568 # number of ReadReq MSHR miss cycles
728system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53839740568 # number of ReadReq MSHR miss cycles
729system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26185332493 # number of WriteReq MSHR miss cycles
730system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26185332493 # number of WriteReq MSHR miss cycles
731system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 33958968357 # number of WriteInvalidateReq MSHR miss cycles
732system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles
733system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles
734system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles
735system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3868892109 # number of StoreCondReq MSHR miss cycles
736system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles
737system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles
738system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles
739system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles
740system.cpu0.dcache.demand_mshr_miss_latency::total 80025073061 # number of demand (read+write) MSHR miss cycles
741system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles
742system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles
743system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles
744system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles
745system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles
746system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles
747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles
749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses
754system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses
757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses
758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses
759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses
760system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses
761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses
762system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses
763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency
764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency
765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency
766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency
767system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency
768system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency
769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency
770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency
771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency
772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency
779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
782system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
783system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
785system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
786system.cpu0.icache.tags.replacements 10307657 # number of replacements
787system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use
788system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks.
789system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks.
790system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks.
791system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit.
792system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor
793system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
794system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
795system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
796system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
797system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id
798system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
799system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses
800system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses
801system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits
802system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits
803system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits
804system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits
805system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits
806system.cpu0.icache.overall_hits::total 261841431 # number of overall hits
807system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses
808system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses
809system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses
810system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses
811system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses
812system.cpu0.icache.overall_misses::total 10308179 # number of overall misses
813system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles
814system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles
815system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles
816system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles
817system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles
818system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles
819system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses)
820system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses)
821system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses
822system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses
823system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses
824system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses
825system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses
826system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses
827system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses
828system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses
829system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses
830system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses
831system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency
832system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency
833system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency
834system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency
835system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency
836system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency
837system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
840system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
841system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
842system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843system.cpu0.icache.fast_writes 0 # number of fast writes performed
844system.cpu0.icache.cache_copies 0 # number of cache copies performed
845system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses
846system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses
847system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses
848system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses
849system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses
850system.cpu0.icache.overall_mshr_misses::total 10308179 # number of overall MSHR misses
851system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93061406416 # number of ReadReq MSHR miss cycles
852system.cpu0.icache.ReadReq_mshr_miss_latency::total 93061406416 # number of ReadReq MSHR miss cycles
853system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93061406416 # number of demand (read+write) MSHR miss cycles
854system.cpu0.icache.demand_mshr_miss_latency::total 93061406416 # number of demand (read+write) MSHR miss cycles
855system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93061406416 # number of overall MSHR miss cycles
856system.cpu0.icache.overall_mshr_miss_latency::total 93061406416 # number of overall MSHR miss cycles
857system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles
858system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles
859system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles
860system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles
861system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for ReadReq accesses
862system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037877 # mshr miss rate for ReadReq accesses
863system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for demand accesses
864system.cpu0.icache.demand_mshr_miss_rate::total 0.037877 # mshr miss rate for demand accesses
865system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for overall accesses
866system.cpu0.icache.overall_mshr_miss_rate::total 0.037877 # mshr miss rate for overall accesses
867system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average ReadReq mshr miss latency
868system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9027.919133 # average ReadReq mshr miss latency
869system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency
870system.cpu0.icache.demand_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency
871system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency
872system.cpu0.icache.overall_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency
873system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
874system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
875system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
876system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
877system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
878system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued
879system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified
880system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue
881system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
882system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
883system.cpu0.l2cache.prefetcher.pfSpanPage 1498641 # number of prefetches not generated due to page crossing
884system.cpu0.l2cache.tags.replacements 3094586 # number of replacements
885system.cpu0.l2cache.tags.tagsinuse 16261.036528 # Cycle average of tags in use
886system.cpu0.l2cache.tags.total_refs 17187399 # Total number of references to valid blocks.
887system.cpu0.l2cache.tags.sampled_refs 3110668 # Sample count of references to valid blocks.
888system.cpu0.l2cache.tags.avg_refs 5.525308 # Average number of references to valid blocks.
889system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit.
890system.cpu0.l2cache.tags.occ_blocks::writebacks 6030.877634 # Average occupied blocks per requestor
891system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.708580 # Average occupied blocks per requestor
892system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.789449 # Average occupied blocks per requestor
893system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5140.303922 # Average occupied blocks per requestor
894system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2691.250303 # Average occupied blocks per requestor
895system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2256.106640 # Average occupied blocks per requestor
896system.cpu0.l2cache.tags.occ_percent::writebacks 0.368096 # Average percentage of cache occupancy
897system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004072 # Average percentage of cache occupancy
898system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004626 # Average percentage of cache occupancy
899system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.313739 # Average percentage of cache occupancy
900system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.164261 # Average percentage of cache occupancy
901system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.137702 # Average percentage of cache occupancy
902system.cpu0.l2cache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy
903system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2268 # Occupied blocks per task id
904system.cpu0.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id
905system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13711 # Occupied blocks per task id
906system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
907system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 410 # Occupied blocks per task id
908system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1208 # Occupied blocks per task id
909system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 648 # Occupied blocks per task id
910system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 10 # Occupied blocks per task id
911system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id
914system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
915system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
916system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3981 # Occupied blocks per task id
918system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4660 # Occupied blocks per task id
919system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3950 # Occupied blocks per task id
920system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.138428 # Percentage of cache occupancy per task id
921system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id
922system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.836853 # Percentage of cache occupancy per task id
923system.cpu0.l2cache.tags.tag_accesses 360310183 # Number of tag accesses
924system.cpu0.l2cache.tags.data_accesses 360310183 # Number of data accesses
925system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541380 # number of ReadReq hits
926system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157488 # number of ReadReq hits
927system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9448425 # number of ReadReq hits
928system.cpu0.l2cache.ReadReq_hits::cpu0.data 3428429 # number of ReadReq hits
929system.cpu0.l2cache.ReadReq_hits::total 13575722 # number of ReadReq hits
930system.cpu0.l2cache.Writeback_hits::writebacks 4374599 # number of Writeback hits
931system.cpu0.l2cache.Writeback_hits::total 4374599 # number of Writeback hits
932system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 237260 # number of WriteInvalidateReq hits
933system.cpu0.l2cache.WriteInvalidateReq_hits::total 237260 # number of WriteInvalidateReq hits
934system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 76611 # number of UpgradeReq hits
935system.cpu0.l2cache.UpgradeReq_hits::total 76611 # number of UpgradeReq hits
936system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 40970 # number of SCUpgradeReq hits
937system.cpu0.l2cache.SCUpgradeReq_hits::total 40970 # number of SCUpgradeReq hits
938system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1008686 # number of ReadExReq hits
939system.cpu0.l2cache.ReadExReq_hits::total 1008686 # number of ReadExReq hits
940system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 541380 # number of demand (read+write) hits
941system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157488 # number of demand (read+write) hits
942system.cpu0.l2cache.demand_hits::cpu0.inst 9448425 # number of demand (read+write) hits
943system.cpu0.l2cache.demand_hits::cpu0.data 4437115 # number of demand (read+write) hits
944system.cpu0.l2cache.demand_hits::total 14584408 # number of demand (read+write) hits
945system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 541380 # number of overall hits
946system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157488 # number of overall hits
947system.cpu0.l2cache.overall_hits::cpu0.inst 9448425 # number of overall hits
948system.cpu0.l2cache.overall_hits::cpu0.data 4437115 # number of overall hits
949system.cpu0.l2cache.overall_hits::total 14584408 # number of overall hits
950system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11963 # number of ReadReq misses
951system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8535 # number of ReadReq misses
952system.cpu0.l2cache.ReadReq_misses::cpu0.inst 859753 # number of ReadReq misses
953system.cpu0.l2cache.ReadReq_misses::cpu0.data 791034 # number of ReadReq misses
954system.cpu0.l2cache.ReadReq_misses::total 1671285 # number of ReadReq misses
955system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 626077 # number of WriteInvalidateReq misses
956system.cpu0.l2cache.WriteInvalidateReq_misses::total 626077 # number of WriteInvalidateReq misses
957system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 129747 # number of UpgradeReq misses
958system.cpu0.l2cache.UpgradeReq_misses::total 129747 # number of UpgradeReq misses
959system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 157450 # number of SCUpgradeReq misses
960system.cpu0.l2cache.SCUpgradeReq_misses::total 157450 # number of SCUpgradeReq misses
961system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
962system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
963system.cpu0.l2cache.ReadExReq_misses::cpu0.data 281357 # number of ReadExReq misses
964system.cpu0.l2cache.ReadExReq_misses::total 281357 # number of ReadExReq misses
965system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11963 # number of demand (read+write) misses
966system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8535 # number of demand (read+write) misses
967system.cpu0.l2cache.demand_misses::cpu0.inst 859753 # number of demand (read+write) misses
968system.cpu0.l2cache.demand_misses::cpu0.data 1072391 # number of demand (read+write) misses
969system.cpu0.l2cache.demand_misses::total 1952642 # number of demand (read+write) misses
970system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11963 # number of overall misses
971system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8535 # number of overall misses
972system.cpu0.l2cache.overall_misses::cpu0.inst 859753 # number of overall misses
973system.cpu0.l2cache.overall_misses::cpu0.data 1072391 # number of overall misses
974system.cpu0.l2cache.overall_misses::total 1952642 # number of overall misses
975system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444201231 # number of ReadReq miss cycles
976system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355740746 # number of ReadReq miss cycles
977system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26443287117 # number of ReadReq miss cycles
978system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 29025017983 # number of ReadReq miss cycles
979system.cpu0.l2cache.ReadReq_miss_latency::total 56268247077 # number of ReadReq miss cycles
980system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 235084146 # number of WriteInvalidateReq miss cycles
981system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 235084146 # number of WriteInvalidateReq miss cycles
982system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2906366764 # number of UpgradeReq miss cycles
983system.cpu0.l2cache.UpgradeReq_miss_latency::total 2906366764 # number of UpgradeReq miss cycles
984system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3310532200 # number of SCUpgradeReq miss cycles
985system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3310532200 # number of SCUpgradeReq miss cycles
986system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2287498 # number of SCUpgradeFailReq miss cycles
987system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2287498 # number of SCUpgradeFailReq miss cycles
988system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14147306643 # number of ReadExReq miss cycles
989system.cpu0.l2cache.ReadExReq_miss_latency::total 14147306643 # number of ReadExReq miss cycles
990system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444201231 # number of demand (read+write) miss cycles
991system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355740746 # number of demand (read+write) miss cycles
992system.cpu0.l2cache.demand_miss_latency::cpu0.inst 26443287117 # number of demand (read+write) miss cycles
993system.cpu0.l2cache.demand_miss_latency::cpu0.data 43172324626 # number of demand (read+write) miss cycles
994system.cpu0.l2cache.demand_miss_latency::total 70415553720 # number of demand (read+write) miss cycles
995system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444201231 # number of overall miss cycles
996system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355740746 # number of overall miss cycles
997system.cpu0.l2cache.overall_miss_latency::cpu0.inst 26443287117 # number of overall miss cycles
998system.cpu0.l2cache.overall_miss_latency::cpu0.data 43172324626 # number of overall miss cycles
999system.cpu0.l2cache.overall_miss_latency::total 70415553720 # number of overall miss cycles
1000system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 553343 # number of ReadReq accesses(hits+misses)
1001system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166023 # number of ReadReq accesses(hits+misses)
1002system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 10308178 # number of ReadReq accesses(hits+misses)
1003system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4219463 # number of ReadReq accesses(hits+misses)
1004system.cpu0.l2cache.ReadReq_accesses::total 15247007 # number of ReadReq accesses(hits+misses)
1005system.cpu0.l2cache.Writeback_accesses::writebacks 4374599 # number of Writeback accesses(hits+misses)
1006system.cpu0.l2cache.Writeback_accesses::total 4374599 # number of Writeback accesses(hits+misses)
1007system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 863337 # number of WriteInvalidateReq accesses(hits+misses)
1008system.cpu0.l2cache.WriteInvalidateReq_accesses::total 863337 # number of WriteInvalidateReq accesses(hits+misses)
1009system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 206358 # number of UpgradeReq accesses(hits+misses)
1010system.cpu0.l2cache.UpgradeReq_accesses::total 206358 # number of UpgradeReq accesses(hits+misses)
1011system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 198420 # number of SCUpgradeReq accesses(hits+misses)
1012system.cpu0.l2cache.SCUpgradeReq_accesses::total 198420 # number of SCUpgradeReq accesses(hits+misses)
1013system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
1014system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
1015system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1290043 # number of ReadExReq accesses(hits+misses)
1016system.cpu0.l2cache.ReadExReq_accesses::total 1290043 # number of ReadExReq accesses(hits+misses)
1017system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 553343 # number of demand (read+write) accesses
1018system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166023 # number of demand (read+write) accesses
1019system.cpu0.l2cache.demand_accesses::cpu0.inst 10308178 # number of demand (read+write) accesses
1020system.cpu0.l2cache.demand_accesses::cpu0.data 5509506 # number of demand (read+write) accesses
1021system.cpu0.l2cache.demand_accesses::total 16537050 # number of demand (read+write) accesses
1022system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 553343 # number of overall (read+write) accesses
1023system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166023 # number of overall (read+write) accesses
1024system.cpu0.l2cache.overall_accesses::cpu0.inst 10308178 # number of overall (read+write) accesses
1025system.cpu0.l2cache.overall_accesses::cpu0.data 5509506 # number of overall (read+write) accesses
1026system.cpu0.l2cache.overall_accesses::total 16537050 # number of overall (read+write) accesses
1027system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for ReadReq accesses
1028system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051409 # miss rate for ReadReq accesses
1029system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.083405 # miss rate for ReadReq accesses
1030system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.187473 # miss rate for ReadReq accesses
1031system.cpu0.l2cache.ReadReq_miss_rate::total 0.109614 # miss rate for ReadReq accesses
1032system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.725183 # miss rate for WriteInvalidateReq accesses
1033system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.725183 # miss rate for WriteInvalidateReq accesses
1034system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.628747 # miss rate for UpgradeReq accesses
1035system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.628747 # miss rate for UpgradeReq accesses
1036system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.793519 # miss rate for SCUpgradeReq accesses
1037system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.793519 # miss rate for SCUpgradeReq accesses
1038system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1039system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1040system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.218099 # miss rate for ReadExReq accesses
1041system.cpu0.l2cache.ReadExReq_miss_rate::total 0.218099 # miss rate for ReadExReq accesses
1042system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for demand accesses
1043system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051409 # miss rate for demand accesses
1044system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.083405 # miss rate for demand accesses
1045system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.194644 # miss rate for demand accesses
1046system.cpu0.l2cache.demand_miss_rate::total 0.118077 # miss rate for demand accesses
1047system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for overall accesses
1048system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051409 # miss rate for overall accesses
1049system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.083405 # miss rate for overall accesses
1050system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.194644 # miss rate for overall accesses
1051system.cpu0.l2cache.overall_miss_rate::total 0.118077 # miss rate for overall accesses
1052system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average ReadReq miss latency
1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41680.228002 # average ReadReq miss latency
1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30756.841927 # average ReadReq miss latency
1055system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36692.503714 # average ReadReq miss latency
1056system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33667.655174 # average ReadReq miss latency
1057system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.487593 # average WriteInvalidateReq miss latency
1058system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.487593 # average WriteInvalidateReq miss latency
1059system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22400.261771 # average UpgradeReq miss latency
1060system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22400.261771 # average UpgradeReq miss latency
1061system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21025.926961 # average SCUpgradeReq miss latency
1062system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21025.926961 # average SCUpgradeReq miss latency
1063system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 457499.600000 # average SCUpgradeFailReq miss latency
1064system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 457499.600000 # average SCUpgradeFailReq miss latency
1065system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50282.405069 # average ReadExReq miss latency
1066system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50282.405069 # average ReadExReq miss latency
1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average overall miss latency
1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41680.228002 # average overall miss latency
1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30756.841927 # average overall miss latency
1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40258.007225 # average overall miss latency
1071system.cpu0.l2cache.demand_avg_miss_latency::total 36061.681414 # average overall miss latency
1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average overall miss latency
1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41680.228002 # average overall miss latency
1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30756.841927 # average overall miss latency
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40258.007225 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 36061.681414 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1085system.cpu0.l2cache.writebacks::writebacks 1572908 # number of writebacks
1086system.cpu0.l2cache.writebacks::total 1572908 # number of writebacks
1087system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits
1088system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 11 # number of ReadReq MSHR hits
1089system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3791 # number of ReadReq MSHR hits
1090system.cpu0.l2cache.ReadReq_mshr_hits::total 3806 # number of ReadReq MSHR hits
1091system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 19 # number of WriteInvalidateReq MSHR hits
1092system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 19 # number of WriteInvalidateReq MSHR hits
1093system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10276 # number of ReadExReq MSHR hits
1094system.cpu0.l2cache.ReadExReq_mshr_hits::total 10276 # number of ReadExReq MSHR hits
1095system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits
1096system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits
1097system.cpu0.l2cache.demand_mshr_hits::cpu0.data 14067 # number of demand (read+write) MSHR hits
1098system.cpu0.l2cache.demand_mshr_hits::total 14082 # number of demand (read+write) MSHR hits
1099system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits
1100system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits
1101system.cpu0.l2cache.overall_mshr_hits::cpu0.data 14067 # number of overall MSHR hits
1102system.cpu0.l2cache.overall_mshr_hits::total 14082 # number of overall MSHR hits
1103system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11963 # number of ReadReq MSHR misses
1104system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8531 # number of ReadReq MSHR misses
1105system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 859742 # number of ReadReq MSHR misses
1106system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 787243 # number of ReadReq MSHR misses
1107system.cpu0.l2cache.ReadReq_mshr_misses::total 1667479 # number of ReadReq MSHR misses
1108system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1152806 # number of HardPFReq MSHR misses
1109system.cpu0.l2cache.HardPFReq_mshr_misses::total 1152806 # number of HardPFReq MSHR misses
1110system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 626058 # number of WriteInvalidateReq MSHR misses
1111system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 626058 # number of WriteInvalidateReq MSHR misses
1112system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 129747 # number of UpgradeReq MSHR misses
1113system.cpu0.l2cache.UpgradeReq_mshr_misses::total 129747 # number of UpgradeReq MSHR misses
1114system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 157450 # number of SCUpgradeReq MSHR misses
1115system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 157450 # number of SCUpgradeReq MSHR misses
1116system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1117system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
1118system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 271081 # number of ReadExReq MSHR misses
1119system.cpu0.l2cache.ReadExReq_mshr_misses::total 271081 # number of ReadExReq MSHR misses
1120system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11963 # number of demand (read+write) MSHR misses
1121system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8531 # number of demand (read+write) MSHR misses
1122system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 859742 # number of demand (read+write) MSHR misses
1123system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1058324 # number of demand (read+write) MSHR misses
1124system.cpu0.l2cache.demand_mshr_misses::total 1938560 # number of demand (read+write) MSHR misses
1125system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11963 # number of overall MSHR misses
1126system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8531 # number of overall MSHR misses
1127system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 859742 # number of overall MSHR misses
1128system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1058324 # number of overall MSHR misses
1129system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1152806 # number of overall MSHR misses
1130system.cpu0.l2cache.overall_mshr_misses::total 3091366 # number of overall MSHR misses
1131system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of ReadReq MSHR miss cycles
1132system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 299632762 # number of ReadReq MSHR miss cycles
1133system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 20823449883 # number of ReadReq MSHR miss cycles
1134system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 23430974203 # number of ReadReq MSHR miss cycles
1135system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44919838115 # number of ReadReq MSHR miss cycles
1136system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 51873044967 # number of HardPFReq MSHR miss cycles
1137system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 51873044967 # number of HardPFReq MSHR miss cycles
1138system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 27342939109 # number of WriteInvalidateReq MSHR miss cycles
1139system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 27342939109 # number of WriteInvalidateReq MSHR miss cycles
1140system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2649227223 # number of UpgradeReq MSHR miss cycles
1141system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2649227223 # number of UpgradeReq MSHR miss cycles
1142system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2380002247 # number of SCUpgradeReq MSHR miss cycles
1143system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380002247 # number of SCUpgradeReq MSHR miss cycles
1144system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1949498 # number of SCUpgradeFailReq MSHR miss cycles
1145system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1949498 # number of SCUpgradeFailReq MSHR miss cycles
1146system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11193177649 # number of ReadExReq MSHR miss cycles
1147system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11193177649 # number of ReadExReq MSHR miss cycles
1148system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of demand (read+write) MSHR miss cycles
1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 299632762 # number of demand (read+write) MSHR miss cycles
1150system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20823449883 # number of demand (read+write) MSHR miss cycles
1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34624151852 # number of demand (read+write) MSHR miss cycles
1152system.cpu0.l2cache.demand_mshr_miss_latency::total 56113015764 # number of demand (read+write) MSHR miss cycles
1153system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of overall MSHR miss cycles
1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 299632762 # number of overall MSHR miss cycles
1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20823449883 # number of overall MSHR miss cycles
1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34624151852 # number of overall MSHR miss cycles
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 51873044967 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::total 107986060731 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles
1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5508458001 # number of ReadReq MSHR uncacheable cycles
1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9899528751 # number of ReadReq MSHR uncacheable cycles
1162system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5233419500 # number of WriteReq MSHR uncacheable cycles
1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5233419500 # number of WriteReq MSHR uncacheable cycles
1164system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles
1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10741877501 # number of overall MSHR uncacheable cycles
1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15132948251 # number of overall MSHR uncacheable cycles
1167system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for ReadReq accesses
1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for ReadReq accesses
1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for ReadReq accesses
1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.186574 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.109364 # mshr miss rate for ReadReq accesses
1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1174system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.725161 # mshr miss rate for WriteInvalidateReq accesses
1175system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.725161 # mshr miss rate for WriteInvalidateReq accesses
1176system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.628747 # mshr miss rate for UpgradeReq accesses
1177system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.628747 # mshr miss rate for UpgradeReq accesses
1178system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793519 # mshr miss rate for SCUpgradeReq accesses
1179system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.793519 # mshr miss rate for SCUpgradeReq accesses
1180system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1181system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1182system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210133 # mshr miss rate for ReadExReq accesses
1183system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210133 # mshr miss rate for ReadExReq accesses
1184system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for demand accesses
1185system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for demand accesses
1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for demand accesses
1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for demand accesses
1188system.cpu0.l2cache.demand_mshr_miss_rate::total 0.117225 # mshr miss rate for demand accesses
1189system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for overall accesses
1190system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for overall accesses
1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for overall accesses
1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for overall accesses
1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1194system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186936 # mshr miss rate for overall accesses
1195system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average ReadReq mshr miss latency
1196system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average ReadReq mshr miss latency
1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average ReadReq mshr miss latency
1198system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29763.331275 # average ReadReq mshr miss latency
1199system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency
1200system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency
1201system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency
1202system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency
1203system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency
1204system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency
1205system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency
1206system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency
1207system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency
1208system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency
1209system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency
1210system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency
1211system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency
1212system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency
1213system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency
1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency
1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency
1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency
1217system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency
1218system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency
1223system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1231system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1232system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution
1233system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution
1234system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution
1235system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution
1236system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution
1237system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution
1238system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution
1239system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution
1241system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution
1242system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution
1243system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
1244system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
1245system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution
1247system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes)
1248system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes)
1249system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes)
1250system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes)
1251system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes)
1252system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes)
1253system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes)
1254system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes)
1255system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes)
1256system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes)
1257system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count)
1258system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram
1259system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram
1260system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram
1261system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1262system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1263system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1264system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1265system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram
1266system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram
1267system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1268system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1269system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
1270system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram
1271system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks)
1272system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1273system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks)
1274system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1275system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks)
1276system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1277system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks)
1278system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1279system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks)
1280system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1281system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks)
1282system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1283system.cpu1.branchPred.lookups 120391711 # Number of BP lookups
1284system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted
1285system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect
1286system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups
1287system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits
1288system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1289system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage
1290system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target.
1291system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions.
1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1295system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1296system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1297system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1298system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1299system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1313system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1314system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1315system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1316system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1317system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1318system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1319system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1320system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1321system.cpu1.dtb.walker.walks 259478 # Table walker walks requested
1322system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors
1323system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate
1324system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate
1325system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency
1326system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1327system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency
1328system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency
1329system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency
1330system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency
1331system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency
1332system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency
1333system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency
1334system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency
1335system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency
1336system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency
1337system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency
1338system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency
1339system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency
1340system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency
1341system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency
1342system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1343system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
1344system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1345system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1346system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1347system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency
1348system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution
1349system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution
1350system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution
1351system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated
1352system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated
1353system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated
1354system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst
1355system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1356system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst
1357system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst
1358system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1359system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst
1360system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst
1361system.cpu1.dtb.inst_hits 0 # ITB inst hits
1362system.cpu1.dtb.inst_misses 0 # ITB inst misses
1363system.cpu1.dtb.read_hits 76628852 # DTB read hits
1364system.cpu1.dtb.read_misses 212787 # DTB read misses
1365system.cpu1.dtb.write_hits 67332330 # DTB write hits
1366system.cpu1.dtb.write_misses 46691 # DTB write misses
1367system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1368system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1369system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
1370system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
1371system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB
1372system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions
1373system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch
1374system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1375system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions
1376system.cpu1.dtb.read_accesses 76841639 # DTB read accesses
1377system.cpu1.dtb.write_accesses 67379021 # DTB write accesses
1378system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1379system.cpu1.dtb.hits 143961182 # DTB hits
1380system.cpu1.dtb.misses 259478 # DTB misses
1381system.cpu1.dtb.accesses 144220660 # DTB accesses
1382system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1383system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1384system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1385system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1386system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1387system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1388system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1389system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1403system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1404system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1405system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1406system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1407system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1408system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1409system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1410system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1411system.cpu1.itb.walker.walks 59975 # Table walker walks requested
1412system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors
1413system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate
1414system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate
1415system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency
1416system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1417system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency
1418system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency
1419system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency
1420system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency
1421system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency
1422system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency
1423system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency
1424system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency
1425system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency
1426system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency
1427system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
1428system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
1429system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1430system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency
1431system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution
1432system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution
1433system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution
1434system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated
1435system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated
1436system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated
1437system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1438system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst
1439system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst
1440system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1441system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst
1442system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst
1443system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst
1444system.cpu1.itb.inst_hits 214508261 # ITB inst hits
1445system.cpu1.itb.inst_misses 59975 # ITB inst misses
1446system.cpu1.itb.read_hits 0 # DTB read hits
1447system.cpu1.itb.read_misses 0 # DTB read misses
1448system.cpu1.itb.write_hits 0 # DTB write hits
1449system.cpu1.itb.write_misses 0 # DTB write misses
1450system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1451system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1452system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID
1453system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID
1454system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB
1455system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1456system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1457system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1458system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions
1459system.cpu1.itb.read_accesses 0 # DTB read accesses
1460system.cpu1.itb.write_accesses 0 # DTB write accesses
1461system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses
1462system.cpu1.itb.hits 214508261 # DTB hits
1463system.cpu1.itb.misses 59975 # DTB misses
1464system.cpu1.itb.accesses 214568236 # DTB accesses
1465system.cpu1.numCycles 819770260 # number of cpu cycles simulated
1466system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1467system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1468system.cpu1.committedInsts 389540668 # Number of instructions committed
1469system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed
1470system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit
1471system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching
1472system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1473system.cpu1.cpi 2.104454 # CPI: cycles per instruction
1474system.cpu1.ipc 0.475183 # IPC: instructions per cycle
1475system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1476system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed
1477system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked
1478system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped
1479system.cpu1.dcache.tags.replacements 4705434 # number of replacements
1480system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use
1481system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks.
1482system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks.
1483system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks.
1484system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit.
1485system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor
1486system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy
1487system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy
1488system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1489system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
1490system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
1491system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
1492system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1493system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses
1494system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses
1495system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits
1496system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits
1497system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits
1498system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits
1499system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits
1500system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits
1501system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits
1502system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits
1503system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits
1504system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits
1505system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits
1506system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits
1507system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits
1508system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits
1509system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses
1510system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses
1511system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses
1512system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses
1513system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses
1514system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses
1515system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses
1516system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses
1517system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses
1518system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses
1519system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses
1520system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses
1521system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses
1522system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses
1523system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles
1524system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles
1525system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles
1526system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles
1527system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles
1528system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles
1529system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles
1530system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles
1531system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles
1532system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles
1533system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles
1534system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles
1535system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles
1536system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles
1537system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles
1538system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles
1539system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses)
1540system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses)
1541system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses)
1542system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses)
1543system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses)
1544system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses)
1545system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses)
1546system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses)
1547system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses)
1548system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses)
1549system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses
1550system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses
1551system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses
1552system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses
1553system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses
1554system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses
1555system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses
1556system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses
1557system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses
1558system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses
1559system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses
1560system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses
1561system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses
1562system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses
1563system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses
1564system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses
1565system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses
1566system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses
1567system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency
1568system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency
1569system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency
1570system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency
1571system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency
1572system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency
1573system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency
1574system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency
1575system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency
1576system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency
1577system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1578system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1579system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency
1580system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency
1581system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency
1582system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency
1583system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1584system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1585system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1586system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1587system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1588system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1589system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1590system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1591system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks
1592system.cpu1.dcache.writebacks::total 3043303 # number of writebacks
1593system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits
1594system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits
1595system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits
1596system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits
1597system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits
1598system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits
1599system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits
1600system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits
1601system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits
1602system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits
1603system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits
1604system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits
1605system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits
1606system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits
1607system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses
1608system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses
1609system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses
1610system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses
1611system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses
1612system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # number of WriteInvalidateReq MSHR misses
1613system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105497 # number of LoadLockedReq MSHR misses
1614system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105497 # number of LoadLockedReq MSHR misses
1615system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 188206 # number of StoreCondReq MSHR misses
1616system.cpu1.dcache.StoreCondReq_mshr_misses::total 188206 # number of StoreCondReq MSHR misses
1617system.cpu1.dcache.demand_mshr_misses::cpu1.data 4524503 # number of demand (read+write) MSHR misses
1618system.cpu1.dcache.demand_mshr_misses::total 4524503 # number of demand (read+write) MSHR misses
1619system.cpu1.dcache.overall_mshr_misses::cpu1.data 4524503 # number of overall MSHR misses
1620system.cpu1.dcache.overall_mshr_misses::total 4524503 # number of overall MSHR misses
1621system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles
1622system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles
1623system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles
1624system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles
1625system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles
1626system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles
1627system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles
1628system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles
1629system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles
1630system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles
1631system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles
1632system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles
1633system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles
1634system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles
1635system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles
1636system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles
1637system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles
1638system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles
1639system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles
1640system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles
1641system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles
1642system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles
1643system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses
1644system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses
1645system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses
1646system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses
1647system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses
1648system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses
1649system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses
1650system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses
1651system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses
1652system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses
1653system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses
1654system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses
1655system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses
1656system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses
1657system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency
1658system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency
1659system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency
1660system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency
1661system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency
1662system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency
1663system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency
1664system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency
1665system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency
1666system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency
1667system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1668system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1669system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency
1670system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency
1671system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency
1672system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency
1673system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1674system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1675system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1676system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1677system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1678system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1679system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1680system.cpu1.icache.tags.replacements 8513181 # number of replacements
1681system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use
1682system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks.
1683system.cpu1.icache.tags.sampled_refs 8513693 # Sample count of references to valid blocks.
1684system.cpu1.icache.tags.avg_refs 24.169969 # Average number of references to valid blocks.
1685system.cpu1.icache.tags.warmup_cycle 8369241421000 # Cycle when the warmup percentage was hit.
1686system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.039853 # Average occupied blocks per requestor
1687system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990312 # Average percentage of cache occupancy
1688system.cpu1.icache.tags.occ_percent::total 0.990312 # Average percentage of cache occupancy
1689system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1690system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
1691system.cpu1.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
1692system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id
1693system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1694system.cpu1.icache.tags.tag_accesses 437092471 # Number of tag accesses
1695system.cpu1.icache.tags.data_accesses 437092471 # Number of data accesses
1696system.cpu1.icache.ReadReq_hits::cpu1.inst 205775695 # number of ReadReq hits
1697system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits
1698system.cpu1.icache.demand_hits::cpu1.inst 205775695 # number of demand (read+write) hits
1699system.cpu1.icache.demand_hits::total 205775695 # number of demand (read+write) hits
1700system.cpu1.icache.overall_hits::cpu1.inst 205775695 # number of overall hits
1701system.cpu1.icache.overall_hits::total 205775695 # number of overall hits
1702system.cpu1.icache.ReadReq_misses::cpu1.inst 8513694 # number of ReadReq misses
1703system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses
1704system.cpu1.icache.demand_misses::cpu1.inst 8513694 # number of demand (read+write) misses
1705system.cpu1.icache.demand_misses::total 8513694 # number of demand (read+write) misses
1706system.cpu1.icache.overall_misses::cpu1.inst 8513694 # number of overall misses
1707system.cpu1.icache.overall_misses::total 8513694 # number of overall misses
1708system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84159322077 # number of ReadReq miss cycles
1709system.cpu1.icache.ReadReq_miss_latency::total 84159322077 # number of ReadReq miss cycles
1710system.cpu1.icache.demand_miss_latency::cpu1.inst 84159322077 # number of demand (read+write) miss cycles
1711system.cpu1.icache.demand_miss_latency::total 84159322077 # number of demand (read+write) miss cycles
1712system.cpu1.icache.overall_miss_latency::cpu1.inst 84159322077 # number of overall miss cycles
1713system.cpu1.icache.overall_miss_latency::total 84159322077 # number of overall miss cycles
1714system.cpu1.icache.ReadReq_accesses::cpu1.inst 214289389 # number of ReadReq accesses(hits+misses)
1715system.cpu1.icache.ReadReq_accesses::total 214289389 # number of ReadReq accesses(hits+misses)
1716system.cpu1.icache.demand_accesses::cpu1.inst 214289389 # number of demand (read+write) accesses
1717system.cpu1.icache.demand_accesses::total 214289389 # number of demand (read+write) accesses
1718system.cpu1.icache.overall_accesses::cpu1.inst 214289389 # number of overall (read+write) accesses
1719system.cpu1.icache.overall_accesses::total 214289389 # number of overall (read+write) accesses
1720system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039730 # miss rate for ReadReq accesses
1721system.cpu1.icache.ReadReq_miss_rate::total 0.039730 # miss rate for ReadReq accesses
1722system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039730 # miss rate for demand accesses
1723system.cpu1.icache.demand_miss_rate::total 0.039730 # miss rate for demand accesses
1724system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039730 # miss rate for overall accesses
1725system.cpu1.icache.overall_miss_rate::total 0.039730 # miss rate for overall accesses
1726system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9885.171123 # average ReadReq miss latency
1727system.cpu1.icache.ReadReq_avg_miss_latency::total 9885.171123 # average ReadReq miss latency
1728system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency
1729system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency
1730system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency
1731system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency
1732system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1733system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1734system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1735system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1736system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1737system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1738system.cpu1.icache.fast_writes 0 # number of fast writes performed
1739system.cpu1.icache.cache_copies 0 # number of cache copies performed
1740system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513694 # number of ReadReq MSHR misses
1741system.cpu1.icache.ReadReq_mshr_misses::total 8513694 # number of ReadReq MSHR misses
1742system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513694 # number of demand (read+write) MSHR misses
1743system.cpu1.icache.demand_mshr_misses::total 8513694 # number of demand (read+write) MSHR misses
1744system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513694 # number of overall MSHR misses
1745system.cpu1.icache.overall_mshr_misses::total 8513694 # number of overall MSHR misses
1746system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75624287377 # number of ReadReq MSHR miss cycles
1747system.cpu1.icache.ReadReq_mshr_miss_latency::total 75624287377 # number of ReadReq MSHR miss cycles
1748system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75624287377 # number of demand (read+write) MSHR miss cycles
1749system.cpu1.icache.demand_mshr_miss_latency::total 75624287377 # number of demand (read+write) MSHR miss cycles
1750system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75624287377 # number of overall MSHR miss cycles
1751system.cpu1.icache.overall_mshr_miss_latency::total 75624287377 # number of overall MSHR miss cycles
1752system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8552000 # number of ReadReq MSHR uncacheable cycles
1753system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles
1754system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles
1755system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles
1756system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses
1757system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses
1758system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses
1759system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses
1760system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses
1761system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses
1762system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency
1763system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency
1764system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency
1765system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency
1766system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency
1767system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency
1768system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1769system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1770system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1771system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1772system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1773system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued
1774system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified
1775system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue
1776system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1777system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1778system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing
1779system.cpu1.l2cache.tags.replacements 2221085 # number of replacements
1780system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use
1781system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks.
1782system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks.
1783system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks.
1784system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit.
1785system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor
1786system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor
1787system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor
1788system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor
1789system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor
1790system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # Average occupied blocks per requestor
1791system.cpu1.l2cache.tags.occ_percent::writebacks 0.322275 # Average percentage of cache occupancy
1792system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004564 # Average percentage of cache occupancy
1793system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005005 # Average percentage of cache occupancy
1794system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.241875 # Average percentage of cache occupancy
1795system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.145903 # Average percentage of cache occupancy
1796system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093924 # Average percentage of cache occupancy
1797system.cpu1.l2cache.tags.occ_percent::total 0.813547 # Average percentage of cache occupancy
1798system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2457 # Occupied blocks per task id
1799system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
1800system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13645 # Occupied blocks per task id
1801system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
1802system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 113 # Occupied blocks per task id
1803system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 719 # Occupied blocks per task id
1804system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 972 # Occupied blocks per task id
1805system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 645 # Occupied blocks per task id
1806system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
1807system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
1808system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
1809system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
1810system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id
1811system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4967 # Occupied blocks per task id
1812system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4448 # Occupied blocks per task id
1813system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3191 # Occupied blocks per task id
1814system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.149963 # Percentage of cache occupancy per task id
1815system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
1816system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832825 # Percentage of cache occupancy per task id
1817system.cpu1.l2cache.tags.tag_accesses 282497183 # Number of tag accesses
1818system.cpu1.l2cache.tags.data_accesses 282497183 # Number of data accesses
1819system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 472812 # number of ReadReq hits
1820system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141552 # number of ReadReq hits
1821system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7799132 # number of ReadReq hits
1822system.cpu1.l2cache.ReadReq_hits::cpu1.data 2711848 # number of ReadReq hits
1823system.cpu1.l2cache.ReadReq_hits::total 11125344 # number of ReadReq hits
1824system.cpu1.l2cache.Writeback_hits::writebacks 3043302 # number of Writeback hits
1825system.cpu1.l2cache.Writeback_hits::total 3043302 # number of Writeback hits
1826system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 157363 # number of WriteInvalidateReq hits
1827system.cpu1.l2cache.WriteInvalidateReq_hits::total 157363 # number of WriteInvalidateReq hits
1828system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71855 # number of UpgradeReq hits
1829system.cpu1.l2cache.UpgradeReq_hits::total 71855 # number of UpgradeReq hits
1830system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32392 # number of SCUpgradeReq hits
1831system.cpu1.l2cache.SCUpgradeReq_hits::total 32392 # number of SCUpgradeReq hits
1832system.cpu1.l2cache.ReadExReq_hits::cpu1.data 766594 # number of ReadExReq hits
1833system.cpu1.l2cache.ReadExReq_hits::total 766594 # number of ReadExReq hits
1834system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 472812 # number of demand (read+write) hits
1835system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141552 # number of demand (read+write) hits
1836system.cpu1.l2cache.demand_hits::cpu1.inst 7799132 # number of demand (read+write) hits
1837system.cpu1.l2cache.demand_hits::cpu1.data 3478442 # number of demand (read+write) hits
1838system.cpu1.l2cache.demand_hits::total 11891938 # number of demand (read+write) hits
1839system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 472812 # number of overall hits
1840system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141552 # number of overall hits
1841system.cpu1.l2cache.overall_hits::cpu1.inst 7799132 # number of overall hits
1842system.cpu1.l2cache.overall_hits::cpu1.data 3478442 # number of overall hits
1843system.cpu1.l2cache.overall_hits::total 11891938 # number of overall hits
1844system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12653 # number of ReadReq misses
1845system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8998 # number of ReadReq misses
1846system.cpu1.l2cache.ReadReq_misses::cpu1.inst 714562 # number of ReadReq misses
1847system.cpu1.l2cache.ReadReq_misses::cpu1.data 692201 # number of ReadReq misses
1848system.cpu1.l2cache.ReadReq_misses::total 1428414 # number of ReadReq misses
1849system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
1850system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
1851system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 224018 # number of WriteInvalidateReq misses
1852system.cpu1.l2cache.WriteInvalidateReq_misses::total 224018 # number of WriteInvalidateReq misses
1853system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142871 # number of UpgradeReq misses
1854system.cpu1.l2cache.UpgradeReq_misses::total 142871 # number of UpgradeReq misses
1855system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 155808 # number of SCUpgradeReq misses
1856system.cpu1.l2cache.SCUpgradeReq_misses::total 155808 # number of SCUpgradeReq misses
1857system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
1858system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
1859system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245850 # number of ReadExReq misses
1860system.cpu1.l2cache.ReadExReq_misses::total 245850 # number of ReadExReq misses
1861system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12653 # number of demand (read+write) misses
1862system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8998 # number of demand (read+write) misses
1863system.cpu1.l2cache.demand_misses::cpu1.inst 714562 # number of demand (read+write) misses
1864system.cpu1.l2cache.demand_misses::cpu1.data 938051 # number of demand (read+write) misses
1865system.cpu1.l2cache.demand_misses::total 1674264 # number of demand (read+write) misses
1866system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12653 # number of overall misses
1867system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8998 # number of overall misses
1868system.cpu1.l2cache.overall_misses::cpu1.inst 714562 # number of overall misses
1869system.cpu1.l2cache.overall_misses::cpu1.data 938051 # number of overall misses
1870system.cpu1.l2cache.overall_misses::total 1674264 # number of overall misses
1871system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 449558190 # number of ReadReq miss cycles
1872system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 345348999 # number of ReadReq miss cycles
1873system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20635717509 # number of ReadReq miss cycles
1874system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 20877681975 # number of ReadReq miss cycles
1875system.cpu1.l2cache.ReadReq_miss_latency::total 42308306673 # number of ReadReq miss cycles
1876system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 229084267 # number of WriteInvalidateReq miss cycles
1877system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 229084267 # number of WriteInvalidateReq miss cycles
1878system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3047787464 # number of UpgradeReq miss cycles
1879system.cpu1.l2cache.UpgradeReq_miss_latency::total 3047787464 # number of UpgradeReq miss cycles
1880system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3209370896 # number of SCUpgradeReq miss cycles
1881system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3209370896 # number of SCUpgradeReq miss cycles
1882system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2764497 # number of SCUpgradeFailReq miss cycles
1883system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2764497 # number of SCUpgradeFailReq miss cycles
1884system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9785037151 # number of ReadExReq miss cycles
1885system.cpu1.l2cache.ReadExReq_miss_latency::total 9785037151 # number of ReadExReq miss cycles
1886system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 449558190 # number of demand (read+write) miss cycles
1887system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 345348999 # number of demand (read+write) miss cycles
1888system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20635717509 # number of demand (read+write) miss cycles
1889system.cpu1.l2cache.demand_miss_latency::cpu1.data 30662719126 # number of demand (read+write) miss cycles
1890system.cpu1.l2cache.demand_miss_latency::total 52093343824 # number of demand (read+write) miss cycles
1891system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449558190 # number of overall miss cycles
1892system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 345348999 # number of overall miss cycles
1893system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20635717509 # number of overall miss cycles
1894system.cpu1.l2cache.overall_miss_latency::cpu1.data 30662719126 # number of overall miss cycles
1895system.cpu1.l2cache.overall_miss_latency::total 52093343824 # number of overall miss cycles
1896system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 485465 # number of ReadReq accesses(hits+misses)
1897system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150550 # number of ReadReq accesses(hits+misses)
1898system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513694 # number of ReadReq accesses(hits+misses)
1899system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3404049 # number of ReadReq accesses(hits+misses)
1900system.cpu1.l2cache.ReadReq_accesses::total 12553758 # number of ReadReq accesses(hits+misses)
1901system.cpu1.l2cache.Writeback_accesses::writebacks 3043303 # number of Writeback accesses(hits+misses)
1902system.cpu1.l2cache.Writeback_accesses::total 3043303 # number of Writeback accesses(hits+misses)
1903system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 381381 # number of WriteInvalidateReq accesses(hits+misses)
1904system.cpu1.l2cache.WriteInvalidateReq_accesses::total 381381 # number of WriteInvalidateReq accesses(hits+misses)
1905system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214726 # number of UpgradeReq accesses(hits+misses)
1906system.cpu1.l2cache.UpgradeReq_accesses::total 214726 # number of UpgradeReq accesses(hits+misses)
1907system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 188200 # number of SCUpgradeReq accesses(hits+misses)
1908system.cpu1.l2cache.SCUpgradeReq_accesses::total 188200 # number of SCUpgradeReq accesses(hits+misses)
1909system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
1910system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
1911system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1012444 # number of ReadExReq accesses(hits+misses)
1912system.cpu1.l2cache.ReadExReq_accesses::total 1012444 # number of ReadExReq accesses(hits+misses)
1913system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 485465 # number of demand (read+write) accesses
1914system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150550 # number of demand (read+write) accesses
1915system.cpu1.l2cache.demand_accesses::cpu1.inst 8513694 # number of demand (read+write) accesses
1916system.cpu1.l2cache.demand_accesses::cpu1.data 4416493 # number of demand (read+write) accesses
1917system.cpu1.l2cache.demand_accesses::total 13566202 # number of demand (read+write) accesses
1918system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 485465 # number of overall (read+write) accesses
1919system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150550 # number of overall (read+write) accesses
1920system.cpu1.l2cache.overall_accesses::cpu1.inst 8513694 # number of overall (read+write) accesses
1921system.cpu1.l2cache.overall_accesses::cpu1.data 4416493 # number of overall (read+write) accesses
1922system.cpu1.l2cache.overall_accesses::total 13566202 # number of overall (read+write) accesses
1923system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for ReadReq accesses
1924system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059768 # miss rate for ReadReq accesses
1925system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.083931 # miss rate for ReadReq accesses
1926system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.203346 # miss rate for ReadReq accesses
1927system.cpu1.l2cache.ReadReq_miss_rate::total 0.113784 # miss rate for ReadReq accesses
1928system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
1929system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
1930system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.587386 # miss rate for WriteInvalidateReq accesses
1931system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.587386 # miss rate for WriteInvalidateReq accesses
1932system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.665364 # miss rate for UpgradeReq accesses
1933system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.665364 # miss rate for UpgradeReq accesses
1934system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.827885 # miss rate for SCUpgradeReq accesses
1935system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.827885 # miss rate for SCUpgradeReq accesses
1936system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1937system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1938system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.242828 # miss rate for ReadExReq accesses
1939system.cpu1.l2cache.ReadExReq_miss_rate::total 0.242828 # miss rate for ReadExReq accesses
1940system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for demand accesses
1941system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059768 # miss rate for demand accesses
1942system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.083931 # miss rate for demand accesses
1943system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212397 # miss rate for demand accesses
1944system.cpu1.l2cache.demand_miss_rate::total 0.123414 # miss rate for demand accesses
1945system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for overall accesses
1946system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059768 # miss rate for overall accesses
1947system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.083931 # miss rate for overall accesses
1948system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212397 # miss rate for overall accesses
1949system.cpu1.l2cache.overall_miss_rate::total 0.123414 # miss rate for overall accesses
1950system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average ReadReq miss latency
1951system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38380.640031 # average ReadReq miss latency
1952system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28878.834180 # average ReadReq miss latency
1953system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30161.299933 # average ReadReq miss latency
1954system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29619.078694 # average ReadReq miss latency
1955system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 1022.615446 # average WriteInvalidateReq miss latency
1956system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 1022.615446 # average WriteInvalidateReq miss latency
1957system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21332.443001 # average UpgradeReq miss latency
1958system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21332.443001 # average UpgradeReq miss latency
1959system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20598.242041 # average SCUpgradeReq miss latency
1960system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20598.242041 # average SCUpgradeReq miss latency
1961system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 460749.500000 # average SCUpgradeFailReq miss latency
1962system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 460749.500000 # average SCUpgradeFailReq miss latency
1963system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39800.842591 # average ReadExReq miss latency
1964system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39800.842591 # average ReadExReq miss latency
1965system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average overall miss latency
1966system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38380.640031 # average overall miss latency
1967system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28878.834180 # average overall miss latency
1968system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32687.688757 # average overall miss latency
1969system.cpu1.l2cache.demand_avg_miss_latency::total 31114.175437 # average overall miss latency
1970system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average overall miss latency
1971system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38380.640031 # average overall miss latency
1972system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28878.834180 # average overall miss latency
1973system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32687.688757 # average overall miss latency
1974system.cpu1.l2cache.overall_avg_miss_latency::total 31114.175437 # average overall miss latency
1975system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1976system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1977system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1978system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1979system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1980system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1981system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1982system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1983system.cpu1.l2cache.writebacks::writebacks 931967 # number of writebacks
1984system.cpu1.l2cache.writebacks::total 931967 # number of writebacks
1985system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
1986system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
1987system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1680 # number of ReadReq MSHR hits
1988system.cpu1.l2cache.ReadReq_mshr_hits::total 1690 # number of ReadReq MSHR hits
1989system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 17 # number of WriteInvalidateReq MSHR hits
1990system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 17 # number of WriteInvalidateReq MSHR hits
1991system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5999 # number of ReadExReq MSHR hits
1992system.cpu1.l2cache.ReadExReq_mshr_hits::total 5999 # number of ReadExReq MSHR hits
1993system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
1994system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
1995system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7679 # number of demand (read+write) MSHR hits
1996system.cpu1.l2cache.demand_mshr_hits::total 7689 # number of demand (read+write) MSHR hits
1997system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
1998system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
1999system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7679 # number of overall MSHR hits
2000system.cpu1.l2cache.overall_mshr_hits::total 7689 # number of overall MSHR hits
2001system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12653 # number of ReadReq MSHR misses
2002system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8995 # number of ReadReq MSHR misses
2003system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 714555 # number of ReadReq MSHR misses
2004system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 690521 # number of ReadReq MSHR misses
2005system.cpu1.l2cache.ReadReq_mshr_misses::total 1426724 # number of ReadReq MSHR misses
2006system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
2007system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
2008system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 936864 # number of HardPFReq MSHR misses
2009system.cpu1.l2cache.HardPFReq_mshr_misses::total 936864 # number of HardPFReq MSHR misses
2010system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 224001 # number of WriteInvalidateReq MSHR misses
2011system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 224001 # number of WriteInvalidateReq MSHR misses
2012system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 142871 # number of UpgradeReq MSHR misses
2013system.cpu1.l2cache.UpgradeReq_mshr_misses::total 142871 # number of UpgradeReq MSHR misses
2014system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 155808 # number of SCUpgradeReq MSHR misses
2015system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 155808 # number of SCUpgradeReq MSHR misses
2016system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
2017system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
2018system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 239851 # number of ReadExReq MSHR misses
2019system.cpu1.l2cache.ReadExReq_mshr_misses::total 239851 # number of ReadExReq MSHR misses
2020system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12653 # number of demand (read+write) MSHR misses
2021system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8995 # number of demand (read+write) MSHR misses
2022system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 714555 # number of demand (read+write) MSHR misses
2023system.cpu1.l2cache.demand_mshr_misses::cpu1.data 930372 # number of demand (read+write) MSHR misses
2024system.cpu1.l2cache.demand_mshr_misses::total 1666575 # number of demand (read+write) MSHR misses
2025system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12653 # number of overall MSHR misses
2026system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8995 # number of overall MSHR misses
2027system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 714555 # number of overall MSHR misses
2028system.cpu1.l2cache.overall_mshr_misses::cpu1.data 930372 # number of overall MSHR misses
2029system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 936864 # number of overall MSHR misses
2030system.cpu1.l2cache.overall_mshr_misses::total 2603439 # number of overall MSHR misses
2031system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of ReadReq MSHR miss cycles
2032system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286315515 # number of ReadReq MSHR miss cycles
2033system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 15972439241 # number of ReadReq MSHR miss cycles
2034system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 16244239643 # number of ReadReq MSHR miss cycles
2035system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 32869715189 # number of ReadReq MSHR miss cycles
2036system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of HardPFReq MSHR miss cycles
2037system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 33861408353 # number of HardPFReq MSHR miss cycles
2038system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6819895822 # number of WriteInvalidateReq MSHR miss cycles
2039system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6819895822 # number of WriteInvalidateReq MSHR miss cycles
2040system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2772663634 # number of UpgradeReq MSHR miss cycles
2041system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2772663634 # number of UpgradeReq MSHR miss cycles
2042system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2270029922 # number of SCUpgradeReq MSHR miss cycles
2043system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2270029922 # number of SCUpgradeReq MSHR miss cycles
2044system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2361497 # number of SCUpgradeFailReq MSHR miss cycles
2045system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2361497 # number of SCUpgradeFailReq MSHR miss cycles
2046system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7617845684 # number of ReadExReq MSHR miss cycles
2047system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7617845684 # number of ReadExReq MSHR miss cycles
2048system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of demand (read+write) MSHR miss cycles
2049system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286315515 # number of demand (read+write) MSHR miss cycles
2050system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15972439241 # number of demand (read+write) MSHR miss cycles
2051system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 23862085327 # number of demand (read+write) MSHR miss cycles
2052system.cpu1.l2cache.demand_mshr_miss_latency::total 40487560873 # number of demand (read+write) MSHR miss cycles
2053system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of overall MSHR miss cycles
2054system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286315515 # number of overall MSHR miss cycles
2055system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15972439241 # number of overall MSHR miss cycles
2056system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 23862085327 # number of overall MSHR miss cycles
2057system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of overall MSHR miss cycles
2058system.cpu1.l2cache.overall_mshr_miss_latency::total 74348969226 # number of overall MSHR miss cycles
2059system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7789000 # number of ReadReq MSHR uncacheable cycles
2060system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 632822249 # number of ReadReq MSHR uncacheable cycles
2061system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 640611249 # number of ReadReq MSHR uncacheable cycles
2062system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 765196000 # number of WriteReq MSHR uncacheable cycles
2063system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 765196000 # number of WriteReq MSHR uncacheable cycles
2064system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7789000 # number of overall MSHR uncacheable cycles
2065system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1398018249 # number of overall MSHR uncacheable cycles
2066system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1405807249 # number of overall MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for ReadReq accesses
2068system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for ReadReq accesses
2069system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for ReadReq accesses
2070system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.202853 # mshr miss rate for ReadReq accesses
2071system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.113649 # mshr miss rate for ReadReq accesses
2072system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
2073system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
2074system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.587342 # mshr miss rate for WriteInvalidateReq accesses
2077system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.587342 # mshr miss rate for WriteInvalidateReq accesses
2078system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.665364 # mshr miss rate for UpgradeReq accesses
2079system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.665364 # mshr miss rate for UpgradeReq accesses
2080system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827885 # mshr miss rate for SCUpgradeReq accesses
2081system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827885 # mshr miss rate for SCUpgradeReq accesses
2082system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2083system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2084system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.236903 # mshr miss rate for ReadExReq accesses
2085system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.236903 # mshr miss rate for ReadExReq accesses
2086system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for demand accesses
2087system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for demand accesses
2088system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for demand accesses
2089system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for demand accesses
2090system.cpu1.l2cache.demand_mshr_miss_rate::total 0.122848 # mshr miss rate for demand accesses
2091system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses
2092system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses
2093system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses
2094system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses
2095system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2096system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses
2097system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency
2098system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency
2099system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency
2100system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency
2101system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency
2102system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency
2103system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency
2104system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency
2105system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency
2106system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency
2107system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency
2108system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency
2109system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency
2110system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency
2111system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency
2112system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency
2113system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency
2114system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency
2115system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency
2116system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency
2117system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency
2118system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency
2119system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency
2120system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency
2121system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency
2125system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2126system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2128system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2129system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2130system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2133system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2134system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution
2135system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution
2136system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution
2137system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution
2138system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution
2139system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution
2140system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution
2141system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution
2142system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution
2143system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution
2144system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution
2145system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
2146system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
2147system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution
2148system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution
2149system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes)
2150system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes)
2151system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes)
2152system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes)
2153system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes)
2154system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes)
2155system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes)
2156system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes)
2157system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes)
2158system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes)
2159system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count)
2160system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram
2161system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram
2162system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram
2163system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2164system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2165system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2166system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2167system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram
2168system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram
2169system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2170system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
2171system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
2172system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram
2173system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks)
2174system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2175system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks)
2176system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2177system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks)
2178system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2179system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks)
2180system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2181system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks)
2182system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2183system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks)
2184system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2185system.iobus.trans_dist::ReadReq 40350 # Transaction distribution
2186system.iobus.trans_dist::ReadResp 40350 # Transaction distribution
2187system.iobus.trans_dist::WriteReq 136657 # Transaction distribution
2188system.iobus.trans_dist::WriteResp 29929 # Transaction distribution
2189system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2190system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes)
2191system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2192system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2193system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2194system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2195system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2196system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2197system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2198system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2199system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2200system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2201system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2202system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2203system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2204system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2205system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes)
2206system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes)
2207system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes)
2208system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2209system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2210system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes)
2211system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes)
2212system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2213system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2214system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2215system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2216system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2217system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2218system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2219system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2220system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2221system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2222system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2223system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2224system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2225system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2226system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes)
2227system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes)
2228system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes)
2229system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2230system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2231system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes)
2232system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks)
2233system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2234system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2235system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2236system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2237system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2238system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2239system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2240system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)

--- 11 unchanged lines hidden (view full) ---

2252system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
2253system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2254system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2255system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2256system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2257system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2258system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2259system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2260system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks)
2261system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2262system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2263system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2264system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks)
2265system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2266system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks)
2267system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2268system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
2269system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2270system.iocache.tags.replacements 115588 # number of replacements
2271system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use
2272system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2273system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks.
2274system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2275system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit.
2276system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor
2277system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor
2278system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy
2279system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy
2280system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy
2281system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2282system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2283system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2284system.iocache.tags.tag_accesses 1040820 # Number of tag accesses
2285system.iocache.tags.data_accesses 1040820 # Number of data accesses
2286system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2287system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses
2288system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses
2289system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2290system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2291system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2292system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2293system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2294system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses
2295system.iocache.demand_misses::total 8919 # number of demand (read+write) misses
2296system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2297system.iocache.overall_misses::realview.ide 8879 # number of overall misses
2298system.iocache.overall_misses::total 8919 # number of overall misses
2299system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
2300system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles
2301system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles
2302system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
2303system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
2304system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles
2305system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles
2306system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
2307system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles
2308system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles
2309system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
2310system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles
2311system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles
2312system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2313system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses)
2314system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses)
2315system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2316system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2317system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
2318system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
2319system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2320system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses
2321system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses
2322system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2323system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses
2324system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses
2325system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2326system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2327system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2328system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2329system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2330system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2331system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2332system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2333system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2334system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2335system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2336system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2337system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2338system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
2339system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency
2340system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency
2341system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
2342system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
2343system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency
2344system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency
2345system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2346system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency
2347system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency
2348system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
2349system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency
2350system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency
2351system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked
2352system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2353system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked
2354system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2355system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked
2356system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2357system.iocache.fast_writes 0 # number of fast writes performed
2358system.iocache.cache_copies 0 # number of cache copies performed
2359system.iocache.writebacks::writebacks 106694 # number of writebacks
2360system.iocache.writebacks::total 106694 # number of writebacks
2361system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2362system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses
2363system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses
2364system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2365system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2366system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
2367system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
2368system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2369system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses
2370system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses
2371system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2372system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses
2373system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses
2374system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
2375system.iocache.ReadReq_mshr_miss_latency::realview.ide 1156744203 # number of ReadReq MSHR miss cycles
2376system.iocache.ReadReq_mshr_miss_latency::total 1160014703 # number of ReadReq MSHR miss cycles
2377system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
2378system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
2379system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14321981281 # number of WriteInvalidateReq MSHR miss cycles
2380system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14321981281 # number of WriteInvalidateReq MSHR miss cycles
2381system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
2382system.iocache.demand_mshr_miss_latency::realview.ide 1156744203 # number of demand (read+write) MSHR miss cycles
2383system.iocache.demand_mshr_miss_latency::total 1160227703 # number of demand (read+write) MSHR miss cycles
2384system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
2385system.iocache.overall_mshr_miss_latency::realview.ide 1156744203 # number of overall MSHR miss cycles
2386system.iocache.overall_mshr_miss_latency::total 1160227703 # number of overall MSHR miss cycles
2387system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2388system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2389system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2390system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2391system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2392system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2393system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2394system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2395system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2396system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2397system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2398system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2399system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2400system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
2401system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency
2402system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency
2403system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
2404system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
2405system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency
2406system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency
2407system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2408system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency
2409system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency
2410system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
2411system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency
2412system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency
2413system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2414system.l2c.tags.replacements 1509391 # number of replacements
2415system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use
2416system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks.
2417system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks.
2418system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks.
2419system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit.
2420system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor
2421system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor
2422system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor
2424system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor
2425system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor
2426system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor
2427system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor
2428system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor
2429system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor
2430system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor
2431system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy
2432system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy
2433system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy
2434system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy
2435system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy
2436system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy
2437system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy
2438system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy
2439system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy
2440system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy
2441system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy
2442system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy
2443system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id
2444system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id
2445system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id
2446system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
2447system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id
2448system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id
2449system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id
2450system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id
2451system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
2452system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id
2453system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
2454system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
2455system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id
2456system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id
2457system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id
2458system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id
2459system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id
2460system.l2c.tags.occ_task_id_percent::1024 0.704132 # Percentage of cache occupancy per task id
2461system.l2c.tags.tag_accesses 65830537 # Number of tag accesses
2462system.l2c.tags.data_accesses 65830537 # Number of data accesses
2463system.l2c.ReadReq_hits::cpu0.dtb.walker 7044 # number of ReadReq hits
2464system.l2c.ReadReq_hits::cpu0.itb.walker 4822 # number of ReadReq hits
2465system.l2c.ReadReq_hits::cpu0.inst 775995 # number of ReadReq hits
2466system.l2c.ReadReq_hits::cpu0.data 424099 # number of ReadReq hits
2467system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 575063 # number of ReadReq hits
2468system.l2c.ReadReq_hits::cpu1.dtb.walker 6552 # number of ReadReq hits
2469system.l2c.ReadReq_hits::cpu1.itb.walker 4575 # number of ReadReq hits
2470system.l2c.ReadReq_hits::cpu1.inst 662903 # number of ReadReq hits
2471system.l2c.ReadReq_hits::cpu1.data 363815 # number of ReadReq hits
2472system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 472407 # number of ReadReq hits
2473system.l2c.ReadReq_hits::total 3297275 # number of ReadReq hits
2474system.l2c.Writeback_hits::writebacks 2504876 # number of Writeback hits
2475system.l2c.Writeback_hits::total 2504876 # number of Writeback hits
2476system.l2c.WriteInvalidateReq_hits::cpu0.data 140601 # number of WriteInvalidateReq hits
2477system.l2c.WriteInvalidateReq_hits::cpu1.data 125515 # number of WriteInvalidateReq hits
2478system.l2c.WriteInvalidateReq_hits::total 266116 # number of WriteInvalidateReq hits
2479system.l2c.UpgradeReq_hits::cpu0.data 34998 # number of UpgradeReq hits
2480system.l2c.UpgradeReq_hits::cpu1.data 27403 # number of UpgradeReq hits
2481system.l2c.UpgradeReq_hits::total 62401 # number of UpgradeReq hits
2482system.l2c.SCUpgradeReq_hits::cpu0.data 7236 # number of SCUpgradeReq hits
2483system.l2c.SCUpgradeReq_hits::cpu1.data 5610 # number of SCUpgradeReq hits
2484system.l2c.SCUpgradeReq_hits::total 12846 # number of SCUpgradeReq hits
2485system.l2c.ReadExReq_hits::cpu0.data 55428 # number of ReadExReq hits
2486system.l2c.ReadExReq_hits::cpu1.data 53807 # number of ReadExReq hits
2487system.l2c.ReadExReq_hits::total 109235 # number of ReadExReq hits
2488system.l2c.demand_hits::cpu0.dtb.walker 7044 # number of demand (read+write) hits
2489system.l2c.demand_hits::cpu0.itb.walker 4822 # number of demand (read+write) hits
2490system.l2c.demand_hits::cpu0.inst 775995 # number of demand (read+write) hits
2491system.l2c.demand_hits::cpu0.data 479527 # number of demand (read+write) hits
2492system.l2c.demand_hits::cpu0.l2cache.prefetcher 575063 # number of demand (read+write) hits
2493system.l2c.demand_hits::cpu1.dtb.walker 6552 # number of demand (read+write) hits
2494system.l2c.demand_hits::cpu1.itb.walker 4575 # number of demand (read+write) hits
2495system.l2c.demand_hits::cpu1.inst 662903 # number of demand (read+write) hits
2496system.l2c.demand_hits::cpu1.data 417622 # number of demand (read+write) hits
2497system.l2c.demand_hits::cpu1.l2cache.prefetcher 472407 # number of demand (read+write) hits
2498system.l2c.demand_hits::total 3406510 # number of demand (read+write) hits
2499system.l2c.overall_hits::cpu0.dtb.walker 7044 # number of overall hits
2500system.l2c.overall_hits::cpu0.itb.walker 4822 # number of overall hits
2501system.l2c.overall_hits::cpu0.inst 775995 # number of overall hits
2502system.l2c.overall_hits::cpu0.data 479527 # number of overall hits
2503system.l2c.overall_hits::cpu0.l2cache.prefetcher 575063 # number of overall hits
2504system.l2c.overall_hits::cpu1.dtb.walker 6552 # number of overall hits
2505system.l2c.overall_hits::cpu1.itb.walker 4575 # number of overall hits
2506system.l2c.overall_hits::cpu1.inst 662903 # number of overall hits
2507system.l2c.overall_hits::cpu1.data 417622 # number of overall hits
2508system.l2c.overall_hits::cpu1.l2cache.prefetcher 472407 # number of overall hits
2509system.l2c.overall_hits::total 3406510 # number of overall hits
2510system.l2c.ReadReq_misses::cpu0.dtb.walker 2214 # number of ReadReq misses
2511system.l2c.ReadReq_misses::cpu0.itb.walker 2052 # number of ReadReq misses
2512system.l2c.ReadReq_misses::cpu0.inst 83747 # number of ReadReq misses
2513system.l2c.ReadReq_misses::cpu0.data 137620 # number of ReadReq misses
2514system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 334397 # number of ReadReq misses
2515system.l2c.ReadReq_misses::cpu1.dtb.walker 2082 # number of ReadReq misses
2516system.l2c.ReadReq_misses::cpu1.itb.walker 1771 # number of ReadReq misses
2517system.l2c.ReadReq_misses::cpu1.inst 51652 # number of ReadReq misses
2518system.l2c.ReadReq_misses::cpu1.data 69122 # number of ReadReq misses
2519system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 204701 # number of ReadReq misses
2520system.l2c.ReadReq_misses::total 889358 # number of ReadReq misses
2521system.l2c.WriteInvalidateReq_misses::cpu0.data 476508 # number of WriteInvalidateReq misses
2522system.l2c.WriteInvalidateReq_misses::cpu1.data 89488 # number of WriteInvalidateReq misses
2523system.l2c.WriteInvalidateReq_misses::total 565996 # number of WriteInvalidateReq misses
2524system.l2c.UpgradeReq_misses::cpu0.data 48344 # number of UpgradeReq misses
2525system.l2c.UpgradeReq_misses::cpu1.data 44372 # number of UpgradeReq misses
2526system.l2c.UpgradeReq_misses::total 92716 # number of UpgradeReq misses
2527system.l2c.SCUpgradeReq_misses::cpu0.data 10817 # number of SCUpgradeReq misses
2528system.l2c.SCUpgradeReq_misses::cpu1.data 7620 # number of SCUpgradeReq misses
2529system.l2c.SCUpgradeReq_misses::total 18437 # number of SCUpgradeReq misses
2530system.l2c.ReadExReq_misses::cpu0.data 83374 # number of ReadExReq misses
2531system.l2c.ReadExReq_misses::cpu1.data 50998 # number of ReadExReq misses
2532system.l2c.ReadExReq_misses::total 134372 # number of ReadExReq misses
2533system.l2c.demand_misses::cpu0.dtb.walker 2214 # number of demand (read+write) misses
2534system.l2c.demand_misses::cpu0.itb.walker 2052 # number of demand (read+write) misses
2535system.l2c.demand_misses::cpu0.inst 83747 # number of demand (read+write) misses
2536system.l2c.demand_misses::cpu0.data 220994 # number of demand (read+write) misses
2537system.l2c.demand_misses::cpu0.l2cache.prefetcher 334397 # number of demand (read+write) misses
2538system.l2c.demand_misses::cpu1.dtb.walker 2082 # number of demand (read+write) misses
2539system.l2c.demand_misses::cpu1.itb.walker 1771 # number of demand (read+write) misses
2540system.l2c.demand_misses::cpu1.inst 51652 # number of demand (read+write) misses
2541system.l2c.demand_misses::cpu1.data 120120 # number of demand (read+write) misses
2542system.l2c.demand_misses::cpu1.l2cache.prefetcher 204701 # number of demand (read+write) misses
2543system.l2c.demand_misses::total 1023730 # number of demand (read+write) misses
2544system.l2c.overall_misses::cpu0.dtb.walker 2214 # number of overall misses
2545system.l2c.overall_misses::cpu0.itb.walker 2052 # number of overall misses
2546system.l2c.overall_misses::cpu0.inst 83747 # number of overall misses
2547system.l2c.overall_misses::cpu0.data 220994 # number of overall misses
2548system.l2c.overall_misses::cpu0.l2cache.prefetcher 334397 # number of overall misses
2549system.l2c.overall_misses::cpu1.dtb.walker 2082 # number of overall misses
2550system.l2c.overall_misses::cpu1.itb.walker 1771 # number of overall misses
2551system.l2c.overall_misses::cpu1.inst 51652 # number of overall misses
2552system.l2c.overall_misses::cpu1.data 120120 # number of overall misses
2553system.l2c.overall_misses::cpu1.l2cache.prefetcher 204701 # number of overall misses
2554system.l2c.overall_misses::total 1023730 # number of overall misses
2555system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 196089257 # number of ReadReq miss cycles
2556system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182667757 # number of ReadReq miss cycles
2557system.l2c.ReadReq_miss_latency::cpu0.inst 7080624634 # number of ReadReq miss cycles
2558system.l2c.ReadReq_miss_latency::cpu0.data 12249130737 # number of ReadReq miss cycles
2559system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of ReadReq miss cycles
2560system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 189088032 # number of ReadReq miss cycles
2561system.l2c.ReadReq_miss_latency::cpu1.itb.walker 162443014 # number of ReadReq miss cycles
2562system.l2c.ReadReq_miss_latency::cpu1.inst 4360864205 # number of ReadReq miss cycles
2563system.l2c.ReadReq_miss_latency::cpu1.data 6107312919 # number of ReadReq miss cycles
2564system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of ReadReq miss cycles
2565system.l2c.ReadReq_miss_latency::total 100258792004 # number of ReadReq miss cycles
2566system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50990906 # number of WriteInvalidateReq miss cycles
2567system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 47594001 # number of WriteInvalidateReq miss cycles
2568system.l2c.WriteInvalidateReq_miss_latency::total 98584907 # number of WriteInvalidateReq miss cycles
2569system.l2c.UpgradeReq_miss_latency::cpu0.data 312691152 # number of UpgradeReq miss cycles
2570system.l2c.UpgradeReq_miss_latency::cpu1.data 283930496 # number of UpgradeReq miss cycles
2571system.l2c.UpgradeReq_miss_latency::total 596621648 # number of UpgradeReq miss cycles
2572system.l2c.SCUpgradeReq_miss_latency::cpu0.data 58172655 # number of SCUpgradeReq miss cycles
2573system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50436899 # number of SCUpgradeReq miss cycles
2574system.l2c.SCUpgradeReq_miss_latency::total 108609554 # number of SCUpgradeReq miss cycles
2575system.l2c.ReadExReq_miss_latency::cpu0.data 7528015770 # number of ReadExReq miss cycles
2576system.l2c.ReadExReq_miss_latency::cpu1.data 4219527160 # number of ReadExReq miss cycles
2577system.l2c.ReadExReq_miss_latency::total 11747542930 # number of ReadExReq miss cycles
2578system.l2c.demand_miss_latency::cpu0.dtb.walker 196089257 # number of demand (read+write) miss cycles
2579system.l2c.demand_miss_latency::cpu0.itb.walker 182667757 # number of demand (read+write) miss cycles
2580system.l2c.demand_miss_latency::cpu0.inst 7080624634 # number of demand (read+write) miss cycles
2581system.l2c.demand_miss_latency::cpu0.data 19777146507 # number of demand (read+write) miss cycles
2582system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of demand (read+write) miss cycles
2583system.l2c.demand_miss_latency::cpu1.dtb.walker 189088032 # number of demand (read+write) miss cycles
2584system.l2c.demand_miss_latency::cpu1.itb.walker 162443014 # number of demand (read+write) miss cycles
2585system.l2c.demand_miss_latency::cpu1.inst 4360864205 # number of demand (read+write) miss cycles
2586system.l2c.demand_miss_latency::cpu1.data 10326840079 # number of demand (read+write) miss cycles
2587system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of demand (read+write) miss cycles
2588system.l2c.demand_miss_latency::total 112006334934 # number of demand (read+write) miss cycles
2589system.l2c.overall_miss_latency::cpu0.dtb.walker 196089257 # number of overall miss cycles
2590system.l2c.overall_miss_latency::cpu0.itb.walker 182667757 # number of overall miss cycles
2591system.l2c.overall_miss_latency::cpu0.inst 7080624634 # number of overall miss cycles
2592system.l2c.overall_miss_latency::cpu0.data 19777146507 # number of overall miss cycles
2593system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of overall miss cycles
2594system.l2c.overall_miss_latency::cpu1.dtb.walker 189088032 # number of overall miss cycles
2595system.l2c.overall_miss_latency::cpu1.itb.walker 162443014 # number of overall miss cycles
2596system.l2c.overall_miss_latency::cpu1.inst 4360864205 # number of overall miss cycles
2597system.l2c.overall_miss_latency::cpu1.data 10326840079 # number of overall miss cycles
2598system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of overall miss cycles
2599system.l2c.overall_miss_latency::total 112006334934 # number of overall miss cycles
2600system.l2c.ReadReq_accesses::cpu0.dtb.walker 9258 # number of ReadReq accesses(hits+misses)
2601system.l2c.ReadReq_accesses::cpu0.itb.walker 6874 # number of ReadReq accesses(hits+misses)
2602system.l2c.ReadReq_accesses::cpu0.inst 859742 # number of ReadReq accesses(hits+misses)
2603system.l2c.ReadReq_accesses::cpu0.data 561719 # number of ReadReq accesses(hits+misses)
2604system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 909460 # number of ReadReq accesses(hits+misses)
2605system.l2c.ReadReq_accesses::cpu1.dtb.walker 8634 # number of ReadReq accesses(hits+misses)
2606system.l2c.ReadReq_accesses::cpu1.itb.walker 6346 # number of ReadReq accesses(hits+misses)
2607system.l2c.ReadReq_accesses::cpu1.inst 714555 # number of ReadReq accesses(hits+misses)
2608system.l2c.ReadReq_accesses::cpu1.data 432937 # number of ReadReq accesses(hits+misses)
2609system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 677108 # number of ReadReq accesses(hits+misses)
2610system.l2c.ReadReq_accesses::total 4186633 # number of ReadReq accesses(hits+misses)
2611system.l2c.Writeback_accesses::writebacks 2504876 # number of Writeback accesses(hits+misses)
2612system.l2c.Writeback_accesses::total 2504876 # number of Writeback accesses(hits+misses)
2613system.l2c.WriteInvalidateReq_accesses::cpu0.data 617109 # number of WriteInvalidateReq accesses(hits+misses)
2614system.l2c.WriteInvalidateReq_accesses::cpu1.data 215003 # number of WriteInvalidateReq accesses(hits+misses)
2615system.l2c.WriteInvalidateReq_accesses::total 832112 # number of WriteInvalidateReq accesses(hits+misses)
2616system.l2c.UpgradeReq_accesses::cpu0.data 83342 # number of UpgradeReq accesses(hits+misses)
2617system.l2c.UpgradeReq_accesses::cpu1.data 71775 # number of UpgradeReq accesses(hits+misses)
2618system.l2c.UpgradeReq_accesses::total 155117 # number of UpgradeReq accesses(hits+misses)
2619system.l2c.SCUpgradeReq_accesses::cpu0.data 18053 # number of SCUpgradeReq accesses(hits+misses)
2620system.l2c.SCUpgradeReq_accesses::cpu1.data 13230 # number of SCUpgradeReq accesses(hits+misses)
2621system.l2c.SCUpgradeReq_accesses::total 31283 # number of SCUpgradeReq accesses(hits+misses)
2622system.l2c.ReadExReq_accesses::cpu0.data 138802 # number of ReadExReq accesses(hits+misses)
2623system.l2c.ReadExReq_accesses::cpu1.data 104805 # number of ReadExReq accesses(hits+misses)
2624system.l2c.ReadExReq_accesses::total 243607 # number of ReadExReq accesses(hits+misses)
2625system.l2c.demand_accesses::cpu0.dtb.walker 9258 # number of demand (read+write) accesses
2626system.l2c.demand_accesses::cpu0.itb.walker 6874 # number of demand (read+write) accesses
2627system.l2c.demand_accesses::cpu0.inst 859742 # number of demand (read+write) accesses
2628system.l2c.demand_accesses::cpu0.data 700521 # number of demand (read+write) accesses
2629system.l2c.demand_accesses::cpu0.l2cache.prefetcher 909460 # number of demand (read+write) accesses
2630system.l2c.demand_accesses::cpu1.dtb.walker 8634 # number of demand (read+write) accesses
2631system.l2c.demand_accesses::cpu1.itb.walker 6346 # number of demand (read+write) accesses
2632system.l2c.demand_accesses::cpu1.inst 714555 # number of demand (read+write) accesses
2633system.l2c.demand_accesses::cpu1.data 537742 # number of demand (read+write) accesses
2634system.l2c.demand_accesses::cpu1.l2cache.prefetcher 677108 # number of demand (read+write) accesses
2635system.l2c.demand_accesses::total 4430240 # number of demand (read+write) accesses
2636system.l2c.overall_accesses::cpu0.dtb.walker 9258 # number of overall (read+write) accesses
2637system.l2c.overall_accesses::cpu0.itb.walker 6874 # number of overall (read+write) accesses
2638system.l2c.overall_accesses::cpu0.inst 859742 # number of overall (read+write) accesses
2639system.l2c.overall_accesses::cpu0.data 700521 # number of overall (read+write) accesses
2640system.l2c.overall_accesses::cpu0.l2cache.prefetcher 909460 # number of overall (read+write) accesses
2641system.l2c.overall_accesses::cpu1.dtb.walker 8634 # number of overall (read+write) accesses
2642system.l2c.overall_accesses::cpu1.itb.walker 6346 # number of overall (read+write) accesses
2643system.l2c.overall_accesses::cpu1.inst 714555 # number of overall (read+write) accesses
2644system.l2c.overall_accesses::cpu1.data 537742 # number of overall (read+write) accesses
2645system.l2c.overall_accesses::cpu1.l2cache.prefetcher 677108 # number of overall (read+write) accesses
2646system.l2c.overall_accesses::total 4430240 # number of overall (read+write) accesses
2647system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for ReadReq accesses
2648system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.298516 # miss rate for ReadReq accesses
2649system.l2c.ReadReq_miss_rate::cpu0.inst 0.097409 # miss rate for ReadReq accesses
2650system.l2c.ReadReq_miss_rate::cpu0.data 0.244998 # miss rate for ReadReq accesses
2651system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for ReadReq accesses
2652system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for ReadReq accesses
2653system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.279073 # miss rate for ReadReq accesses
2654system.l2c.ReadReq_miss_rate::cpu1.inst 0.072286 # miss rate for ReadReq accesses
2655system.l2c.ReadReq_miss_rate::cpu1.data 0.159658 # miss rate for ReadReq accesses
2656system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for ReadReq accesses
2657system.l2c.ReadReq_miss_rate::total 0.212428 # miss rate for ReadReq accesses
2658system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.772162 # miss rate for WriteInvalidateReq accesses
2659system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.416217 # miss rate for WriteInvalidateReq accesses
2660system.l2c.WriteInvalidateReq_miss_rate::total 0.680192 # miss rate for WriteInvalidateReq accesses
2661system.l2c.UpgradeReq_miss_rate::cpu0.data 0.580068 # miss rate for UpgradeReq accesses
2662system.l2c.UpgradeReq_miss_rate::cpu1.data 0.618210 # miss rate for UpgradeReq accesses
2663system.l2c.UpgradeReq_miss_rate::total 0.597717 # miss rate for UpgradeReq accesses
2664system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599180 # miss rate for SCUpgradeReq accesses
2665system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.575964 # miss rate for SCUpgradeReq accesses
2666system.l2c.SCUpgradeReq_miss_rate::total 0.589362 # miss rate for SCUpgradeReq accesses
2667system.l2c.ReadExReq_miss_rate::cpu0.data 0.600669 # miss rate for ReadExReq accesses
2668system.l2c.ReadExReq_miss_rate::cpu1.data 0.486599 # miss rate for ReadExReq accesses
2669system.l2c.ReadExReq_miss_rate::total 0.551593 # miss rate for ReadExReq accesses
2670system.l2c.demand_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for demand accesses
2671system.l2c.demand_miss_rate::cpu0.itb.walker 0.298516 # miss rate for demand accesses
2672system.l2c.demand_miss_rate::cpu0.inst 0.097409 # miss rate for demand accesses
2673system.l2c.demand_miss_rate::cpu0.data 0.315471 # miss rate for demand accesses
2674system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for demand accesses
2675system.l2c.demand_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for demand accesses
2676system.l2c.demand_miss_rate::cpu1.itb.walker 0.279073 # miss rate for demand accesses
2677system.l2c.demand_miss_rate::cpu1.inst 0.072286 # miss rate for demand accesses
2678system.l2c.demand_miss_rate::cpu1.data 0.223378 # miss rate for demand accesses
2679system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for demand accesses
2680system.l2c.demand_miss_rate::total 0.231078 # miss rate for demand accesses
2681system.l2c.overall_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for overall accesses
2682system.l2c.overall_miss_rate::cpu0.itb.walker 0.298516 # miss rate for overall accesses
2683system.l2c.overall_miss_rate::cpu0.inst 0.097409 # miss rate for overall accesses
2684system.l2c.overall_miss_rate::cpu0.data 0.315471 # miss rate for overall accesses
2685system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for overall accesses
2686system.l2c.overall_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for overall accesses
2687system.l2c.overall_miss_rate::cpu1.itb.walker 0.279073 # miss rate for overall accesses
2688system.l2c.overall_miss_rate::cpu1.inst 0.072286 # miss rate for overall accesses
2689system.l2c.overall_miss_rate::cpu1.data 0.223378 # miss rate for overall accesses
2690system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for overall accesses
2691system.l2c.overall_miss_rate::total 0.231078 # miss rate for overall accesses
2692system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average ReadReq miss latency
2693system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89019.374756 # average ReadReq miss latency
2694system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84547.800327 # average ReadReq miss latency
2695system.l2c.ReadReq_avg_miss_latency::cpu0.data 89006.908422 # average ReadReq miss latency
2696system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average ReadReq miss latency
2697system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average ReadReq miss latency
2698system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 91723.892716 # average ReadReq miss latency
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2704system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 531.847857 # average WriteInvalidateReq miss latency
2705system.l2c.WriteInvalidateReq_avg_miss_latency::total 174.179512 # average WriteInvalidateReq miss latency
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2707system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.866312 # average UpgradeReq miss latency
2708system.l2c.UpgradeReq_avg_miss_latency::total 6434.937314 # average UpgradeReq miss latency
2709system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5377.891744 # average SCUpgradeReq miss latency
2710system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6619.015617 # average SCUpgradeReq miss latency
2711system.l2c.SCUpgradeReq_avg_miss_latency::total 5890.847426 # average SCUpgradeReq miss latency
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2713system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82739.071336 # average ReadExReq miss latency
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2720system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency
2721system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency
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2726system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average overall miss latency
2727system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89019.374756 # average overall miss latency
2728system.l2c.overall_avg_miss_latency::cpu0.inst 84547.800327 # average overall miss latency
2729system.l2c.overall_avg_miss_latency::cpu0.data 89491.780352 # average overall miss latency
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2731system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency
2732system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency
2733system.l2c.overall_avg_miss_latency::cpu1.inst 84427.789921 # average overall miss latency
2734system.l2c.overall_avg_miss_latency::cpu1.data 85971.029629 # average overall miss latency
2735system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average overall miss latency
2736system.l2c.overall_avg_miss_latency::total 109410.034808 # average overall miss latency
2737system.l2c.blocked_cycles::no_mshrs 12831 # number of cycles access was blocked
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2739system.l2c.blocked::no_mshrs 343 # number of cycles access was blocked
2740system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2741system.l2c.avg_blocked_cycles::no_mshrs 37.408163 # average number of cycles each access was blocked
2742system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2743system.l2c.fast_writes 0 # number of fast writes performed
2744system.l2c.cache_copies 0 # number of cache copies performed
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2746system.l2c.writebacks::total 1128341 # number of writebacks
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2856system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4878632500 # number of ReadReq MSHR uncacheable cycles
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2858system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 506298251 # number of ReadReq MSHR uncacheable cycles
2859system.l2c.ReadReq_mshr_uncacheable_latency::total 8578645501 # number of ReadReq MSHR uncacheable cycles
2860system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4641261500 # number of WriteReq MSHR uncacheable cycles
2861system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 642209001 # number of WriteReq MSHR uncacheable cycles
2862system.l2c.WriteReq_mshr_uncacheable_latency::total 5283470501 # number of WriteReq MSHR uncacheable cycles
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2866system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1148507252 # number of overall MSHR uncacheable cycles
2867system.l2c.overall_mshr_uncacheable_latency::total 13862116002 # number of overall MSHR uncacheable cycles
2868system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for ReadReq accesses
2869system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for ReadReq accesses
2870system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for ReadReq accesses
2871system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.244973 # mshr miss rate for ReadReq accesses
2872system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for ReadReq accesses
2873system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for ReadReq accesses
2874system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for ReadReq accesses
2875system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for ReadReq accesses
2876system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.159598 # mshr miss rate for ReadReq accesses
2877system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for ReadReq accesses
2878system.l2c.ReadReq_mshr_miss_rate::total 0.212332 # mshr miss rate for ReadReq accesses
2879system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.772162 # mshr miss rate for WriteInvalidateReq accesses
2880system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.416217 # mshr miss rate for WriteInvalidateReq accesses
2881system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.680192 # mshr miss rate for WriteInvalidateReq accesses
2882system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.580068 # mshr miss rate for UpgradeReq accesses
2883system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.618210 # mshr miss rate for UpgradeReq accesses
2884system.l2c.UpgradeReq_mshr_miss_rate::total 0.597717 # mshr miss rate for UpgradeReq accesses
2885system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599180 # mshr miss rate for SCUpgradeReq accesses
2886system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.575964 # mshr miss rate for SCUpgradeReq accesses
2887system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.589362 # mshr miss rate for SCUpgradeReq accesses
2888system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.600669 # mshr miss rate for ReadExReq accesses
2889system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486599 # mshr miss rate for ReadExReq accesses
2890system.l2c.ReadExReq_mshr_miss_rate::total 0.551593 # mshr miss rate for ReadExReq accesses
2891system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for demand accesses
2892system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for demand accesses
2893system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for demand accesses
2894system.l2c.demand_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for demand accesses
2895system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for demand accesses
2896system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for demand accesses
2897system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for demand accesses
2898system.l2c.demand_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for demand accesses
2899system.l2c.demand_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for demand accesses
2900system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for demand accesses
2901system.l2c.demand_mshr_miss_rate::total 0.230987 # mshr miss rate for demand accesses
2902system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for overall accesses
2903system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for overall accesses
2904system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for overall accesses
2905system.l2c.overall_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for overall accesses
2906system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for overall accesses
2907system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for overall accesses
2908system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for overall accesses
2909system.l2c.overall_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for overall accesses
2910system.l2c.overall_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for overall accesses
2911system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for overall accesses
2912system.l2c.overall_mshr_miss_rate::total 0.230987 # mshr miss rate for overall accesses
2913system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average ReadReq mshr miss latency
2914system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average ReadReq mshr miss latency
2915system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average ReadReq mshr miss latency
2916system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76466.442328 # average ReadReq mshr miss latency
2917system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average ReadReq mshr miss latency
2918system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average ReadReq mshr miss latency
2919system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average ReadReq mshr miss latency
2920system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average ReadReq mshr miss latency
2921system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75811.991013 # average ReadReq mshr miss latency
2922system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average ReadReq mshr miss latency
2923system.l2c.ReadReq_avg_mshr_miss_latency::total 100350.980614 # average ReadReq mshr miss latency
2924system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33488.206062 # average WriteInvalidateReq mshr miss latency
2925system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31928.465258 # average WriteInvalidateReq mshr miss latency
2926system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33241.599928 # average WriteInvalidateReq mshr miss latency
2927system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17801.475985 # average UpgradeReq mshr miss latency
2928system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.410326 # average UpgradeReq mshr miss latency
2929system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.437228 # average UpgradeReq mshr miss latency
2930system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17783.190071 # average SCUpgradeReq mshr miss latency
2931system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17807.754199 # average SCUpgradeReq mshr miss latency
2932system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17793.342409 # average SCUpgradeReq mshr miss latency
2933system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77798.752969 # average ReadExReq mshr miss latency
2934system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70220.005490 # average ReadExReq mshr miss latency
2935system.l2c.ReadExReq_avg_mshr_miss_latency::total 74922.402509 # average ReadExReq mshr miss latency
2936system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency
2937system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency
2938system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency
2939system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency
2940system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency
2941system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency
2942system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency
2943system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency
2944system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency
2945system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency
2946system.l2c.demand_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency
2947system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency
2948system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency
2949system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency
2950system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency
2951system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency
2952system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency
2953system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency
2954system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency
2955system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency
2956system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency
2957system.l2c.overall_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency
2958system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
2959system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
2960system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2961system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2962system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2963system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
2964system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2965system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2966system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
2967system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
2968system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2969system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2970system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2971system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2972system.membus.trans_dist::ReadReq 988965 # Transaction distribution
2973system.membus.trans_dist::ReadResp 988965 # Transaction distribution
2974system.membus.trans_dist::WriteReq 38599 # Transaction distribution
2975system.membus.trans_dist::WriteResp 38599 # Transaction distribution
2976system.membus.trans_dist::Writeback 1235035 # Transaction distribution
2977system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution
2978system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution
2979system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution
2980system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution
2981system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution
2982system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution
2983system.membus.trans_dist::ReadExReq 147271 # Transaction distribution
2984system.membus.trans_dist::ReadExResp 130046 # Transaction distribution
2985system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes)
2986system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
2987system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes)
2988system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes)
2989system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes)
2990system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes)
2991system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes)
2992system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes)
2993system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes)
2994system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
2995system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes)
2996system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes)
2997system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes)
2998system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes)
2999system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes)
3000system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes)
3001system.membus.snoops 645066 # Total snoops (count)
3002system.membus.snoop_fanout::samples 3693594 # Request fanout histogram
3003system.membus.snoop_fanout::mean 1 # Request fanout histogram
3004system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3005system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3006system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3007system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram
3008system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3009system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3010system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3011system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3012system.membus.snoop_fanout::total 3693594 # Request fanout histogram
3013system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks)
3014system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3015system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
3016system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3017system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks)
3018system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3019system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks)
3020system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3021system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks)
3022system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3023system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks)
3024system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3025system.realview.ethernet.txBytes 966 # Bytes Transmitted
3026system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3027system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3028system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3029system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3030system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3031system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3059system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3060system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3061system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3062system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3063system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3064system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3065system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3066system.realview.ethernet.droppedPackets 0 # number of packets dropped
3067system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution
3068system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution
3069system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution
3070system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution
3071system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution
3072system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution
3073system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution
3074system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution
3075system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution
3076system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution
3077system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution
3078system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution
3079system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution
3080system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution
3081system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes)
3082system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes)
3083system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes)
3084system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes)
3085system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes)
3086system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes)
3087system.toL2Bus.snoops 1680481 # Total snoops (count)
3088system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram
3089system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram
3090system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram
3091system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3092system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3093system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram
3094system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram
3095system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3096system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3097system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3098system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram
3099system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks)
3100system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3101system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks)
3102system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3103system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks)
3104system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3105system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks)
3106system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3107
3108---------- End Simulation Statistics ----------