1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.349389 # Number of seconds simulated
4sim_ticks 47349388766500 # Number of ticks simulated
5final_tick 47349388766500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 148460 # Simulator instruction rate (inst/s)
8host_op_rate 174619 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 7799944718 # Simulator tick rate (ticks/s)
10host_mem_usage 883812 # Number of bytes of host memory used
11host_seconds 6070.48 # Real time elapsed on the host
12sim_insts 901223526 # Number of instructions simulated
13sim_ops 1060022042 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 126592 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 108352 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 12219800 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.l2cache.prefetcher 55224576 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.dtb.walker 171840 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.itb.walker 160768 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 11630176 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.l2cache.prefetcher 36221056 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 451968 # Number of bytes read from this memory
25system.physmem.bytes_read::total 116315128 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 4075008 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 659840 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 4734848 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 84862912 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.inst 20812 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.inst 4 # Number of bytes written to this memory
32system.physmem.bytes_written::total 84883728 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 1978 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 1693 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 190956 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.l2cache.prefetcher 862884 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.dtb.walker 2685 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.itb.walker 2512 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.inst 181736 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.l2cache.prefetcher 565954 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 7062 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 1817460 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 1325983 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.inst 2602 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.inst 1 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 1328586 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 2674 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 2288 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 258077 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.l2cache.prefetcher 1166321 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.dtb.walker 3629 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.itb.walker 3395 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.inst 245625 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.l2cache.prefetcher 764974 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 9545 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 2456529 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 86063 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 13936 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 99998 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 1792270 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.inst 440 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.inst 0 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 1792710 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 1792270 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 2674 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 2288 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 258517 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.l2cache.prefetcher 1166321 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu1.dtb.walker 3629 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.itb.walker 3395 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.inst 245625 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.l2cache.prefetcher 764974 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 9545 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 4249239 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.readReqs 1817460 # Number of read requests accepted
76system.physmem.writeReqs 1459105 # Number of write requests accepted
77system.physmem.readBursts 1817460 # Number of DRAM read bursts, including those serviced by the write queue
78system.physmem.writeBursts 1459105 # Number of DRAM write bursts, including those merged in the write queue
79system.physmem.bytesReadDRAM 116259968 # Total number of bytes read from DRAM
80system.physmem.bytesReadWrQ 57472 # Total number of bytes read from write queue
81system.physmem.bytesWritten 92884608 # Total number of bytes written to DRAM
82system.physmem.bytesReadSys 116315128 # Total read bytes from the system interface side
83system.physmem.bytesWrittenSys 93236944 # Total written bytes from the system interface side
84system.physmem.servicedByWrQ 898 # Number of DRAM read bursts serviced by the write queue
85system.physmem.mergedWrBursts 7766 # Number of DRAM write bursts merged with an existing one
86system.physmem.neitherReadNorWriteReqs 92270 # Number of requests that are neither read nor write
87system.physmem.perBankRdBursts::0 109521 # Per bank write bursts
88system.physmem.perBankRdBursts::1 125500 # Per bank write bursts
89system.physmem.perBankRdBursts::2 109858 # Per bank write bursts
90system.physmem.perBankRdBursts::3 118807 # Per bank write bursts
91system.physmem.perBankRdBursts::4 114750 # Per bank write bursts
92system.physmem.perBankRdBursts::5 133958 # Per bank write bursts
93system.physmem.perBankRdBursts::6 108183 # Per bank write bursts
94system.physmem.perBankRdBursts::7 109296 # Per bank write bursts
95system.physmem.perBankRdBursts::8 104951 # Per bank write bursts
96system.physmem.perBankRdBursts::9 157608 # Per bank write bursts
97system.physmem.perBankRdBursts::10 96466 # Per bank write bursts
98system.physmem.perBankRdBursts::11 111139 # Per bank write bursts
99system.physmem.perBankRdBursts::12 103753 # Per bank write bursts
100system.physmem.perBankRdBursts::13 116262 # Per bank write bursts
101system.physmem.perBankRdBursts::14 95073 # Per bank write bursts
102system.physmem.perBankRdBursts::15 101437 # Per bank write bursts
103system.physmem.perBankWrBursts::0 88391 # Per bank write bursts
104system.physmem.perBankWrBursts::1 94888 # Per bank write bursts
105system.physmem.perBankWrBursts::2 89089 # Per bank write bursts
106system.physmem.perBankWrBursts::3 94540 # Per bank write bursts
107system.physmem.perBankWrBursts::4 92096 # Per bank write bursts
108system.physmem.perBankWrBursts::5 104028 # Per bank write bursts
109system.physmem.perBankWrBursts::6 87215 # Per bank write bursts
110system.physmem.perBankWrBursts::7 89925 # Per bank write bursts
111system.physmem.perBankWrBursts::8 85891 # Per bank write bursts
112system.physmem.perBankWrBursts::9 90043 # Per bank write bursts
113system.physmem.perBankWrBursts::10 85085 # Per bank write bursts
114system.physmem.perBankWrBursts::11 94536 # Per bank write bursts
115system.physmem.perBankWrBursts::12 86659 # Per bank write bursts
116system.physmem.perBankWrBursts::13 94890 # Per bank write bursts
117system.physmem.perBankWrBursts::14 85144 # Per bank write bursts
118system.physmem.perBankWrBursts::15 88902 # Per bank write bursts
119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
121system.physmem.totGap 47349386828500 # Total gap between requests
122system.physmem.readPktSize::0 0 # Read request sizes (log2)
123system.physmem.readPktSize::1 0 # Read request sizes (log2)
124system.physmem.readPktSize::2 0 # Read request sizes (log2)
125system.physmem.readPktSize::3 37 # Read request sizes (log2)
126system.physmem.readPktSize::4 5 # Read request sizes (log2)
127system.physmem.readPktSize::5 0 # Read request sizes (log2)
128system.physmem.readPktSize::6 1817418 # Read request sizes (log2)
129system.physmem.writePktSize::0 0 # Write request sizes (log2)
130system.physmem.writePktSize::1 0 # Write request sizes (log2)
131system.physmem.writePktSize::2 2 # Write request sizes (log2)
132system.physmem.writePktSize::3 2601 # Write request sizes (log2)
133system.physmem.writePktSize::4 0 # Write request sizes (log2)
134system.physmem.writePktSize::5 0 # Write request sizes (log2)
135system.physmem.writePktSize::6 1456502 # Write request sizes (log2)
136system.physmem.rdQLenPdf::0 724796 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::1 275224 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::2 218778 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::3 130576 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::4 121480 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::5 92297 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::6 78276 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::7 67824 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::8 54542 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::9 29215 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::10 6539 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::11 4680 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::12 3658 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::13 2988 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::14 2241 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::15 1701 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::16 695 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::17 500 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::18 325 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::19 212 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see

--- 7 unchanged lines hidden (view full) ---

175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 20715 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::16 26374 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 37146 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::18 48711 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 55470 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 62560 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 67793 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 75025 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::23 82665 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 93812 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 97796 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 101866 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::27 103500 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 107192 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 100425 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 103030 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 105997 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 102597 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::33 17377 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::34 13177 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::35 9215 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::36 5577 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::37 2562 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::38 1460 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::39 1101 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::40 881 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::41 790 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::42 689 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::43 632 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::44 612 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::45 557 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::46 530 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::47 487 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::48 467 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::49 457 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::50 413 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::51 360 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::52 293 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::53 254 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::54 234 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::56 108 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::57 69 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see
232system.physmem.bytesPerActivate::samples 894898 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::mean 233.707153 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::gmean 136.846498 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::stdev 284.283402 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::0-127 463489 51.79% 51.79% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::128-255 185877 20.77% 72.56% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::256-383 67737 7.57% 80.13% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::384-511 36988 4.13% 84.27% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::512-639 29329 3.28% 87.54% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::640-767 22133 2.47% 90.02% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::768-895 15835 1.77% 91.79% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::896-1023 13649 1.53% 93.31% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::1024-1151 59861 6.69% 100.00% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::total 894898 # Bytes accessed per row activation
246system.physmem.rdPerTurnAround::samples 77790 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::mean 23.351999 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::stdev 144.403085 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::0-1023 77788 100.00% 100.00% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::total 77790 # Reads before turning the bus around for writes
253system.physmem.wrPerTurnAround::samples 77790 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::mean 18.656922 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::gmean 17.550932 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::stdev 11.537959 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::16-23 73893 94.99% 94.99% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::24-31 1079 1.39% 96.38% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::32-39 616 0.79% 97.17% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::40-47 255 0.33% 97.50% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::48-55 611 0.79% 98.28% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::56-63 159 0.20% 98.49% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::64-71 204 0.26% 98.75% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::72-79 127 0.16% 98.91% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::80-87 198 0.25% 99.17% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::88-95 57 0.07% 99.24% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::96-103 225 0.29% 99.53% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::104-111 47 0.06% 99.59% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::112-119 57 0.07% 99.66% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::120-127 49 0.06% 99.73% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::128-135 102 0.13% 99.86% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::136-143 22 0.03% 99.89% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::144-151 26 0.03% 99.92% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::152-159 10 0.01% 99.93% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::160-167 13 0.02% 99.95% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::168-175 6 0.01% 99.96% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::176-183 9 0.01% 99.97% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::184-191 5 0.01% 99.97% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::192-199 3 0.00% 99.98% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::200-207 2 0.00% 99.98% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::208-215 2 0.00% 99.98% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::216-223 2 0.00% 99.99% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::224-231 5 0.01% 99.99% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::248-255 4 0.01% 100.00% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::total 77790 # Writes before turning the bus around for reads
288system.physmem.totQLat 101322311265 # Total ticks spent queuing
289system.physmem.totMemAccLat 135382848765 # Total ticks spent from burst creation until serviced by the DRAM
290system.physmem.totBusLat 9082810000 # Total ticks spent in databus transfers
291system.physmem.avgQLat 55776.96 # Average queueing delay per DRAM burst
292system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
293system.physmem.avgMemAccLat 74526.96 # Average memory access latency per DRAM burst
294system.physmem.avgRdBW 2.46 # Average DRAM read bandwidth in MiByte/s
295system.physmem.avgWrBW 1.96 # Average achieved write bandwidth in MiByte/s
296system.physmem.avgRdBWSys 2.46 # Average system read bandwidth in MiByte/s
297system.physmem.avgWrBWSys 1.97 # Average system write bandwidth in MiByte/s
298system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
299system.physmem.busUtil 0.03 # Data bus utilization in percentage
300system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
301system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
302system.physmem.avgRdQLen 1.40 # Average read queue length when enqueuing
303system.physmem.avgWrQLen 27.53 # Average write queue length when enqueuing
304system.physmem.readRowHits 1479200 # Number of row buffer hits during reads
305system.physmem.writeRowHits 893785 # Number of row buffer hits during writes
306system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads
307system.physmem.writeRowHitRate 61.58 # Row buffer hit rate for writes
308system.physmem.avgGap 14450922.48 # Average gap between requests
309system.physmem.pageHitRate 72.61 # Row buffer hit rate, read and write combined
310system.physmem.memoryStateTime::IDLE 45452153624500 # Time in different power states
311system.physmem.memoryStateTime::REF 1581100040000 # Time in different power states
312system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
313system.physmem.memoryStateTime::ACT 316134376000 # Time in different power states
314system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
315system.physmem.actEnergy::0 3577346640 # Energy for activate commands per rank (pJ)
316system.physmem.actEnergy::1 3188082240 # Energy for activate commands per rank (pJ)
317system.physmem.preEnergy::0 1951925250 # Energy for precharge commands per rank (pJ)
318system.physmem.preEnergy::1 1739529000 # Energy for precharge commands per rank (pJ)
319system.physmem.readEnergy::0 7253009400 # Energy for read commands per rank (pJ)
320system.physmem.readEnergy::1 6916111800 # Energy for read commands per rank (pJ)
321system.physmem.writeEnergy::0 4796314560 # Energy for write commands per rank (pJ)
322system.physmem.writeEnergy::1 4608252000 # Energy for write commands per rank (pJ)
323system.physmem.refreshEnergy::0 3092631678240 # Energy for refresh commands per rank (pJ)
324system.physmem.refreshEnergy::1 3092631678240 # Energy for refresh commands per rank (pJ)
325system.physmem.actBackEnergy::0 1196963299980 # Energy for active background per rank (pJ)
326system.physmem.actBackEnergy::1 1185023558430 # Energy for active background per rank (pJ)
327system.physmem.preBackEnergy::0 27359663548500 # Energy for precharge background per rank (pJ)
328system.physmem.preBackEnergy::1 27370137006000 # Energy for precharge background per rank (pJ)
329system.physmem.totalEnergy::0 31666837122570 # Total energy per rank (pJ)
330system.physmem.totalEnergy::1 31664244217710 # Total energy per rank (pJ)
331system.physmem.averagePower::0 668.790877 # Core power per rank (mW)
332system.physmem.averagePower::1 668.736116 # Core power per rank (mW)
333system.realview.nvmem.bytes_read::cpu0.inst 740 # Number of bytes read from this memory
334system.realview.nvmem.bytes_read::cpu1.inst 584 # Number of bytes read from this memory
335system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory
336system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory
337system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory
338system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory
339system.realview.nvmem.num_reads::cpu0.inst 16 # Number of read requests responded to by this memory
340system.realview.nvmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
341system.realview.nvmem.num_reads::total 26 # Number of read requests responded to by this memory
342system.realview.nvmem.bw_read::cpu0.inst 16 # Total read bandwidth from this memory (bytes/s)
343system.realview.nvmem.bw_read::cpu1.inst 12 # Total read bandwidth from this memory (bytes/s)
344system.realview.nvmem.bw_read::total 28 # Total read bandwidth from this memory (bytes/s)
345system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s)
346system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s)
347system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s)
348system.realview.nvmem.bw_total::cpu0.inst 16 # Total bandwidth to/from this memory (bytes/s)
349system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s)
350system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s)
351system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
352system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
353system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
354system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
355system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
356system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
357system.cpu0.branchPred.lookups 127854962 # Number of BP lookups
358system.cpu0.branchPred.condPredicted 91169153 # Number of conditional branches predicted
359system.cpu0.branchPred.condIncorrect 5795491 # Number of conditional branches incorrect
360system.cpu0.branchPred.BTBLookups 97464931 # Number of BTB lookups
361system.cpu0.branchPred.BTBHits 70565780 # Number of BTB hits
362system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
363system.cpu0.branchPred.BTBHitPct 72.401200 # BTB Hit Percentage
364system.cpu0.branchPred.usedRAS 14662444 # Number of times the RAS was used to get a target.
365system.cpu0.branchPred.RASInCorrect 979053 # Number of incorrect RAS predictions.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
368system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
369system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
370system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
371system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
372system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
373system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
374system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

382system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
383system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
384system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
385system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
386system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
387system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
388system.cpu0.dtb.inst_hits 0 # ITB inst hits
389system.cpu0.dtb.inst_misses 0 # ITB inst misses
390system.cpu0.dtb.read_hits 80634882 # DTB read hits
391system.cpu0.dtb.read_misses 217470 # DTB read misses
392system.cpu0.dtb.write_hits 71942682 # DTB write hits
393system.cpu0.dtb.write_misses 47848 # DTB write misses
394system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
395system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
396system.cpu0.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
397system.cpu0.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
398system.cpu0.dtb.flush_entries 34852 # Number of entries that have been flushed from TLB
399system.cpu0.dtb.align_faults 1874 # Number of TLB faults due to alignment restrictions
400system.cpu0.dtb.prefetch_faults 8493 # Number of TLB faults due to prefetch
401system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
402system.cpu0.dtb.perms_faults 11561 # Number of TLB faults due to permissions restrictions
403system.cpu0.dtb.read_accesses 80852352 # DTB read accesses
404system.cpu0.dtb.write_accesses 71990530 # DTB write accesses
405system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
406system.cpu0.dtb.hits 152577564 # DTB hits
407system.cpu0.dtb.misses 265318 # DTB misses
408system.cpu0.dtb.accesses 152842882 # DTB accesses
409system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
410system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
411system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
412system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
413system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
414system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
416system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

422system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
423system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
424system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
425system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
426system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
427system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
428system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
429system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
430system.cpu0.itb.inst_hits 228743332 # ITB inst hits
431system.cpu0.itb.inst_misses 63317 # ITB inst misses
432system.cpu0.itb.read_hits 0 # DTB read hits
433system.cpu0.itb.read_misses 0 # DTB read misses
434system.cpu0.itb.write_hits 0 # DTB write hits
435system.cpu0.itb.write_misses 0 # DTB write misses
436system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
437system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
438system.cpu0.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
439system.cpu0.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
440system.cpu0.itb.flush_entries 24510 # Number of entries that have been flushed from TLB
441system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
442system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
443system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
444system.cpu0.itb.perms_faults 202277 # Number of TLB faults due to permissions restrictions
445system.cpu0.itb.read_accesses 0 # DTB read accesses
446system.cpu0.itb.write_accesses 0 # DTB write accesses
447system.cpu0.itb.inst_accesses 228806649 # ITB inst accesses
448system.cpu0.itb.hits 228743332 # DTB hits
449system.cpu0.itb.misses 63317 # DTB misses
450system.cpu0.itb.accesses 228806649 # DTB accesses
451system.cpu0.numCycles 867293351 # number of cpu cycles simulated
452system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
453system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
454system.cpu0.committedInsts 417325536 # Number of instructions committed
455system.cpu0.committedOps 490736323 # Number of ops (including micro ops) committed
456system.cpu0.discardedOps 44793539 # Number of ops (including micro ops) which were discarded before commit
457system.cpu0.numFetchSuspends 4342 # Number of times Execute suspended instruction fetching
458system.cpu0.quiesceCycles 93832115526 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
459system.cpu0.cpi 2.078218 # CPI: cycles per instruction
460system.cpu0.ipc 0.481182 # IPC: instructions per cycle
461system.cpu0.kern.inst.arm 0 # number of arm instructions executed
462system.cpu0.kern.inst.quiesce 4790 # number of quiesce instructions executed
463system.cpu0.tickCycles 682045150 # Number of cycles that the object actually ticked
464system.cpu0.idleCycles 185248201 # Total number of cycles that the object has spent stopped
465system.cpu0.dcache.tags.replacements 5375859 # number of replacements
466system.cpu0.dcache.tags.tagsinuse 504.387778 # Cycle average of tags in use
467system.cpu0.dcache.tags.total_refs 144555742 # Total number of references to valid blocks.
468system.cpu0.dcache.tags.sampled_refs 5376371 # Sample count of references to valid blocks.
469system.cpu0.dcache.tags.avg_refs 26.887233 # Average number of references to valid blocks.
470system.cpu0.dcache.tags.warmup_cycle 4951320000 # Cycle when the warmup percentage was hit.
471system.cpu0.dcache.tags.occ_blocks::cpu0.inst 504.387778 # Average occupied blocks per requestor
472system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.985132 # Average percentage of cache occupancy
473system.cpu0.dcache.tags.occ_percent::total 0.985132 # Average percentage of cache occupancy
474system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
475system.cpu0.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
476system.cpu0.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
477system.cpu0.dcache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
478system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
479system.cpu0.dcache.tags.tag_accesses 308078040 # Number of tag accesses
480system.cpu0.dcache.tags.data_accesses 308078040 # Number of data accesses
481system.cpu0.dcache.ReadReq_hits::cpu0.inst 74032777 # number of ReadReq hits
482system.cpu0.dcache.ReadReq_hits::total 74032777 # number of ReadReq hits
483system.cpu0.dcache.WriteReq_hits::cpu0.inst 66638302 # number of WriteReq hits
484system.cpu0.dcache.WriteReq_hits::total 66638302 # number of WriteReq hits
485system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.inst 115191 # number of WriteInvalidateReq hits
486system.cpu0.dcache.WriteInvalidateReq_hits::total 115191 # number of WriteInvalidateReq hits
487system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 1688442 # number of LoadLockedReq hits
488system.cpu0.dcache.LoadLockedReq_hits::total 1688442 # number of LoadLockedReq hits
489system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 1614699 # number of StoreCondReq hits
490system.cpu0.dcache.StoreCondReq_hits::total 1614699 # number of StoreCondReq hits
491system.cpu0.dcache.demand_hits::cpu0.inst 140671079 # number of demand (read+write) hits
492system.cpu0.dcache.demand_hits::total 140671079 # number of demand (read+write) hits
493system.cpu0.dcache.overall_hits::cpu0.inst 140671079 # number of overall hits
494system.cpu0.dcache.overall_hits::total 140671079 # number of overall hits
495system.cpu0.dcache.ReadReq_misses::cpu0.inst 3863790 # number of ReadReq misses
496system.cpu0.dcache.ReadReq_misses::total 3863790 # number of ReadReq misses
497system.cpu0.dcache.WriteReq_misses::cpu0.inst 2319255 # number of WriteReq misses
498system.cpu0.dcache.WriteReq_misses::total 2319255 # number of WriteReq misses
499system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.inst 742685 # number of WriteInvalidateReq misses
500system.cpu0.dcache.WriteInvalidateReq_misses::total 742685 # number of WriteInvalidateReq misses
501system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 105957 # number of LoadLockedReq misses
502system.cpu0.dcache.LoadLockedReq_misses::total 105957 # number of LoadLockedReq misses
503system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 178436 # number of StoreCondReq misses
504system.cpu0.dcache.StoreCondReq_misses::total 178436 # number of StoreCondReq misses
505system.cpu0.dcache.demand_misses::cpu0.inst 6183045 # number of demand (read+write) misses
506system.cpu0.dcache.demand_misses::total 6183045 # number of demand (read+write) misses
507system.cpu0.dcache.overall_misses::cpu0.inst 6183045 # number of overall misses
508system.cpu0.dcache.overall_misses::total 6183045 # number of overall misses
509system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 54382834533 # number of ReadReq miss cycles
510system.cpu0.dcache.ReadReq_miss_latency::total 54382834533 # number of ReadReq miss cycles
511system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 36195221997 # number of WriteReq miss cycles
512system.cpu0.dcache.WriteReq_miss_latency::total 36195221997 # number of WriteReq miss cycles
513system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.inst 21037893950 # number of WriteInvalidateReq miss cycles
514system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 21037893950 # number of WriteInvalidateReq miss cycles
515system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 1466052740 # number of LoadLockedReq miss cycles
516system.cpu0.dcache.LoadLockedReq_miss_latency::total 1466052740 # number of LoadLockedReq miss cycles
517system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 3737583856 # number of StoreCondReq miss cycles
518system.cpu0.dcache.StoreCondReq_miss_latency::total 3737583856 # number of StoreCondReq miss cycles
519system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 3062000 # number of StoreCondFailReq miss cycles
520system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3062000 # number of StoreCondFailReq miss cycles
521system.cpu0.dcache.demand_miss_latency::cpu0.inst 90578056530 # number of demand (read+write) miss cycles
522system.cpu0.dcache.demand_miss_latency::total 90578056530 # number of demand (read+write) miss cycles
523system.cpu0.dcache.overall_miss_latency::cpu0.inst 90578056530 # number of overall miss cycles
524system.cpu0.dcache.overall_miss_latency::total 90578056530 # number of overall miss cycles
525system.cpu0.dcache.ReadReq_accesses::cpu0.inst 77896567 # number of ReadReq accesses(hits+misses)
526system.cpu0.dcache.ReadReq_accesses::total 77896567 # number of ReadReq accesses(hits+misses)
527system.cpu0.dcache.WriteReq_accesses::cpu0.inst 68957557 # number of WriteReq accesses(hits+misses)
528system.cpu0.dcache.WriteReq_accesses::total 68957557 # number of WriteReq accesses(hits+misses)
529system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.inst 857876 # number of WriteInvalidateReq accesses(hits+misses)
530system.cpu0.dcache.WriteInvalidateReq_accesses::total 857876 # number of WriteInvalidateReq accesses(hits+misses)
531system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 1794399 # number of LoadLockedReq accesses(hits+misses)
532system.cpu0.dcache.LoadLockedReq_accesses::total 1794399 # number of LoadLockedReq accesses(hits+misses)
533system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 1793135 # number of StoreCondReq accesses(hits+misses)
534system.cpu0.dcache.StoreCondReq_accesses::total 1793135 # number of StoreCondReq accesses(hits+misses)
535system.cpu0.dcache.demand_accesses::cpu0.inst 146854124 # number of demand (read+write) accesses
536system.cpu0.dcache.demand_accesses::total 146854124 # number of demand (read+write) accesses
537system.cpu0.dcache.overall_accesses::cpu0.inst 146854124 # number of overall (read+write) accesses
538system.cpu0.dcache.overall_accesses::total 146854124 # number of overall (read+write) accesses
539system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.049602 # miss rate for ReadReq accesses
540system.cpu0.dcache.ReadReq_miss_rate::total 0.049602 # miss rate for ReadReq accesses
541system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.033633 # miss rate for WriteReq accesses
542system.cpu0.dcache.WriteReq_miss_rate::total 0.033633 # miss rate for WriteReq accesses
543system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.inst 0.865725 # miss rate for WriteInvalidateReq accesses
544system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.865725 # miss rate for WriteInvalidateReq accesses
545system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.059049 # miss rate for LoadLockedReq accesses
546system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059049 # miss rate for LoadLockedReq accesses
547system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.099511 # miss rate for StoreCondReq accesses
548system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099511 # miss rate for StoreCondReq accesses
549system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.042103 # miss rate for demand accesses
550system.cpu0.dcache.demand_miss_rate::total 0.042103 # miss rate for demand accesses
551system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.042103 # miss rate for overall accesses
552system.cpu0.dcache.overall_miss_rate::total 0.042103 # miss rate for overall accesses
553system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 14074.997485 # average ReadReq miss latency
554system.cpu0.dcache.ReadReq_avg_miss_latency::total 14074.997485 # average ReadReq miss latency
555system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15606.400330 # average WriteReq miss latency
556system.cpu0.dcache.WriteReq_avg_miss_latency::total 15606.400330 # average WriteReq miss latency
557system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 28326.806048 # average WriteInvalidateReq miss latency
558system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 28326.806048 # average WriteInvalidateReq miss latency
559system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 13836.299065 # average LoadLockedReq miss latency
560system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13836.299065 # average LoadLockedReq miss latency
561system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 20946.355309 # average StoreCondReq miss latency
562system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20946.355309 # average StoreCondReq miss latency
563system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency
564system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
565system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency
566system.cpu0.dcache.demand_avg_miss_latency::total 14649.425409 # average overall miss latency
567system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 14649.425409 # average overall miss latency
568system.cpu0.dcache.overall_avg_miss_latency::total 14649.425409 # average overall miss latency
569system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
570system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
571system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
572system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
573system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
574system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
575system.cpu0.dcache.fast_writes 0 # number of fast writes performed
576system.cpu0.dcache.cache_copies 0 # number of cache copies performed
577system.cpu0.dcache.writebacks::writebacks 3741617 # number of writebacks
578system.cpu0.dcache.writebacks::total 3741617 # number of writebacks
579system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 374932 # number of ReadReq MSHR hits
580system.cpu0.dcache.ReadReq_mshr_hits::total 374932 # number of ReadReq MSHR hits
581system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 967778 # number of WriteReq MSHR hits
582system.cpu0.dcache.WriteReq_mshr_hits::total 967778 # number of WriteReq MSHR hits
583system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.inst 26 # number of WriteInvalidateReq MSHR hits
584system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 26 # number of WriteInvalidateReq MSHR hits
585system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 53 # number of LoadLockedReq MSHR hits
586system.cpu0.dcache.LoadLockedReq_mshr_hits::total 53 # number of LoadLockedReq MSHR hits
587system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.inst 76 # number of StoreCondReq MSHR hits
588system.cpu0.dcache.StoreCondReq_mshr_hits::total 76 # number of StoreCondReq MSHR hits
589system.cpu0.dcache.demand_mshr_hits::cpu0.inst 1342710 # number of demand (read+write) MSHR hits
590system.cpu0.dcache.demand_mshr_hits::total 1342710 # number of demand (read+write) MSHR hits
591system.cpu0.dcache.overall_mshr_hits::cpu0.inst 1342710 # number of overall MSHR hits
592system.cpu0.dcache.overall_mshr_hits::total 1342710 # number of overall MSHR hits
593system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 3488858 # number of ReadReq MSHR misses
594system.cpu0.dcache.ReadReq_mshr_misses::total 3488858 # number of ReadReq MSHR misses
595system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 1351477 # number of WriteReq MSHR misses
596system.cpu0.dcache.WriteReq_mshr_misses::total 1351477 # number of WriteReq MSHR misses
597system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.inst 742659 # number of WriteInvalidateReq MSHR misses
598system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 742659 # number of WriteInvalidateReq MSHR misses
599system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 105904 # number of LoadLockedReq MSHR misses
600system.cpu0.dcache.LoadLockedReq_mshr_misses::total 105904 # number of LoadLockedReq MSHR misses
601system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 178360 # number of StoreCondReq MSHR misses
602system.cpu0.dcache.StoreCondReq_mshr_misses::total 178360 # number of StoreCondReq MSHR misses
603system.cpu0.dcache.demand_mshr_misses::cpu0.inst 4840335 # number of demand (read+write) MSHR misses
604system.cpu0.dcache.demand_mshr_misses::total 4840335 # number of demand (read+write) MSHR misses
605system.cpu0.dcache.overall_mshr_misses::cpu0.inst 4840335 # number of overall MSHR misses
606system.cpu0.dcache.overall_mshr_misses::total 4840335 # number of overall MSHR misses
607system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 42020078260 # number of ReadReq MSHR miss cycles
608system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42020078260 # number of ReadReq MSHR miss cycles
609system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 19120911908 # number of WriteReq MSHR miss cycles
610system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19120911908 # number of WriteReq MSHR miss cycles
611system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 19537847050 # number of WriteInvalidateReq MSHR miss cycles
612system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 19537847050 # number of WriteInvalidateReq MSHR miss cycles
613system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 1252614238 # number of LoadLockedReq MSHR miss cycles
614system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1252614238 # number of LoadLockedReq MSHR miss cycles
615system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 3369767592 # number of StoreCondReq MSHR miss cycles
616system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3369767592 # number of StoreCondReq MSHR miss cycles
617system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 2341000 # number of StoreCondFailReq MSHR miss cycles
618system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341000 # number of StoreCondFailReq MSHR miss cycles
619system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 61140990168 # number of demand (read+write) MSHR miss cycles
620system.cpu0.dcache.demand_mshr_miss_latency::total 61140990168 # number of demand (read+write) MSHR miss cycles
621system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 61140990168 # number of overall MSHR miss cycles
622system.cpu0.dcache.overall_mshr_miss_latency::total 61140990168 # number of overall MSHR miss cycles
623system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2949307890 # number of ReadReq MSHR uncacheable cycles
624system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2949307890 # number of ReadReq MSHR uncacheable cycles
625system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 3070097397 # number of WriteReq MSHR uncacheable cycles
626system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3070097397 # number of WriteReq MSHR uncacheable cycles
627system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 6019405287 # number of overall MSHR uncacheable cycles
628system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6019405287 # number of overall MSHR uncacheable cycles
629system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.044788 # mshr miss rate for ReadReq accesses
630system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.044788 # mshr miss rate for ReadReq accesses
631system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.019599 # mshr miss rate for WriteReq accesses
632system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019599 # mshr miss rate for WriteReq accesses
633system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.865695 # mshr miss rate for WriteInvalidateReq accesses
634system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.865695 # mshr miss rate for WriteInvalidateReq accesses
635system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.059019 # mshr miss rate for LoadLockedReq accesses
636system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059019 # mshr miss rate for LoadLockedReq accesses
637system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.099468 # mshr miss rate for StoreCondReq accesses
638system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099468 # mshr miss rate for StoreCondReq accesses
639system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for demand accesses
640system.cpu0.dcache.demand_mshr_miss_rate::total 0.032960 # mshr miss rate for demand accesses
641system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.032960 # mshr miss rate for overall accesses
642system.cpu0.dcache.overall_mshr_miss_rate::total 0.032960 # mshr miss rate for overall accesses
643system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12044.078108 # average ReadReq mshr miss latency
644system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.078108 # average ReadReq mshr miss latency
645system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14148.159316 # average WriteReq mshr miss latency
646system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14148.159316 # average WriteReq mshr miss latency
647system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 26307.965096 # average WriteInvalidateReq mshr miss latency
648system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26307.965096 # average WriteInvalidateReq mshr miss latency
649system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 11827.827447 # average LoadLockedReq mshr miss latency
650system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11827.827447 # average LoadLockedReq mshr miss latency
651system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 18893.067908 # average StoreCondReq mshr miss latency
652system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18893.067908 # average StoreCondReq mshr miss latency
653system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
654system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
655system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency
656system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency
657system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 12631.561693 # average overall mshr miss latency
658system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12631.561693 # average overall mshr miss latency
659system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
660system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
661system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
662system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
663system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
664system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
665system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
666system.cpu0.icache.tags.replacements 8781546 # number of replacements
667system.cpu0.icache.tags.tagsinuse 511.937582 # Cycle average of tags in use
668system.cpu0.icache.tags.total_refs 219752565 # Total number of references to valid blocks.
669system.cpu0.icache.tags.sampled_refs 8782058 # Sample count of references to valid blocks.
670system.cpu0.icache.tags.avg_refs 25.022901 # Average number of references to valid blocks.
671system.cpu0.icache.tags.warmup_cycle 16633914000 # Cycle when the warmup percentage was hit.
672system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937582 # Average occupied blocks per requestor
673system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999878 # Average percentage of cache occupancy
674system.cpu0.icache.tags.occ_percent::total 0.999878 # Average percentage of cache occupancy
675system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
676system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
677system.cpu0.icache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id
678system.cpu0.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
679system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
680system.cpu0.icache.tags.tag_accesses 465851331 # Number of tag accesses
681system.cpu0.icache.tags.data_accesses 465851331 # Number of data accesses
682system.cpu0.icache.ReadReq_hits::cpu0.inst 219752565 # number of ReadReq hits
683system.cpu0.icache.ReadReq_hits::total 219752565 # number of ReadReq hits
684system.cpu0.icache.demand_hits::cpu0.inst 219752565 # number of demand (read+write) hits
685system.cpu0.icache.demand_hits::total 219752565 # number of demand (read+write) hits
686system.cpu0.icache.overall_hits::cpu0.inst 219752565 # number of overall hits
687system.cpu0.icache.overall_hits::total 219752565 # number of overall hits
688system.cpu0.icache.ReadReq_misses::cpu0.inst 8782067 # number of ReadReq misses
689system.cpu0.icache.ReadReq_misses::total 8782067 # number of ReadReq misses
690system.cpu0.icache.demand_misses::cpu0.inst 8782067 # number of demand (read+write) misses
691system.cpu0.icache.demand_misses::total 8782067 # number of demand (read+write) misses
692system.cpu0.icache.overall_misses::cpu0.inst 8782067 # number of overall misses
693system.cpu0.icache.overall_misses::total 8782067 # number of overall misses
694system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 75181971221 # number of ReadReq miss cycles
695system.cpu0.icache.ReadReq_miss_latency::total 75181971221 # number of ReadReq miss cycles
696system.cpu0.icache.demand_miss_latency::cpu0.inst 75181971221 # number of demand (read+write) miss cycles
697system.cpu0.icache.demand_miss_latency::total 75181971221 # number of demand (read+write) miss cycles
698system.cpu0.icache.overall_miss_latency::cpu0.inst 75181971221 # number of overall miss cycles
699system.cpu0.icache.overall_miss_latency::total 75181971221 # number of overall miss cycles
700system.cpu0.icache.ReadReq_accesses::cpu0.inst 228534632 # number of ReadReq accesses(hits+misses)
701system.cpu0.icache.ReadReq_accesses::total 228534632 # number of ReadReq accesses(hits+misses)
702system.cpu0.icache.demand_accesses::cpu0.inst 228534632 # number of demand (read+write) accesses
703system.cpu0.icache.demand_accesses::total 228534632 # number of demand (read+write) accesses
704system.cpu0.icache.overall_accesses::cpu0.inst 228534632 # number of overall (read+write) accesses
705system.cpu0.icache.overall_accesses::total 228534632 # number of overall (read+write) accesses
706system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038428 # miss rate for ReadReq accesses
707system.cpu0.icache.ReadReq_miss_rate::total 0.038428 # miss rate for ReadReq accesses
708system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038428 # miss rate for demand accesses
709system.cpu0.icache.demand_miss_rate::total 0.038428 # miss rate for demand accesses
710system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038428 # miss rate for overall accesses
711system.cpu0.icache.overall_miss_rate::total 0.038428 # miss rate for overall accesses
712system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8560.851474 # average ReadReq miss latency
713system.cpu0.icache.ReadReq_avg_miss_latency::total 8560.851474 # average ReadReq miss latency
714system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency
715system.cpu0.icache.demand_avg_miss_latency::total 8560.851474 # average overall miss latency
716system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8560.851474 # average overall miss latency
717system.cpu0.icache.overall_avg_miss_latency::total 8560.851474 # average overall miss latency
718system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
719system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
720system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
721system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
722system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
723system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
724system.cpu0.icache.fast_writes 0 # number of fast writes performed
725system.cpu0.icache.cache_copies 0 # number of cache copies performed
726system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8782067 # number of ReadReq MSHR misses
727system.cpu0.icache.ReadReq_mshr_misses::total 8782067 # number of ReadReq MSHR misses
728system.cpu0.icache.demand_mshr_misses::cpu0.inst 8782067 # number of demand (read+write) MSHR misses
729system.cpu0.icache.demand_mshr_misses::total 8782067 # number of demand (read+write) MSHR misses
730system.cpu0.icache.overall_mshr_misses::cpu0.inst 8782067 # number of overall MSHR misses
731system.cpu0.icache.overall_mshr_misses::total 8782067 # number of overall MSHR misses
732system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61997855741 # number of ReadReq MSHR miss cycles
733system.cpu0.icache.ReadReq_mshr_miss_latency::total 61997855741 # number of ReadReq MSHR miss cycles
734system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61997855741 # number of demand (read+write) MSHR miss cycles
735system.cpu0.icache.demand_mshr_miss_latency::total 61997855741 # number of demand (read+write) MSHR miss cycles
736system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61997855741 # number of overall MSHR miss cycles
737system.cpu0.icache.overall_mshr_miss_latency::total 61997855741 # number of overall MSHR miss cycles
738system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles
739system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles
740system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles
741system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles
742system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for ReadReq accesses
743system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.038428 # mshr miss rate for ReadReq accesses
744system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for demand accesses
745system.cpu0.icache.demand_mshr_miss_rate::total 0.038428 # mshr miss rate for demand accesses
746system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038428 # mshr miss rate for overall accesses
747system.cpu0.icache.overall_mshr_miss_rate::total 0.038428 # mshr miss rate for overall accesses
748system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average ReadReq mshr miss latency
749system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7059.597216 # average ReadReq mshr miss latency
750system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency
751system.cpu0.icache.demand_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency
752system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7059.597216 # average overall mshr miss latency
753system.cpu0.icache.overall_avg_mshr_miss_latency::total 7059.597216 # average overall mshr miss latency
754system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
755system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
756system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
757system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
758system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
759system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 84003023 # number of hwpf identified
760system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 4398912 # number of hwpf that were already in mshr
761system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 74572645 # number of hwpf that were already in the cache
762system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1090360 # number of hwpf that were already in the prefetch queue
763system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
764system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 154166 # number of hwpf removed because MSHR allocated
765system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 3786940 # number of hwpf issued
766system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 6742713 # number of hwpf spanning a virtual page
767system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
768system.cpu0.l2cache.tags.replacements 4037603 # number of replacements
769system.cpu0.l2cache.tags.tagsinuse 16229.874548 # Cycle average of tags in use
770system.cpu0.l2cache.tags.total_refs 15269588 # Total number of references to valid blocks.
771system.cpu0.l2cache.tags.sampled_refs 4053811 # Sample count of references to valid blocks.
772system.cpu0.l2cache.tags.avg_refs 3.766724 # Average number of references to valid blocks.
773system.cpu0.l2cache.tags.warmup_cycle 14918796500 # Cycle when the warmup percentage was hit.
774system.cpu0.l2cache.tags.occ_blocks::writebacks 3465.639505 # Average occupied blocks per requestor
775system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.958286 # Average occupied blocks per requestor
776system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.625357 # Average occupied blocks per requestor
777system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2577.016988 # Average occupied blocks per requestor
778system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 10118.634411 # Average occupied blocks per requestor
779system.cpu0.l2cache.tags.occ_percent::writebacks 0.211526 # Average percentage of cache occupancy
780system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002500 # Average percentage of cache occupancy
781system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001686 # Average percentage of cache occupancy
782system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.157289 # Average percentage of cache occupancy
783system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.617592 # Average percentage of cache occupancy
784system.cpu0.l2cache.tags.occ_percent::total 0.990593 # Average percentage of cache occupancy
785system.cpu0.l2cache.tags.occ_task_id_blocks::1022 10250 # Occupied blocks per task id
786system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
787system.cpu0.l2cache.tags.occ_task_id_blocks::1024 5866 # Occupied blocks per task id
788system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 116 # Occupied blocks per task id
789system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 1048 # Occupied blocks per task id
790system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 4016 # Occupied blocks per task id
791system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3415 # Occupied blocks per task id
792system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1655 # Occupied blocks per task id
793system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id
794system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
795system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
796system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
797system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
798system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 525 # Occupied blocks per task id
799system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2441 # Occupied blocks per task id
800system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1975 # Occupied blocks per task id
801system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id
802system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.625610 # Percentage of cache occupancy per task id
803system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id
804system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.358032 # Percentage of cache occupancy per task id
805system.cpu0.l2cache.tags.tag_accesses 311163440 # Number of tag accesses
806system.cpu0.l2cache.tags.data_accesses 311163440 # Number of data accesses
807system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 470272 # number of ReadReq hits
808system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 147367 # number of ReadReq hits
809system.cpu0.l2cache.ReadReq_hits::cpu0.inst 11429450 # number of ReadReq hits
810system.cpu0.l2cache.ReadReq_hits::total 12047089 # number of ReadReq hits
811system.cpu0.l2cache.Writeback_hits::writebacks 3741617 # number of Writeback hits
812system.cpu0.l2cache.Writeback_hits::total 3741617 # number of Writeback hits
813system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.inst 295044 # number of WriteInvalidateReq hits
814system.cpu0.l2cache.WriteInvalidateReq_hits::total 295044 # number of WriteInvalidateReq hits
815system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 86443 # number of UpgradeReq hits
816system.cpu0.l2cache.UpgradeReq_hits::total 86443 # number of UpgradeReq hits
817system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 36465 # number of SCUpgradeReq hits
818system.cpu0.l2cache.SCUpgradeReq_hits::total 36465 # number of SCUpgradeReq hits
819system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 911350 # number of ReadExReq hits
820system.cpu0.l2cache.ReadExReq_hits::total 911350 # number of ReadExReq hits
821system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 470272 # number of demand (read+write) hits
822system.cpu0.l2cache.demand_hits::cpu0.itb.walker 147367 # number of demand (read+write) hits
823system.cpu0.l2cache.demand_hits::cpu0.inst 12340800 # number of demand (read+write) hits
824system.cpu0.l2cache.demand_hits::total 12958439 # number of demand (read+write) hits
825system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 470272 # number of overall hits
826system.cpu0.l2cache.overall_hits::cpu0.itb.walker 147367 # number of overall hits
827system.cpu0.l2cache.overall_hits::cpu0.inst 12340800 # number of overall hits
828system.cpu0.l2cache.overall_hits::total 12958439 # number of overall hits
829system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13865 # number of ReadReq misses
830system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10088 # number of ReadReq misses
831system.cpu0.l2cache.ReadReq_misses::cpu0.inst 947171 # number of ReadReq misses
832system.cpu0.l2cache.ReadReq_misses::total 971124 # number of ReadReq misses
833system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.inst 446451 # number of WriteInvalidateReq misses
834system.cpu0.l2cache.WriteInvalidateReq_misses::total 446451 # number of WriteInvalidateReq misses
835system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 123568 # number of UpgradeReq misses
836system.cpu0.l2cache.UpgradeReq_misses::total 123568 # number of UpgradeReq misses
837system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 141888 # number of SCUpgradeReq misses
838system.cpu0.l2cache.SCUpgradeReq_misses::total 141888 # number of SCUpgradeReq misses
839system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 7 # number of SCUpgradeFailReq misses
840system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
841system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 231493 # number of ReadExReq misses
842system.cpu0.l2cache.ReadExReq_misses::total 231493 # number of ReadExReq misses
843system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13865 # number of demand (read+write) misses
844system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10088 # number of demand (read+write) misses
845system.cpu0.l2cache.demand_misses::cpu0.inst 1178664 # number of demand (read+write) misses
846system.cpu0.l2cache.demand_misses::total 1202617 # number of demand (read+write) misses
847system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13865 # number of overall misses
848system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10088 # number of overall misses
849system.cpu0.l2cache.overall_misses::cpu0.inst 1178664 # number of overall misses
850system.cpu0.l2cache.overall_misses::total 1202617 # number of overall misses
851system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 459903131 # number of ReadReq miss cycles
852system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 354751936 # number of ReadReq miss cycles
853system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 28411115925 # number of ReadReq miss cycles
854system.cpu0.l2cache.ReadReq_miss_latency::total 29225770992 # number of ReadReq miss cycles
855system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.inst 15916059245 # number of WriteInvalidateReq miss cycles
856system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 15916059245 # number of WriteInvalidateReq miss cycles
857system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 2454108805 # number of UpgradeReq miss cycles
858system.cpu0.l2cache.UpgradeReq_miss_latency::total 2454108805 # number of UpgradeReq miss cycles
859system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 2872469472 # number of SCUpgradeReq miss cycles
860system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2872469472 # number of SCUpgradeReq miss cycles
861system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 2284000 # number of SCUpgradeFailReq miss cycles
862system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2284000 # number of SCUpgradeFailReq miss cycles
863system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 8822124839 # number of ReadExReq miss cycles
864system.cpu0.l2cache.ReadExReq_miss_latency::total 8822124839 # number of ReadExReq miss cycles
865system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 459903131 # number of demand (read+write) miss cycles
866system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 354751936 # number of demand (read+write) miss cycles
867system.cpu0.l2cache.demand_miss_latency::cpu0.inst 37233240764 # number of demand (read+write) miss cycles
868system.cpu0.l2cache.demand_miss_latency::total 38047895831 # number of demand (read+write) miss cycles
869system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 459903131 # number of overall miss cycles
870system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 354751936 # number of overall miss cycles
871system.cpu0.l2cache.overall_miss_latency::cpu0.inst 37233240764 # number of overall miss cycles
872system.cpu0.l2cache.overall_miss_latency::total 38047895831 # number of overall miss cycles
873system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 484137 # number of ReadReq accesses(hits+misses)
874system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 157455 # number of ReadReq accesses(hits+misses)
875system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 12376621 # number of ReadReq accesses(hits+misses)
876system.cpu0.l2cache.ReadReq_accesses::total 13018213 # number of ReadReq accesses(hits+misses)
877system.cpu0.l2cache.Writeback_accesses::writebacks 3741617 # number of Writeback accesses(hits+misses)
878system.cpu0.l2cache.Writeback_accesses::total 3741617 # number of Writeback accesses(hits+misses)
879system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.inst 741495 # number of WriteInvalidateReq accesses(hits+misses)
880system.cpu0.l2cache.WriteInvalidateReq_accesses::total 741495 # number of WriteInvalidateReq accesses(hits+misses)
881system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 210011 # number of UpgradeReq accesses(hits+misses)
882system.cpu0.l2cache.UpgradeReq_accesses::total 210011 # number of UpgradeReq accesses(hits+misses)
883system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 178353 # number of SCUpgradeReq accesses(hits+misses)
884system.cpu0.l2cache.SCUpgradeReq_accesses::total 178353 # number of SCUpgradeReq accesses(hits+misses)
885system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 7 # number of SCUpgradeFailReq accesses(hits+misses)
886system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
887system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 1142843 # number of ReadExReq accesses(hits+misses)
888system.cpu0.l2cache.ReadExReq_accesses::total 1142843 # number of ReadExReq accesses(hits+misses)
889system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 484137 # number of demand (read+write) accesses
890system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 157455 # number of demand (read+write) accesses
891system.cpu0.l2cache.demand_accesses::cpu0.inst 13519464 # number of demand (read+write) accesses
892system.cpu0.l2cache.demand_accesses::total 14161056 # number of demand (read+write) accesses
893system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 484137 # number of overall (read+write) accesses
894system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 157455 # number of overall (read+write) accesses
895system.cpu0.l2cache.overall_accesses::cpu0.inst 13519464 # number of overall (read+write) accesses
896system.cpu0.l2cache.overall_accesses::total 14161056 # number of overall (read+write) accesses
897system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for ReadReq accesses
898system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064069 # miss rate for ReadReq accesses
899system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.076529 # miss rate for ReadReq accesses
900system.cpu0.l2cache.ReadReq_miss_rate::total 0.074597 # miss rate for ReadReq accesses
901system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.inst 0.602096 # miss rate for WriteInvalidateReq accesses
902system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.602096 # miss rate for WriteInvalidateReq accesses
903system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.588388 # miss rate for UpgradeReq accesses
904system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.588388 # miss rate for UpgradeReq accesses
905system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.795546 # miss rate for SCUpgradeReq accesses
906system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.795546 # miss rate for SCUpgradeReq accesses
907system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses
908system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
909system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.202559 # miss rate for ReadExReq accesses
910system.cpu0.l2cache.ReadExReq_miss_rate::total 0.202559 # miss rate for ReadExReq accesses
911system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for demand accesses
912system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064069 # miss rate for demand accesses
913system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.087183 # miss rate for demand accesses
914system.cpu0.l2cache.demand_miss_rate::total 0.084924 # miss rate for demand accesses
915system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028639 # miss rate for overall accesses
916system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064069 # miss rate for overall accesses
917system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.087183 # miss rate for overall accesses
918system.cpu0.l2cache.overall_miss_rate::total 0.084924 # miss rate for overall accesses
919system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average ReadReq miss latency
920system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 35165.735131 # average ReadReq miss latency
921system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29995.762038 # average ReadReq miss latency
922system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30094.788093 # average ReadReq miss latency
923system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.inst 35650.181644 # average WriteInvalidateReq miss latency
924system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 35650.181644 # average WriteInvalidateReq miss latency
925system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 19860.391080 # average UpgradeReq miss latency
926system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 19860.391080 # average UpgradeReq miss latency
927system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 20244.625846 # average SCUpgradeReq miss latency
928system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20244.625846 # average SCUpgradeReq miss latency
929system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 326285.714286 # average SCUpgradeFailReq miss latency
930system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 326285.714286 # average SCUpgradeFailReq miss latency
931system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 38109.682967 # average ReadExReq miss latency
932system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 38109.682967 # average ReadExReq miss latency
933system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency
934system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency
935system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency
936system.cpu0.l2cache.demand_avg_miss_latency::total 31637.583562 # average overall miss latency
937system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 33170.077966 # average overall miss latency
938system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 35165.735131 # average overall miss latency
939system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31589.359448 # average overall miss latency
940system.cpu0.l2cache.overall_avg_miss_latency::total 31637.583562 # average overall miss latency
941system.cpu0.l2cache.blocked_cycles::no_mshrs 196093 # number of cycles access was blocked
942system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
943system.cpu0.l2cache.blocked::no_mshrs 2541 # number of cycles access was blocked
944system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
945system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 77.171586 # average number of cycles each access was blocked
946system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
947system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
948system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
949system.cpu0.l2cache.writebacks::writebacks 1602519 # number of writebacks
950system.cpu0.l2cache.writebacks::total 1602519 # number of writebacks
951system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits
952system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 5 # number of ReadReq MSHR hits
953system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 79969 # number of ReadReq MSHR hits
954system.cpu0.l2cache.ReadReq_mshr_hits::total 79976 # number of ReadReq MSHR hits
955system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.inst 383227 # number of WriteInvalidateReq MSHR hits
956system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 383227 # number of WriteInvalidateReq MSHR hits
957system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 9177 # number of ReadExReq MSHR hits
958system.cpu0.l2cache.ReadExReq_mshr_hits::total 9177 # number of ReadExReq MSHR hits
959system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits
960system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 5 # number of demand (read+write) MSHR hits
961system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 89146 # number of demand (read+write) MSHR hits
962system.cpu0.l2cache.demand_mshr_hits::total 89153 # number of demand (read+write) MSHR hits
963system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits
964system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 5 # number of overall MSHR hits
965system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 89146 # number of overall MSHR hits
966system.cpu0.l2cache.overall_mshr_hits::total 89153 # number of overall MSHR hits
967system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13863 # number of ReadReq MSHR misses
968system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10083 # number of ReadReq MSHR misses
969system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 867202 # number of ReadReq MSHR misses
970system.cpu0.l2cache.ReadReq_mshr_misses::total 891148 # number of ReadReq MSHR misses
971system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of HardPFReq MSHR misses
972system.cpu0.l2cache.HardPFReq_mshr_misses::total 3786879 # number of HardPFReq MSHR misses
973system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.inst 63224 # number of WriteInvalidateReq MSHR misses
974system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 63224 # number of WriteInvalidateReq MSHR misses
975system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 123568 # number of UpgradeReq MSHR misses
976system.cpu0.l2cache.UpgradeReq_mshr_misses::total 123568 # number of UpgradeReq MSHR misses
977system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 141888 # number of SCUpgradeReq MSHR misses
978system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 141888 # number of SCUpgradeReq MSHR misses
979system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 7 # number of SCUpgradeFailReq MSHR misses
980system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
981system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 222316 # number of ReadExReq MSHR misses
982system.cpu0.l2cache.ReadExReq_mshr_misses::total 222316 # number of ReadExReq MSHR misses
983system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13863 # number of demand (read+write) MSHR misses
984system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10083 # number of demand (read+write) MSHR misses
985system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 1089518 # number of demand (read+write) MSHR misses
986system.cpu0.l2cache.demand_mshr_misses::total 1113464 # number of demand (read+write) MSHR misses
987system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13863 # number of overall MSHR misses
988system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10083 # number of overall MSHR misses
989system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 1089518 # number of overall MSHR misses
990system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 3786879 # number of overall MSHR misses
991system.cpu0.l2cache.overall_mshr_misses::total 4900343 # number of overall MSHR misses
992system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of ReadReq MSHR miss cycles
993system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 283585554 # number of ReadReq MSHR miss cycles
994system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 20498207280 # number of ReadReq MSHR miss cycles
995system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 21143980631 # number of ReadReq MSHR miss cycles
996system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of HardPFReq MSHR miss cycles
997system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 168439656794 # number of HardPFReq MSHR miss cycles
998system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 1410635970 # number of WriteInvalidateReq MSHR miss cycles
999system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1410635970 # number of WriteInvalidateReq MSHR miss cycles
1000system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 2082130886 # number of UpgradeReq MSHR miss cycles
1001system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2082130886 # number of UpgradeReq MSHR miss cycles
1002system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 1980278880 # number of SCUpgradeReq MSHR miss cycles
1003system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1980278880 # number of SCUpgradeReq MSHR miss cycles
1004system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 1885000 # number of SCUpgradeFailReq MSHR miss cycles
1005system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1885000 # number of SCUpgradeFailReq MSHR miss cycles
1006system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 6408519883 # number of ReadExReq MSHR miss cycles
1007system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 6408519883 # number of ReadExReq MSHR miss cycles
1008system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of demand (read+write) MSHR miss cycles
1009system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 283585554 # number of demand (read+write) MSHR miss cycles
1010system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 26906727163 # number of demand (read+write) MSHR miss cycles
1011system.cpu0.l2cache.demand_mshr_miss_latency::total 27552500514 # number of demand (read+write) MSHR miss cycles
1012system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 362187797 # number of overall MSHR miss cycles
1013system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 283585554 # number of overall MSHR miss cycles
1014system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 26906727163 # number of overall MSHR miss cycles
1015system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 168439656794 # number of overall MSHR miss cycles
1016system.cpu0.l2cache.overall_mshr_miss_latency::total 195992157308 # number of overall MSHR miss cycles
1017system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6920870357 # number of ReadReq MSHR uncacheable cycles
1018system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6920870357 # number of ReadReq MSHR uncacheable cycles
1019system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 2922560102 # number of WriteReq MSHR uncacheable cycles
1020system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2922560102 # number of WriteReq MSHR uncacheable cycles
1021system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 9843430459 # number of overall MSHR uncacheable cycles
1022system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9843430459 # number of overall MSHR uncacheable cycles
1023system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for ReadReq accesses
1024system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for ReadReq accesses
1025system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.070068 # mshr miss rate for ReadReq accesses
1026system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.068454 # mshr miss rate for ReadReq accesses
1027system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1028system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1029system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.085266 # mshr miss rate for WriteInvalidateReq accesses
1030system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.085266 # mshr miss rate for WriteInvalidateReq accesses
1031system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.588388 # mshr miss rate for UpgradeReq accesses
1032system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.588388 # mshr miss rate for UpgradeReq accesses
1033system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.795546 # mshr miss rate for SCUpgradeReq accesses
1034system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.795546 # mshr miss rate for SCUpgradeReq accesses
1035system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
1036system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1037system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.194529 # mshr miss rate for ReadExReq accesses
1038system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.194529 # mshr miss rate for ReadExReq accesses
1039system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for demand accesses
1040system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for demand accesses
1041system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for demand accesses
1042system.cpu0.l2cache.demand_mshr_miss_rate::total 0.078629 # mshr miss rate for demand accesses
1043system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.028634 # mshr miss rate for overall accesses
1044system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064037 # mshr miss rate for overall accesses
1045system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080589 # mshr miss rate for overall accesses
1046system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1047system.cpu0.l2cache.overall_mshr_miss_rate::total 0.346044 # mshr miss rate for overall accesses
1048system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average ReadReq mshr miss latency
1049system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average ReadReq mshr miss latency
1050system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23637.177128 # average ReadReq mshr miss latency
1051system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23726.676861 # average ReadReq mshr miss latency
1052system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average HardPFReq mshr miss latency
1053system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44479.809572 # average HardPFReq mshr miss latency
1054system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22311.716595 # average WriteInvalidateReq mshr miss latency
1055system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 22311.716595 # average WriteInvalidateReq mshr miss latency
1056system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 16850.081623 # average UpgradeReq mshr miss latency
1057system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16850.081623 # average UpgradeReq mshr miss latency
1058system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13956.633965 # average SCUpgradeReq mshr miss latency
1059system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13956.633965 # average SCUpgradeReq mshr miss latency
1060system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 269285.714286 # average SCUpgradeFailReq mshr miss latency
1061system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 269285.714286 # average SCUpgradeFailReq mshr miss latency
1062system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 28826.174828 # average ReadExReq mshr miss latency
1063system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 28826.174828 # average ReadExReq mshr miss latency
1064system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency
1065system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency
1066system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency
1067system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 24744.850767 # average overall mshr miss latency
1068system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26126.220659 # average overall mshr miss latency
1069system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28125.116929 # average overall mshr miss latency
1070system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24695.991404 # average overall mshr miss latency
1071system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44479.809572 # average overall mshr miss latency
1072system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39995.599759 # average overall mshr miss latency
1073system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1074system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1075system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
1076system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1077system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1078system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1079system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1080system.cpu0.toL2Bus.trans_dist::ReadReq 17406363 # Transaction distribution
1081system.cpu0.toL2Bus.trans_dist::ReadResp 13329872 # Transaction distribution
1082system.cpu0.toL2Bus.trans_dist::WriteReq 19688 # Transaction distribution
1083system.cpu0.toL2Bus.trans_dist::WriteResp 19687 # Transaction distribution
1084system.cpu0.toL2Bus.trans_dist::Writeback 3741617 # Transaction distribution
1085system.cpu0.toL2Bus.trans_dist::HardPFReq 5530609 # Transaction distribution
1086system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 862152 # Transaction distribution
1087system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 741495 # Transaction distribution
1088system.cpu0.toL2Bus.trans_dist::UpgradeReq 486160 # Transaction distribution
1089system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 325301 # Transaction distribution
1090system.cpu0.toL2Bus.trans_dist::UpgradeResp 465486 # Transaction distribution
1091system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution
1092system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
1093system.cpu0.toL2Bus.trans_dist::ReadExReq 1278141 # Transaction distribution
1094system.cpu0.toL2Bus.trans_dist::ReadExResp 1152631 # Transaction distribution
1095system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17668715 # Packet count per connected master and slave (bytes)
1096system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15752783 # Packet count per connected master and slave (bytes)
1097system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 346532 # Packet count per connected master and slave (bytes)
1098system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1063511 # Packet count per connected master and slave (bytes)
1099system.cpu0.toL2Bus.pkt_count::total 34831541 # Packet count per connected master and slave (bytes)
1100system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 565398848 # Cumulative packet size per connected master and slave (bytes)
1101system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598192623 # Cumulative packet size per connected master and slave (bytes)
1102system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1259640 # Cumulative packet size per connected master and slave (bytes)
1103system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3873096 # Cumulative packet size per connected master and slave (bytes)
1104system.cpu0.toL2Bus.pkt_size::total 1168724207 # Cumulative packet size per connected master and slave (bytes)
1105system.cpu0.toL2Bus.snoops 10729638 # Total snoops (count)
1106system.cpu0.toL2Bus.snoop_fanout::samples 29561564 # Request fanout histogram
1107system.cpu0.toL2Bus.snoop_fanout::mean 5.351841 # Request fanout histogram
1108system.cpu0.toL2Bus.snoop_fanout::stdev 0.477545 # Request fanout histogram
1109system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1110system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1111system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1112system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1113system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1114system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1115system.cpu0.toL2Bus.snoop_fanout::5 19160579 64.82% 64.82% # Request fanout histogram
1116system.cpu0.toL2Bus.snoop_fanout::6 10400985 35.18% 100.00% # Request fanout histogram
1117system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1118system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1119system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1120system.cpu0.toL2Bus.snoop_fanout::total 29561564 # Request fanout histogram
1121system.cpu0.toL2Bus.reqLayer0.occupancy 14119794312 # Layer occupancy (ticks)
1122system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1123system.cpu0.toL2Bus.snoopLayer0.occupancy 225496496 # Layer occupancy (ticks)
1124system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1125system.cpu0.toL2Bus.respLayer0.occupancy 13269247990 # Layer occupancy (ticks)
1126system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1127system.cpu0.toL2Bus.respLayer1.occupancy 7748577182 # Layer occupancy (ticks)
1128system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1129system.cpu0.toL2Bus.respLayer2.occupancy 189385144 # Layer occupancy (ticks)
1130system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1131system.cpu0.toL2Bus.respLayer3.occupancy 579874631 # Layer occupancy (ticks)
1132system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1133system.cpu1.branchPred.lookups 146637664 # Number of BP lookups
1134system.cpu1.branchPred.condPredicted 104244557 # Number of conditional branches predicted
1135system.cpu1.branchPred.condIncorrect 6464776 # Number of conditional branches incorrect
1136system.cpu1.branchPred.BTBLookups 109760718 # Number of BTB lookups
1137system.cpu1.branchPred.BTBHits 80092874 # Number of BTB hits
1138system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1139system.cpu1.branchPred.BTBHitPct 72.970436 # BTB Hit Percentage
1140system.cpu1.branchPred.usedRAS 17287162 # Number of times the RAS was used to get a target.
1141system.cpu1.branchPred.RASInCorrect 1125459 # Number of incorrect RAS predictions.
1142system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1143system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1144system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1145system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1146system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1147system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1148system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1149system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1157system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1158system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1159system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1160system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1161system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1162system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1163system.cpu1.dtb.inst_hits 0 # ITB inst hits
1164system.cpu1.dtb.inst_misses 0 # ITB inst misses
1165system.cpu1.dtb.read_hits 95196820 # DTB read hits
1166system.cpu1.dtb.read_misses 258683 # DTB read misses
1167system.cpu1.dtb.write_hits 82774540 # DTB write hits
1168system.cpu1.dtb.write_misses 48918 # DTB write misses
1169system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1170system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1171system.cpu1.dtb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
1172system.cpu1.dtb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
1173system.cpu1.dtb.flush_entries 40938 # Number of entries that have been flushed from TLB
1174system.cpu1.dtb.align_faults 1166 # Number of TLB faults due to alignment restrictions
1175system.cpu1.dtb.prefetch_faults 8454 # Number of TLB faults due to prefetch
1176system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1177system.cpu1.dtb.perms_faults 11190 # Number of TLB faults due to permissions restrictions
1178system.cpu1.dtb.read_accesses 95455503 # DTB read accesses
1179system.cpu1.dtb.write_accesses 82823458 # DTB write accesses
1180system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1181system.cpu1.dtb.hits 177971360 # DTB hits
1182system.cpu1.dtb.misses 307601 # DTB misses
1183system.cpu1.dtb.accesses 178278961 # DTB accesses
1184system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1185system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1186system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1187system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1188system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1189system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1190system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1191system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1197system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1198system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1199system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1200system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1201system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1202system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1203system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1204system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1205system.cpu1.itb.inst_hits 262373201 # ITB inst hits
1206system.cpu1.itb.inst_misses 66107 # ITB inst misses
1207system.cpu1.itb.read_hits 0 # DTB read hits
1208system.cpu1.itb.read_misses 0 # DTB read misses
1209system.cpu1.itb.write_hits 0 # DTB write hits
1210system.cpu1.itb.write_misses 0 # DTB write misses
1211system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1212system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1213system.cpu1.itb.flush_tlb_mva_asid 42758 # Number of times TLB was flushed by MVA & ASID
1214system.cpu1.itb.flush_tlb_asid 1054 # Number of times TLB was flushed by ASID
1215system.cpu1.itb.flush_entries 29545 # Number of entries that have been flushed from TLB
1216system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1217system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1218system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1219system.cpu1.itb.perms_faults 222220 # Number of TLB faults due to permissions restrictions
1220system.cpu1.itb.read_accesses 0 # DTB read accesses
1221system.cpu1.itb.write_accesses 0 # DTB write accesses
1222system.cpu1.itb.inst_accesses 262439308 # ITB inst accesses
1223system.cpu1.itb.hits 262373201 # DTB hits
1224system.cpu1.itb.misses 66107 # DTB misses
1225system.cpu1.itb.accesses 262439308 # DTB accesses
1226system.cpu1.numCycles 965776076 # number of cpu cycles simulated
1227system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1228system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1229system.cpu1.committedInsts 483897990 # Number of instructions committed
1230system.cpu1.committedOps 569285719 # Number of ops (including micro ops) committed
1231system.cpu1.discardedOps 49152054 # Number of ops (including micro ops) which were discarded before commit
1232system.cpu1.numFetchSuspends 5850 # Number of times Execute suspended instruction fetching
1233system.cpu1.quiesceCycles 93733878410 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1234system.cpu1.cpi 1.995826 # CPI: cycles per instruction
1235system.cpu1.ipc 0.501046 # IPC: instructions per cycle
1236system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1237system.cpu1.kern.inst.quiesce 14403 # number of quiesce instructions executed
1238system.cpu1.tickCycles 777604637 # Number of cycles that the object actually ticked
1239system.cpu1.idleCycles 188171439 # Total number of cycles that the object has spent stopped
1240system.cpu1.dcache.tags.replacements 5691678 # number of replacements
1241system.cpu1.dcache.tags.tagsinuse 432.252247 # Cycle average of tags in use
1242system.cpu1.dcache.tags.total_refs 169393329 # Total number of references to valid blocks.
1243system.cpu1.dcache.tags.sampled_refs 5692190 # Sample count of references to valid blocks.
1244system.cpu1.dcache.tags.avg_refs 29.758903 # Average number of references to valid blocks.
1245system.cpu1.dcache.tags.warmup_cycle 8364525946500 # Cycle when the warmup percentage was hit.
1246system.cpu1.dcache.tags.occ_blocks::cpu1.inst 432.252247 # Average occupied blocks per requestor
1247system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.844243 # Average percentage of cache occupancy
1248system.cpu1.dcache.tags.occ_percent::total 0.844243 # Average percentage of cache occupancy
1249system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1250system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
1251system.cpu1.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id
1252system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
1253system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1254system.cpu1.dcache.tags.tag_accesses 358720623 # Number of tag accesses
1255system.cpu1.dcache.tags.data_accesses 358720623 # Number of data accesses
1256system.cpu1.dcache.ReadReq_hits::cpu1.inst 87552380 # number of ReadReq hits
1257system.cpu1.dcache.ReadReq_hits::total 87552380 # number of ReadReq hits
1258system.cpu1.dcache.WriteReq_hits::cpu1.inst 77214593 # number of WriteReq hits
1259system.cpu1.dcache.WriteReq_hits::total 77214593 # number of WriteReq hits
1260system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.inst 211985 # number of WriteInvalidateReq hits
1261system.cpu1.dcache.WriteInvalidateReq_hits::total 211985 # number of WriteInvalidateReq hits
1262system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 1994962 # number of LoadLockedReq hits
1263system.cpu1.dcache.LoadLockedReq_hits::total 1994962 # number of LoadLockedReq hits
1264system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 1944639 # number of StoreCondReq hits
1265system.cpu1.dcache.StoreCondReq_hits::total 1944639 # number of StoreCondReq hits
1266system.cpu1.dcache.demand_hits::cpu1.inst 164766973 # number of demand (read+write) hits
1267system.cpu1.dcache.demand_hits::total 164766973 # number of demand (read+write) hits
1268system.cpu1.dcache.overall_hits::cpu1.inst 164766973 # number of overall hits
1269system.cpu1.dcache.overall_hits::total 164766973 # number of overall hits
1270system.cpu1.dcache.ReadReq_misses::cpu1.inst 4362572 # number of ReadReq misses
1271system.cpu1.dcache.ReadReq_misses::total 4362572 # number of ReadReq misses
1272system.cpu1.dcache.WriteReq_misses::cpu1.inst 2362737 # number of WriteReq misses
1273system.cpu1.dcache.WriteReq_misses::total 2362737 # number of WriteReq misses
1274system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.inst 497251 # number of WriteInvalidateReq misses
1275system.cpu1.dcache.WriteInvalidateReq_misses::total 497251 # number of WriteInvalidateReq misses
1276system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 139927 # number of LoadLockedReq misses
1277system.cpu1.dcache.LoadLockedReq_misses::total 139927 # number of LoadLockedReq misses
1278system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 188742 # number of StoreCondReq misses
1279system.cpu1.dcache.StoreCondReq_misses::total 188742 # number of StoreCondReq misses
1280system.cpu1.dcache.demand_misses::cpu1.inst 6725309 # number of demand (read+write) misses
1281system.cpu1.dcache.demand_misses::total 6725309 # number of demand (read+write) misses
1282system.cpu1.dcache.overall_misses::cpu1.inst 6725309 # number of overall misses
1283system.cpu1.dcache.overall_misses::total 6725309 # number of overall misses
1284system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 63153941750 # number of ReadReq miss cycles
1285system.cpu1.dcache.ReadReq_miss_latency::total 63153941750 # number of ReadReq miss cycles
1286system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 37295206516 # number of WriteReq miss cycles
1287system.cpu1.dcache.WriteReq_miss_latency::total 37295206516 # number of WriteReq miss cycles
1288system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.inst 9223332559 # number of WriteInvalidateReq miss cycles
1289system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 9223332559 # number of WriteInvalidateReq miss cycles
1290system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 1921743254 # number of LoadLockedReq miss cycles
1291system.cpu1.dcache.LoadLockedReq_miss_latency::total 1921743254 # number of LoadLockedReq miss cycles
1292system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 3886161820 # number of StoreCondReq miss cycles
1293system.cpu1.dcache.StoreCondReq_miss_latency::total 3886161820 # number of StoreCondReq miss cycles
1294system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 3267000 # number of StoreCondFailReq miss cycles
1295system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3267000 # number of StoreCondFailReq miss cycles
1296system.cpu1.dcache.demand_miss_latency::cpu1.inst 100449148266 # number of demand (read+write) miss cycles
1297system.cpu1.dcache.demand_miss_latency::total 100449148266 # number of demand (read+write) miss cycles
1298system.cpu1.dcache.overall_miss_latency::cpu1.inst 100449148266 # number of overall miss cycles
1299system.cpu1.dcache.overall_miss_latency::total 100449148266 # number of overall miss cycles
1300system.cpu1.dcache.ReadReq_accesses::cpu1.inst 91914952 # number of ReadReq accesses(hits+misses)
1301system.cpu1.dcache.ReadReq_accesses::total 91914952 # number of ReadReq accesses(hits+misses)
1302system.cpu1.dcache.WriteReq_accesses::cpu1.inst 79577330 # number of WriteReq accesses(hits+misses)
1303system.cpu1.dcache.WriteReq_accesses::total 79577330 # number of WriteReq accesses(hits+misses)
1304system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.inst 709236 # number of WriteInvalidateReq accesses(hits+misses)
1305system.cpu1.dcache.WriteInvalidateReq_accesses::total 709236 # number of WriteInvalidateReq accesses(hits+misses)
1306system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 2134889 # number of LoadLockedReq accesses(hits+misses)
1307system.cpu1.dcache.LoadLockedReq_accesses::total 2134889 # number of LoadLockedReq accesses(hits+misses)
1308system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 2133381 # number of StoreCondReq accesses(hits+misses)
1309system.cpu1.dcache.StoreCondReq_accesses::total 2133381 # number of StoreCondReq accesses(hits+misses)
1310system.cpu1.dcache.demand_accesses::cpu1.inst 171492282 # number of demand (read+write) accesses
1311system.cpu1.dcache.demand_accesses::total 171492282 # number of demand (read+write) accesses
1312system.cpu1.dcache.overall_accesses::cpu1.inst 171492282 # number of overall (read+write) accesses
1313system.cpu1.dcache.overall_accesses::total 171492282 # number of overall (read+write) accesses
1314system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.047463 # miss rate for ReadReq accesses
1315system.cpu1.dcache.ReadReq_miss_rate::total 0.047463 # miss rate for ReadReq accesses
1316system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.029691 # miss rate for WriteReq accesses
1317system.cpu1.dcache.WriteReq_miss_rate::total 0.029691 # miss rate for WriteReq accesses
1318system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.inst 0.701108 # miss rate for WriteInvalidateReq accesses
1319system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.701108 # miss rate for WriteInvalidateReq accesses
1320system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.065543 # miss rate for LoadLockedReq accesses
1321system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.065543 # miss rate for LoadLockedReq accesses
1322system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.088471 # miss rate for StoreCondReq accesses
1323system.cpu1.dcache.StoreCondReq_miss_rate::total 0.088471 # miss rate for StoreCondReq accesses
1324system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.039216 # miss rate for demand accesses
1325system.cpu1.dcache.demand_miss_rate::total 0.039216 # miss rate for demand accesses
1326system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.039216 # miss rate for overall accesses
1327system.cpu1.dcache.overall_miss_rate::total 0.039216 # miss rate for overall accesses
1328system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14476.309331 # average ReadReq miss latency
1329system.cpu1.dcache.ReadReq_avg_miss_latency::total 14476.309331 # average ReadReq miss latency
1330system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 15784.747315 # average WriteReq miss latency
1331system.cpu1.dcache.WriteReq_avg_miss_latency::total 15784.747315 # average WriteReq miss latency
1332system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 18548.645571 # average WriteInvalidateReq miss latency
1333system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 18548.645571 # average WriteInvalidateReq miss latency
1334system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 13733.898776 # average LoadLockedReq miss latency
1335system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13733.898776 # average LoadLockedReq miss latency
1336system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 20589.809475 # average StoreCondReq miss latency
1337system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20589.809475 # average StoreCondReq miss latency
1338system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
1339system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1340system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency
1341system.cpu1.dcache.demand_avg_miss_latency::total 14935.990044 # average overall miss latency
1342system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14935.990044 # average overall miss latency
1343system.cpu1.dcache.overall_avg_miss_latency::total 14935.990044 # average overall miss latency
1344system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1345system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1346system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1347system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1348system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1349system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1350system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1351system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1352system.cpu1.dcache.writebacks::writebacks 3739270 # number of writebacks
1353system.cpu1.dcache.writebacks::total 3739270 # number of writebacks
1354system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 400087 # number of ReadReq MSHR hits
1355system.cpu1.dcache.ReadReq_mshr_hits::total 400087 # number of ReadReq MSHR hits
1356system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 959724 # number of WriteReq MSHR hits
1357system.cpu1.dcache.WriteReq_mshr_hits::total 959724 # number of WriteReq MSHR hits
1358system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.inst 47 # number of WriteInvalidateReq MSHR hits
1359system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits
1360system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 67 # number of LoadLockedReq MSHR hits
1361system.cpu1.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits
1362system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.inst 75 # number of StoreCondReq MSHR hits
1363system.cpu1.dcache.StoreCondReq_mshr_hits::total 75 # number of StoreCondReq MSHR hits
1364system.cpu1.dcache.demand_mshr_hits::cpu1.inst 1359811 # number of demand (read+write) MSHR hits
1365system.cpu1.dcache.demand_mshr_hits::total 1359811 # number of demand (read+write) MSHR hits
1366system.cpu1.dcache.overall_mshr_hits::cpu1.inst 1359811 # number of overall MSHR hits
1367system.cpu1.dcache.overall_mshr_hits::total 1359811 # number of overall MSHR hits
1368system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 3962485 # number of ReadReq MSHR misses
1369system.cpu1.dcache.ReadReq_mshr_misses::total 3962485 # number of ReadReq MSHR misses
1370system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 1403013 # number of WriteReq MSHR misses
1371system.cpu1.dcache.WriteReq_mshr_misses::total 1403013 # number of WriteReq MSHR misses
1372system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.inst 497204 # number of WriteInvalidateReq MSHR misses
1373system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497204 # number of WriteInvalidateReq MSHR misses
1374system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 139860 # number of LoadLockedReq MSHR misses
1375system.cpu1.dcache.LoadLockedReq_mshr_misses::total 139860 # number of LoadLockedReq MSHR misses
1376system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 188667 # number of StoreCondReq MSHR misses
1377system.cpu1.dcache.StoreCondReq_mshr_misses::total 188667 # number of StoreCondReq MSHR misses
1378system.cpu1.dcache.demand_mshr_misses::cpu1.inst 5365498 # number of demand (read+write) MSHR misses
1379system.cpu1.dcache.demand_mshr_misses::total 5365498 # number of demand (read+write) MSHR misses
1380system.cpu1.dcache.overall_mshr_misses::cpu1.inst 5365498 # number of overall MSHR misses
1381system.cpu1.dcache.overall_mshr_misses::total 5365498 # number of overall MSHR misses
1382system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 49100377691 # number of ReadReq MSHR miss cycles
1383system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49100377691 # number of ReadReq MSHR miss cycles
1384system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 20233474919 # number of WriteReq MSHR miss cycles
1385system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20233474919 # number of WriteReq MSHR miss cycles
1386system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 8220345441 # number of WriteInvalidateReq MSHR miss cycles
1387system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 8220345441 # number of WriteInvalidateReq MSHR miss cycles
1388system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 1640188222 # number of LoadLockedReq MSHR miss cycles
1389system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1640188222 # number of LoadLockedReq MSHR miss cycles
1390system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 3498307132 # number of StoreCondReq MSHR miss cycles
1391system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498307132 # number of StoreCondReq MSHR miss cycles
1392system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 2504000 # number of StoreCondFailReq MSHR miss cycles
1393system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2504000 # number of StoreCondFailReq MSHR miss cycles
1394system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 69333852610 # number of demand (read+write) MSHR miss cycles
1395system.cpu1.dcache.demand_mshr_miss_latency::total 69333852610 # number of demand (read+write) MSHR miss cycles
1396system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 69333852610 # number of overall MSHR miss cycles
1397system.cpu1.dcache.overall_mshr_miss_latency::total 69333852610 # number of overall MSHR miss cycles
1398system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411173732 # number of ReadReq MSHR uncacheable cycles
1399system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3411173732 # number of ReadReq MSHR uncacheable cycles
1400system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 3123925989 # number of WriteReq MSHR uncacheable cycles
1401system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3123925989 # number of WriteReq MSHR uncacheable cycles
1402system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 6535099721 # number of overall MSHR uncacheable cycles
1403system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6535099721 # number of overall MSHR uncacheable cycles
1404system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.043110 # mshr miss rate for ReadReq accesses
1405system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043110 # mshr miss rate for ReadReq accesses
1406system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.017631 # mshr miss rate for WriteReq accesses
1407system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017631 # mshr miss rate for WriteReq accesses
1408system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.701042 # mshr miss rate for WriteInvalidateReq accesses
1409system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.701042 # mshr miss rate for WriteInvalidateReq accesses
1410system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.065512 # mshr miss rate for LoadLockedReq accesses
1411system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065512 # mshr miss rate for LoadLockedReq accesses
1412system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.088436 # mshr miss rate for StoreCondReq accesses
1413system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088436 # mshr miss rate for StoreCondReq accesses
1414system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for demand accesses
1415system.cpu1.dcache.demand_mshr_miss_rate::total 0.031287 # mshr miss rate for demand accesses
1416system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.031287 # mshr miss rate for overall accesses
1417system.cpu1.dcache.overall_mshr_miss_rate::total 0.031287 # mshr miss rate for overall accesses
1418system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12391.309416 # average ReadReq mshr miss latency
1419system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12391.309416 # average ReadReq mshr miss latency
1420system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14421.445075 # average WriteReq mshr miss latency
1421system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14421.445075 # average WriteReq mshr miss latency
1422system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 16533.144225 # average WriteInvalidateReq mshr miss latency
1423system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 16533.144225 # average WriteInvalidateReq mshr miss latency
1424system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 11727.357515 # average LoadLockedReq mshr miss latency
1425system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11727.357515 # average LoadLockedReq mshr miss latency
1426system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 18542.231190 # average StoreCondReq mshr miss latency
1427system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18542.231190 # average StoreCondReq mshr miss latency
1428system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
1429system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1430system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency
1431system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency
1432system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12922.165400 # average overall mshr miss latency
1433system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12922.165400 # average overall mshr miss latency
1434system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1435system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1436system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
1437system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1438system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1439system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1440system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1441system.cpu1.icache.tags.replacements 10003641 # number of replacements
1442system.cpu1.icache.tags.tagsinuse 507.113561 # Cycle average of tags in use
1443system.cpu1.icache.tags.total_refs 252141010 # Total number of references to valid blocks.
1444system.cpu1.icache.tags.sampled_refs 10004153 # Sample count of references to valid blocks.
1445system.cpu1.icache.tags.avg_refs 25.203634 # Average number of references to valid blocks.
1446system.cpu1.icache.tags.warmup_cycle 8364450905000 # Cycle when the warmup percentage was hit.
1447system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.113561 # Average occupied blocks per requestor
1448system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990456 # Average percentage of cache occupancy
1449system.cpu1.icache.tags.occ_percent::total 0.990456 # Average percentage of cache occupancy
1450system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1451system.cpu1.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id
1452system.cpu1.icache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
1453system.cpu1.icache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id
1454system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1455system.cpu1.icache.tags.tag_accesses 534294484 # Number of tag accesses
1456system.cpu1.icache.tags.data_accesses 534294484 # Number of data accesses
1457system.cpu1.icache.ReadReq_hits::cpu1.inst 252141010 # number of ReadReq hits
1458system.cpu1.icache.ReadReq_hits::total 252141010 # number of ReadReq hits
1459system.cpu1.icache.demand_hits::cpu1.inst 252141010 # number of demand (read+write) hits
1460system.cpu1.icache.demand_hits::total 252141010 # number of demand (read+write) hits
1461system.cpu1.icache.overall_hits::cpu1.inst 252141010 # number of overall hits
1462system.cpu1.icache.overall_hits::total 252141010 # number of overall hits
1463system.cpu1.icache.ReadReq_misses::cpu1.inst 10004155 # number of ReadReq misses
1464system.cpu1.icache.ReadReq_misses::total 10004155 # number of ReadReq misses
1465system.cpu1.icache.demand_misses::cpu1.inst 10004155 # number of demand (read+write) misses
1466system.cpu1.icache.demand_misses::total 10004155 # number of demand (read+write) misses
1467system.cpu1.icache.overall_misses::cpu1.inst 10004155 # number of overall misses
1468system.cpu1.icache.overall_misses::total 10004155 # number of overall misses
1469system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 85019530358 # number of ReadReq miss cycles
1470system.cpu1.icache.ReadReq_miss_latency::total 85019530358 # number of ReadReq miss cycles
1471system.cpu1.icache.demand_miss_latency::cpu1.inst 85019530358 # number of demand (read+write) miss cycles
1472system.cpu1.icache.demand_miss_latency::total 85019530358 # number of demand (read+write) miss cycles
1473system.cpu1.icache.overall_miss_latency::cpu1.inst 85019530358 # number of overall miss cycles
1474system.cpu1.icache.overall_miss_latency::total 85019530358 # number of overall miss cycles
1475system.cpu1.icache.ReadReq_accesses::cpu1.inst 262145165 # number of ReadReq accesses(hits+misses)
1476system.cpu1.icache.ReadReq_accesses::total 262145165 # number of ReadReq accesses(hits+misses)
1477system.cpu1.icache.demand_accesses::cpu1.inst 262145165 # number of demand (read+write) accesses
1478system.cpu1.icache.demand_accesses::total 262145165 # number of demand (read+write) accesses
1479system.cpu1.icache.overall_accesses::cpu1.inst 262145165 # number of overall (read+write) accesses
1480system.cpu1.icache.overall_accesses::total 262145165 # number of overall (read+write) accesses
1481system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038163 # miss rate for ReadReq accesses
1482system.cpu1.icache.ReadReq_miss_rate::total 0.038163 # miss rate for ReadReq accesses
1483system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038163 # miss rate for demand accesses
1484system.cpu1.icache.demand_miss_rate::total 0.038163 # miss rate for demand accesses
1485system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038163 # miss rate for overall accesses
1486system.cpu1.icache.overall_miss_rate::total 0.038163 # miss rate for overall accesses
1487system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8498.421941 # average ReadReq miss latency
1488system.cpu1.icache.ReadReq_avg_miss_latency::total 8498.421941 # average ReadReq miss latency
1489system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency
1490system.cpu1.icache.demand_avg_miss_latency::total 8498.421941 # average overall miss latency
1491system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8498.421941 # average overall miss latency
1492system.cpu1.icache.overall_avg_miss_latency::total 8498.421941 # average overall miss latency
1493system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1494system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1495system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1496system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1497system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1498system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1499system.cpu1.icache.fast_writes 0 # number of fast writes performed
1500system.cpu1.icache.cache_copies 0 # number of cache copies performed
1501system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 10004155 # number of ReadReq MSHR misses
1502system.cpu1.icache.ReadReq_mshr_misses::total 10004155 # number of ReadReq MSHR misses
1503system.cpu1.icache.demand_mshr_misses::cpu1.inst 10004155 # number of demand (read+write) MSHR misses
1504system.cpu1.icache.demand_mshr_misses::total 10004155 # number of demand (read+write) MSHR misses
1505system.cpu1.icache.overall_mshr_misses::cpu1.inst 10004155 # number of overall MSHR misses
1506system.cpu1.icache.overall_mshr_misses::total 10004155 # number of overall MSHR misses
1507system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 70001431618 # number of ReadReq MSHR miss cycles
1508system.cpu1.icache.ReadReq_mshr_miss_latency::total 70001431618 # number of ReadReq MSHR miss cycles
1509system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 70001431618 # number of demand (read+write) MSHR miss cycles
1510system.cpu1.icache.demand_mshr_miss_latency::total 70001431618 # number of demand (read+write) MSHR miss cycles
1511system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 70001431618 # number of overall MSHR miss cycles
1512system.cpu1.icache.overall_mshr_miss_latency::total 70001431618 # number of overall MSHR miss cycles
1513system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8751000 # number of ReadReq MSHR uncacheable cycles
1514system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8751000 # number of ReadReq MSHR uncacheable cycles
1515system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8751000 # number of overall MSHR uncacheable cycles
1516system.cpu1.icache.overall_mshr_uncacheable_latency::total 8751000 # number of overall MSHR uncacheable cycles
1517system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for ReadReq accesses
1518system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038163 # mshr miss rate for ReadReq accesses
1519system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for demand accesses
1520system.cpu1.icache.demand_mshr_miss_rate::total 0.038163 # mshr miss rate for demand accesses
1521system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038163 # mshr miss rate for overall accesses
1522system.cpu1.icache.overall_mshr_miss_rate::total 0.038163 # mshr miss rate for overall accesses
1523system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average ReadReq mshr miss latency
1524system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6997.235810 # average ReadReq mshr miss latency
1525system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency
1526system.cpu1.icache.demand_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency
1527system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6997.235810 # average overall mshr miss latency
1528system.cpu1.icache.overall_avg_mshr_miss_latency::total 6997.235810 # average overall mshr miss latency
1529system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1530system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1531system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1532system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1533system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1534system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 91266400 # number of hwpf identified
1535system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2590593 # number of hwpf that were already in mshr
1536system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 83739964 # number of hwpf that were already in the cache
1537system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1124296 # number of hwpf that were already in the prefetch queue
1538system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1539system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 159143 # number of hwpf removed because MSHR allocated
1540system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 3652396 # number of hwpf issued
1541system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 7945944 # number of hwpf spanning a virtual page
1542system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1543system.cpu1.l2cache.tags.replacements 3964575 # number of replacements
1544system.cpu1.l2cache.tags.tagsinuse 13771.716542 # Cycle average of tags in use
1545system.cpu1.l2cache.tags.total_refs 17209014 # Total number of references to valid blocks.
1546system.cpu1.l2cache.tags.sampled_refs 3980703 # Sample count of references to valid blocks.
1547system.cpu1.l2cache.tags.avg_refs 4.323109 # Average number of references to valid blocks.
1548system.cpu1.l2cache.tags.warmup_cycle 9604482251250 # Cycle when the warmup percentage was hit.
1549system.cpu1.l2cache.tags.occ_blocks::writebacks 4186.861890 # Average occupied blocks per requestor
1550system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.243250 # Average occupied blocks per requestor
1551system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.010570 # Average occupied blocks per requestor
1552system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2902.209445 # Average occupied blocks per requestor
1553system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6553.391387 # Average occupied blocks per requestor
1554system.cpu1.l2cache.tags.occ_percent::writebacks 0.255546 # Average percentage of cache occupancy
1555system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004043 # Average percentage of cache occupancy
1556system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003846 # Average percentage of cache occupancy
1557system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.177137 # Average percentage of cache occupancy
1558system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.399987 # Average percentage of cache occupancy
1559system.cpu1.l2cache.tags.occ_percent::total 0.840559 # Average percentage of cache occupancy
1560system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9777 # Occupied blocks per task id
1561system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id
1562system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6309 # Occupied blocks per task id
1563system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 89 # Occupied blocks per task id
1564system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 734 # Occupied blocks per task id
1565system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4083 # Occupied blocks per task id
1566system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 3317 # Occupied blocks per task id
1567system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1554 # Occupied blocks per task id
1568system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1569system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id
1570system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
1571system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
1572system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
1573system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 691 # Occupied blocks per task id
1574system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3097 # Occupied blocks per task id
1575system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1911 # Occupied blocks per task id
1576system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 531 # Occupied blocks per task id
1577system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.596741 # Percentage of cache occupancy per task id
1578system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id
1579system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.385071 # Percentage of cache occupancy per task id
1580system.cpu1.l2cache.tags.tag_accesses 336896441 # Number of tag accesses
1581system.cpu1.l2cache.tags.data_accesses 336896441 # Number of data accesses
1582system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 545727 # number of ReadReq hits
1583system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151675 # number of ReadReq hits
1584system.cpu1.l2cache.ReadReq_hits::cpu1.inst 13043643 # number of ReadReq hits
1585system.cpu1.l2cache.ReadReq_hits::total 13741045 # number of ReadReq hits
1586system.cpu1.l2cache.Writeback_hits::writebacks 3739269 # number of Writeback hits
1587system.cpu1.l2cache.Writeback_hits::total 3739269 # number of Writeback hits
1588system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.inst 314994 # number of WriteInvalidateReq hits
1589system.cpu1.l2cache.WriteInvalidateReq_hits::total 314994 # number of WriteInvalidateReq hits
1590system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 88927 # number of UpgradeReq hits
1591system.cpu1.l2cache.UpgradeReq_hits::total 88927 # number of UpgradeReq hits
1592system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 41659 # number of SCUpgradeReq hits
1593system.cpu1.l2cache.SCUpgradeReq_hits::total 41659 # number of SCUpgradeReq hits
1594system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 944385 # number of ReadExReq hits
1595system.cpu1.l2cache.ReadExReq_hits::total 944385 # number of ReadExReq hits
1596system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 545727 # number of demand (read+write) hits
1597system.cpu1.l2cache.demand_hits::cpu1.itb.walker 151675 # number of demand (read+write) hits
1598system.cpu1.l2cache.demand_hits::cpu1.inst 13988028 # number of demand (read+write) hits
1599system.cpu1.l2cache.demand_hits::total 14685430 # number of demand (read+write) hits
1600system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 545727 # number of overall hits
1601system.cpu1.l2cache.overall_hits::cpu1.itb.walker 151675 # number of overall hits
1602system.cpu1.l2cache.overall_hits::cpu1.inst 13988028 # number of overall hits
1603system.cpu1.l2cache.overall_hits::total 14685430 # number of overall hits
1604system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 14704 # number of ReadReq misses
1605system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10320 # number of ReadReq misses
1606system.cpu1.l2cache.ReadReq_misses::cpu1.inst 1062508 # number of ReadReq misses
1607system.cpu1.l2cache.ReadReq_misses::total 1087532 # number of ReadReq misses
1608system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.inst 180857 # number of WriteInvalidateReq misses
1609system.cpu1.l2cache.WriteInvalidateReq_misses::total 180857 # number of WriteInvalidateReq misses
1610system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 132678 # number of UpgradeReq misses
1611system.cpu1.l2cache.UpgradeReq_misses::total 132678 # number of UpgradeReq misses
1612system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 147002 # number of SCUpgradeReq misses
1613system.cpu1.l2cache.SCUpgradeReq_misses::total 147002 # number of SCUpgradeReq misses
1614system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 6 # number of SCUpgradeFailReq misses
1615system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
1616system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 238730 # number of ReadExReq misses
1617system.cpu1.l2cache.ReadExReq_misses::total 238730 # number of ReadExReq misses
1618system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 14704 # number of demand (read+write) misses
1619system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10320 # number of demand (read+write) misses
1620system.cpu1.l2cache.demand_misses::cpu1.inst 1301238 # number of demand (read+write) misses
1621system.cpu1.l2cache.demand_misses::total 1326262 # number of demand (read+write) misses
1622system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 14704 # number of overall misses
1623system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10320 # number of overall misses
1624system.cpu1.l2cache.overall_misses::cpu1.inst 1301238 # number of overall misses
1625system.cpu1.l2cache.overall_misses::total 1326262 # number of overall misses
1626system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 525735124 # number of ReadReq miss cycles
1627system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 414121710 # number of ReadReq miss cycles
1628system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 33089400106 # number of ReadReq miss cycles
1629system.cpu1.l2cache.ReadReq_miss_latency::total 34029256940 # number of ReadReq miss cycles
1630system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.inst 5173608568 # number of WriteInvalidateReq miss cycles
1631system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 5173608568 # number of WriteInvalidateReq miss cycles
1632system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 2603383383 # number of UpgradeReq miss cycles
1633system.cpu1.l2cache.UpgradeReq_miss_latency::total 2603383383 # number of UpgradeReq miss cycles
1634system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 2990869344 # number of SCUpgradeReq miss cycles
1635system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2990869344 # number of SCUpgradeReq miss cycles
1636system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 2444000 # number of SCUpgradeFailReq miss cycles
1637system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2444000 # number of SCUpgradeFailReq miss cycles
1638system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 9524400999 # number of ReadExReq miss cycles
1639system.cpu1.l2cache.ReadExReq_miss_latency::total 9524400999 # number of ReadExReq miss cycles
1640system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 525735124 # number of demand (read+write) miss cycles
1641system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 414121710 # number of demand (read+write) miss cycles
1642system.cpu1.l2cache.demand_miss_latency::cpu1.inst 42613801105 # number of demand (read+write) miss cycles
1643system.cpu1.l2cache.demand_miss_latency::total 43553657939 # number of demand (read+write) miss cycles
1644system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 525735124 # number of overall miss cycles
1645system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 414121710 # number of overall miss cycles
1646system.cpu1.l2cache.overall_miss_latency::cpu1.inst 42613801105 # number of overall miss cycles
1647system.cpu1.l2cache.overall_miss_latency::total 43553657939 # number of overall miss cycles
1648system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560431 # number of ReadReq accesses(hits+misses)
1649system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 161995 # number of ReadReq accesses(hits+misses)
1650system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 14106151 # number of ReadReq accesses(hits+misses)
1651system.cpu1.l2cache.ReadReq_accesses::total 14828577 # number of ReadReq accesses(hits+misses)
1652system.cpu1.l2cache.Writeback_accesses::writebacks 3739269 # number of Writeback accesses(hits+misses)
1653system.cpu1.l2cache.Writeback_accesses::total 3739269 # number of Writeback accesses(hits+misses)
1654system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.inst 495851 # number of WriteInvalidateReq accesses(hits+misses)
1655system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495851 # number of WriteInvalidateReq accesses(hits+misses)
1656system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 221605 # number of UpgradeReq accesses(hits+misses)
1657system.cpu1.l2cache.UpgradeReq_accesses::total 221605 # number of UpgradeReq accesses(hits+misses)
1658system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 188661 # number of SCUpgradeReq accesses(hits+misses)
1659system.cpu1.l2cache.SCUpgradeReq_accesses::total 188661 # number of SCUpgradeReq accesses(hits+misses)
1660system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 6 # number of SCUpgradeFailReq accesses(hits+misses)
1661system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
1662system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 1183115 # number of ReadExReq accesses(hits+misses)
1663system.cpu1.l2cache.ReadExReq_accesses::total 1183115 # number of ReadExReq accesses(hits+misses)
1664system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560431 # number of demand (read+write) accesses
1665system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 161995 # number of demand (read+write) accesses
1666system.cpu1.l2cache.demand_accesses::cpu1.inst 15289266 # number of demand (read+write) accesses
1667system.cpu1.l2cache.demand_accesses::total 16011692 # number of demand (read+write) accesses
1668system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560431 # number of overall (read+write) accesses
1669system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 161995 # number of overall (read+write) accesses
1670system.cpu1.l2cache.overall_accesses::cpu1.inst 15289266 # number of overall (read+write) accesses
1671system.cpu1.l2cache.overall_accesses::total 16011692 # number of overall (read+write) accesses
1672system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for ReadReq accesses
1673system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.063706 # miss rate for ReadReq accesses
1674system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.075322 # miss rate for ReadReq accesses
1675system.cpu1.l2cache.ReadReq_miss_rate::total 0.073340 # miss rate for ReadReq accesses
1676system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.inst 0.364741 # miss rate for WriteInvalidateReq accesses
1677system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.364741 # miss rate for WriteInvalidateReq accesses
1678system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.598714 # miss rate for UpgradeReq accesses
1679system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.598714 # miss rate for UpgradeReq accesses
1680system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.779186 # miss rate for SCUpgradeReq accesses
1681system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.779186 # miss rate for SCUpgradeReq accesses
1682system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.inst 1 # miss rate for SCUpgradeFailReq accesses
1683system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1684system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.201781 # miss rate for ReadExReq accesses
1685system.cpu1.l2cache.ReadExReq_miss_rate::total 0.201781 # miss rate for ReadExReq accesses
1686system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for demand accesses
1687system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.063706 # miss rate for demand accesses
1688system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085108 # miss rate for demand accesses
1689system.cpu1.l2cache.demand_miss_rate::total 0.082831 # miss rate for demand accesses
1690system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026237 # miss rate for overall accesses
1691system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.063706 # miss rate for overall accesses
1692system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085108 # miss rate for overall accesses
1693system.cpu1.l2cache.overall_miss_rate::total 0.082831 # miss rate for overall accesses
1694system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average ReadReq miss latency
1695system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40128.072674 # average ReadReq miss latency
1696system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31142.730319 # average ReadReq miss latency
1697system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31290.350022 # average ReadReq miss latency
1698system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.inst 28606.073130 # average WriteInvalidateReq miss latency
1699system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 28606.073130 # average WriteInvalidateReq miss latency
1700system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 19621.816601 # average UpgradeReq miss latency
1701system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19621.816601 # average UpgradeReq miss latency
1702system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 20345.773146 # average SCUpgradeReq miss latency
1703system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20345.773146 # average SCUpgradeReq miss latency
1704system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst 407333.333333 # average SCUpgradeFailReq miss latency
1705system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 407333.333333 # average SCUpgradeFailReq miss latency
1706system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 39896.121137 # average ReadExReq miss latency
1707system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39896.121137 # average ReadExReq miss latency
1708system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency
1709system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency
1710system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency
1711system.cpu1.l2cache.demand_avg_miss_latency::total 32839.407251 # average overall miss latency
1712system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35754.565016 # average overall miss latency
1713system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40128.072674 # average overall miss latency
1714system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32748.660203 # average overall miss latency
1715system.cpu1.l2cache.overall_avg_miss_latency::total 32839.407251 # average overall miss latency
1716system.cpu1.l2cache.blocked_cycles::no_mshrs 95890 # number of cycles access was blocked
1717system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1718system.cpu1.l2cache.blocked::no_mshrs 1623 # number of cycles access was blocked
1719system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1720system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 59.081947 # average number of cycles each access was blocked
1721system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1722system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1723system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1724system.cpu1.l2cache.writebacks::writebacks 1340101 # number of writebacks
1725system.cpu1.l2cache.writebacks::total 1340101 # number of writebacks
1726system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
1727system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits
1728system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 83863 # number of ReadReq MSHR hits
1729system.cpu1.l2cache.ReadReq_mshr_hits::total 83867 # number of ReadReq MSHR hits
1730system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.inst 117019 # number of WriteInvalidateReq MSHR hits
1731system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 117019 # number of WriteInvalidateReq MSHR hits
1732system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 10752 # number of ReadExReq MSHR hits
1733system.cpu1.l2cache.ReadExReq_mshr_hits::total 10752 # number of ReadExReq MSHR hits
1734system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
1735system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits
1736system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 94615 # number of demand (read+write) MSHR hits
1737system.cpu1.l2cache.demand_mshr_hits::total 94619 # number of demand (read+write) MSHR hits
1738system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
1739system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits
1740system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 94615 # number of overall MSHR hits
1741system.cpu1.l2cache.overall_mshr_hits::total 94619 # number of overall MSHR hits
1742system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 14703 # number of ReadReq MSHR misses
1743system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10317 # number of ReadReq MSHR misses
1744system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 978645 # number of ReadReq MSHR misses
1745system.cpu1.l2cache.ReadReq_mshr_misses::total 1003665 # number of ReadReq MSHR misses
1746system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of HardPFReq MSHR misses
1747system.cpu1.l2cache.HardPFReq_mshr_misses::total 3652327 # number of HardPFReq MSHR misses
1748system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.inst 63838 # number of WriteInvalidateReq MSHR misses
1749system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 63838 # number of WriteInvalidateReq MSHR misses
1750system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 132678 # number of UpgradeReq MSHR misses
1751system.cpu1.l2cache.UpgradeReq_mshr_misses::total 132678 # number of UpgradeReq MSHR misses
1752system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 147002 # number of SCUpgradeReq MSHR misses
1753system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147002 # number of SCUpgradeReq MSHR misses
1754system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.inst 6 # number of SCUpgradeFailReq MSHR misses
1755system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
1756system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 227978 # number of ReadExReq MSHR misses
1757system.cpu1.l2cache.ReadExReq_mshr_misses::total 227978 # number of ReadExReq MSHR misses
1758system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 14703 # number of demand (read+write) MSHR misses
1759system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10317 # number of demand (read+write) MSHR misses
1760system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 1206623 # number of demand (read+write) MSHR misses
1761system.cpu1.l2cache.demand_mshr_misses::total 1231643 # number of demand (read+write) MSHR misses
1762system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 14703 # number of overall MSHR misses
1763system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10317 # number of overall MSHR misses
1764system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 1206623 # number of overall MSHR misses
1765system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 3652327 # number of overall MSHR misses
1766system.cpu1.l2cache.overall_mshr_misses::total 4883970 # number of overall MSHR misses
1767system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of ReadReq MSHR miss cycles
1768system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 341099282 # number of ReadReq MSHR miss cycles
1769system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 24526546457 # number of ReadReq MSHR miss cycles
1770system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 25289617509 # number of ReadReq MSHR miss cycles
1771system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of HardPFReq MSHR miss cycles
1772system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 110063206845 # number of HardPFReq MSHR miss cycles
1773system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 1132471294 # number of WriteInvalidateReq MSHR miss cycles
1774system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 1132471294 # number of WriteInvalidateReq MSHR miss cycles
1775system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 2172031189 # number of UpgradeReq MSHR miss cycles
1776system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2172031189 # number of UpgradeReq MSHR miss cycles
1777system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 2030926339 # number of SCUpgradeReq MSHR miss cycles
1778system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2030926339 # number of SCUpgradeReq MSHR miss cycles
1779system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 2024000 # number of SCUpgradeFailReq MSHR miss cycles
1780system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2024000 # number of SCUpgradeFailReq MSHR miss cycles
1781system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 6846769063 # number of ReadExReq MSHR miss cycles
1782system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6846769063 # number of ReadExReq MSHR miss cycles
1783system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of demand (read+write) MSHR miss cycles
1784system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 341099282 # number of demand (read+write) MSHR miss cycles
1785system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 31373315520 # number of demand (read+write) MSHR miss cycles
1786system.cpu1.l2cache.demand_mshr_miss_latency::total 32136386572 # number of demand (read+write) MSHR miss cycles
1787system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 421971770 # number of overall MSHR miss cycles
1788system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 341099282 # number of overall MSHR miss cycles
1789system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 31373315520 # number of overall MSHR miss cycles
1790system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 110063206845 # number of overall MSHR miss cycles
1791system.cpu1.l2cache.overall_mshr_miss_latency::total 142199593417 # number of overall MSHR miss cycles
1792system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3254469267 # number of ReadReq MSHR uncacheable cycles
1793system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3254469267 # number of ReadReq MSHR uncacheable cycles
1794system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 2984537511 # number of WriteReq MSHR uncacheable cycles
1795system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2984537511 # number of WriteReq MSHR uncacheable cycles
1796system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6239006778 # number of overall MSHR uncacheable cycles
1797system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6239006778 # number of overall MSHR uncacheable cycles
1798system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for ReadReq accesses
1799system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for ReadReq accesses
1800system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.069377 # mshr miss rate for ReadReq accesses
1801system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.067685 # mshr miss rate for ReadReq accesses
1802system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1803system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1804system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.128744 # mshr miss rate for WriteInvalidateReq accesses
1805system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.128744 # mshr miss rate for WriteInvalidateReq accesses
1806system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.598714 # mshr miss rate for UpgradeReq accesses
1807system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.598714 # mshr miss rate for UpgradeReq accesses
1808system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.779186 # mshr miss rate for SCUpgradeReq accesses
1809system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.779186 # mshr miss rate for SCUpgradeReq accesses
1810system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.inst 1 # mshr miss rate for SCUpgradeFailReq accesses
1811system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1812system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.192693 # mshr miss rate for ReadExReq accesses
1813system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.192693 # mshr miss rate for ReadExReq accesses
1814system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for demand accesses
1815system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for demand accesses
1816system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for demand accesses
1817system.cpu1.l2cache.demand_mshr_miss_rate::total 0.076921 # mshr miss rate for demand accesses
1818system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026235 # mshr miss rate for overall accesses
1819system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.063687 # mshr miss rate for overall accesses
1820system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.078920 # mshr miss rate for overall accesses
1821system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
1822system.cpu1.l2cache.overall_mshr_miss_rate::total 0.305025 # mshr miss rate for overall accesses
1823system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average ReadReq mshr miss latency
1824system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average ReadReq mshr miss latency
1825system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 25061.739913 # average ReadReq mshr miss latency
1826system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25197.269516 # average ReadReq mshr miss latency
1827system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average HardPFReq mshr miss latency
1828system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 30135.091093 # average HardPFReq mshr miss latency
1829system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 17739.767756 # average WriteInvalidateReq mshr miss latency
1830system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 17739.767756 # average WriteInvalidateReq mshr miss latency
1831system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16370.695888 # average UpgradeReq mshr miss latency
1832system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16370.695888 # average UpgradeReq mshr miss latency
1833system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13815.637468 # average SCUpgradeReq mshr miss latency
1834system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13815.637468 # average SCUpgradeReq mshr miss latency
1835system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 337333.333333 # average SCUpgradeFailReq mshr miss latency
1836system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 337333.333333 # average SCUpgradeFailReq mshr miss latency
1837system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30032.586754 # average ReadExReq mshr miss latency
1838system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30032.586754 # average ReadExReq mshr miss latency
1839system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency
1840system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency
1841system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency
1842system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26092.290194 # average overall mshr miss latency
1843system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28699.705502 # average overall mshr miss latency
1844system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33061.867016 # average overall mshr miss latency
1845system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26000.926155 # average overall mshr miss latency
1846system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 30135.091093 # average overall mshr miss latency
1847system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29115.574710 # average overall mshr miss latency
1848system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1849system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1850system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
1851system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1852system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1853system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1854system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1855system.cpu1.toL2Bus.trans_dist::ReadReq 19283354 # Transaction distribution
1856system.cpu1.toL2Bus.trans_dist::ReadResp 15081139 # Transaction distribution
1857system.cpu1.toL2Bus.trans_dist::WriteReq 18583 # Transaction distribution
1858system.cpu1.toL2Bus.trans_dist::WriteResp 18583 # Transaction distribution
1859system.cpu1.toL2Bus.trans_dist::Writeback 3739269 # Transaction distribution
1860system.cpu1.toL2Bus.trans_dist::HardPFReq 5170827 # Transaction distribution
1861system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 625737 # Transaction distribution
1862system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495851 # Transaction distribution
1863system.cpu1.toL2Bus.trans_dist::UpgradeReq 477449 # Transaction distribution
1864system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330499 # Transaction distribution
1865system.cpu1.toL2Bus.trans_dist::UpgradeResp 473092 # Transaction distribution
1866system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
1867system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
1868system.cpu1.toL2Bus.trans_dist::ReadExReq 1314338 # Transaction distribution
1869system.cpu1.toL2Bus.trans_dist::ReadExResp 1188302 # Transaction distribution
1870system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 20008489 # Packet count per connected master and slave (bytes)
1871system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16359278 # Packet count per connected master and slave (bytes)
1872system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 359533 # Packet count per connected master and slave (bytes)
1873system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1226091 # Packet count per connected master and slave (bytes)
1874system.cpu1.toL2Bus.pkt_count::total 37953391 # Packet count per connected master and slave (bytes)
1875system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 640271616 # Cumulative packet size per connected master and slave (bytes)
1876system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 615594373 # Cumulative packet size per connected master and slave (bytes)
1877system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1295960 # Cumulative packet size per connected master and slave (bytes)
1878system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4483448 # Cumulative packet size per connected master and slave (bytes)
1879system.cpu1.toL2Bus.pkt_size::total 1261645397 # Cumulative packet size per connected master and slave (bytes)
1880system.cpu1.toL2Bus.snoops 10423087 # Total snoops (count)
1881system.cpu1.toL2Bus.snoop_fanout::samples 30921485 # Request fanout histogram
1882system.cpu1.toL2Bus.snoop_fanout::mean 5.327379 # Request fanout histogram
1883system.cpu1.toL2Bus.snoop_fanout::stdev 0.469257 # Request fanout histogram
1884system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1885system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1886system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1887system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1888system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1889system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1890system.cpu1.toL2Bus.snoop_fanout::5 20798445 67.26% 67.26% # Request fanout histogram
1891system.cpu1.toL2Bus.snoop_fanout::6 10123040 32.74% 100.00% # Request fanout histogram
1892system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1893system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1894system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1895system.cpu1.toL2Bus.snoop_fanout::total 30921485 # Request fanout histogram
1896system.cpu1.toL2Bus.reqLayer0.occupancy 14664539498 # Layer occupancy (ticks)
1897system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1898system.cpu1.toL2Bus.snoopLayer0.occupancy 176010242 # Layer occupancy (ticks)
1899system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1900system.cpu1.toL2Bus.respLayer0.occupancy 15012316370 # Layer occupancy (ticks)
1901system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1902system.cpu1.toL2Bus.respLayer1.occupancy 8461463125 # Layer occupancy (ticks)
1903system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1904system.cpu1.toL2Bus.respLayer2.occupancy 197959664 # Layer occupancy (ticks)
1905system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1906system.cpu1.toL2Bus.respLayer3.occupancy 666269864 # Layer occupancy (ticks)
1907system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1908system.iobus.trans_dist::ReadReq 40348 # Transaction distribution
1909system.iobus.trans_dist::ReadResp 40348 # Transaction distribution
1910system.iobus.trans_dist::WriteReq 136740 # Transaction distribution
1911system.iobus.trans_dist::WriteResp 30012 # Transaction distribution
1912system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
1913system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48044 # Packet count per connected master and slave (bytes)
1914system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
1915system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
1916system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
1917system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1918system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1919system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1920system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1921system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
1922system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1923system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
1924system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
1925system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
1926system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
1927system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
1928system.iobus.pkt_count_system.bridge.master::total 122926 # Packet count per connected master and slave (bytes)
1929system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231170 # Packet count per connected master and slave (bytes)
1930system.iobus.pkt_count_system.realview.ide.dma::total 231170 # Packet count per connected master and slave (bytes)
1931system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
1932system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
1933system.iobus.pkt_count::total 354176 # Packet count per connected master and slave (bytes)
1934system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48064 # Cumulative packet size per connected master and slave (bytes)
1935system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
1936system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
1937system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
1938system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1939system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1940system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1941system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1942system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
1943system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1944system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
1945system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
1946system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
1947system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
1948system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
1949system.iobus.pkt_size_system.bridge.master::total 156056 # Cumulative packet size per connected master and slave (bytes)
1950system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338696 # Cumulative packet size per connected master and slave (bytes)
1951system.iobus.pkt_size_system.realview.ide.dma::total 7338696 # Cumulative packet size per connected master and slave (bytes)
1952system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
1953system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
1954system.iobus.pkt_size::total 7496838 # Cumulative packet size per connected master and slave (bytes)
1955system.iobus.reqLayer0.occupancy 36517000 # Layer occupancy (ticks)
1956system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1957system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
1958system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1959system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
1960system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1961system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
1962system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1963system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1964system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1965system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1966system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1967system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
1968system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1969system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1970system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1971system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
1972system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1973system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1974system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1975system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
1976system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1977system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
1978system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
1979system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
1980system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
1981system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
1982system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
1983system.iobus.reqLayer27.occupancy 1042881499 # Layer occupancy (ticks)
1984system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
1985system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
1986system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
1987system.iobus.respLayer0.occupancy 92917000 # Layer occupancy (ticks)
1988system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
1989system.iobus.respLayer3.occupancy 179159841 # Layer occupancy (ticks)
1990system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1991system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
1992system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
1993system.iocache.tags.replacements 115566 # number of replacements
1994system.iocache.tags.tagsinuse 11.298842 # Cycle average of tags in use
1995system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
1996system.iocache.tags.sampled_refs 115582 # Sample count of references to valid blocks.
1997system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
1998system.iocache.tags.warmup_cycle 9120788284000 # Cycle when the warmup percentage was hit.
1999system.iocache.tags.occ_blocks::realview.ethernet 3.841658 # Average occupied blocks per requestor
2000system.iocache.tags.occ_blocks::realview.ide 7.457184 # Average occupied blocks per requestor
2001system.iocache.tags.occ_percent::realview.ethernet 0.240104 # Average percentage of cache occupancy
2002system.iocache.tags.occ_percent::realview.ide 0.466074 # Average percentage of cache occupancy
2003system.iocache.tags.occ_percent::total 0.706178 # Average percentage of cache occupancy
2004system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2005system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2006system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2007system.iocache.tags.tag_accesses 1040622 # Number of tag accesses
2008system.iocache.tags.data_accesses 1040622 # Number of data accesses
2009system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2010system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses
2011system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses
2012system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2013system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2014system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2015system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2016system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2017system.iocache.demand_misses::realview.ide 8857 # number of demand (read+write) misses
2018system.iocache.demand_misses::total 8897 # number of demand (read+write) misses
2019system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2020system.iocache.overall_misses::realview.ide 8857 # number of overall misses
2021system.iocache.overall_misses::total 8897 # number of overall misses
2022system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles
2023system.iocache.ReadReq_miss_latency::realview.ide 1971462847 # number of ReadReq miss cycles
2024system.iocache.ReadReq_miss_latency::total 1977169847 # number of ReadReq miss cycles
2025system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles
2026system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles
2027system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28907198811 # number of WriteInvalidateReq miss cycles
2028system.iocache.WriteInvalidateReq_miss_latency::total 28907198811 # number of WriteInvalidateReq miss cycles
2029system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles
2030system.iocache.demand_miss_latency::realview.ide 1971462847 # number of demand (read+write) miss cycles
2031system.iocache.demand_miss_latency::total 1977526847 # number of demand (read+write) miss cycles
2032system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles
2033system.iocache.overall_miss_latency::realview.ide 1971462847 # number of overall miss cycles
2034system.iocache.overall_miss_latency::total 1977526847 # number of overall miss cycles
2035system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2036system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses)
2037system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses)
2038system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2039system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2040system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
2041system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
2042system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2043system.iocache.demand_accesses::realview.ide 8857 # number of demand (read+write) accesses
2044system.iocache.demand_accesses::total 8897 # number of demand (read+write) accesses
2045system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2046system.iocache.overall_accesses::realview.ide 8857 # number of overall (read+write) accesses
2047system.iocache.overall_accesses::total 8897 # number of overall (read+write) accesses
2048system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2049system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2050system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2051system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2052system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2053system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2054system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2055system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2056system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2057system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2058system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2059system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2060system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2061system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency
2062system.iocache.ReadReq_avg_miss_latency::realview.ide 222588.105115 # average ReadReq miss latency
2063system.iocache.ReadReq_avg_miss_latency::total 222303.783112 # average ReadReq miss latency
2064system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency
2065system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency
2066system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270849.250534 # average WriteInvalidateReq miss latency
2067system.iocache.WriteInvalidateReq_avg_miss_latency::total 270849.250534 # average WriteInvalidateReq miss latency
2068system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency
2069system.iocache.demand_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency
2070system.iocache.demand_avg_miss_latency::total 222268.949871 # average overall miss latency
2071system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency
2072system.iocache.overall_avg_miss_latency::realview.ide 222588.105115 # average overall miss latency
2073system.iocache.overall_avg_miss_latency::total 222268.949871 # average overall miss latency
2074system.iocache.blocked_cycles::no_mshrs 228015 # number of cycles access was blocked
2075system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2076system.iocache.blocked::no_mshrs 27566 # number of cycles access was blocked
2077system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2078system.iocache.avg_blocked_cycles::no_mshrs 8.271603 # average number of cycles each access was blocked
2079system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2080system.iocache.fast_writes 0 # number of fast writes performed
2081system.iocache.cache_copies 0 # number of cache copies performed
2082system.iocache.writebacks::writebacks 106694 # number of writebacks
2083system.iocache.writebacks::total 106694 # number of writebacks
2084system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2085system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses
2086system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses
2087system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2088system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2089system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
2090system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
2091system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2092system.iocache.demand_mshr_misses::realview.ide 8857 # number of demand (read+write) MSHR misses
2093system.iocache.demand_mshr_misses::total 8897 # number of demand (read+write) MSHR misses
2094system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2095system.iocache.overall_mshr_misses::realview.ide 8857 # number of overall MSHR misses
2096system.iocache.overall_mshr_misses::total 8897 # number of overall MSHR misses
2097system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles
2098system.iocache.ReadReq_mshr_miss_latency::realview.ide 1510755865 # number of ReadReq MSHR miss cycles
2099system.iocache.ReadReq_mshr_miss_latency::total 1514538865 # number of ReadReq MSHR miss cycles
2100system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
2101system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
2102system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23356679475 # number of WriteInvalidateReq MSHR miss cycles
2103system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23356679475 # number of WriteInvalidateReq MSHR miss cycles
2104system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles
2105system.iocache.demand_mshr_miss_latency::realview.ide 1510755865 # number of demand (read+write) MSHR miss cycles
2106system.iocache.demand_mshr_miss_latency::total 1514739865 # number of demand (read+write) MSHR miss cycles
2107system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles
2108system.iocache.overall_mshr_miss_latency::realview.ide 1510755865 # number of overall MSHR miss cycles
2109system.iocache.overall_mshr_miss_latency::total 1514739865 # number of overall MSHR miss cycles
2110system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2111system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2112system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2113system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2114system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2115system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2116system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2117system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2118system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2119system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2120system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2121system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2122system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2123system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency
2124system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170571.961725 # average ReadReq mshr miss latency
2125system.iocache.ReadReq_avg_mshr_miss_latency::total 170287.706881 # average ReadReq mshr miss latency
2126system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
2127system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
2128system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218843.035333 # average WriteInvalidateReq mshr miss latency
2129system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218843.035333 # average WriteInvalidateReq mshr miss latency
2130system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
2131system.iocache.demand_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency
2132system.iocache.demand_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency
2133system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
2134system.iocache.overall_avg_mshr_miss_latency::realview.ide 170571.961725 # average overall mshr miss latency
2135system.iocache.overall_avg_mshr_miss_latency::total 170252.879060 # average overall mshr miss latency
2136system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2137system.l2c.tags.replacements 1797599 # number of replacements
2138system.l2c.tags.tagsinuse 64905.725288 # Cycle average of tags in use
2139system.l2c.tags.total_refs 8591301 # Total number of references to valid blocks.
2140system.l2c.tags.sampled_refs 1860596 # Sample count of references to valid blocks.
2141system.l2c.tags.avg_refs 4.617499 # Average number of references to valid blocks.
2142system.l2c.tags.warmup_cycle 6896032000 # Cycle when the warmup percentage was hit.
2143system.l2c.tags.occ_blocks::writebacks 7600.616161 # Average occupied blocks per requestor
2144system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.639535 # Average occupied blocks per requestor
2145system.l2c.tags.occ_blocks::cpu0.itb.walker 9.409863 # Average occupied blocks per requestor
2146system.l2c.tags.occ_blocks::cpu0.inst 1890.006249 # Average occupied blocks per requestor
2147system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16961.129535 # Average occupied blocks per requestor
2148system.l2c.tags.occ_blocks::cpu1.dtb.walker 324.497512 # Average occupied blocks per requestor
2149system.l2c.tags.occ_blocks::cpu1.itb.walker 441.216776 # Average occupied blocks per requestor
2150system.l2c.tags.occ_blocks::cpu1.inst 10554.786238 # Average occupied blocks per requestor
2151system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 27107.423418 # Average occupied blocks per requestor
2152system.l2c.tags.occ_percent::writebacks 0.115976 # Average percentage of cache occupancy
2153system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000254 # Average percentage of cache occupancy
2154system.l2c.tags.occ_percent::cpu0.itb.walker 0.000144 # Average percentage of cache occupancy
2155system.l2c.tags.occ_percent::cpu0.inst 0.028839 # Average percentage of cache occupancy
2156system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.258806 # Average percentage of cache occupancy
2157system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004951 # Average percentage of cache occupancy
2158system.l2c.tags.occ_percent::cpu1.itb.walker 0.006732 # Average percentage of cache occupancy
2159system.l2c.tags.occ_percent::cpu1.inst 0.161053 # Average percentage of cache occupancy
2160system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.413626 # Average percentage of cache occupancy
2161system.l2c.tags.occ_percent::total 0.990383 # Average percentage of cache occupancy
2162system.l2c.tags.occ_task_id_blocks::1022 43530 # Occupied blocks per task id
2163system.l2c.tags.occ_task_id_blocks::1023 179 # Occupied blocks per task id
2164system.l2c.tags.occ_task_id_blocks::1024 19288 # Occupied blocks per task id
2165system.l2c.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
2166system.l2c.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id
2167system.l2c.tags.age_task_id_blocks_1022::2 1656 # Occupied blocks per task id
2168system.l2c.tags.age_task_id_blocks_1022::3 6242 # Occupied blocks per task id
2169system.l2c.tags.age_task_id_blocks_1022::4 35370 # Occupied blocks per task id
2170system.l2c.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
2171system.l2c.tags.age_task_id_blocks_1023::4 173 # Occupied blocks per task id
2172system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
2173system.l2c.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
2174system.l2c.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id
2175system.l2c.tags.age_task_id_blocks_1024::3 1730 # Occupied blocks per task id
2176system.l2c.tags.age_task_id_blocks_1024::4 16555 # Occupied blocks per task id
2177system.l2c.tags.occ_task_id_percent::1022 0.664215 # Percentage of cache occupancy per task id
2178system.l2c.tags.occ_task_id_percent::1023 0.002731 # Percentage of cache occupancy per task id
2179system.l2c.tags.occ_task_id_percent::1024 0.294312 # Percentage of cache occupancy per task id
2180system.l2c.tags.tag_accesses 89688959 # Number of tag accesses
2181system.l2c.tags.data_accesses 89688959 # Number of data accesses
2182system.l2c.ReadReq_hits::cpu0.dtb.walker 8987 # number of ReadReq hits
2183system.l2c.ReadReq_hits::cpu0.itb.walker 6604 # number of ReadReq hits
2184system.l2c.ReadReq_hits::cpu0.inst 578381 # number of ReadReq hits
2185system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 2301852 # number of ReadReq hits
2186system.l2c.ReadReq_hits::cpu1.dtb.walker 8168 # number of ReadReq hits
2187system.l2c.ReadReq_hits::cpu1.itb.walker 5333 # number of ReadReq hits
2188system.l2c.ReadReq_hits::cpu1.inst 630016 # number of ReadReq hits
2189system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 2353942 # number of ReadReq hits
2190system.l2c.ReadReq_hits::total 5893283 # number of ReadReq hits
2191system.l2c.Writeback_hits::writebacks 2942617 # number of Writeback hits
2192system.l2c.Writeback_hits::total 2942617 # number of Writeback hits
2193system.l2c.WriteInvalidateReq_hits::cpu0.inst 6235 # number of WriteInvalidateReq hits
2194system.l2c.WriteInvalidateReq_hits::cpu1.inst 6750 # number of WriteInvalidateReq hits
2195system.l2c.WriteInvalidateReq_hits::total 12985 # number of WriteInvalidateReq hits
2196system.l2c.UpgradeReq_hits::cpu0.inst 39044 # number of UpgradeReq hits
2197system.l2c.UpgradeReq_hits::cpu1.inst 35229 # number of UpgradeReq hits
2198system.l2c.UpgradeReq_hits::total 74273 # number of UpgradeReq hits
2199system.l2c.SCUpgradeReq_hits::cpu0.inst 7514 # number of SCUpgradeReq hits
2200system.l2c.SCUpgradeReq_hits::cpu1.inst 7779 # number of SCUpgradeReq hits
2201system.l2c.SCUpgradeReq_hits::total 15293 # number of SCUpgradeReq hits
2202system.l2c.ReadExReq_hits::cpu0.inst 64131 # number of ReadExReq hits
2203system.l2c.ReadExReq_hits::cpu1.inst 55187 # number of ReadExReq hits
2204system.l2c.ReadExReq_hits::total 119318 # number of ReadExReq hits
2205system.l2c.demand_hits::cpu0.dtb.walker 8987 # number of demand (read+write) hits
2206system.l2c.demand_hits::cpu0.itb.walker 6604 # number of demand (read+write) hits
2207system.l2c.demand_hits::cpu0.inst 642512 # number of demand (read+write) hits
2208system.l2c.demand_hits::cpu0.l2cache.prefetcher 2301852 # number of demand (read+write) hits
2209system.l2c.demand_hits::cpu1.dtb.walker 8168 # number of demand (read+write) hits
2210system.l2c.demand_hits::cpu1.itb.walker 5333 # number of demand (read+write) hits
2211system.l2c.demand_hits::cpu1.inst 685203 # number of demand (read+write) hits
2212system.l2c.demand_hits::cpu1.l2cache.prefetcher 2353942 # number of demand (read+write) hits
2213system.l2c.demand_hits::total 6012601 # number of demand (read+write) hits
2214system.l2c.overall_hits::cpu0.dtb.walker 8987 # number of overall hits
2215system.l2c.overall_hits::cpu0.itb.walker 6604 # number of overall hits
2216system.l2c.overall_hits::cpu0.inst 642512 # number of overall hits
2217system.l2c.overall_hits::cpu0.l2cache.prefetcher 2301852 # number of overall hits
2218system.l2c.overall_hits::cpu1.dtb.walker 8168 # number of overall hits
2219system.l2c.overall_hits::cpu1.itb.walker 5333 # number of overall hits
2220system.l2c.overall_hits::cpu1.inst 685203 # number of overall hits
2221system.l2c.overall_hits::cpu1.l2cache.prefetcher 2353942 # number of overall hits
2222system.l2c.overall_hits::total 6012601 # number of overall hits
2223system.l2c.ReadReq_misses::cpu0.dtb.walker 1978 # number of ReadReq misses
2224system.l2c.ReadReq_misses::cpu0.itb.walker 1693 # number of ReadReq misses
2225system.l2c.ReadReq_misses::cpu0.inst 95514 # number of ReadReq misses
2226system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 863521 # number of ReadReq misses
2227system.l2c.ReadReq_misses::cpu1.dtb.walker 2685 # number of ReadReq misses
2228system.l2c.ReadReq_misses::cpu1.itb.walker 2512 # number of ReadReq misses
2229system.l2c.ReadReq_misses::cpu1.inst 131326 # number of ReadReq misses
2230system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 566480 # number of ReadReq misses
2231system.l2c.ReadReq_misses::total 1665709 # number of ReadReq misses
2232system.l2c.WriteInvalidateReq_misses::cpu0.inst 16918 # number of WriteInvalidateReq misses
2233system.l2c.WriteInvalidateReq_misses::cpu1.inst 7174 # number of WriteInvalidateReq misses
2234system.l2c.WriteInvalidateReq_misses::total 24092 # number of WriteInvalidateReq misses
2235system.l2c.UpgradeReq_misses::cpu0.inst 36442 # number of UpgradeReq misses
2236system.l2c.UpgradeReq_misses::cpu1.inst 33251 # number of UpgradeReq misses
2237system.l2c.UpgradeReq_misses::total 69693 # number of UpgradeReq misses
2238system.l2c.SCUpgradeReq_misses::cpu0.inst 9494 # number of SCUpgradeReq misses
2239system.l2c.SCUpgradeReq_misses::cpu1.inst 9010 # number of SCUpgradeReq misses
2240system.l2c.SCUpgradeReq_misses::total 18504 # number of SCUpgradeReq misses
2241system.l2c.ReadExReq_misses::cpu0.inst 45340 # number of ReadExReq misses
2242system.l2c.ReadExReq_misses::cpu1.inst 52041 # number of ReadExReq misses
2243system.l2c.ReadExReq_misses::total 97381 # number of ReadExReq misses
2244system.l2c.demand_misses::cpu0.dtb.walker 1978 # number of demand (read+write) misses
2245system.l2c.demand_misses::cpu0.itb.walker 1693 # number of demand (read+write) misses
2246system.l2c.demand_misses::cpu0.inst 140854 # number of demand (read+write) misses
2247system.l2c.demand_misses::cpu0.l2cache.prefetcher 863521 # number of demand (read+write) misses
2248system.l2c.demand_misses::cpu1.dtb.walker 2685 # number of demand (read+write) misses
2249system.l2c.demand_misses::cpu1.itb.walker 2512 # number of demand (read+write) misses
2250system.l2c.demand_misses::cpu1.inst 183367 # number of demand (read+write) misses
2251system.l2c.demand_misses::cpu1.l2cache.prefetcher 566480 # number of demand (read+write) misses
2252system.l2c.demand_misses::total 1763090 # number of demand (read+write) misses
2253system.l2c.overall_misses::cpu0.dtb.walker 1978 # number of overall misses
2254system.l2c.overall_misses::cpu0.itb.walker 1693 # number of overall misses
2255system.l2c.overall_misses::cpu0.inst 140854 # number of overall misses
2256system.l2c.overall_misses::cpu0.l2cache.prefetcher 863521 # number of overall misses
2257system.l2c.overall_misses::cpu1.dtb.walker 2685 # number of overall misses
2258system.l2c.overall_misses::cpu1.itb.walker 2512 # number of overall misses
2259system.l2c.overall_misses::cpu1.inst 183367 # number of overall misses
2260system.l2c.overall_misses::cpu1.l2cache.prefetcher 566480 # number of overall misses
2261system.l2c.overall_misses::total 1763090 # number of overall misses
2262system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 165226748 # number of ReadReq miss cycles
2263system.l2c.ReadReq_miss_latency::cpu0.itb.walker 144557248 # number of ReadReq miss cycles
2264system.l2c.ReadReq_miss_latency::cpu0.inst 7974806913 # number of ReadReq miss cycles
2265system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of ReadReq miss cycles
2266system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 222345248 # number of ReadReq miss cycles
2267system.l2c.ReadReq_miss_latency::cpu1.itb.walker 209364000 # number of ReadReq miss cycles
2268system.l2c.ReadReq_miss_latency::cpu1.inst 10644136699 # number of ReadReq miss cycles
2269system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of ReadReq miss cycles
2270system.l2c.ReadReq_miss_latency::total 220050587910 # number of ReadReq miss cycles
2271system.l2c.WriteInvalidateReq_miss_latency::cpu0.inst 3639850 # number of WriteInvalidateReq miss cycles
2272system.l2c.WriteInvalidateReq_miss_latency::cpu1.inst 3440357 # number of WriteInvalidateReq miss cycles
2273system.l2c.WriteInvalidateReq_miss_latency::total 7080207 # number of WriteInvalidateReq miss cycles
2274system.l2c.UpgradeReq_miss_latency::cpu0.inst 167282107 # number of UpgradeReq miss cycles
2275system.l2c.UpgradeReq_miss_latency::cpu1.inst 155790979 # number of UpgradeReq miss cycles
2276system.l2c.UpgradeReq_miss_latency::total 323073086 # number of UpgradeReq miss cycles
2277system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 53447323 # number of SCUpgradeReq miss cycles
2278system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 50683879 # number of SCUpgradeReq miss cycles
2279system.l2c.SCUpgradeReq_miss_latency::total 104131202 # number of SCUpgradeReq miss cycles
2280system.l2c.ReadExReq_miss_latency::cpu0.inst 3468272337 # number of ReadExReq miss cycles
2281system.l2c.ReadExReq_miss_latency::cpu1.inst 3934530582 # number of ReadExReq miss cycles
2282system.l2c.ReadExReq_miss_latency::total 7402802919 # number of ReadExReq miss cycles
2283system.l2c.demand_miss_latency::cpu0.dtb.walker 165226748 # number of demand (read+write) miss cycles
2284system.l2c.demand_miss_latency::cpu0.itb.walker 144557248 # number of demand (read+write) miss cycles
2285system.l2c.demand_miss_latency::cpu0.inst 11443079250 # number of demand (read+write) miss cycles
2286system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of demand (read+write) miss cycles
2287system.l2c.demand_miss_latency::cpu1.dtb.walker 222345248 # number of demand (read+write) miss cycles
2288system.l2c.demand_miss_latency::cpu1.itb.walker 209364000 # number of demand (read+write) miss cycles
2289system.l2c.demand_miss_latency::cpu1.inst 14578667281 # number of demand (read+write) miss cycles
2290system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of demand (read+write) miss cycles
2291system.l2c.demand_miss_latency::total 227453390829 # number of demand (read+write) miss cycles
2292system.l2c.overall_miss_latency::cpu0.dtb.walker 165226748 # number of overall miss cycles
2293system.l2c.overall_miss_latency::cpu0.itb.walker 144557248 # number of overall miss cycles
2294system.l2c.overall_miss_latency::cpu0.inst 11443079250 # number of overall miss cycles
2295system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 129814567894 # number of overall miss cycles
2296system.l2c.overall_miss_latency::cpu1.dtb.walker 222345248 # number of overall miss cycles
2297system.l2c.overall_miss_latency::cpu1.itb.walker 209364000 # number of overall miss cycles
2298system.l2c.overall_miss_latency::cpu1.inst 14578667281 # number of overall miss cycles
2299system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 70875583160 # number of overall miss cycles
2300system.l2c.overall_miss_latency::total 227453390829 # number of overall miss cycles
2301system.l2c.ReadReq_accesses::cpu0.dtb.walker 10965 # number of ReadReq accesses(hits+misses)
2302system.l2c.ReadReq_accesses::cpu0.itb.walker 8297 # number of ReadReq accesses(hits+misses)
2303system.l2c.ReadReq_accesses::cpu0.inst 673895 # number of ReadReq accesses(hits+misses)
2304system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 3165373 # number of ReadReq accesses(hits+misses)
2305system.l2c.ReadReq_accesses::cpu1.dtb.walker 10853 # number of ReadReq accesses(hits+misses)
2306system.l2c.ReadReq_accesses::cpu1.itb.walker 7845 # number of ReadReq accesses(hits+misses)
2307system.l2c.ReadReq_accesses::cpu1.inst 761342 # number of ReadReq accesses(hits+misses)
2308system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2920422 # number of ReadReq accesses(hits+misses)
2309system.l2c.ReadReq_accesses::total 7558992 # number of ReadReq accesses(hits+misses)
2310system.l2c.Writeback_accesses::writebacks 2942617 # number of Writeback accesses(hits+misses)
2311system.l2c.Writeback_accesses::total 2942617 # number of Writeback accesses(hits+misses)
2312system.l2c.WriteInvalidateReq_accesses::cpu0.inst 23153 # number of WriteInvalidateReq accesses(hits+misses)
2313system.l2c.WriteInvalidateReq_accesses::cpu1.inst 13924 # number of WriteInvalidateReq accesses(hits+misses)
2314system.l2c.WriteInvalidateReq_accesses::total 37077 # number of WriteInvalidateReq accesses(hits+misses)
2315system.l2c.UpgradeReq_accesses::cpu0.inst 75486 # number of UpgradeReq accesses(hits+misses)
2316system.l2c.UpgradeReq_accesses::cpu1.inst 68480 # number of UpgradeReq accesses(hits+misses)
2317system.l2c.UpgradeReq_accesses::total 143966 # number of UpgradeReq accesses(hits+misses)
2318system.l2c.SCUpgradeReq_accesses::cpu0.inst 17008 # number of SCUpgradeReq accesses(hits+misses)
2319system.l2c.SCUpgradeReq_accesses::cpu1.inst 16789 # number of SCUpgradeReq accesses(hits+misses)
2320system.l2c.SCUpgradeReq_accesses::total 33797 # number of SCUpgradeReq accesses(hits+misses)
2321system.l2c.ReadExReq_accesses::cpu0.inst 109471 # number of ReadExReq accesses(hits+misses)
2322system.l2c.ReadExReq_accesses::cpu1.inst 107228 # number of ReadExReq accesses(hits+misses)
2323system.l2c.ReadExReq_accesses::total 216699 # number of ReadExReq accesses(hits+misses)
2324system.l2c.demand_accesses::cpu0.dtb.walker 10965 # number of demand (read+write) accesses
2325system.l2c.demand_accesses::cpu0.itb.walker 8297 # number of demand (read+write) accesses
2326system.l2c.demand_accesses::cpu0.inst 783366 # number of demand (read+write) accesses
2327system.l2c.demand_accesses::cpu0.l2cache.prefetcher 3165373 # number of demand (read+write) accesses
2328system.l2c.demand_accesses::cpu1.dtb.walker 10853 # number of demand (read+write) accesses
2329system.l2c.demand_accesses::cpu1.itb.walker 7845 # number of demand (read+write) accesses
2330system.l2c.demand_accesses::cpu1.inst 868570 # number of demand (read+write) accesses
2331system.l2c.demand_accesses::cpu1.l2cache.prefetcher 2920422 # number of demand (read+write) accesses
2332system.l2c.demand_accesses::total 7775691 # number of demand (read+write) accesses
2333system.l2c.overall_accesses::cpu0.dtb.walker 10965 # number of overall (read+write) accesses
2334system.l2c.overall_accesses::cpu0.itb.walker 8297 # number of overall (read+write) accesses
2335system.l2c.overall_accesses::cpu0.inst 783366 # number of overall (read+write) accesses
2336system.l2c.overall_accesses::cpu0.l2cache.prefetcher 3165373 # number of overall (read+write) accesses
2337system.l2c.overall_accesses::cpu1.dtb.walker 10853 # number of overall (read+write) accesses
2338system.l2c.overall_accesses::cpu1.itb.walker 7845 # number of overall (read+write) accesses
2339system.l2c.overall_accesses::cpu1.inst 868570 # number of overall (read+write) accesses
2340system.l2c.overall_accesses::cpu1.l2cache.prefetcher 2920422 # number of overall (read+write) accesses
2341system.l2c.overall_accesses::total 7775691 # number of overall (read+write) accesses
2342system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for ReadReq accesses
2343system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.204050 # miss rate for ReadReq accesses
2344system.l2c.ReadReq_miss_rate::cpu0.inst 0.141734 # miss rate for ReadReq accesses
2345system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for ReadReq accesses
2346system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for ReadReq accesses
2347system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.320204 # miss rate for ReadReq accesses
2348system.l2c.ReadReq_miss_rate::cpu1.inst 0.172493 # miss rate for ReadReq accesses
2349system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for ReadReq accesses
2350system.l2c.ReadReq_miss_rate::total 0.220361 # miss rate for ReadReq accesses
2351system.l2c.WriteInvalidateReq_miss_rate::cpu0.inst 0.730704 # miss rate for WriteInvalidateReq accesses
2352system.l2c.WriteInvalidateReq_miss_rate::cpu1.inst 0.515226 # miss rate for WriteInvalidateReq accesses
2353system.l2c.WriteInvalidateReq_miss_rate::total 0.649783 # miss rate for WriteInvalidateReq accesses
2354system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.482765 # miss rate for UpgradeReq accesses
2355system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.485558 # miss rate for UpgradeReq accesses
2356system.l2c.UpgradeReq_miss_rate::total 0.484093 # miss rate for UpgradeReq accesses
2357system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.558208 # miss rate for SCUpgradeReq accesses
2358system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.536661 # miss rate for SCUpgradeReq accesses
2359system.l2c.SCUpgradeReq_miss_rate::total 0.547504 # miss rate for SCUpgradeReq accesses
2360system.l2c.ReadExReq_miss_rate::cpu0.inst 0.414174 # miss rate for ReadExReq accesses
2361system.l2c.ReadExReq_miss_rate::cpu1.inst 0.485330 # miss rate for ReadExReq accesses
2362system.l2c.ReadExReq_miss_rate::total 0.449384 # miss rate for ReadExReq accesses
2363system.l2c.demand_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for demand accesses
2364system.l2c.demand_miss_rate::cpu0.itb.walker 0.204050 # miss rate for demand accesses
2365system.l2c.demand_miss_rate::cpu0.inst 0.179806 # miss rate for demand accesses
2366system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for demand accesses
2367system.l2c.demand_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for demand accesses
2368system.l2c.demand_miss_rate::cpu1.itb.walker 0.320204 # miss rate for demand accesses
2369system.l2c.demand_miss_rate::cpu1.inst 0.211114 # miss rate for demand accesses
2370system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for demand accesses
2371system.l2c.demand_miss_rate::total 0.226744 # miss rate for demand accesses
2372system.l2c.overall_miss_rate::cpu0.dtb.walker 0.180392 # miss rate for overall accesses
2373system.l2c.overall_miss_rate::cpu0.itb.walker 0.204050 # miss rate for overall accesses
2374system.l2c.overall_miss_rate::cpu0.inst 0.179806 # miss rate for overall accesses
2375system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.272802 # miss rate for overall accesses
2376system.l2c.overall_miss_rate::cpu1.dtb.walker 0.247397 # miss rate for overall accesses
2377system.l2c.overall_miss_rate::cpu1.itb.walker 0.320204 # miss rate for overall accesses
2378system.l2c.overall_miss_rate::cpu1.inst 0.211114 # miss rate for overall accesses
2379system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.193972 # miss rate for overall accesses
2380system.l2c.overall_miss_rate::total 0.226744 # miss rate for overall accesses
2381system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average ReadReq miss latency
2382system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85385.261666 # average ReadReq miss latency
2383system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83493.591651 # average ReadReq miss latency
2384system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average ReadReq miss latency
2385system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average ReadReq miss latency
2386system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83345.541401 # average ReadReq miss latency
2387system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81051.251839 # average ReadReq miss latency
2388system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average ReadReq miss latency
2389system.l2c.ReadReq_avg_miss_latency::total 132106.261004 # average ReadReq miss latency
2390system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.inst 215.146589 # average WriteInvalidateReq miss latency
2391system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.inst 479.559102 # average WriteInvalidateReq miss latency
2392system.l2c.WriteInvalidateReq_avg_miss_latency::total 293.882077 # average WriteInvalidateReq miss latency
2393system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 4590.365704 # average UpgradeReq miss latency
2394system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 4685.302066 # average UpgradeReq miss latency
2395system.l2c.UpgradeReq_avg_miss_latency::total 4635.660482 # average UpgradeReq miss latency
2396system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 5629.589530 # average SCUpgradeReq miss latency
2397system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 5625.291787 # average SCUpgradeReq miss latency
2398system.l2c.SCUpgradeReq_avg_miss_latency::total 5627.496866 # average SCUpgradeReq miss latency
2399system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 76494.758205 # average ReadExReq miss latency
2400system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 75604.438462 # average ReadExReq miss latency
2401system.l2c.ReadExReq_avg_miss_latency::total 76018.965907 # average ReadExReq miss latency
2402system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency
2403system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency
2404system.l2c.demand_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency
2405system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency
2406system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency
2407system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency
2408system.l2c.demand_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency
2409system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency
2410system.l2c.demand_avg_miss_latency::total 129008.383480 # average overall miss latency
2411system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83532.228514 # average overall miss latency
2412system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85385.261666 # average overall miss latency
2413system.l2c.overall_avg_miss_latency::cpu0.inst 81240.712014 # average overall miss latency
2414system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 150331.686078 # average overall miss latency
2415system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82810.148231 # average overall miss latency
2416system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83345.541401 # average overall miss latency
2417system.l2c.overall_avg_miss_latency::cpu1.inst 79505.403268 # average overall miss latency
2418system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 125115.773125 # average overall miss latency
2419system.l2c.overall_avg_miss_latency::total 129008.383480 # average overall miss latency
2420system.l2c.blocked_cycles::no_mshrs 43295 # number of cycles access was blocked
2421system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2422system.l2c.blocked::no_mshrs 946 # number of cycles access was blocked
2423system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2424system.l2c.avg_blocked_cycles::no_mshrs 45.766385 # average number of cycles each access was blocked
2425system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2426system.l2c.fast_writes 0 # number of fast writes performed
2427system.l2c.cache_copies 0 # number of cache copies performed
2428system.l2c.writebacks::writebacks 1219289 # number of writebacks
2429system.l2c.writebacks::total 1219289 # number of writebacks
2430system.l2c.ReadReq_mshr_hits::cpu0.inst 49 # number of ReadReq MSHR hits
2431system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 228 # number of ReadReq MSHR hits
2432system.l2c.ReadReq_mshr_hits::cpu1.inst 53 # number of ReadReq MSHR hits
2433system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 251 # number of ReadReq MSHR hits
2434system.l2c.ReadReq_mshr_hits::total 581 # number of ReadReq MSHR hits
2435system.l2c.demand_mshr_hits::cpu0.inst 49 # number of demand (read+write) MSHR hits
2436system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 228 # number of demand (read+write) MSHR hits
2437system.l2c.demand_mshr_hits::cpu1.inst 53 # number of demand (read+write) MSHR hits
2438system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 251 # number of demand (read+write) MSHR hits
2439system.l2c.demand_mshr_hits::total 581 # number of demand (read+write) MSHR hits
2440system.l2c.overall_mshr_hits::cpu0.inst 49 # number of overall MSHR hits
2441system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 228 # number of overall MSHR hits
2442system.l2c.overall_mshr_hits::cpu1.inst 53 # number of overall MSHR hits
2443system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 251 # number of overall MSHR hits
2444system.l2c.overall_mshr_hits::total 581 # number of overall MSHR hits
2445system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1978 # number of ReadReq MSHR misses
2446system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1693 # number of ReadReq MSHR misses
2447system.l2c.ReadReq_mshr_misses::cpu0.inst 95465 # number of ReadReq MSHR misses
2448system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of ReadReq MSHR misses
2449system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2685 # number of ReadReq MSHR misses
2450system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2512 # number of ReadReq MSHR misses
2451system.l2c.ReadReq_mshr_misses::cpu1.inst 131273 # number of ReadReq MSHR misses
2452system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of ReadReq MSHR misses
2453system.l2c.ReadReq_mshr_misses::total 1665128 # number of ReadReq MSHR misses
2454system.l2c.WriteInvalidateReq_mshr_misses::cpu0.inst 16918 # number of WriteInvalidateReq MSHR misses
2455system.l2c.WriteInvalidateReq_mshr_misses::cpu1.inst 7174 # number of WriteInvalidateReq MSHR misses
2456system.l2c.WriteInvalidateReq_mshr_misses::total 24092 # number of WriteInvalidateReq MSHR misses
2457system.l2c.UpgradeReq_mshr_misses::cpu0.inst 36442 # number of UpgradeReq MSHR misses
2458system.l2c.UpgradeReq_mshr_misses::cpu1.inst 33251 # number of UpgradeReq MSHR misses
2459system.l2c.UpgradeReq_mshr_misses::total 69693 # number of UpgradeReq MSHR misses
2460system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 9494 # number of SCUpgradeReq MSHR misses
2461system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 9010 # number of SCUpgradeReq MSHR misses
2462system.l2c.SCUpgradeReq_mshr_misses::total 18504 # number of SCUpgradeReq MSHR misses
2463system.l2c.ReadExReq_mshr_misses::cpu0.inst 45340 # number of ReadExReq MSHR misses
2464system.l2c.ReadExReq_mshr_misses::cpu1.inst 52041 # number of ReadExReq MSHR misses
2465system.l2c.ReadExReq_mshr_misses::total 97381 # number of ReadExReq MSHR misses
2466system.l2c.demand_mshr_misses::cpu0.dtb.walker 1978 # number of demand (read+write) MSHR misses
2467system.l2c.demand_mshr_misses::cpu0.itb.walker 1693 # number of demand (read+write) MSHR misses
2468system.l2c.demand_mshr_misses::cpu0.inst 140805 # number of demand (read+write) MSHR misses
2469system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of demand (read+write) MSHR misses
2470system.l2c.demand_mshr_misses::cpu1.dtb.walker 2685 # number of demand (read+write) MSHR misses
2471system.l2c.demand_mshr_misses::cpu1.itb.walker 2512 # number of demand (read+write) MSHR misses
2472system.l2c.demand_mshr_misses::cpu1.inst 183314 # number of demand (read+write) MSHR misses
2473system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of demand (read+write) MSHR misses
2474system.l2c.demand_mshr_misses::total 1762509 # number of demand (read+write) MSHR misses
2475system.l2c.overall_mshr_misses::cpu0.dtb.walker 1978 # number of overall MSHR misses
2476system.l2c.overall_mshr_misses::cpu0.itb.walker 1693 # number of overall MSHR misses
2477system.l2c.overall_mshr_misses::cpu0.inst 140805 # number of overall MSHR misses
2478system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 863293 # number of overall MSHR misses
2479system.l2c.overall_mshr_misses::cpu1.dtb.walker 2685 # number of overall MSHR misses
2480system.l2c.overall_mshr_misses::cpu1.itb.walker 2512 # number of overall MSHR misses
2481system.l2c.overall_mshr_misses::cpu1.inst 183314 # number of overall MSHR misses
2482system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 566229 # number of overall MSHR misses
2483system.l2c.overall_mshr_misses::total 1762509 # number of overall MSHR misses
2484system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of ReadReq MSHR miss cycles
2485system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 123414748 # number of ReadReq MSHR miss cycles
2486system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 6776817493 # number of ReadReq MSHR miss cycles
2487system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of ReadReq MSHR miss cycles
2488system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of ReadReq MSHR miss cycles
2489system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 177898500 # number of ReadReq MSHR miss cycles
2490system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 8997883953 # number of ReadReq MSHR miss cycles
2491system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of ReadReq MSHR miss cycles
2492system.l2c.ReadReq_mshr_miss_latency::total 199639162524 # number of ReadReq MSHR miss cycles
2493system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.inst 385829647 # number of WriteInvalidateReq MSHR miss cycles
2494system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.inst 157261640 # number of WriteInvalidateReq MSHR miss cycles
2495system.l2c.WriteInvalidateReq_mshr_miss_latency::total 543091287 # number of WriteInvalidateReq MSHR miss cycles
2496system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 371667466 # number of UpgradeReq MSHR miss cycles
2497system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 338371346 # number of UpgradeReq MSHR miss cycles
2498system.l2c.UpgradeReq_mshr_miss_latency::total 710038812 # number of UpgradeReq MSHR miss cycles
2499system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 97958865 # number of SCUpgradeReq MSHR miss cycles
2500system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 92039394 # number of SCUpgradeReq MSHR miss cycles
2501system.l2c.SCUpgradeReq_mshr_miss_latency::total 189998259 # number of SCUpgradeReq MSHR miss cycles
2502system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 2897122081 # number of ReadExReq MSHR miss cycles
2503system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 3278712382 # number of ReadExReq MSHR miss cycles
2504system.l2c.ReadExReq_mshr_miss_latency::total 6175834463 # number of ReadExReq MSHR miss cycles
2505system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of demand (read+write) MSHR miss cycles
2506system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 123414748 # number of demand (read+write) MSHR miss cycles
2507system.l2c.demand_mshr_miss_latency::cpu0.inst 9673939574 # number of demand (read+write) MSHR miss cycles
2508system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of demand (read+write) MSHR miss cycles
2509system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of demand (read+write) MSHR miss cycles
2510system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 177898500 # number of demand (read+write) MSHR miss cycles
2511system.l2c.demand_mshr_miss_latency::cpu1.inst 12276596335 # number of demand (read+write) MSHR miss cycles
2512system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of demand (read+write) MSHR miss cycles
2513system.l2c.demand_mshr_miss_latency::total 205814996987 # number of demand (read+write) MSHR miss cycles
2514system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 140499248 # number of overall MSHR miss cycles
2515system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 123414748 # number of overall MSHR miss cycles
2516system.l2c.overall_mshr_miss_latency::cpu0.inst 9673939574 # number of overall MSHR miss cycles
2517system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 119301017674 # number of overall MSHR miss cycles
2518system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 188732748 # number of overall MSHR miss cycles
2519system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 177898500 # number of overall MSHR miss cycles
2520system.l2c.overall_mshr_miss_latency::cpu1.inst 12276596335 # number of overall MSHR miss cycles
2521system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 63932898160 # number of overall MSHR miss cycles
2522system.l2c.overall_mshr_miss_latency::total 205814996987 # number of overall MSHR miss cycles
2523system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5245081248 # number of ReadReq MSHR uncacheable cycles
2524system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2881233750 # number of ReadReq MSHR uncacheable cycles
2525system.l2c.ReadReq_mshr_uncacheable_latency::total 8126314998 # number of ReadReq MSHR uncacheable cycles
2526system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 2584862001 # number of WriteReq MSHR uncacheable cycles
2527system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 2667893000 # number of WriteReq MSHR uncacheable cycles
2528system.l2c.WriteReq_mshr_uncacheable_latency::total 5252755001 # number of WriteReq MSHR uncacheable cycles
2529system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7829943249 # number of overall MSHR uncacheable cycles
2530system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5549126750 # number of overall MSHR uncacheable cycles
2531system.l2c.overall_mshr_uncacheable_latency::total 13379069999 # number of overall MSHR uncacheable cycles
2532system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for ReadReq accesses
2533system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for ReadReq accesses
2534system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.141662 # mshr miss rate for ReadReq accesses
2535system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for ReadReq accesses
2536system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for ReadReq accesses
2537system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for ReadReq accesses
2538system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172423 # mshr miss rate for ReadReq accesses
2539system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for ReadReq accesses
2540system.l2c.ReadReq_mshr_miss_rate::total 0.220284 # mshr miss rate for ReadReq accesses
2541system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.inst 0.730704 # mshr miss rate for WriteInvalidateReq accesses
2542system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.inst 0.515226 # mshr miss rate for WriteInvalidateReq accesses
2543system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.649783 # mshr miss rate for WriteInvalidateReq accesses
2544system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.482765 # mshr miss rate for UpgradeReq accesses
2545system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.485558 # mshr miss rate for UpgradeReq accesses
2546system.l2c.UpgradeReq_mshr_miss_rate::total 0.484093 # mshr miss rate for UpgradeReq accesses
2547system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.558208 # mshr miss rate for SCUpgradeReq accesses
2548system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.536661 # mshr miss rate for SCUpgradeReq accesses
2549system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.547504 # mshr miss rate for SCUpgradeReq accesses
2550system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.414174 # mshr miss rate for ReadExReq accesses
2551system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.485330 # mshr miss rate for ReadExReq accesses
2552system.l2c.ReadExReq_mshr_miss_rate::total 0.449384 # mshr miss rate for ReadExReq accesses
2553system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for demand accesses
2554system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for demand accesses
2555system.l2c.demand_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for demand accesses
2556system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for demand accesses
2557system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for demand accesses
2558system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for demand accesses
2559system.l2c.demand_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for demand accesses
2560system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for demand accesses
2561system.l2c.demand_mshr_miss_rate::total 0.226669 # mshr miss rate for demand accesses
2562system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.180392 # mshr miss rate for overall accesses
2563system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.204050 # mshr miss rate for overall accesses
2564system.l2c.overall_mshr_miss_rate::cpu0.inst 0.179744 # mshr miss rate for overall accesses
2565system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.272730 # mshr miss rate for overall accesses
2566system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.247397 # mshr miss rate for overall accesses
2567system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.320204 # mshr miss rate for overall accesses
2568system.l2c.overall_mshr_miss_rate::cpu1.inst 0.211053 # mshr miss rate for overall accesses
2569system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.193886 # mshr miss rate for overall accesses
2570system.l2c.overall_mshr_miss_rate::total 0.226669 # mshr miss rate for overall accesses
2571system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average ReadReq mshr miss latency
2572system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average ReadReq mshr miss latency
2573system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70987.456062 # average ReadReq mshr miss latency
2574system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average ReadReq mshr miss latency
2575system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average ReadReq mshr miss latency
2576system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average ReadReq mshr miss latency
2577system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68543.294912 # average ReadReq mshr miss latency
2578system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average ReadReq mshr miss latency
2579system.l2c.ReadReq_avg_mshr_miss_latency::total 119894.183825 # average ReadReq mshr miss latency
2580system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.inst 22805.866355 # average WriteInvalidateReq mshr miss latency
2581system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.inst 21921.053805 # average WriteInvalidateReq mshr miss latency
2582system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22542.391126 # average WriteInvalidateReq mshr miss latency
2583system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10198.876736 # average UpgradeReq mshr miss latency
2584system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10176.275781 # average UpgradeReq mshr miss latency
2585system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10188.093668 # average UpgradeReq mshr miss latency
2586system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10317.976090 # average SCUpgradeReq mshr miss latency
2587system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10215.249057 # average SCUpgradeReq mshr miss latency
2588system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10267.956064 # average SCUpgradeReq mshr miss latency
2589system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 63897.708006 # average ReadExReq mshr miss latency
2590system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 63002.486155 # average ReadExReq mshr miss latency
2591system.l2c.ReadExReq_avg_mshr_miss_latency::total 63419.295992 # average ReadExReq mshr miss latency
2592system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency
2593system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency
2594system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency
2595system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency
2596system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency
2597system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency
2598system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency
2599system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency
2600system.l2c.demand_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency
2601system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71030.964611 # average overall mshr miss latency
2602system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72897.075015 # average overall mshr miss latency
2603system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68704.517411 # average overall mshr miss latency
2604system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 138192.963077 # average overall mshr miss latency
2605system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70291.526257 # average overall mshr miss latency
2606system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70819.466561 # average overall mshr miss latency
2607system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66970.315060 # average overall mshr miss latency
2608system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 112909.967805 # average overall mshr miss latency
2609system.l2c.overall_avg_mshr_miss_latency::total 116773.870084 # average overall mshr miss latency
2610system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
2611system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2612system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2613system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
2614system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
2615system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2616system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
2617system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2618system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2619system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2620system.membus.trans_dist::ReadReq 1764688 # Transaction distribution
2621system.membus.trans_dist::ReadResp 1764688 # Transaction distribution
2622system.membus.trans_dist::WriteReq 38271 # Transaction distribution
2623system.membus.trans_dist::WriteResp 38271 # Transaction distribution
2624system.membus.trans_dist::Writeback 1325983 # Transaction distribution
2625system.membus.trans_dist::WriteInvalidateReq 130519 # Transaction distribution
2626system.membus.trans_dist::WriteInvalidateResp 130519 # Transaction distribution
2627system.membus.trans_dist::UpgradeReq 461811 # Transaction distribution
2628system.membus.trans_dist::SCUpgradeReq 273493 # Transaction distribution
2629system.membus.trans_dist::UpgradeResp 92294 # Transaction distribution
2630system.membus.trans_dist::ReadExReq 109929 # Transaction distribution
2631system.membus.trans_dist::ReadExResp 93588 # Transaction distribution
2632system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122926 # Packet count per connected master and slave (bytes)
2633system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
2634system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24884 # Packet count per connected master and slave (bytes)
2635system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5737506 # Packet count per connected master and slave (bytes)
2636system.membus.pkt_count_system.l2c.mem_side::total 5885368 # Packet count per connected master and slave (bytes)
2637system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336109 # Packet count per connected master and slave (bytes)
2638system.membus.pkt_count_system.iocache.mem_side::total 336109 # Packet count per connected master and slave (bytes)
2639system.membus.pkt_count::total 6221477 # Packet count per connected master and slave (bytes)
2640system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156056 # Cumulative packet size per connected master and slave (bytes)
2641system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
2642system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49768 # Cumulative packet size per connected master and slave (bytes)
2643system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 195441096 # Cumulative packet size per connected master and slave (bytes)
2644system.membus.pkt_size_system.l2c.mem_side::total 195648244 # Cumulative packet size per connected master and slave (bytes)
2645system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14110976 # Cumulative packet size per connected master and slave (bytes)
2646system.membus.pkt_size_system.iocache.mem_side::total 14110976 # Cumulative packet size per connected master and slave (bytes)
2647system.membus.pkt_size::total 209759220 # Cumulative packet size per connected master and slave (bytes)
2648system.membus.snoops 661928 # Total snoops (count)
2649system.membus.snoop_fanout::samples 3975767 # Request fanout histogram
2650system.membus.snoop_fanout::mean 1 # Request fanout histogram
2651system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2652system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2653system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2654system.membus.snoop_fanout::1 3975767 100.00% 100.00% # Request fanout histogram
2655system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2656system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2657system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2658system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2659system.membus.snoop_fanout::total 3975767 # Request fanout histogram
2660system.membus.reqLayer0.occupancy 109763969 # Layer occupancy (ticks)
2661system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2662system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks)
2663system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2664system.membus.reqLayer2.occupancy 20835993 # Layer occupancy (ticks)
2665system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2666system.membus.reqLayer5.occupancy 15443357238 # Layer occupancy (ticks)
2667system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2668system.membus.respLayer2.occupancy 16944581187 # Layer occupancy (ticks)
2669system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2670system.membus.respLayer3.occupancy 187180159 # Layer occupancy (ticks)
2671system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2672system.realview.ethernet.txBytes 966 # Bytes Transmitted
2673system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
2674system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
2675system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
2676system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
2677system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2678system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2679system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2680system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2681system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
2682system.realview.ethernet.totPackets 3 # Total Packets
2683system.realview.ethernet.totBytes 966 # Total Bytes
2684system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
2685system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
2686system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
2687system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2688system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
2689system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2690system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2691system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
2692system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2693system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2694system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
2695system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2696system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2697system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
2698system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2699system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2700system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
2701system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2702system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2703system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
2704system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2705system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2706system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
2707system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2708system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2709system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
2710system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2711system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
2712system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
2713system.realview.ethernet.droppedPackets 0 # number of packets dropped
2714system.toL2Bus.trans_dist::ReadReq 8566773 # Transaction distribution
2715system.toL2Bus.trans_dist::ReadResp 8559524 # Transaction distribution
2716system.toL2Bus.trans_dist::WriteReq 38271 # Transaction distribution
2717system.toL2Bus.trans_dist::WriteResp 38271 # Transaction distribution
2718system.toL2Bus.trans_dist::Writeback 2942617 # Transaction distribution
2719system.toL2Bus.trans_dist::WriteInvalidateReq 143810 # Transaction distribution
2720system.toL2Bus.trans_dist::WriteInvalidateResp 37077 # Transaction distribution
2721system.toL2Bus.trans_dist::UpgradeReq 531990 # Transaction distribution
2722system.toL2Bus.trans_dist::SCUpgradeReq 288786 # Transaction distribution
2723system.toL2Bus.trans_dist::UpgradeResp 820776 # Transaction distribution
2724system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution
2725system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
2726system.toL2Bus.trans_dist::ReadExReq 266520 # Transaction distribution
2727system.toL2Bus.trans_dist::ReadExResp 266520 # Transaction distribution
2728system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10703555 # Packet count per connected master and slave (bytes)
2729system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10080815 # Packet count per connected master and slave (bytes)
2730system.toL2Bus.pkt_count::total 20784370 # Packet count per connected master and slave (bytes)
2731system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 361515951 # Cumulative packet size per connected master and slave (bytes)
2732system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 330513413 # Cumulative packet size per connected master and slave (bytes)
2733system.toL2Bus.pkt_size::total 692029364 # Cumulative packet size per connected master and slave (bytes)
2734system.toL2Bus.snoops 1718447 # Total snoops (count)
2735system.toL2Bus.snoop_fanout::samples 12650717 # Request fanout histogram
2736system.toL2Bus.snoop_fanout::mean 1.009140 # Request fanout histogram
2737system.toL2Bus.snoop_fanout::stdev 0.095166 # Request fanout histogram
2738system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2739system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2740system.toL2Bus.snoop_fanout::1 12535087 99.09% 99.09% # Request fanout histogram
2741system.toL2Bus.snoop_fanout::2 115630 0.91% 100.00% # Request fanout histogram
2742system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2743system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2744system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2745system.toL2Bus.snoop_fanout::total 12650717 # Request fanout histogram
2746system.toL2Bus.reqLayer0.occupancy 18290340474 # Layer occupancy (ticks)
2747system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2748system.toL2Bus.snoopLayer0.occupancy 7404000 # Layer occupancy (ticks)
2749system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2750system.toL2Bus.respLayer0.occupancy 20424320611 # Layer occupancy (ticks)
2751system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2752system.toL2Bus.respLayer1.occupancy 19750107809 # Layer occupancy (ticks)
2753system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2754
2755---------- End Simulation Statistics ----------