| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing |
| 39mem_ranges=2147483648:2415919103 | 39mem_ranges=2147483648:2415919103:0:0:0:0 |
| 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null | 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null |
| 76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 | 76ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 |
| 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 118 unchanged lines hidden (view full) --- 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 206useIndirect=true 207 208[system.cpu0.dcache] 209type=Cache 210children=tags | 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 118 unchanged lines hidden (view full) --- 203localHistoryTableSize=2048 204localPredictorSize=2048 205numThreads=1 206useIndirect=true 207 208[system.cpu0.dcache] 209type=Cache 210children=tags |
| 211addr_ranges=0:18446744073709551615 | 211addr_ranges=0:18446744073709551615:0:0:0:0 |
| 212assoc=2 213clk_domain=system.cpu_clk_domain 214clusivity=mostly_incl 215default_p_state=UNDEFINED 216demand_mshr_reserve=1 217eventq_index=0 218hit_latency=2 219is_read_only=false --- 463 unchanged lines hidden (view full) --- 683[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1] 684type=MinorOpClass 685eventq_index=0 686opClass=InstPrefetch 687 688[system.cpu0.icache] 689type=Cache 690children=tags | 212assoc=2 213clk_domain=system.cpu_clk_domain 214clusivity=mostly_incl 215default_p_state=UNDEFINED 216demand_mshr_reserve=1 217eventq_index=0 218hit_latency=2 219is_read_only=false --- 463 unchanged lines hidden (view full) --- 683[system.cpu0.executeFuncUnits.funcUnits6.opClasses.opClasses1] 684type=MinorOpClass 685eventq_index=0 686opClass=InstPrefetch 687 688[system.cpu0.icache] 689type=Cache 690children=tags |
| 691addr_ranges=0:18446744073709551615 | 691addr_ranges=0:18446744073709551615:0:0:0:0 |
| 692assoc=2 693clk_domain=system.cpu_clk_domain 694clusivity=mostly_incl 695default_p_state=UNDEFINED 696demand_mshr_reserve=1 697eventq_index=0 698hit_latency=1 699is_read_only=true --- 43 unchanged lines hidden (view full) --- 743id_aa64afr0_el1=0 744id_aa64afr1_el1=0 745id_aa64dfr0_el1=1052678 746id_aa64dfr1_el1=0 747id_aa64isar0_el1=0 748id_aa64isar1_el1=0 749id_aa64mmfr0_el1=15728642 750id_aa64mmfr1_el1=0 | 692assoc=2 693clk_domain=system.cpu_clk_domain 694clusivity=mostly_incl 695default_p_state=UNDEFINED 696demand_mshr_reserve=1 697eventq_index=0 698hit_latency=1 699is_read_only=true --- 43 unchanged lines hidden (view full) --- 743id_aa64afr0_el1=0 744id_aa64afr1_el1=0 745id_aa64dfr0_el1=1052678 746id_aa64dfr1_el1=0 747id_aa64isar0_el1=0 748id_aa64isar1_el1=0 749id_aa64mmfr0_el1=15728642 750id_aa64mmfr1_el1=0 |
| 751id_aa64pfr0_el1=17 | 751id_aa64pfr0_el1=34 |
| 752id_aa64pfr1_el1=0 753id_isar0=34607377 754id_isar1=34677009 755id_isar2=555950401 756id_isar3=17899825 757id_isar4=268501314 758id_isar5=0 759id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 815p_state_clk_gate_min=1000 816power_model=Null 817sys=system 818port=system.cpu0.toL2Bus.slave[2] 819 820[system.cpu0.l2cache] 821type=Cache 822children=prefetcher tags | 752id_aa64pfr1_el1=0 753id_isar0=34607377 754id_isar1=34677009 755id_isar2=555950401 756id_isar3=17899825 757id_isar4=268501314 758id_isar5=0 759id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 815p_state_clk_gate_min=1000 816power_model=Null 817sys=system 818port=system.cpu0.toL2Bus.slave[2] 819 820[system.cpu0.l2cache] 821type=Cache 822children=prefetcher tags |
| 823addr_ranges=0:18446744073709551615 | 823addr_ranges=0:18446744073709551615:0:0:0:0 |
| 824assoc=16 825clk_domain=system.cpu_clk_domain 826clusivity=mostly_excl 827default_p_state=UNDEFINED 828demand_mshr_reserve=1 829eventq_index=0 830hit_latency=12 831is_read_only=false --- 187 unchanged lines hidden (view full) --- 1019localHistoryTableSize=2048 1020localPredictorSize=2048 1021numThreads=1 1022useIndirect=true 1023 1024[system.cpu1.dcache] 1025type=Cache 1026children=tags | 824assoc=16 825clk_domain=system.cpu_clk_domain 826clusivity=mostly_excl 827default_p_state=UNDEFINED 828demand_mshr_reserve=1 829eventq_index=0 830hit_latency=12 831is_read_only=false --- 187 unchanged lines hidden (view full) --- 1019localHistoryTableSize=2048 1020localPredictorSize=2048 1021numThreads=1 1022useIndirect=true 1023 1024[system.cpu1.dcache] 1025type=Cache 1026children=tags |
| 1027addr_ranges=0:18446744073709551615 | 1027addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1028assoc=2 1029clk_domain=system.cpu_clk_domain 1030clusivity=mostly_incl 1031default_p_state=UNDEFINED 1032demand_mshr_reserve=1 1033eventq_index=0 1034hit_latency=2 1035is_read_only=false --- 463 unchanged lines hidden (view full) --- 1499[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1] 1500type=MinorOpClass 1501eventq_index=0 1502opClass=InstPrefetch 1503 1504[system.cpu1.icache] 1505type=Cache 1506children=tags | 1028assoc=2 1029clk_domain=system.cpu_clk_domain 1030clusivity=mostly_incl 1031default_p_state=UNDEFINED 1032demand_mshr_reserve=1 1033eventq_index=0 1034hit_latency=2 1035is_read_only=false --- 463 unchanged lines hidden (view full) --- 1499[system.cpu1.executeFuncUnits.funcUnits6.opClasses.opClasses1] 1500type=MinorOpClass 1501eventq_index=0 1502opClass=InstPrefetch 1503 1504[system.cpu1.icache] 1505type=Cache 1506children=tags |
| 1507addr_ranges=0:18446744073709551615 | 1507addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1508assoc=2 1509clk_domain=system.cpu_clk_domain 1510clusivity=mostly_incl 1511default_p_state=UNDEFINED 1512demand_mshr_reserve=1 1513eventq_index=0 1514hit_latency=1 1515is_read_only=true --- 43 unchanged lines hidden (view full) --- 1559id_aa64afr0_el1=0 1560id_aa64afr1_el1=0 1561id_aa64dfr0_el1=1052678 1562id_aa64dfr1_el1=0 1563id_aa64isar0_el1=0 1564id_aa64isar1_el1=0 1565id_aa64mmfr0_el1=15728642 1566id_aa64mmfr1_el1=0 | 1508assoc=2 1509clk_domain=system.cpu_clk_domain 1510clusivity=mostly_incl 1511default_p_state=UNDEFINED 1512demand_mshr_reserve=1 1513eventq_index=0 1514hit_latency=1 1515is_read_only=true --- 43 unchanged lines hidden (view full) --- 1559id_aa64afr0_el1=0 1560id_aa64afr1_el1=0 1561id_aa64dfr0_el1=1052678 1562id_aa64dfr1_el1=0 1563id_aa64isar0_el1=0 1564id_aa64isar1_el1=0 1565id_aa64mmfr0_el1=15728642 1566id_aa64mmfr1_el1=0 |
| 1567id_aa64pfr0_el1=17 | 1567id_aa64pfr0_el1=34 |
| 1568id_aa64pfr1_el1=0 1569id_isar0=34607377 1570id_isar1=34677009 1571id_isar2=555950401 1572id_isar3=17899825 1573id_isar4=268501314 1574id_isar5=0 1575id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 1631p_state_clk_gate_min=1000 1632power_model=Null 1633sys=system 1634port=system.cpu1.toL2Bus.slave[2] 1635 1636[system.cpu1.l2cache] 1637type=Cache 1638children=prefetcher tags | 1568id_aa64pfr1_el1=0 1569id_isar0=34607377 1570id_isar1=34677009 1571id_isar2=555950401 1572id_isar3=17899825 1573id_isar4=268501314 1574id_isar5=0 1575id_mmfr0=270536963 --- 55 unchanged lines hidden (view full) --- 1631p_state_clk_gate_min=1000 1632power_model=Null 1633sys=system 1634port=system.cpu1.toL2Bus.slave[2] 1635 1636[system.cpu1.l2cache] 1637type=Cache 1638children=prefetcher tags |
| 1639addr_ranges=0:18446744073709551615 | 1639addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1640assoc=16 1641clk_domain=system.cpu_clk_domain 1642clusivity=mostly_excl 1643default_p_state=UNDEFINED 1644demand_mshr_reserve=1 1645eventq_index=0 1646hit_latency=12 1647is_read_only=false --- 130 unchanged lines hidden (view full) --- 1778use_default_range=false 1779width=16 1780master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 1781slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 1782 1783[system.iocache] 1784type=Cache 1785children=tags | 1640assoc=16 1641clk_domain=system.cpu_clk_domain 1642clusivity=mostly_excl 1643default_p_state=UNDEFINED 1644demand_mshr_reserve=1 1645eventq_index=0 1646hit_latency=12 1647is_read_only=false --- 130 unchanged lines hidden (view full) --- 1778use_default_range=false 1779width=16 1780master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 1781slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 1782 1783[system.iocache] 1784type=Cache 1785children=tags |
| 1786addr_ranges=2147483648:2415919103 | 1786addr_ranges=2147483648:2415919103:0:0:0:0 |
| 1787assoc=8 1788clk_domain=system.clk_domain 1789clusivity=mostly_incl 1790default_p_state=UNDEFINED 1791demand_mshr_reserve=1 1792eventq_index=0 1793hit_latency=50 1794is_read_only=false --- 29 unchanged lines hidden (view full) --- 1824p_state_clk_gate_min=1000 1825power_model=Null 1826sequential_access=false 1827size=1024 1828 1829[system.l2c] 1830type=Cache 1831children=tags | 1787assoc=8 1788clk_domain=system.clk_domain 1789clusivity=mostly_incl 1790default_p_state=UNDEFINED 1791demand_mshr_reserve=1 1792eventq_index=0 1793hit_latency=50 1794is_read_only=false --- 29 unchanged lines hidden (view full) --- 1824p_state_clk_gate_min=1000 1825power_model=Null 1826sequential_access=false 1827size=1024 1828 1829[system.l2c] 1830type=Cache 1831children=tags |
| 1832addr_ranges=0:18446744073709551615 | 1832addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1833assoc=8 1834clk_domain=system.cpu_clk_domain 1835clusivity=mostly_incl 1836default_p_state=UNDEFINED 1837demand_mshr_reserve=1 1838eventq_index=0 1839hit_latency=20 1840is_read_only=false --- 81 unchanged lines hidden (view full) --- 1922type=SnoopFilter 1923eventq_index=0 1924lookup_latency=1 1925max_capacity=8388608 1926system=system 1927 1928[system.physmem] 1929type=DRAMCtrl | 1833assoc=8 1834clk_domain=system.cpu_clk_domain 1835clusivity=mostly_incl 1836default_p_state=UNDEFINED 1837demand_mshr_reserve=1 1838eventq_index=0 1839hit_latency=20 1840is_read_only=false --- 81 unchanged lines hidden (view full) --- 1922type=SnoopFilter 1923eventq_index=0 1924lookup_latency=1 1925max_capacity=8388608 1926system=system 1927 1928[system.physmem] 1929type=DRAMCtrl |
| 1930IDD0=0.075000 | 1930IDD0=0.055000 |
| 1931IDD02=0.000000 | 1931IDD02=0.000000 |
| 1932IDD2N=0.050000 | 1932IDD2N=0.032000 |
| 1933IDD2N2=0.000000 1934IDD2P0=0.000000 1935IDD2P02=0.000000 | 1933IDD2N2=0.000000 1934IDD2P0=0.000000 1935IDD2P02=0.000000 |
| 1936IDD2P1=0.000000 | 1936IDD2P1=0.032000 |
| 1937IDD2P12=0.000000 | 1937IDD2P12=0.000000 |
| 1938IDD3N=0.057000 | 1938IDD3N=0.038000 |
| 1939IDD3N2=0.000000 1940IDD3P0=0.000000 1941IDD3P02=0.000000 | 1939IDD3N2=0.000000 1940IDD3P0=0.000000 1941IDD3P02=0.000000 |
| 1942IDD3P1=0.000000 | 1942IDD3P1=0.038000 |
| 1943IDD3P12=0.000000 | 1943IDD3P12=0.000000 |
| 1944IDD4R=0.187000 | 1944IDD4R=0.157000 |
| 1945IDD4R2=0.000000 | 1945IDD4R2=0.000000 |
| 1946IDD4W=0.165000 | 1946IDD4W=0.125000 |
| 1947IDD4W2=0.000000 | 1947IDD4W2=0.000000 |
| 1948IDD5=0.220000 | 1948IDD5=0.235000 |
| 1949IDD52=0.000000 | 1949IDD52=0.000000 |
| 1950IDD6=0.000000 | 1950IDD6=0.020000 |
| 1951IDD62=0.000000 1952VDD=1.500000 1953VDD2=0.000000 1954activation_limit=4 1955addr_mapping=RoRaBaCoCh 1956bank_groups_per_rank=0 1957banks_per_rank=8 1958burst_length=8 1959channels=1 1960clk_domain=system.clk_domain 1961conf_table_reported=true 1962default_p_state=UNDEFINED 1963device_bus_width=8 1964device_rowbuffer_size=1024 1965device_size=536870912 1966devices_per_rank=8 1967dll=true 1968eventq_index=0 1969in_addr_map=true | 1951IDD62=0.000000 1952VDD=1.500000 1953VDD2=0.000000 1954activation_limit=4 1955addr_mapping=RoRaBaCoCh 1956bank_groups_per_rank=0 1957banks_per_rank=8 1958burst_length=8 1959channels=1 1960clk_domain=system.clk_domain 1961conf_table_reported=true 1962default_p_state=UNDEFINED 1963device_bus_width=8 1964device_rowbuffer_size=1024 1965device_size=536870912 1966devices_per_rank=8 1967dll=true 1968eventq_index=0 1969in_addr_map=true |
| 1970kvm_map=true |
|
| 1970max_accesses_per_row=16 1971mem_sched_policy=frfcfs 1972min_writes_per_switch=16 1973null=false 1974p_state_clk_gate_bins=20 1975p_state_clk_gate_max=1000000000000 1976p_state_clk_gate_min=1000 1977page_policy=open_adaptive 1978power_model=Null | 1971max_accesses_per_row=16 1972mem_sched_policy=frfcfs 1973min_writes_per_switch=16 1974null=false 1975p_state_clk_gate_bins=20 1976p_state_clk_gate_max=1000000000000 1977p_state_clk_gate_min=1000 1978page_policy=open_adaptive 1979power_model=Null |
| 1979range=2147483648:2415919103 | 1980range=2147483648:2415919103:0:0:0:0 |
| 1980ranks_per_channel=2 1981read_buffer_size=32 1982static_backend_latency=10000 1983static_frontend_latency=10000 1984tBURST=5000 1985tCCD_L=0 1986tCK=1250 1987tCL=13750 --- 5 unchanged lines hidden (view full) --- 1993tRP=13750 1994tRRD=6000 1995tRRD_L=0 1996tRTP=7500 1997tRTW=2500 1998tWR=15000 1999tWTR=7500 2000tXAW=30000 | 1981ranks_per_channel=2 1982read_buffer_size=32 1983static_backend_latency=10000 1984static_frontend_latency=10000 1985tBURST=5000 1986tCCD_L=0 1987tCK=1250 1988tCL=13750 --- 5 unchanged lines hidden (view full) --- 1994tRP=13750 1995tRRD=6000 1996tRRD_L=0 1997tRTP=7500 1998tRTW=2500 1999tWR=15000 2000tWTR=7500 2001tXAW=30000 |
| 2001tXP=0 | 2002tXP=6000 |
| 2002tXPDLL=0 | 2003tXPDLL=0 |
| 2003tXS=0 | 2004tXS=270000 |
| 2004tXSDLL=0 2005write_buffer_size=64 2006write_high_thresh_perc=85 2007write_low_thresh_perc=50 2008port=system.membus.master[5] 2009 2010[system.realview] 2011type=RealView --- 336 unchanged lines hidden (view full) --- 2348type=Pl390 2349clk_domain=system.clk_domain 2350cpu_addr=738205696 2351cpu_pio_delay=10000 2352default_p_state=UNDEFINED 2353dist_addr=738201600 2354dist_pio_delay=10000 2355eventq_index=0 | 2005tXSDLL=0 2006write_buffer_size=64 2007write_high_thresh_perc=85 2008write_low_thresh_perc=50 2009port=system.membus.master[5] 2010 2011[system.realview] 2012type=RealView --- 336 unchanged lines hidden (view full) --- 2349type=Pl390 2350clk_domain=system.clk_domain 2351cpu_addr=738205696 2352cpu_pio_delay=10000 2353default_p_state=UNDEFINED 2354dist_addr=738201600 2355dist_pio_delay=10000 2356eventq_index=0 |
| 2356gem5_extensions=true | 2357gem5_extensions=false |
| 2357int_latency=10000 2358it_lines=128 2359p_state_clk_gate_bins=20 2360p_state_clk_gate_max=1000000000000 2361p_state_clk_gate_min=1000 2362platform=system.realview 2363power_model=Null 2364system=system --- 296 unchanged lines hidden (view full) --- 2661power_model=Null 2662system=system 2663pio=system.iobus.master[21] 2664 2665[system.realview.nvmem] 2666type=SimpleMemory 2667bandwidth=73.000000 2668clk_domain=system.clk_domain | 2358int_latency=10000 2359it_lines=128 2360p_state_clk_gate_bins=20 2361p_state_clk_gate_max=1000000000000 2362p_state_clk_gate_min=1000 2363platform=system.realview 2364power_model=Null 2365system=system --- 296 unchanged lines hidden (view full) --- 2662power_model=Null 2663system=system 2664pio=system.iobus.master[21] 2665 2666[system.realview.nvmem] 2667type=SimpleMemory 2668bandwidth=73.000000 2669clk_domain=system.clk_domain |
| 2669conf_table_reported=true | 2670conf_table_reported=false |
| 2670default_p_state=UNDEFINED 2671eventq_index=0 2672in_addr_map=true | 2671default_p_state=UNDEFINED 2672eventq_index=0 2673in_addr_map=true |
| 2674kvm_map=true |
|
| 2673latency=30000 2674latency_var=0 2675null=false 2676p_state_clk_gate_bins=20 2677p_state_clk_gate_max=1000000000000 2678p_state_clk_gate_min=1000 2679power_model=Null | 2675latency=30000 2676latency_var=0 2677null=false 2678p_state_clk_gate_bins=20 2679p_state_clk_gate_max=1000000000000 2680p_state_clk_gate_min=1000 2681power_model=Null |
| 2680range=0:67108863 | 2682range=0:67108863:0:0:0:0 |
| 2681port=system.membus.master[1] 2682 2683[system.realview.pci_host] 2684type=GenericPciHost 2685clk_domain=system.clk_domain 2686conf_base=805306368 2687conf_device_bits=12 2688conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2903[system.realview.vram] 2904type=SimpleMemory 2905bandwidth=73.000000 2906clk_domain=system.clk_domain 2907conf_table_reported=false 2908default_p_state=UNDEFINED 2909eventq_index=0 2910in_addr_map=true | 2683port=system.membus.master[1] 2684 2685[system.realview.pci_host] 2686type=GenericPciHost 2687clk_domain=system.clk_domain 2688conf_base=805306368 2689conf_device_bits=12 2690conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2905[system.realview.vram] 2906type=SimpleMemory 2907bandwidth=73.000000 2908clk_domain=system.clk_domain 2909conf_table_reported=false 2910default_p_state=UNDEFINED 2911eventq_index=0 2912in_addr_map=true |
| 2913kvm_map=true |
|
| 2911latency=30000 2912latency_var=0 2913null=false 2914p_state_clk_gate_bins=20 2915p_state_clk_gate_max=1000000000000 2916p_state_clk_gate_min=1000 2917power_model=Null | 2914latency=30000 2915latency_var=0 2916null=false 2917p_state_clk_gate_bins=20 2918p_state_clk_gate_max=1000000000000 2919p_state_clk_gate_min=1000 2920power_model=Null |
| 2918range=402653184:436207615 | 2921range=402653184:436207615:0:0:0:0 |
| 2919port=system.iobus.master[11] 2920 2921[system.realview.watchdog_fake] 2922type=AmbaFake 2923amba_id=0 2924clk_domain=system.clk_domain 2925default_p_state=UNDEFINED 2926eventq_index=0 --- 59 unchanged lines hidden --- | 2922port=system.iobus.master[11] 2923 2924[system.realview.watchdog_fake] 2925type=AmbaFake 2926amba_id=0 2927clk_domain=system.clk_domain 2928default_p_state=UNDEFINED 2929eventq_index=0 --- 59 unchanged lines hidden --- |