15c15
< boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
---
> boot_loader=/dist/m5/system/binaries/boot_emm.arm64
20c20
< dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
---
> dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
33c33
< kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
---
> kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
40c40,41
< memories=system.physmem system.realview.vram system.realview.nvmem
---
> memories=system.physmem system.realview.nvmem system.realview.vram
> mmap_using_noreserve=false
46c47
< readfile=/work/gem5.latest/tests/halt.sh
---
> readfile=/z/stever/hg/gem5/tests/halt.sh
89c90
< image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
---
> image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
188a190
> demand_mshr_reserve=1
222a225
> sys=system
240d242
< port=system.cpu0.toL2Bus.slave[5]
647a650
> demand_mshr_reserve=1
715a719
> sys=system
733d736
< port=system.cpu0.toL2Bus.slave[4]
757a761
> demand_mshr_reserve=1
778a783
> cache_snoop=false
780,781d784
< cross_pages=false
< data_accesses_only=false
784d786
< inst_tagged=true
786,790c788,798
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
791a800,803
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
808c820,822
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
809a824
> snoop_response_latency=1
814c829
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
908a924
> demand_mshr_reserve=1
942a959
> sys=system
960d976
< port=system.cpu1.toL2Bus.slave[5]
1367a1384
> demand_mshr_reserve=1
1435a1453
> sys=system
1453d1470
< port=system.cpu1.toL2Bus.slave[4]
1477a1495
> demand_mshr_reserve=1
1498a1517
> cache_snoop=false
1500,1501d1518
< cross_pages=false
< data_accesses_only=false
1504d1520
< inst_tagged=true
1506,1510c1522,1532
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
1511a1534,1537
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
1528c1554,1556
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1529a1558
> snoop_response_latency=1
1534c1563
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1565c1594,1596
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
1567c1598
< width=8
---
> width=16
1577a1609
> demand_mshr_reserve=1
1612a1645
> demand_mshr_reserve=1
1647c1680,1682
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
1648a1684
> snoop_response_latency=4
1651c1687
< width=8
---
> width=16
1701c1737
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
2412c2448,2450
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
2413a2452
> snoop_response_latency=1
2416c2455
< width=8
---
> width=32
< boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
---
> boot_loader=/dist/m5/system/binaries/boot_emm.arm64
20c20
< dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
---
> dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
33c33
< kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
---
> kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
40c40,41
< memories=system.physmem system.realview.vram system.realview.nvmem
---
> memories=system.physmem system.realview.nvmem system.realview.vram
> mmap_using_noreserve=false
46c47
< readfile=/work/gem5.latest/tests/halt.sh
---
> readfile=/z/stever/hg/gem5/tests/halt.sh
89c90
< image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
---
> image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
188a190
> demand_mshr_reserve=1
222a225
> sys=system
240d242
< port=system.cpu0.toL2Bus.slave[5]
647a650
> demand_mshr_reserve=1
715a719
> sys=system
733d736
< port=system.cpu0.toL2Bus.slave[4]
757a761
> demand_mshr_reserve=1
778a783
> cache_snoop=false
780,781d784
< cross_pages=false
< data_accesses_only=false
784d786
< inst_tagged=true
786,790c788,798
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
791a800,803
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
808c820,822
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
809a824
> snoop_response_latency=1
814c829
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
908a924
> demand_mshr_reserve=1
942a959
> sys=system
960d976
< port=system.cpu1.toL2Bus.slave[5]
1367a1384
> demand_mshr_reserve=1
1435a1453
> sys=system
1453d1470
< port=system.cpu1.toL2Bus.slave[4]
1477a1495
> demand_mshr_reserve=1
1498a1517
> cache_snoop=false
1500,1501d1518
< cross_pages=false
< data_accesses_only=false
1504d1520
< inst_tagged=true
1506,1510c1522,1532
< on_miss_only=false
< on_prefetch=true
< on_read_only=false
< serial_squash=false
< size=100
---
> max_conf=7
> min_conf=0
> on_data=true
> on_inst=true
> on_miss=false
> on_read=true
> on_write=true
> queue_filter=true
> queue_size=32
> queue_squash=true
> start_conf=4
1511a1534,1537
> table_assoc=4
> table_sets=16
> tag_prefetch=true
> thresh_conf=4
1528c1554,1556
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1529a1558
> snoop_response_latency=1
1534c1563
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
1565c1594,1596
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
1567c1598
< width=8
---
> width=16
1577a1609
> demand_mshr_reserve=1
1612a1645
> demand_mshr_reserve=1
1647c1680,1682
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
1648a1684
> snoop_response_latency=4
1651c1687
< width=8
---
> width=16
1701c1737
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
2412c2448,2450
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
2413a2452
> snoop_response_latency=1
2416c2455
< width=8
---
> width=32