1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17boot_release_addr=65528
18cache_line_size=64
19clk_domain=system.clk_domain
20dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24flags_addr=469827632
25gic_cpu_addr=738205696
26have_generic_timer=false
27have_large_asid_64=false
28have_lpae=false
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM64
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.vram system.realview.nvmem
41multi_proc=true
42num_work_ids=16
43panic_on_oops=true
44panic_on_panic=true
45phys_addr_range_64=40
46readfile=/work/gem5.latest/tests/halt.sh
47reset_addr_64=0
48symbolfile=
49work_begin_ckpt_count=0
50work_begin_cpu_id_exit=-1
51work_begin_exit_count=0
52work_cpus_ckpt_count=0
53work_end_ckpt_count=0
54work_end_exit_count=0
--- 26 unchanged lines hidden (view full) ---
81eventq_index=0
82image_file=
83read_only=false
84table_size=65536
85
86[system.cf0.image.child]
87type=RawDiskImage
88eventq_index=0
89image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
90read_only=true
91
92[system.clk_domain]
93type=SrcClockDomain
94clock=1000
95domain_id=-1
96eventq_index=0
97init_perf_level=0
--- 83 unchanged lines hidden (view full) ---
181predType=tournament
182
183[system.cpu0.dcache]
184type=BaseCache
185children=tags
186addr_ranges=0:18446744073709551615
187assoc=2
188clk_domain=system.cpu_clk_domain
189eventq_index=0
190forward_snoops=true
191hit_latency=2
192is_top_level=true
193max_miss_count=0
194mshrs=6
195prefetch_on_access=false
196prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
215sequential_access=false
216size=32768
217
218[system.cpu0.dstage2_mmu]
219type=ArmStage2MMU
220children=stage2_tlb
221eventq_index=0
222stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
223tlb=system.cpu0.dtb
224
225[system.cpu0.dstage2_mmu.stage2_tlb]
226type=ArmTLB
227children=walker
228eventq_index=0
229is_stage2=true
230size=32
231walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
232
233[system.cpu0.dstage2_mmu.stage2_tlb.walker]
234type=ArmTableWalker
235clk_domain=system.cpu_clk_domain
236eventq_index=0
237is_stage2=true
238num_squash_per_cycle=2
239sys=system
240port=system.cpu0.toL2Bus.slave[5]
241
242[system.cpu0.dtb]
243type=ArmTLB
244children=walker
245eventq_index=0
246is_stage2=false
247size=64
248walker=system.cpu0.dtb.walker
--- 391 unchanged lines hidden (view full) ---
640opClass=InstPrefetch
641
642[system.cpu0.icache]
643type=BaseCache
644children=tags
645addr_ranges=0:18446744073709551615
646assoc=2
647clk_domain=system.cpu_clk_domain
648eventq_index=0
649forward_snoops=true
650hit_latency=1
651is_top_level=true
652max_miss_count=0
653mshrs=2
654prefetch_on_access=false
655prefetcher=Null
--- 52 unchanged lines hidden (view full) ---
708pmu=Null
709system=system
710
711[system.cpu0.istage2_mmu]
712type=ArmStage2MMU
713children=stage2_tlb
714eventq_index=0
715stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
716tlb=system.cpu0.itb
717
718[system.cpu0.istage2_mmu.stage2_tlb]
719type=ArmTLB
720children=walker
721eventq_index=0
722is_stage2=true
723size=32
724walker=system.cpu0.istage2_mmu.stage2_tlb.walker
725
726[system.cpu0.istage2_mmu.stage2_tlb.walker]
727type=ArmTableWalker
728clk_domain=system.cpu_clk_domain
729eventq_index=0
730is_stage2=true
731num_squash_per_cycle=2
732sys=system
733port=system.cpu0.toL2Bus.slave[4]
734
735[system.cpu0.itb]
736type=ArmTLB
737children=walker
738eventq_index=0
739is_stage2=false
740size=64
741walker=system.cpu0.itb.walker
--- 8 unchanged lines hidden (view full) ---
750port=system.cpu0.toL2Bus.slave[2]
751
752[system.cpu0.l2cache]
753type=BaseCache
754children=prefetcher tags
755addr_ranges=0:18446744073709551615
756assoc=16
757clk_domain=system.cpu_clk_domain
758eventq_index=0
759forward_snoops=true
760hit_latency=12
761is_top_level=false
762max_miss_count=0
763mshrs=16
764prefetch_on_access=true
765prefetcher=system.cpu0.l2cache.prefetcher
--- 5 unchanged lines hidden (view full) ---
771tgts_per_mshr=8
772two_queue=false
773write_buffers=8
774cpu_side=system.cpu0.toL2Bus.master[0]
775mem_side=system.toL2Bus.slave[0]
776
777[system.cpu0.l2cache.prefetcher]
778type=StridePrefetcher
779clk_domain=system.cpu_clk_domain
780cross_pages=false
781data_accesses_only=false
782degree=8
783eventq_index=0
784inst_tagged=true
785latency=1
786on_miss_only=false
787on_prefetch=true
788on_read_only=false
789serial_squash=false
790size=100
791sys=system
792use_master_id=true
793
794[system.cpu0.l2cache.tags]
795type=RandomRepl
796assoc=16
797block_size=64
798clk_domain=system.cpu_clk_domain
799eventq_index=0
800hit_latency=12
801sequential_access=false
802size=1048576
803
804[system.cpu0.toL2Bus]
805type=CoherentXBar
806clk_domain=system.cpu_clk_domain
807eventq_index=0
808header_cycles=1
809snoop_filter=Null
810system=system
811use_default_range=false
812width=32
813master=system.cpu0.l2cache.cpu_side
814slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
815
816[system.cpu0.tracer]
817type=ExeTracer
818eventq_index=0
819
820[system.cpu1]
821type=MinorCPU
822children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 78 unchanged lines hidden (view full) ---
901predType=tournament
902
903[system.cpu1.dcache]
904type=BaseCache
905children=tags
906addr_ranges=0:18446744073709551615
907assoc=2
908clk_domain=system.cpu_clk_domain
909eventq_index=0
910forward_snoops=true
911hit_latency=2
912is_top_level=true
913max_miss_count=0
914mshrs=6
915prefetch_on_access=false
916prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
935sequential_access=false
936size=32768
937
938[system.cpu1.dstage2_mmu]
939type=ArmStage2MMU
940children=stage2_tlb
941eventq_index=0
942stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
943tlb=system.cpu1.dtb
944
945[system.cpu1.dstage2_mmu.stage2_tlb]
946type=ArmTLB
947children=walker
948eventq_index=0
949is_stage2=true
950size=32
951walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
952
953[system.cpu1.dstage2_mmu.stage2_tlb.walker]
954type=ArmTableWalker
955clk_domain=system.cpu_clk_domain
956eventq_index=0
957is_stage2=true
958num_squash_per_cycle=2
959sys=system
960port=system.cpu1.toL2Bus.slave[5]
961
962[system.cpu1.dtb]
963type=ArmTLB
964children=walker
965eventq_index=0
966is_stage2=false
967size=64
968walker=system.cpu1.dtb.walker
--- 391 unchanged lines hidden (view full) ---
1360opClass=InstPrefetch
1361
1362[system.cpu1.icache]
1363type=BaseCache
1364children=tags
1365addr_ranges=0:18446744073709551615
1366assoc=2
1367clk_domain=system.cpu_clk_domain
1368eventq_index=0
1369forward_snoops=true
1370hit_latency=1
1371is_top_level=true
1372max_miss_count=0
1373mshrs=2
1374prefetch_on_access=false
1375prefetcher=Null
--- 52 unchanged lines hidden (view full) ---
1428pmu=Null
1429system=system
1430
1431[system.cpu1.istage2_mmu]
1432type=ArmStage2MMU
1433children=stage2_tlb
1434eventq_index=0
1435stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1436tlb=system.cpu1.itb
1437
1438[system.cpu1.istage2_mmu.stage2_tlb]
1439type=ArmTLB
1440children=walker
1441eventq_index=0
1442is_stage2=true
1443size=32
1444walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1445
1446[system.cpu1.istage2_mmu.stage2_tlb.walker]
1447type=ArmTableWalker
1448clk_domain=system.cpu_clk_domain
1449eventq_index=0
1450is_stage2=true
1451num_squash_per_cycle=2
1452sys=system
1453port=system.cpu1.toL2Bus.slave[4]
1454
1455[system.cpu1.itb]
1456type=ArmTLB
1457children=walker
1458eventq_index=0
1459is_stage2=false
1460size=64
1461walker=system.cpu1.itb.walker
--- 8 unchanged lines hidden (view full) ---
1470port=system.cpu1.toL2Bus.slave[2]
1471
1472[system.cpu1.l2cache]
1473type=BaseCache
1474children=prefetcher tags
1475addr_ranges=0:18446744073709551615
1476assoc=16
1477clk_domain=system.cpu_clk_domain
1478eventq_index=0
1479forward_snoops=true
1480hit_latency=12
1481is_top_level=false
1482max_miss_count=0
1483mshrs=16
1484prefetch_on_access=true
1485prefetcher=system.cpu1.l2cache.prefetcher
--- 5 unchanged lines hidden (view full) ---
1491tgts_per_mshr=8
1492two_queue=false
1493write_buffers=8
1494cpu_side=system.cpu1.toL2Bus.master[0]
1495mem_side=system.toL2Bus.slave[1]
1496
1497[system.cpu1.l2cache.prefetcher]
1498type=StridePrefetcher
1499clk_domain=system.cpu_clk_domain
1500cross_pages=false
1501data_accesses_only=false
1502degree=8
1503eventq_index=0
1504inst_tagged=true
1505latency=1
1506on_miss_only=false
1507on_prefetch=true
1508on_read_only=false
1509serial_squash=false
1510size=100
1511sys=system
1512use_master_id=true
1513
1514[system.cpu1.l2cache.tags]
1515type=RandomRepl
1516assoc=16
1517block_size=64
1518clk_domain=system.cpu_clk_domain
1519eventq_index=0
1520hit_latency=12
1521sequential_access=false
1522size=1048576
1523
1524[system.cpu1.toL2Bus]
1525type=CoherentXBar
1526clk_domain=system.cpu_clk_domain
1527eventq_index=0
1528header_cycles=1
1529snoop_filter=Null
1530system=system
1531use_default_range=false
1532width=32
1533master=system.cpu1.l2cache.cpu_side
1534slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
1535
1536[system.cpu1.tracer]
1537type=ExeTracer
1538eventq_index=0
1539
1540[system.cpu_clk_domain]
1541type=SrcClockDomain
1542clock=500
--- 14 unchanged lines hidden (view full) ---
1557type=IntrControl
1558eventq_index=0
1559sys=system
1560
1561[system.iobus]
1562type=NoncoherentXBar
1563clk_domain=system.clk_domain
1564eventq_index=0
1565header_cycles=1
1566use_default_range=true
1567width=8
1568default=system.realview.pciconfig.pio
1569master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
1570slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
1571
1572[system.iocache]
1573type=BaseCache
1574children=tags
1575addr_ranges=2147483648:2415919103
1576assoc=8
1577clk_domain=system.clk_domain
1578eventq_index=0
1579forward_snoops=false
1580hit_latency=50
1581is_top_level=true
1582max_miss_count=0
1583mshrs=20
1584prefetch_on_access=false
1585prefetcher=Null
--- 19 unchanged lines hidden (view full) ---
1605size=1024
1606
1607[system.l2c]
1608type=BaseCache
1609children=tags
1610addr_ranges=0:18446744073709551615
1611assoc=8
1612clk_domain=system.cpu_clk_domain
1613eventq_index=0
1614forward_snoops=true
1615hit_latency=20
1616is_top_level=false
1617max_miss_count=0
1618mshrs=20
1619prefetch_on_access=false
1620prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
1639sequential_access=false
1640size=4194304
1641
1642[system.membus]
1643type=CoherentXBar
1644children=badaddr_responder
1645clk_domain=system.clk_domain
1646eventq_index=0
1647header_cycles=1
1648snoop_filter=Null
1649system=system
1650use_default_range=false
1651width=8
1652default=system.membus.badaddr_responder.pio
1653master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
1654slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1655
1656[system.membus.badaddr_responder]
1657type=IsaFake
1658clk_domain=system.clk_domain
1659eventq_index=0
--- 33 unchanged lines hidden (view full) ---
1693IDD4W2=0.000000
1694IDD5=0.220000
1695IDD52=0.000000
1696IDD6=0.000000
1697IDD62=0.000000
1698VDD=1.500000
1699VDD2=0.000000
1700activation_limit=4
1701addr_mapping=RoRaBaChCo
1702bank_groups_per_rank=0
1703banks_per_rank=8
1704burst_length=8
1705channels=1
1706clk_domain=system.clk_domain
1707conf_table_reported=true
1708device_bus_width=8
1709device_rowbuffer_size=1024
--- 694 unchanged lines hidden (view full) ---
2404number=0
2405output=true
2406port=3456
2407
2408[system.toL2Bus]
2409type=CoherentXBar
2410clk_domain=system.cpu_clk_domain
2411eventq_index=0
2412header_cycles=1
2413snoop_filter=Null
2414system=system
2415use_default_range=false
2416width=8
2417master=system.l2c.cpu_side
2418slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2419
2420[system.vncserver]
2421type=VncServer
2422eventq_index=0
2423frame_capture=false
2424number=0
2425port=5900
2426
2427[system.voltage_domain]
2428type=VoltageDomain
2429eventq_index=0
2430voltage=1.000000
2431
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17boot_release_addr=65528
18cache_line_size=64
19clk_domain=system.clk_domain
20dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24flags_addr=469827632
25gic_cpu_addr=738205696
26have_generic_timer=false
27have_large_asid_64=false
28have_lpae=false
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM64
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.vram system.realview.nvmem
41multi_proc=true
42num_work_ids=16
43panic_on_oops=true
44panic_on_panic=true
45phys_addr_range_64=40
46readfile=/work/gem5.latest/tests/halt.sh
47reset_addr_64=0
48symbolfile=
49work_begin_ckpt_count=0
50work_begin_cpu_id_exit=-1
51work_begin_exit_count=0
52work_cpus_ckpt_count=0
53work_end_ckpt_count=0
54work_end_exit_count=0
--- 26 unchanged lines hidden (view full) ---
81eventq_index=0
82image_file=
83read_only=false
84table_size=65536
85
86[system.cf0.image.child]
87type=RawDiskImage
88eventq_index=0
89image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
90read_only=true
91
92[system.clk_domain]
93type=SrcClockDomain
94clock=1000
95domain_id=-1
96eventq_index=0
97init_perf_level=0
--- 83 unchanged lines hidden (view full) ---
181predType=tournament
182
183[system.cpu0.dcache]
184type=BaseCache
185children=tags
186addr_ranges=0:18446744073709551615
187assoc=2
188clk_domain=system.cpu_clk_domain
189eventq_index=0
190forward_snoops=true
191hit_latency=2
192is_top_level=true
193max_miss_count=0
194mshrs=6
195prefetch_on_access=false
196prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
215sequential_access=false
216size=32768
217
218[system.cpu0.dstage2_mmu]
219type=ArmStage2MMU
220children=stage2_tlb
221eventq_index=0
222stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
223tlb=system.cpu0.dtb
224
225[system.cpu0.dstage2_mmu.stage2_tlb]
226type=ArmTLB
227children=walker
228eventq_index=0
229is_stage2=true
230size=32
231walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
232
233[system.cpu0.dstage2_mmu.stage2_tlb.walker]
234type=ArmTableWalker
235clk_domain=system.cpu_clk_domain
236eventq_index=0
237is_stage2=true
238num_squash_per_cycle=2
239sys=system
240port=system.cpu0.toL2Bus.slave[5]
241
242[system.cpu0.dtb]
243type=ArmTLB
244children=walker
245eventq_index=0
246is_stage2=false
247size=64
248walker=system.cpu0.dtb.walker
--- 391 unchanged lines hidden (view full) ---
640opClass=InstPrefetch
641
642[system.cpu0.icache]
643type=BaseCache
644children=tags
645addr_ranges=0:18446744073709551615
646assoc=2
647clk_domain=system.cpu_clk_domain
648eventq_index=0
649forward_snoops=true
650hit_latency=1
651is_top_level=true
652max_miss_count=0
653mshrs=2
654prefetch_on_access=false
655prefetcher=Null
--- 52 unchanged lines hidden (view full) ---
708pmu=Null
709system=system
710
711[system.cpu0.istage2_mmu]
712type=ArmStage2MMU
713children=stage2_tlb
714eventq_index=0
715stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
716tlb=system.cpu0.itb
717
718[system.cpu0.istage2_mmu.stage2_tlb]
719type=ArmTLB
720children=walker
721eventq_index=0
722is_stage2=true
723size=32
724walker=system.cpu0.istage2_mmu.stage2_tlb.walker
725
726[system.cpu0.istage2_mmu.stage2_tlb.walker]
727type=ArmTableWalker
728clk_domain=system.cpu_clk_domain
729eventq_index=0
730is_stage2=true
731num_squash_per_cycle=2
732sys=system
733port=system.cpu0.toL2Bus.slave[4]
734
735[system.cpu0.itb]
736type=ArmTLB
737children=walker
738eventq_index=0
739is_stage2=false
740size=64
741walker=system.cpu0.itb.walker
--- 8 unchanged lines hidden (view full) ---
750port=system.cpu0.toL2Bus.slave[2]
751
752[system.cpu0.l2cache]
753type=BaseCache
754children=prefetcher tags
755addr_ranges=0:18446744073709551615
756assoc=16
757clk_domain=system.cpu_clk_domain
758eventq_index=0
759forward_snoops=true
760hit_latency=12
761is_top_level=false
762max_miss_count=0
763mshrs=16
764prefetch_on_access=true
765prefetcher=system.cpu0.l2cache.prefetcher
--- 5 unchanged lines hidden (view full) ---
771tgts_per_mshr=8
772two_queue=false
773write_buffers=8
774cpu_side=system.cpu0.toL2Bus.master[0]
775mem_side=system.toL2Bus.slave[0]
776
777[system.cpu0.l2cache.prefetcher]
778type=StridePrefetcher
779clk_domain=system.cpu_clk_domain
780cross_pages=false
781data_accesses_only=false
782degree=8
783eventq_index=0
784inst_tagged=true
785latency=1
786on_miss_only=false
787on_prefetch=true
788on_read_only=false
789serial_squash=false
790size=100
791sys=system
792use_master_id=true
793
794[system.cpu0.l2cache.tags]
795type=RandomRepl
796assoc=16
797block_size=64
798clk_domain=system.cpu_clk_domain
799eventq_index=0
800hit_latency=12
801sequential_access=false
802size=1048576
803
804[system.cpu0.toL2Bus]
805type=CoherentXBar
806clk_domain=system.cpu_clk_domain
807eventq_index=0
808header_cycles=1
809snoop_filter=Null
810system=system
811use_default_range=false
812width=32
813master=system.cpu0.l2cache.cpu_side
814slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
815
816[system.cpu0.tracer]
817type=ExeTracer
818eventq_index=0
819
820[system.cpu1]
821type=MinorCPU
822children=branchPred dcache dstage2_mmu dtb executeFuncUnits icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 78 unchanged lines hidden (view full) ---
901predType=tournament
902
903[system.cpu1.dcache]
904type=BaseCache
905children=tags
906addr_ranges=0:18446744073709551615
907assoc=2
908clk_domain=system.cpu_clk_domain
909eventq_index=0
910forward_snoops=true
911hit_latency=2
912is_top_level=true
913max_miss_count=0
914mshrs=6
915prefetch_on_access=false
916prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
935sequential_access=false
936size=32768
937
938[system.cpu1.dstage2_mmu]
939type=ArmStage2MMU
940children=stage2_tlb
941eventq_index=0
942stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
943tlb=system.cpu1.dtb
944
945[system.cpu1.dstage2_mmu.stage2_tlb]
946type=ArmTLB
947children=walker
948eventq_index=0
949is_stage2=true
950size=32
951walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
952
953[system.cpu1.dstage2_mmu.stage2_tlb.walker]
954type=ArmTableWalker
955clk_domain=system.cpu_clk_domain
956eventq_index=0
957is_stage2=true
958num_squash_per_cycle=2
959sys=system
960port=system.cpu1.toL2Bus.slave[5]
961
962[system.cpu1.dtb]
963type=ArmTLB
964children=walker
965eventq_index=0
966is_stage2=false
967size=64
968walker=system.cpu1.dtb.walker
--- 391 unchanged lines hidden (view full) ---
1360opClass=InstPrefetch
1361
1362[system.cpu1.icache]
1363type=BaseCache
1364children=tags
1365addr_ranges=0:18446744073709551615
1366assoc=2
1367clk_domain=system.cpu_clk_domain
1368eventq_index=0
1369forward_snoops=true
1370hit_latency=1
1371is_top_level=true
1372max_miss_count=0
1373mshrs=2
1374prefetch_on_access=false
1375prefetcher=Null
--- 52 unchanged lines hidden (view full) ---
1428pmu=Null
1429system=system
1430
1431[system.cpu1.istage2_mmu]
1432type=ArmStage2MMU
1433children=stage2_tlb
1434eventq_index=0
1435stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
1436tlb=system.cpu1.itb
1437
1438[system.cpu1.istage2_mmu.stage2_tlb]
1439type=ArmTLB
1440children=walker
1441eventq_index=0
1442is_stage2=true
1443size=32
1444walker=system.cpu1.istage2_mmu.stage2_tlb.walker
1445
1446[system.cpu1.istage2_mmu.stage2_tlb.walker]
1447type=ArmTableWalker
1448clk_domain=system.cpu_clk_domain
1449eventq_index=0
1450is_stage2=true
1451num_squash_per_cycle=2
1452sys=system
1453port=system.cpu1.toL2Bus.slave[4]
1454
1455[system.cpu1.itb]
1456type=ArmTLB
1457children=walker
1458eventq_index=0
1459is_stage2=false
1460size=64
1461walker=system.cpu1.itb.walker
--- 8 unchanged lines hidden (view full) ---
1470port=system.cpu1.toL2Bus.slave[2]
1471
1472[system.cpu1.l2cache]
1473type=BaseCache
1474children=prefetcher tags
1475addr_ranges=0:18446744073709551615
1476assoc=16
1477clk_domain=system.cpu_clk_domain
1478eventq_index=0
1479forward_snoops=true
1480hit_latency=12
1481is_top_level=false
1482max_miss_count=0
1483mshrs=16
1484prefetch_on_access=true
1485prefetcher=system.cpu1.l2cache.prefetcher
--- 5 unchanged lines hidden (view full) ---
1491tgts_per_mshr=8
1492two_queue=false
1493write_buffers=8
1494cpu_side=system.cpu1.toL2Bus.master[0]
1495mem_side=system.toL2Bus.slave[1]
1496
1497[system.cpu1.l2cache.prefetcher]
1498type=StridePrefetcher
1499clk_domain=system.cpu_clk_domain
1500cross_pages=false
1501data_accesses_only=false
1502degree=8
1503eventq_index=0
1504inst_tagged=true
1505latency=1
1506on_miss_only=false
1507on_prefetch=true
1508on_read_only=false
1509serial_squash=false
1510size=100
1511sys=system
1512use_master_id=true
1513
1514[system.cpu1.l2cache.tags]
1515type=RandomRepl
1516assoc=16
1517block_size=64
1518clk_domain=system.cpu_clk_domain
1519eventq_index=0
1520hit_latency=12
1521sequential_access=false
1522size=1048576
1523
1524[system.cpu1.toL2Bus]
1525type=CoherentXBar
1526clk_domain=system.cpu_clk_domain
1527eventq_index=0
1528header_cycles=1
1529snoop_filter=Null
1530system=system
1531use_default_range=false
1532width=32
1533master=system.cpu1.l2cache.cpu_side
1534slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
1535
1536[system.cpu1.tracer]
1537type=ExeTracer
1538eventq_index=0
1539
1540[system.cpu_clk_domain]
1541type=SrcClockDomain
1542clock=500
--- 14 unchanged lines hidden (view full) ---
1557type=IntrControl
1558eventq_index=0
1559sys=system
1560
1561[system.iobus]
1562type=NoncoherentXBar
1563clk_domain=system.clk_domain
1564eventq_index=0
1565header_cycles=1
1566use_default_range=true
1567width=8
1568default=system.realview.pciconfig.pio
1569master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
1570slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
1571
1572[system.iocache]
1573type=BaseCache
1574children=tags
1575addr_ranges=2147483648:2415919103
1576assoc=8
1577clk_domain=system.clk_domain
1578eventq_index=0
1579forward_snoops=false
1580hit_latency=50
1581is_top_level=true
1582max_miss_count=0
1583mshrs=20
1584prefetch_on_access=false
1585prefetcher=Null
--- 19 unchanged lines hidden (view full) ---
1605size=1024
1606
1607[system.l2c]
1608type=BaseCache
1609children=tags
1610addr_ranges=0:18446744073709551615
1611assoc=8
1612clk_domain=system.cpu_clk_domain
1613eventq_index=0
1614forward_snoops=true
1615hit_latency=20
1616is_top_level=false
1617max_miss_count=0
1618mshrs=20
1619prefetch_on_access=false
1620prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
1639sequential_access=false
1640size=4194304
1641
1642[system.membus]
1643type=CoherentXBar
1644children=badaddr_responder
1645clk_domain=system.clk_domain
1646eventq_index=0
1647header_cycles=1
1648snoop_filter=Null
1649system=system
1650use_default_range=false
1651width=8
1652default=system.membus.badaddr_responder.pio
1653master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
1654slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
1655
1656[system.membus.badaddr_responder]
1657type=IsaFake
1658clk_domain=system.clk_domain
1659eventq_index=0
--- 33 unchanged lines hidden (view full) ---
1693IDD4W2=0.000000
1694IDD5=0.220000
1695IDD52=0.000000
1696IDD6=0.000000
1697IDD62=0.000000
1698VDD=1.500000
1699VDD2=0.000000
1700activation_limit=4
1701addr_mapping=RoRaBaChCo
1702bank_groups_per_rank=0
1703banks_per_rank=8
1704burst_length=8
1705channels=1
1706clk_domain=system.clk_domain
1707conf_table_reported=true
1708device_bus_width=8
1709device_rowbuffer_size=1024
--- 694 unchanged lines hidden (view full) ---
2404number=0
2405output=true
2406port=3456
2407
2408[system.toL2Bus]
2409type=CoherentXBar
2410clk_domain=system.cpu_clk_domain
2411eventq_index=0
2412header_cycles=1
2413snoop_filter=Null
2414system=system
2415use_default_range=false
2416width=8
2417master=system.l2c.cpu_side
2418slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
2419
2420[system.vncserver]
2421type=VncServer
2422eventq_index=0
2423frame_capture=false
2424number=0
2425port=5900
2426
2427[system.voltage_domain]
2428type=VoltageDomain
2429eventq_index=0
2430voltage=1.000000
2431