| stats.txt (9924:31ef410b6843) | stats.txt (9978:81d7551dd3be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.524310 # Number of seconds simulated 4sim_ticks 2524309551500 # Number of ticks simulated 5final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.525141 # Number of seconds simulated 4sim_ticks 2525141046500 # Number of ticks simulated 5final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 65403 # Simulator instruction rate (inst/s) 8host_op_rate 84155 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2737677908 # Simulator tick rate (ticks/s) 10host_mem_usage 401408 # Number of bytes of host memory used 11host_seconds 922.06 # Real time elapsed on the host 12sim_insts 60305560 # Number of instructions simulated 13sim_ops 77596391 # Number of ops (including micro ops) simulated | 7host_inst_rate 61643 # Simulator instruction rate (inst/s) 8host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2581152882 # Simulator tick rate (ticks/s) 10host_mem_usage 426780 # Number of bytes of host memory used 11host_seconds 978.30 # Real time elapsed on the host 12sim_insts 60305756 # Number of instructions simulated 13sim_ops 77596741 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory | 15system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory | 24system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory |
| 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory | 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller 53system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller 54system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 55system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 56system.physmem.bytesRead 966197440 # Total number of bytes read from memory 57system.physmem.bytesWritten 52040704 # Total number of bytes written to memory 58system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize() 59system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize() 60system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q 61system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed 62system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis 78system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis 94system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 95system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 96system.physmem.totGap 2524308440000 # Total gap between requests 97system.physmem.readPktSize::0 0 # Categorize read packet sizes 98system.physmem.readPktSize::1 0 # Categorize read packet sizes 99system.physmem.readPktSize::2 36 # Categorize read packet sizes 100system.physmem.readPktSize::3 14942208 # Categorize read packet sizes 101system.physmem.readPktSize::4 0 # Categorize read packet sizes 102system.physmem.readPktSize::5 0 # Categorize read packet sizes 103system.physmem.readPktSize::6 154591 # Categorize read packet sizes 104system.physmem.writePktSize::0 0 # Categorize write packet sizes 105system.physmem.writePktSize::1 0 # Categorize write packet sizes 106system.physmem.writePktSize::2 754018 # Categorize write packet sizes 107system.physmem.writePktSize::3 0 # Categorize write packet sizes 108system.physmem.writePktSize::4 0 # Categorize write packet sizes 109system.physmem.writePktSize::5 0 # Categorize write packet sizes 110system.physmem.writePktSize::6 59118 # Categorize write packet sizes 111system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see | 33system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15096843 # Number of read requests accepted 53system.physmem.writeReqs 813143 # Number of write requests accepted 54system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue 55system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue 56system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM 57system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue 58system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM 59system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side 60system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side 61system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue 62system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one 63system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write 64system.physmem.perBankRdBursts::0 943582 # Per bank write bursts 65system.physmem.perBankRdBursts::1 943145 # Per bank write bursts 66system.physmem.perBankRdBursts::2 939291 # Per bank write bursts 67system.physmem.perBankRdBursts::3 939307 # Per bank write bursts 68system.physmem.perBankRdBursts::4 943115 # Per bank write bursts 69system.physmem.perBankRdBursts::5 943141 # Per bank write bursts 70system.physmem.perBankRdBursts::6 939138 # Per bank write bursts 71system.physmem.perBankRdBursts::7 938546 # Per bank write bursts 72system.physmem.perBankRdBursts::8 943996 # Per bank write bursts 73system.physmem.perBankRdBursts::9 943390 # Per bank write bursts 74system.physmem.perBankRdBursts::10 938426 # Per bank write bursts 75system.physmem.perBankRdBursts::11 937974 # Per bank write bursts 76system.physmem.perBankRdBursts::12 943928 # Per bank write bursts 77system.physmem.perBankRdBursts::13 943533 # Per bank write bursts 78system.physmem.perBankRdBursts::14 939234 # Per bank write bursts 79system.physmem.perBankRdBursts::15 938672 # Per bank write bursts 80system.physmem.perBankWrBursts::0 6704 # Per bank write bursts 81system.physmem.perBankWrBursts::1 6457 # Per bank write bursts 82system.physmem.perBankWrBursts::2 6598 # Per bank write bursts 83system.physmem.perBankWrBursts::3 6635 # Per bank write bursts 84system.physmem.perBankWrBursts::4 6561 # Per bank write bursts 85system.physmem.perBankWrBursts::5 6794 # Per bank write bursts 86system.physmem.perBankWrBursts::6 6789 # Per bank write bursts 87system.physmem.perBankWrBursts::7 6723 # Per bank write bursts 88system.physmem.perBankWrBursts::8 7136 # Per bank write bursts 89system.physmem.perBankWrBursts::9 6877 # Per bank write bursts 90system.physmem.perBankWrBursts::10 6538 # Per bank write bursts 91system.physmem.perBankWrBursts::11 6183 # Per bank write bursts 92system.physmem.perBankWrBursts::12 7149 # Per bank write bursts 93system.physmem.perBankWrBursts::13 6765 # Per bank write bursts 94system.physmem.perBankWrBursts::14 7038 # Per bank write bursts 95system.physmem.perBankWrBursts::15 6899 # Per bank write bursts 96system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 97system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 98system.physmem.totGap 2525139929000 # Total gap between requests 99system.physmem.readPktSize::0 0 # Read request sizes (log2) 100system.physmem.readPktSize::1 0 # Read request sizes (log2) 101system.physmem.readPktSize::2 36 # Read request sizes (log2) 102system.physmem.readPktSize::3 14942208 # Read request sizes (log2) 103system.physmem.readPktSize::4 0 # Read request sizes (log2) 104system.physmem.readPktSize::5 0 # Read request sizes (log2) 105system.physmem.readPktSize::6 154599 # Read request sizes (log2) 106system.physmem.writePktSize::0 0 # Write request sizes (log2) 107system.physmem.writePktSize::1 0 # Write request sizes (log2) 108system.physmem.writePktSize::2 754018 # Write request sizes (log2) 109system.physmem.writePktSize::3 0 # Write request sizes (log2) 110system.physmem.writePktSize::4 0 # Write request sizes (log2) 111system.physmem.writePktSize::5 0 # Write request sizes (log2) 112system.physmem.writePktSize::6 59125 # Write request sizes (log2) 113system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 132system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see | 145system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 171system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 175system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation 410system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays 411system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests 412system.physmem.totBusLat 75453215000 # Total cycles spent in databus access 413system.physmem.totBankLat 15307050000 # Total cycles spent in bank access 414system.physmem.avgQLat 19314.15 # Average queueing delay per request 415system.physmem.avgBankLat 1014.34 # Average bank access latency per request 416system.physmem.avgBusLat 5000.00 # Average bus latency per request 417system.physmem.avgMemAccLat 25328.49 # Average memory access latency 418system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s 419system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s 420system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s 421system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s 422system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 423system.physmem.busUtil 3.15 # Data bus utilization in percentage 424system.physmem.avgRdQLen 0.15 # Average read queue length over time 425system.physmem.avgWrQLen 14.41 # Average write queue length over time 426system.physmem.readRowHits 15065383 # Number of row buffer hits during reads 427system.physmem.writeRowHits 94229 # Number of row buffer hits during writes 428system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads 429system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes 430system.physmem.avgGap 158662.04 # Average gap between requests | 177system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation 181system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation 606system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation 607system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation 608system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation 609system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation 610system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation 611system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation 612system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation 613system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation 614system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation 615system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation 616system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation 617system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation 618system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation 619system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation 620system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation 621system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation 622system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation 623system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation 624system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation 625system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation 626system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation 627system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation 628system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation 629system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation 630system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation 631system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation 632system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation 633system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation 634system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation 635system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation 636system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation 637system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation 638system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation 639system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation 640system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation 641system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation 642system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation 643system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation 644system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation 645system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation 646system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation 647system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation 648system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation 649system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation 650system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation 651system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation 652system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation 653system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation 654system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation 655system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation 656system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation 657system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation 658system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation 659system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation 660system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation 661system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation 662system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation 663system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation 664system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation 665system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation 666system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation 667system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation 668system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation 669system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation 670system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation 671system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation 672system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation 673system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation 674system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation 675system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation 676system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation 677system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation 678system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation 679system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation 680system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation 681system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation 682system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation 683system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation 684system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation 685system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation 686system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation 687system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation 688system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation 689system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation 690system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation 691system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation 692system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation 693system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation 694system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation 695system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation 696system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation 697system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation 698system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation 699system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation 700system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation 701system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation 702system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation 703system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation 704system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation 705system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation 706system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation 707system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation 708system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation 709system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation 710system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation 711system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation 712system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation 713system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation 714system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation 715system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation 716system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation 717system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation 718system.physmem.totQLat 365610387500 # Total ticks spent queuing 719system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM 720system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers 721system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks 722system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst 723system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst 724system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 725system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst 726system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s 727system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s 728system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s 729system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s 730system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 731system.physmem.busUtil 3.00 # Data bus utilization in percentage 732system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads 733system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 734system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing 735system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing 736system.physmem.readRowHits 14986740 # Number of row buffer hits during reads 737system.physmem.writeRowHits 93410 # Number of row buffer hits during writes 738system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 739system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes 740system.physmem.avgGap 158714.15 # Average gap between requests 741system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined 742system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state |
| 431system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 432system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 433system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 434system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 435system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 436system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 437system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 438system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 439system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 440system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 441system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 442system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) | 743system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 744system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 745system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 746system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 747system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 748system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 749system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 750system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 751system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 752system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 753system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 754system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) |
| 443system.membus.throughput 54917647 # Throughput (bytes/s) | 755system.membus.throughput 54899945 # Throughput (bytes/s) |
| 444system.membus.trans_dist::ReadReq 16149440 # Transaction distribution 445system.membus.trans_dist::ReadResp 16149440 # Transaction distribution 446system.membus.trans_dist::WriteReq 763332 # Transaction distribution 447system.membus.trans_dist::WriteResp 763332 # Transaction distribution | 756system.membus.trans_dist::ReadReq 16149440 # Transaction distribution 757system.membus.trans_dist::ReadResp 16149440 # Transaction distribution 758system.membus.trans_dist::WriteReq 763332 # Transaction distribution 759system.membus.trans_dist::WriteResp 763332 # Transaction distribution |
| 448system.membus.trans_dist::Writeback 59118 # Transaction distribution 449system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution 450system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 451system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution 452system.membus.trans_dist::ReadExReq 131433 # Transaction distribution 453system.membus.trans_dist::ReadExResp 131433 # Transaction distribution 454system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes) | 760system.membus.trans_dist::Writeback 59125 # Transaction distribution 761system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution 762system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 763system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution 764system.membus.trans_dist::ReadExReq 131442 # Transaction distribution 765system.membus.trans_dist::ReadExResp 131442 # Transaction distribution 766system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) |
| 455system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 456system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 767system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 768system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 769system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 458system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes) 459system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes) | 770system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) 771system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) |
| 460system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 461system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) | 772system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 773system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) |
| 462system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes) 463system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes) | 774system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) 775system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) |
| 464system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 465system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 466system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 776system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 777system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 778system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 467system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) 468system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes) | 779system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) 780system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) |
| 469system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 470system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) | 781system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 782system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) |
| 471system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes) 472system.membus.data_through_bus 138629141 # Total data (bytes) | 783system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) 784system.membus.data_through_bus 138630105 # Total data (bytes) |
| 473system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 785system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 474system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks) | 786system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) |
| 475system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 476system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 477system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 787system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 788system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 789system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 478system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks) | 790system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) |
| 479system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 480system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 481system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 791system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 792system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 793system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 482system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks) | 794system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) |
| 483system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 795system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 484system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks) | 796system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) |
| 485system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 797system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 486system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks) | 798system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) |
| 487system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 488system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 489system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 490system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 491system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 492system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 493system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 799system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 800system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 801system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 802system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 803system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 804system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 805system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 494system.iobus.throughput 48301509 # Throughput (bytes/s) 495system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution 496system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution | 806system.iobus.throughput 48285606 # Throughput (bytes/s) 807system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution 808system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution |
| 497system.iobus.trans_dist::WriteReq 8157 # Transaction distribution 498system.iobus.trans_dist::WriteResp 8157 # Transaction distribution 499system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) | 809system.iobus.trans_dist::WriteReq 8157 # Transaction distribution 810system.iobus.trans_dist::WriteResp 8157 # Transaction distribution 811system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) |
| 500system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) | 812system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) |
| 501system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 502system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 503system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 504system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 505system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 506system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 507system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 508system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 514system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 515system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 516system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 517system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 518system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 519system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 520system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 521system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) | 813system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 814system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 815system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 816system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 817system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 818system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 819system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 820system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 826system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 827system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 828system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 829system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 830system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 831system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 832system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 833system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) |
| 522system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes) | 834system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes) |
| 523system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 524system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) | 835system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 836system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) |
| 525system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes) | 837system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes) |
| 526system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) | 838system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) |
| 527system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) | 839system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) |
| 528system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 529system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 530system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 531system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 532system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 533system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 534system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 535system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 541system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 542system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 543system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 544system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 545system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 546system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 547system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 548system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) | 840system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 841system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 842system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 843system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 844system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 845system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 846system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 847system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 853system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 854system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 855system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 856system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 857system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 858system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 859system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 860system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 549system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes) | 861system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes) |
| 550system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 551system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) | 862system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 863system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) |
| 552system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes) 553system.iobus.data_through_bus 121927961 # Total data (bytes) | 864system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes) 865system.iobus.data_through_bus 121927965 # Total data (bytes) |
| 554system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 555system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 866system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 867system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 556system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks) | 868system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) |
| 557system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 558system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 559system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 561system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 562system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 563system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 564system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 594system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 595system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 596system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 597system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 598system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 599system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 600system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 601system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 869system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 870system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 871system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 872system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 873system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 874system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 875system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 876system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) --- 29 unchanged lines hidden (view full) --- 906system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 907system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 908system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 909system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 910system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 911system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 912system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 913system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) |
| 602system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks) | 914system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) |
| 603system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 915system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 604system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks) | 916system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) |
| 605system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) | 917system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) |
| 606system.cpu.branchPred.lookups 14390442 # Number of BP lookups 607system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted 608system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect 609system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups 610system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits | 918system.cpu.branchPred.lookups 14384905 # Number of BP lookups 919system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted 920system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect 921system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups 922system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits |
| 611system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 923system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 612system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage 613system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target. 614system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions. | 924system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage 925system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. 926system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. |
| 615system.cpu.dtb.inst_hits 0 # ITB inst hits 616system.cpu.dtb.inst_misses 0 # ITB inst misses | 927system.cpu.dtb.inst_hits 0 # ITB inst hits 928system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 617system.cpu.dtb.read_hits 51188083 # DTB read hits 618system.cpu.dtb.read_misses 64353 # DTB read misses 619system.cpu.dtb.write_hits 11697459 # DTB write hits 620system.cpu.dtb.write_misses 15788 # DTB write misses | 929system.cpu.dtb.read_hits 51179212 # DTB read hits 930system.cpu.dtb.read_misses 64531 # DTB read misses 931system.cpu.dtb.write_hits 11698539 # DTB write hits 932system.cpu.dtb.write_misses 15837 # DTB write misses |
| 621system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 622system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 623system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 624system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 933system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 934system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 935system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 936system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 625system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB 626system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions 627system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch | 937system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB 938system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions 939system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch |
| 628system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 940system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 629system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions 630system.cpu.dtb.read_accesses 51252436 # DTB read accesses 631system.cpu.dtb.write_accesses 11713247 # DTB write accesses | 941system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions 942system.cpu.dtb.read_accesses 51243743 # DTB read accesses 943system.cpu.dtb.write_accesses 11714376 # DTB write accesses |
| 632system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 944system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 633system.cpu.dtb.hits 62885542 # DTB hits 634system.cpu.dtb.misses 80141 # DTB misses 635system.cpu.dtb.accesses 62965683 # DTB accesses 636system.cpu.itb.inst_hits 11520428 # ITB inst hits 637system.cpu.itb.inst_misses 11439 # ITB inst misses | 945system.cpu.dtb.hits 62877751 # DTB hits 946system.cpu.dtb.misses 80368 # DTB misses 947system.cpu.dtb.accesses 62958119 # DTB accesses 948system.cpu.itb.inst_hits 11513998 # ITB inst hits 949system.cpu.itb.inst_misses 11344 # ITB inst misses |
| 638system.cpu.itb.read_hits 0 # DTB read hits 639system.cpu.itb.read_misses 0 # DTB read misses 640system.cpu.itb.write_hits 0 # DTB write hits 641system.cpu.itb.write_misses 0 # DTB write misses 642system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 643system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 644system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 645system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 950system.cpu.itb.read_hits 0 # DTB read hits 951system.cpu.itb.read_misses 0 # DTB read misses 952system.cpu.itb.write_hits 0 # DTB write hits 953system.cpu.itb.write_misses 0 # DTB write misses 954system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 955system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 956system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 957system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 646system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB | 958system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB |
| 647system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 648system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 649system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 959system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 960system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 961system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 650system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions | 962system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions |
| 651system.cpu.itb.read_accesses 0 # DTB read accesses 652system.cpu.itb.write_accesses 0 # DTB write accesses | 963system.cpu.itb.read_accesses 0 # DTB read accesses 964system.cpu.itb.write_accesses 0 # DTB write accesses |
| 653system.cpu.itb.inst_accesses 11531867 # ITB inst accesses 654system.cpu.itb.hits 11520428 # DTB hits 655system.cpu.itb.misses 11439 # DTB misses 656system.cpu.itb.accesses 11531867 # DTB accesses 657system.cpu.numCycles 473080437 # number of cpu cycles simulated | 965system.cpu.itb.inst_accesses 11525342 # ITB inst accesses 966system.cpu.itb.hits 11513998 # DTB hits 967system.cpu.itb.misses 11344 # DTB misses 968system.cpu.itb.accesses 11525342 # DTB accesses 969system.cpu.numCycles 474882944 # number of cpu cycles simulated |
| 658system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 659system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 970system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 971system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 660system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss 661system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed 662system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered 663system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken 664system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked 665system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing 666system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb 667system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked 668system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 669system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps 670system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions 671system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR 672system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched 673system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed 674system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed 675system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total) 676system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total) 677system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total) | 972system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss 973system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed 974system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered 975system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken 976system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked 977system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing 978system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb 979system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked 980system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 981system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps 982system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions 983system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR 984system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched 985system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed 986system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed 987system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) 988system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) 989system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) |
| 678system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 990system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 679system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total) 680system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total) 681system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total) 682system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total) 683system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total) 684system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total) 685system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total) 686system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total) 687system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total) | 991system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) 992system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) 993system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) 994system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) 995system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) 996system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) 997system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) 998system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) 999system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) |
| 688system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 689system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 690system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 1000system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1001system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1002system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 691system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total) 692system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle 693system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle 694system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle 695system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked 696system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running 697system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking 698system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing 699system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch 700system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction 701system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode 702system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode 703system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing 704system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle 705system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking 706system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst 707system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running 708system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking 709system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename 710system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full 711system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full 712system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full 713system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers 714system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed 715system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made 716system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups 717system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups 718system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed 719system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing 720system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed 721system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed 722system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer 723system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit. 724system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit. 725system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads. 726system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores. 727system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec) 728system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ 729system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued 730system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued 731system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling 732system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph 733system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed 734system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle 735system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle 736system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle | 1003system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) 1004system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle 1005system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle 1006system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle 1007system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked 1008system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running 1009system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking 1010system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing 1011system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch 1012system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction 1013system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode 1014system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode 1015system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing 1016system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle 1017system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking 1018system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst 1019system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running 1020system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking 1021system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename 1022system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full 1023system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full 1024system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full 1025system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers 1026system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed 1027system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made 1028system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups 1029system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups 1030system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed 1031system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing 1032system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed 1033system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed 1034system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer 1035system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. 1036system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. 1037system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. 1038system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. 1039system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) 1040system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ 1041system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued 1042system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued 1043system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling 1044system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph 1045system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed 1046system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle 1047system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle 1048system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle |
| 737system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1049system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 738system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle 739system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle 740system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle 741system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle 742system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle 743system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle 744system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle 745system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle 746system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle | 1050system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle 1051system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle 1052system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle 1053system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle 1054system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle 1055system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle 1056system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle 1057system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle 1058system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle |
| 747system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 748system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 749system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 1059system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1060system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1061system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 750system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle | 1062system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle |
| 751system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1063system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 752system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available 753system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available | 1064system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available 1065system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available |
| 754system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available 755system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available 756system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available 757system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available 758system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available 759system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available 760system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available 761system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 773system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available 774system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available 775system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available 776system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available 777system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available 778system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available 779system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available 780system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available | 1066system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available 1067system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available 1068system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available 1069system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available 1070system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available 1071system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available 1072system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available 1073system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 1085system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available 1086system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available 1087system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available 1088system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available 1089system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available 1090system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available 1091system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available 1092system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available |
| 781system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available 782system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available | 1093system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available 1094system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available |
| 783system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 784system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 785system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued | 1095system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1096system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1097system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued |
| 786system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued 787system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued | 1098system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued 1099system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued |
| 788system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued 789system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued 790system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued 791system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued 792system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued 793system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued 794system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued 795system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued 796system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued 797system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued 798system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued 799system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued | 1100system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued 1101system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued 1102system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued 1103system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued 1104system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued 1105system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued 1106system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued 1107system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued 1108system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued 1109system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued 1110system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued 1111system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued |
| 800system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued | 1112system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued |
| 801system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued 802system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued 803system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued | 1113system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued 1114system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued 1115system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued |
| 804system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued | 1116system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued |
| 805system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued 806system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued 807system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued 808system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued 809system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued 810system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued | 1117system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued 1118system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued 1119system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued 1120system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued 1121system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued 1122system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued |
| 811system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued | 1123system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued |
| 812system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued | 1124system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued |
| 813system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued | 1125system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued |
| 814system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued | 1126system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued |
| 815system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued 816system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued | 1127system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued 1128system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued |
| 817system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 818system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1129system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1130system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 819system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued 820system.cpu.iq.rate 0.259812 # Inst issue rate 821system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested 822system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst) 823system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads 824system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes 825system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses 826system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads 827system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes 828system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses 829system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses 830system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses 831system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores | 1131system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued 1132system.cpu.iq.rate 0.258795 # Inst issue rate 1133system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested 1134system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) 1135system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads 1136system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes 1137system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses 1138system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads 1139system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes 1140system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses 1141system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses 1142system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses 1143system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores |
| 832system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1144system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 833system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed 834system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed 835system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations 836system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed | 1145system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed 1146system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed 1147system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations 1148system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed |
| 837system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 838system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1149system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1150system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 839system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled 840system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked | 1151system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled 1152system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked |
| 841system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 1153system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 842system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing 843system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking 844system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking 845system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ 846system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch 847system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions 848system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions 849system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions 850system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall 851system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall 852system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations 853system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly 854system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly 855system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute 856system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions 857system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed 858system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute | 1154system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing 1155system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking 1156system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking 1157system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ 1158system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch 1159system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions 1160system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions 1161system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions 1162system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall 1163system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall 1164system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations 1165system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly 1166system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly 1167system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute 1168system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions 1169system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed 1170system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute |
| 859system.cpu.iew.exec_swp 0 # number of swp insts executed | 1171system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 860system.cpu.iew.exec_nop 221034 # number of nop insts executed 861system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed 862system.cpu.iew.exec_branches 11474602 # Number of branches executed 863system.cpu.iew.exec_stores 12209197 # Number of stores executed 864system.cpu.iew.exec_rate 0.255417 # Inst execution rate 865system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit 866system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back 867system.cpu.iew.wb_producers 47030253 # num instructions producing a value 868system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value | 1172system.cpu.iew.exec_nop 221869 # number of nop insts executed 1173system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed 1174system.cpu.iew.exec_branches 11475076 # Number of branches executed 1175system.cpu.iew.exec_stores 12210518 # Number of stores executed 1176system.cpu.iew.exec_rate 0.254424 # Inst execution rate 1177system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit 1178system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back 1179system.cpu.iew.wb_producers 47026181 # num instructions producing a value 1180system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value |
| 869system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 1181system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 870system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle 871system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back | 1182system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle 1183system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back |
| 872system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 1184system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 873system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit 874system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards 875system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted 876system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle 877system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle 878system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle | 1185system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit 1186system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards 1187system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted 1188system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle 1189system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle 1190system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle |
| 879system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 1191system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 880system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle 881system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle 882system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle 883system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle 884system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle 885system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle 886system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle 887system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle 888system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle | 1192system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle 1193system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle 1194system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle 1195system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle 1196system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle 1197system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle 1198system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle 1199system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle 1200system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle |
| 889system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 890system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 891system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 1201system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 1202system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 1203system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 892system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle 893system.cpu.commit.committedInsts 60455941 # Number of instructions committed 894system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed | 1204system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle 1205system.cpu.commit.committedInsts 60456137 # Number of instructions committed 1206system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed |
| 895system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 1207system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 896system.cpu.commit.refs 27385481 # Number of memory references committed 897system.cpu.commit.loads 15653838 # Number of loads committed 898system.cpu.commit.membars 403568 # Number of memory barriers committed 899system.cpu.commit.branches 9961054 # Number of branches committed | 1208system.cpu.commit.refs 27385736 # Number of memory references committed 1209system.cpu.commit.loads 15654008 # Number of loads committed 1210system.cpu.commit.membars 403573 # Number of memory barriers committed 1211system.cpu.commit.branches 9961077 # Number of branches committed |
| 900system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. | 1212system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. |
| 901system.cpu.commit.int_insts 68852229 # Number of committed integer instructions. 902system.cpu.commit.function_calls 991205 # Number of function calls committed. 903system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached | 1213system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. 1214system.cpu.commit.function_calls 991208 # Number of function calls committed. 1215system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached |
| 904system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 1216system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 905system.cpu.rob.rob_reads 239241509 # The number of ROB reads 906system.cpu.rob.rob_writes 195965670 # The number of ROB writes 907system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself 908system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling 909system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 910system.cpu.committedInsts 60305560 # Number of Instructions Simulated 911system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated 912system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated 913system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction 914system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads 915system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle 916system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads 917system.cpu.int_regfile_reads 547265501 # number of integer regfile reads 918system.cpu.int_regfile_writes 87536109 # number of integer regfile writes 919system.cpu.fp_regfile_reads 8349 # number of floating regfile reads 920system.cpu.fp_regfile_writes 2916 # number of floating regfile writes 921system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads 922system.cpu.misc_regfile_writes 831835 # number of misc regfile writes 923system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s) 924system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution 925system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution | 1217system.cpu.rob.rob_reads 240636318 # The number of ROB reads 1218system.cpu.rob.rob_writes 195934369 # The number of ROB writes 1219system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself 1220system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling 1221system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1222system.cpu.committedInsts 60305756 # Number of Instructions Simulated 1223system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated 1224system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated 1225system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction 1226system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads 1227system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle 1228system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads 1229system.cpu.int_regfile_reads 547208469 # number of integer regfile reads 1230system.cpu.int_regfile_writes 87526188 # number of integer regfile writes 1231system.cpu.fp_regfile_reads 8624 # number of floating regfile reads 1232system.cpu.fp_regfile_writes 3008 # number of floating regfile writes 1233system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads 1234system.cpu.misc_regfile_writes 831837 # number of misc regfile writes 1235system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) 1236system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution 1237system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution |
| 926system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution 927system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution | 1238system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution 1239system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution |
| 928system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution | 1240system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution |
| 929system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution | 1241system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution |
| 930system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution 934system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes) 937system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes) 938system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes) 939system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes) 940system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes) 941system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes) 942system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes) 943system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes) 944system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes) 945system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes) 946system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks) | 1242system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution 1243system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution 1244system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution 1245system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution 1246system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) 1247system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) 1248system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) 1249system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) 1250system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) 1251system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) 1252system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) 1253system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) 1254system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) 1255system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) 1256system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) 1257system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) 1258system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) |
| 947system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1259system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 948system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks) | 1260system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks) |
| 949system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1261system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 950system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks) | 1262system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks) |
| 951system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1263system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 952system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks) | 1264system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks) |
| 953system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1265system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 954system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks) | 1266system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks) |
| 955system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1267system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 956system.cpu.icache.tags.replacements 979660 # number of replacements 957system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use 958system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks. 959system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks. 960system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks. 961system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit. 962system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor 963system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy 964system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy 965system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits 966system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits 967system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits 968system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits 969system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits 970system.cpu.icache.overall_hits::total 10456897 # number of overall hits 971system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses 972system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses 973system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses 974system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses 975system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses 976system.cpu.icache.overall_misses::total 1059959 # number of overall misses 977system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles 978system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles 979system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles 980system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles 981system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles 982system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles 983system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses) 984system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses) 985system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses 986system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses 987system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses 988system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses 989system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses 990system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses 991system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses 992system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses 993system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses 994system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses 995system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency 996system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency 997system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency 998system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency 999system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency 1000system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency 1001system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked | 1268system.cpu.icache.tags.replacements 980741 # number of replacements 1269system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use 1270system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks. 1271system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks. 1272system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks. 1273system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit. 1274system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor 1275system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy 1276system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy 1277system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits 1278system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits 1279system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits 1280system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits 1281system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits 1282system.cpu.icache.overall_hits::total 10449649 # number of overall hits 1283system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses 1284system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses 1285system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses 1286system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses 1287system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses 1288system.cpu.icache.overall_misses::total 1060761 # number of overall misses 1289system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles 1290system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles 1291system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles 1292system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles 1293system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles 1294system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles 1295system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) 1296system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) 1297system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses 1298system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses 1299system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses 1300system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses 1301system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses 1302system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses 1303system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses 1304system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses 1305system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses 1306system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses 1307system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency 1308system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency 1309system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency 1310system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency 1311system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency 1312system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency 1313system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked |
| 1002system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1314system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1003system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked | 1315system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked |
| 1004system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1316system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1005system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked | 1317system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked |
| 1006system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1007system.cpu.icache.fast_writes 0 # number of fast writes performed 1008system.cpu.icache.cache_copies 0 # number of cache copies performed | 1318system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1319system.cpu.icache.fast_writes 0 # number of fast writes performed 1320system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 1009system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits 1010system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits 1011system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits 1012system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits 1013system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits 1014system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits 1015system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses 1016system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses 1017system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses 1018system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses 1019system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses 1020system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses 1021system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles 1022system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles 1023system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles 1024system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles 1025system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles 1026system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles 1027system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles 1028system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles 1029system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles 1030system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles 1031system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses 1032system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses 1033system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses 1034system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses 1035system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses 1036system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses 1037system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency 1038system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency 1039system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency 1040system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency 1041system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency 1042system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency | 1321system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits 1322system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits 1323system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits 1324system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits 1325system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits 1326system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits 1327system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses 1328system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses 1329system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses 1330system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses 1331system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses 1332system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses 1333system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles 1334system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles 1335system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles 1336system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles 1337system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles 1338system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles 1339system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles 1340system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles 1341system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles 1342system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles 1343system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses 1344system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses 1345system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses 1346system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses 1347system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses 1348system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses 1349system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency 1350system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency 1351system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency 1352system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency 1353system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency 1354system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency |
| 1043system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1044system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1045system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1046system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1047system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1355system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1356system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1357system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1358system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1359system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1048system.cpu.l2cache.tags.replacements 64363 # number of replacements 1049system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use 1050system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks. 1051system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks. 1052system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks. 1053system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit. 1054system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor 1055system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor 1056system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor 1057system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor 1058system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor 1059system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy 1060system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy | 1360system.cpu.l2cache.tags.replacements 64371 # number of replacements 1361system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use 1362system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. 1363system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. 1364system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. 1365system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit. 1366system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor 1367system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor 1368system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor 1369system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor 1370system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor 1371system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy 1372system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy |
| 1061system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 1373system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 1062system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy 1063system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy 1064system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy 1065system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits 1066system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits 1067system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits 1068system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits 1069system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits 1070system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits 1071system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits 1072system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits 1073system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits | 1374system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy 1375system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy 1376system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy 1377system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits 1378system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits 1379system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits 1380system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits 1381system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits 1382system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits 1383system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits 1384system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits 1385system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits |
| 1074system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 1075system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits | 1386system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 1387system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits |
| 1076system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits 1077system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits 1078system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits 1079system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits 1080system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits 1081system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits 1082system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits 1083system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits 1084system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits 1085system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits 1086system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits 1087system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits 1088system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses 1089system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1090system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses 1091system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses 1092system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses 1093system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses 1094system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses 1095system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1096system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1097system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses 1098system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses 1099system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses 1100system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1101system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses 1102system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses 1103system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses 1104system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses 1105system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1106system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses 1107system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses 1108system.cpu.l2cache.overall_misses::total 156307 # number of overall misses 1109system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles 1110system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles 1111system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles 1112system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles 1113system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles 1114system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles 1115system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles 1116system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles 1117system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles 1118system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles 1119system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles 1120system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles 1121system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles 1122system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles 1123system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles 1124system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles 1125system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles 1126system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles 1127system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles 1128system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses) 1129system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses) 1130system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses) 1131system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses) 1132system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses) 1133system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses) 1134system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses) | 1388system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits 1389system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits 1390system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits 1391system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits 1392system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits 1393system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits 1394system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits 1395system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits 1396system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits 1397system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits 1398system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits 1399system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits 1400system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses 1401system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 1402system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses 1403system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses 1404system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses 1405system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses 1406system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses 1407system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1408system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1409system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses 1410system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses 1411system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses 1412system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 1413system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses 1414system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses 1415system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses 1416system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses 1417system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 1418system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses 1419system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses 1420system.cpu.l2cache.overall_misses::total 156313 # number of overall misses 1421system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles 1422system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles 1423system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles 1424system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles 1425system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles 1426system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles 1427system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles 1428system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles 1429system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles 1430system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles 1431system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles 1432system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles 1433system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles 1434system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles 1435system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles 1436system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles 1437system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles 1438system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles 1439system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles 1440system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses) 1441system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses) 1442system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses) 1443system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses) 1444system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses) 1445system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses) 1446system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses) |
| 1135system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) 1136system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) | 1447system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses) 1448system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses) |
| 1137system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses) 1138system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) 1139system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses) 1140system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses) 1141system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses 1142system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses 1143system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses 1144system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses 1145system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses 1146system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses 1147system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses 1148system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses 1149system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses 1150system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses 1151system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses 1152system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses 1153system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses 1154system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses 1155system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses 1156system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses 1157system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses 1158system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses 1159system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses 1160system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses 1161system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses 1162system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses 1163system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses 1164system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses 1165system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses 1166system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses 1167system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses 1168system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses 1169system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses 1170system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses 1171system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses 1172system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency 1173system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency 1174system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency 1175system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency 1176system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency 1177system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency 1178system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency 1179system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency 1180system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency 1181system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency 1182system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency 1183system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency 1184system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency 1185system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency 1186system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency 1187system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency 1188system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency 1189system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency 1190system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency | 1449system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) 1450system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) 1451system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses) 1452system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses) 1453system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses 1454system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses 1455system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses 1456system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses 1457system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses 1458system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses 1459system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses 1460system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses 1461system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses 1462system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses 1463system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses 1464system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses 1465system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses 1466system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses 1467system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses 1468system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses 1469system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses 1470system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 1471system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 1472system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses 1473system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses 1474system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses 1475system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses 1476system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses 1477system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses 1478system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses 1479system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses 1480system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses 1481system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses 1482system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses 1483system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses 1484system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency 1485system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency 1486system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency 1487system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency 1488system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency 1489system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency 1490system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency 1491system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency 1492system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency 1493system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency 1494system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency 1495system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency 1496system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency 1497system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency 1498system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency 1499system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency 1500system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency 1501system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency 1502system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency |
| 1191system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1192system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1193system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1194system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1195system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1196system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1197system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1198system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1503system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1504system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1505system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1506system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1507system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1508system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1509system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1510system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1199system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks 1200system.cpu.l2cache.writebacks::total 59118 # number of writebacks 1201system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits | 1511system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks 1512system.cpu.l2cache.writebacks::total 59125 # number of writebacks 1513system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits |
| 1202system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits | 1514system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits |
| 1203system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 1204system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits | 1515system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 1516system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits |
| 1205system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits | 1517system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits |
| 1206system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits 1207system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits | 1518system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits 1519system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits |
| 1208system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits | 1520system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits |
| 1209system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits 1210system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses 1211system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1212system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses 1213system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses 1214system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses 1215system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses 1216system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses 1217system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1218system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1219system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses 1220system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses 1221system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses 1222system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1223system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses 1224system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses 1225system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses 1226system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses 1227system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1228system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses 1229system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses 1230system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses 1231system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles 1232system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles 1233system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles 1234system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles 1235system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles 1236system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles 1237system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles 1238system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 1239system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles 1240system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles 1241system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles 1242system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles 1243system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles 1244system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles 1245system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles 1246system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles 1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles 1248system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles 1249system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles 1250system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles 1251system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles 1252system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles 1253system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles 1254system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles 1255system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles 1256system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles 1257system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles 1258system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles 1259system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles 1260system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses 1261system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses 1262system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses 1263system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses 1264system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses 1265system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses 1266system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses 1267system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses 1268system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses 1269system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses 1270system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses 1271system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses 1272system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses 1273system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses 1274system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses 1275system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses 1276system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses 1277system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses 1278system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses 1279system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses 1280system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses 1281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency 1282system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency 1283system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency 1284system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency 1285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency 1286system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency 1287system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency | 1521system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits 1522system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses 1523system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses 1524system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses 1525system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses 1526system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses 1527system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses 1528system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses 1529system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1530system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1531system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses 1532system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses 1533system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses 1534system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses 1535system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses 1536system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses 1537system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses 1538system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses 1539system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses 1540system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses 1541system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses 1542system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses 1543system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles 1544system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles 1545system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles 1546system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles 1547system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles 1548system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles 1549system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles 1550system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1551system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1552system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles 1553system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles 1554system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles 1555system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles 1556system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles 1557system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles 1558system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles 1559system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles 1560system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles 1561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles 1562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles 1563system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles 1564system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles 1565system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles 1566system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles 1567system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles 1568system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles 1569system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles 1570system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles 1571system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles 1572system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses 1573system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses 1574system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses 1575system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses 1576system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses 1577system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses 1578system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses 1579system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 1580system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 1581system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses 1582system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses 1583system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses 1584system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses 1585system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses 1586system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses 1587system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses 1588system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses 1589system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses 1590system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses 1591system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses 1592system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses 1593system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency 1594system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency 1595system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency 1596system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency 1597system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency 1598system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency 1599system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency |
| 1288system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1289system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1600system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1601system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1290system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency 1291system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency 1292system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency 1293system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1294system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency 1295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency 1296system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency 1297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency 1298system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency 1300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency 1301system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency | 1602system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency 1603system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency 1604system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency 1605system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency 1606system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency 1607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency 1608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency 1609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency 1610system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency 1611system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency 1612system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency 1613system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency |
| 1302system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1303system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1304system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1305system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1306system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1307system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1308system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1309system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1310system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1614system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1615system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1616system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1617system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1618system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1619system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1620system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1621system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1622system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1311system.cpu.dcache.tags.replacements 643614 # number of replacements 1312system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use 1313system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks. 1314system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks. 1315system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks. 1316system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit. 1317system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor | 1623system.cpu.dcache.tags.replacements 643382 # number of replacements 1624system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use 1625system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. 1626system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. 1627system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. 1628system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. 1629system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor |
| 1318system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1319system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy | 1630system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1631system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy |
| 1320system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits 1321system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits 1322system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits 1323system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits 1324system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits 1325system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits 1326system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits 1327system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits 1328system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits 1329system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits 1330system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits 1331system.cpu.dcache.overall_hits::total 21018772 # number of overall hits 1332system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses 1333system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses 1334system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses 1335system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses 1336system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses 1337system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses 1338system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses 1339system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses 1340system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses 1341system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses 1342system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses 1343system.cpu.dcache.overall_misses::total 3700946 # number of overall misses 1344system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles 1345system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles 1346system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles 1347system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles 1348system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles 1349system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles 1350system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles 1351system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles 1352system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles 1353system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles 1354system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles 1355system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles 1356system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses) 1357system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses) 1358system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses) 1359system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses) 1360system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses) 1361system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses) | 1632system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits 1633system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits 1634system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits 1635system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits 1636system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits 1637system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits 1638system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits 1639system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits 1640system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits 1641system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits 1642system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits 1643system.cpu.dcache.overall_hits::total 21010251 # number of overall hits 1644system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses 1645system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses 1646system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses 1647system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses 1648system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses 1649system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses 1650system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses 1651system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses 1652system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses 1653system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses 1654system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses 1655system.cpu.dcache.overall_misses::total 3701471 # number of overall misses 1656system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles 1657system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles 1658system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles 1659system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles 1660system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles 1661system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles 1662system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles 1663system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles 1664system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles 1665system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles 1666system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles 1667system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles 1668system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) 1669system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) 1670system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) 1671system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) 1672system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) 1673system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) |
| 1362system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) 1363system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) | 1674system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) 1675system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) |
| 1364system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses 1365system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses 1366system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses 1367system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses 1368system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses 1369system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses 1370system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses 1371system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses 1372system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses 1373system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses 1374system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses 1375system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses 1376system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses 1377system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses 1378system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses 1379system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses 1380system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency 1381system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency 1382system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency 1383system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency 1384system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency 1385system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency 1386system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency 1387system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency 1388system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency 1389system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency 1390system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency 1391system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency 1392system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked 1393system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked 1394system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked 1395system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked 1396system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked 1397system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked | 1676system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses 1677system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses 1678system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses 1679system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses 1680system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses 1681system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses 1682system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses 1683system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses 1684system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses 1685system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses 1686system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses 1687system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses 1688system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses 1689system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses 1690system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses 1691system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses 1692system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency 1693system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency 1694system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency 1695system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency 1696system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency 1697system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency 1698system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency 1699system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency 1700system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency 1701system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency 1702system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency 1703system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency 1704system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked 1705system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked 1706system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked 1707system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked 1708system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked 1709system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked |
| 1398system.cpu.dcache.fast_writes 0 # number of fast writes performed 1399system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1710system.cpu.dcache.fast_writes 0 # number of fast writes performed 1711system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1400system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks 1401system.cpu.dcache.writebacks::total 607864 # number of writebacks 1402system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits 1403system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits 1404system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits 1405system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits 1406system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits 1407system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits 1408system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits 1409system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits 1410system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits 1411system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits 1412system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses 1413system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses 1414system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses 1415system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses 1416system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses 1417system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses 1418system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses 1419system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses 1420system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses 1421system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses 1422system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses 1423system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses 1424system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles 1425system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles 1426system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles 1427system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles 1428system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles 1429system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles 1430system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles 1431system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles 1432system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles 1433system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles 1434system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles 1435system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles 1436system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles 1437system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles 1438system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles 1439system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles 1440system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles 1441system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles 1442system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses 1443system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses 1444system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses 1445system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses 1446system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses 1447system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses 1448system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses 1449system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses 1450system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses 1451system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses 1452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses 1453system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses 1454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency 1455system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency 1456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency 1457system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency 1458system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency 1459system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency 1460system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency 1461system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency 1462system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency 1463system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency 1464system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency 1465system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency | 1712system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks 1713system.cpu.dcache.writebacks::total 607699 # number of writebacks 1714system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits 1715system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits 1716system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits 1717system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits 1718system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits 1719system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits 1720system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits 1721system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits 1722system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits 1723system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits 1724system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses 1725system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses 1726system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses 1727system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses 1728system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses 1729system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses 1730system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses 1731system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses 1732system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses 1733system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses 1734system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses 1735system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses 1736system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles 1737system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles 1738system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles 1739system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles 1740system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles 1741system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles 1742system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles 1743system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles 1744system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles 1745system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles 1746system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles 1747system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles 1748system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles 1749system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles 1750system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles 1751system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles 1752system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles 1753system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles 1754system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses 1755system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses 1756system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses 1757system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses 1758system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses 1759system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses 1760system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses 1761system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses 1762system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses 1763system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses 1764system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses 1765system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses 1766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency 1767system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency 1768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency 1769system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency 1770system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency 1771system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency 1772system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency 1773system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency 1774system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency 1775system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency 1776system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency 1777system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency |
| 1466system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1467system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1468system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1469system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1470system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1471system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1473system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1479system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1480system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1481system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1482system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1483system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1484system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1485system.iocache.fast_writes 0 # number of fast writes performed 1486system.iocache.cache_copies 0 # number of cache copies performed | 1778system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1779system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1780system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1781system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1782system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1783system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1784system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1785system.iocache.tags.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1791system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1792system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1793system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1794system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1795system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1796system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1797system.iocache.fast_writes 0 # number of fast writes performed 1798system.iocache.cache_copies 0 # number of cache copies performed |
| 1487system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles 1488system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles 1489system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles 1490system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles | 1799system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles 1800system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles 1801system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles 1802system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles |
| 1491system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1492system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1493system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1494system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1495system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1496system.cpu.kern.inst.arm 0 # number of arm instructions executed 1497system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed 1498 1499---------- End Simulation Statistics ---------- | 1803system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1804system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1805system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1806system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1807system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1808system.cpu.kern.inst.arm 0 # number of arm instructions executed 1809system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed 1810 1811---------- End Simulation Statistics ---------- |