| stats.txt (9661:18755c467503) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.533116 # Number of seconds simulated 4sim_ticks 2533115780500 # Number of ticks simulated 5final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.534279 # Number of seconds simulated 4sim_ticks 2534279149500 # Number of ticks simulated 5final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 64757 # Simulator instruction rate (inst/s) 8host_op_rate 83325 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2720016614 # Simulator tick rate (ticks/s) 10host_mem_usage 398876 # Number of bytes of host memory used 11host_seconds 931.29 # Real time elapsed on the host 12sim_insts 60307726 # Number of instructions simulated 13sim_ops 77599286 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory | 7host_inst_rate 51469 # Simulator instruction rate (inst/s) 8host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2162854547 # Simulator tick rate (ticks/s) 10host_mem_usage 400508 # Number of bytes of host memory used 11host_seconds 1171.73 # Real time elapsed on the host 12sim_insts 60307893 # Number of instructions simulated 13sim_ops 77599512 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory | 17system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory 19system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15096806 # Total number of read requests seen 53system.physmem.writeReqs 813108 # Total number of write requests seen 54system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966195584 # Total number of bytes read from memory 56system.physmem.bytesWritten 52038912 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis | 49system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15098054 # Total number of read requests seen 53system.physmem.writeReqs 813133 # Total number of write requests seen 54system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 966275456 # Total number of bytes read from memory 56system.physmem.bytesWritten 52040512 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis |
| 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry | 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| 94system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2533114676500 # Total gap between requests | 94system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry 95system.physmem.totGap 2534279100000 # Total gap between requests |
| 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes | 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 36 # Categorize read packet sizes |
| 99system.physmem.readPktSize::3 14942208 # Categorize read packet sizes | 99system.physmem.readPktSize::3 14943424 # Categorize read packet sizes |
| 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes | 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 102system.physmem.readPktSize::6 154562 # Categorize read packet sizes | 102system.physmem.readPktSize::6 154594 # Categorize read packet sizes |
| 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes | 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 109system.physmem.writePktSize::6 59090 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see | 109system.physmem.writePktSize::6 59115 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see |
| 128system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see |
| 130system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see | 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 142system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 2829 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see 174system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests 176system.physmem.totBusLat 75482470000 # Total cycles spent in databus access 177system.physmem.totBankLat 16917518750 # Total cycles spent in bank access 178system.physmem.avgQLat 26047.39 # Average queueing delay per request 179system.physmem.avgBankLat 1120.63 # Average bank access latency per request | 142system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see 174system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation 441system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays 442system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests 443system.physmem.totBusLat 75488575000 # Total cycles spent in databus access 444system.physmem.totBankLat 15730536250 # Total cycles spent in bank access 445system.physmem.avgQLat 23521.25 # Average queueing delay per request 446system.physmem.avgBankLat 1041.92 # Average bank access latency per request |
| 180system.physmem.avgBusLat 5000.00 # Average bus latency per request | 447system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 32168.02 # Average memory access latency 182system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s | 448system.physmem.avgMemAccLat 29563.16 # Average memory access latency 449system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s 450system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s 451system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s |
| 185system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.14 # Data bus utilization in percentage | 452system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s 453system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 454system.physmem.busUtil 3.14 # Data bus utilization in percentage |
| 188system.physmem.avgRdQLen 0.19 # Average read queue length over time 189system.physmem.avgWrQLen 11.11 # Average write queue length over time 190system.physmem.readRowHits 15020181 # Number of row buffer hits during reads 191system.physmem.writeRowHits 793022 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes 194system.physmem.avgGap 159216.11 # Average gap between requests | 455system.physmem.avgRdQLen 0.18 # Average read queue length over time 456system.physmem.avgWrQLen 11.71 # Average write queue length over time 457system.physmem.readRowHits 15070837 # Number of row buffer hits during reads 458system.physmem.writeRowHits 797438 # Number of row buffer hits during writes 459system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads 460system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes 461system.physmem.avgGap 159276.56 # Average gap between requests |
| 195system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 196system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 197system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 198system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 199system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 200system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 201system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 202system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 203system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 204system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 205system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 206system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) | 462system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 463system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 464system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 465system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 466system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 467system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 468system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 469system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 470system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 471system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 472system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 473system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) |
| 474system.membus.throughput 54705448 # Throughput (bytes/s) 475system.membus.trans_dist::ReadReq 16150672 # Transaction distribution 476system.membus.trans_dist::ReadResp 16150669 # Transaction distribution 477system.membus.trans_dist::WriteReq 763336 # Transaction distribution 478system.membus.trans_dist::WriteResp 763336 # Transaction distribution 479system.membus.trans_dist::Writeback 59115 # Transaction distribution 480system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution 481system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 482system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution 483system.membus.trans_dist::ReadExReq 131424 # Transaction distribution 484system.membus.trans_dist::ReadExResp 131424 # Transaction distribution 485system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) 486system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) 488system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 489system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 490system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) 491system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) 492system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) 493system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) 494system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 495system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) 496system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) 497system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 498system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) 499system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) 500system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 501system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) 502system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 503system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 504system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) 505system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) 506system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) 507system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) 508system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 509system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) 510system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) 511system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 512system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) 513system.membus.data_through_bus 138638877 # Total data (bytes) 514system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 515system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) 516system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 517system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 518system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 519system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) 520system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 521system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) 522system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 523system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) 524system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 525system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) 526system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 527system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) 528system.membus.respLayer2.utilization 1.3 # Layer utilization (%) |
|
| 207system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 208system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 211system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 212system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 529system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 530system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 531system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 532system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 533system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 534system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 213system.cpu.branchPred.lookups 14672817 # Number of BP lookups 214system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted 215system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect 216system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups 217system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits | 535system.iobus.throughput 48115298 # Throughput (bytes/s) 536system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution 537system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution 538system.iobus.trans_dist::WriteReq 8158 # Transaction distribution 539system.iobus.trans_dist::WriteResp 8158 # Transaction distribution 540system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 548system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 549system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 550system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 551system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 552system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 553system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 555system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 556system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 557system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 558system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 559system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 560system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 561system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 562system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 563system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) 564system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) 565system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) 566system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 567system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 568system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) 569system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) 570system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 571system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 572system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 576system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 577system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 578system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 579system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 580system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 581system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 585system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 586system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 587system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 588system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 589system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) 590system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) 591system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 592system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 593system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 594system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 595system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 596system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 597system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 598system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 599system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 600system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 601system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 602system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 603system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 604system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 605system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 606system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 607system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 608system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 609system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 610system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 611system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 612system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 613system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 614system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) 615system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) 616system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) 617system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 618system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 619system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 630system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 631system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 632system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 633system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 634system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 635system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 636system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 637system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 638system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 639system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 640system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) 641system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.data_through_bus 121937597 # Total data (bytes) 643system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 644system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 645system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 646system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 647system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) 648system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 649system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks) 650system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 651system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 652system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 653system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 654system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 655system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 656system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 657system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 658system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 659system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 660system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 661system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 662system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 663system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 664system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 665system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 666system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 667system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 668system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 669system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 670system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 671system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 672system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 673system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 674system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 675system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 676system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 678system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 679system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 680system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 681system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 682system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 683system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 684system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 685system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 686system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 687system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 688system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 689system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) 690system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 691system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) 692system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 693system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) 694system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) 695system.cpu.branchPred.lookups 14673159 # Number of BP lookups 696system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted 697system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect 698system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups 699system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits |
| 218system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 700system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 219system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage 220system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. 221system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. | 701system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage 702system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. 703system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. |
| 222system.cpu.dtb.inst_hits 0 # ITB inst hits 223system.cpu.dtb.inst_misses 0 # ITB inst misses | 704system.cpu.dtb.inst_hits 0 # ITB inst hits 705system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 224system.cpu.dtb.read_hits 51400888 # DTB read hits 225system.cpu.dtb.read_misses 64225 # DTB read misses 226system.cpu.dtb.write_hits 11700104 # DTB write hits 227system.cpu.dtb.write_misses 15848 # DTB write misses | 706system.cpu.dtb.read_hits 51397173 # DTB read hits 707system.cpu.dtb.read_misses 63986 # DTB read misses 708system.cpu.dtb.write_hits 11699533 # DTB write hits 709system.cpu.dtb.write_misses 15890 # DTB write misses |
| 228system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 229system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 230system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 231system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 710system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 711system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 712system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 713system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 232system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB 233system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions 234system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch | 714system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB 715system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions 716system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch |
| 235system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 717system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 236system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions 237system.cpu.dtb.read_accesses 51465113 # DTB read accesses 238system.cpu.dtb.write_accesses 11715952 # DTB write accesses | 718system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions 719system.cpu.dtb.read_accesses 51461159 # DTB read accesses 720system.cpu.dtb.write_accesses 11715423 # DTB write accesses |
| 239system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 721system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 240system.cpu.dtb.hits 63100992 # DTB hits 241system.cpu.dtb.misses 80073 # DTB misses 242system.cpu.dtb.accesses 63181065 # DTB accesses 243system.cpu.itb.inst_hits 12331220 # ITB inst hits 244system.cpu.itb.inst_misses 11422 # ITB inst misses | 722system.cpu.dtb.hits 63096706 # DTB hits 723system.cpu.dtb.misses 79876 # DTB misses 724system.cpu.dtb.accesses 63176582 # DTB accesses 725system.cpu.itb.inst_hits 12260245 # ITB inst hits 726system.cpu.itb.inst_misses 11468 # ITB inst misses |
| 245system.cpu.itb.read_hits 0 # DTB read hits 246system.cpu.itb.read_misses 0 # DTB read misses 247system.cpu.itb.write_hits 0 # DTB write hits 248system.cpu.itb.write_misses 0 # DTB write misses 249system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 250system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 251system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 252system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 727system.cpu.itb.read_hits 0 # DTB read hits 728system.cpu.itb.read_misses 0 # DTB read misses 729system.cpu.itb.write_hits 0 # DTB write hits 730system.cpu.itb.write_misses 0 # DTB write misses 731system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 732system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 733system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 734system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 253system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB | 735system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB |
| 254system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 255system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 256system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 736system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 737system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 738system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 257system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions | 739system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions |
| 258system.cpu.itb.read_accesses 0 # DTB read accesses 259system.cpu.itb.write_accesses 0 # DTB write accesses | 740system.cpu.itb.read_accesses 0 # DTB read accesses 741system.cpu.itb.write_accesses 0 # DTB write accesses |
| 260system.cpu.itb.inst_accesses 12342642 # ITB inst accesses 261system.cpu.itb.hits 12331220 # DTB hits 262system.cpu.itb.misses 11422 # DTB misses 263system.cpu.itb.accesses 12342642 # DTB accesses 264system.cpu.numCycles 471822965 # number of cpu cycles simulated | 742system.cpu.itb.inst_accesses 12271713 # ITB inst accesses 743system.cpu.itb.hits 12260245 # DTB hits 744system.cpu.itb.misses 11468 # DTB misses 745system.cpu.itb.accesses 12271713 # DTB accesses 746system.cpu.numCycles 475189978 # number of cpu cycles simulated |
| 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 747system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 748system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 267system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken 271system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked 272system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing 273system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb 274system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked 275system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 276system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps 277system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions 278system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed 282system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) | 749system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss 750system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed 751system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered 752system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken 753system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked 754system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing 755system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb 756system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked 757system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 758system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps 759system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions 760system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR 761system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched 762system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed 763system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed 764system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) 765system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) 766system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) |
| 285system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 767system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 286system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) | 768system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) 769system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) 770system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) 771system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) 772system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) 773system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) 774system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) 775system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) 776system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) |
| 295system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 777system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 778system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 779system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle 300system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle 301system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle 302system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked 303system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running 304system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking 305system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing 306system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch 307system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction 308system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode 309system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode 310system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing 311system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle 312system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking 313system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst 314system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running 315system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking 316system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename 317system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full 318system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full 319system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full 320system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers 321system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed 322system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made 323system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups 324system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups 325system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed 326system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing 327system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed 328system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed 329system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer 330system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. 331system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. 332system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. 333system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. 334system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) 335system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ 336system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued 337system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued 338system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling 339system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph 340system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed 341system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle | 780system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) 781system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle 782system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle 783system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle 784system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked 785system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running 786system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking 787system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing 788system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch 789system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction 790system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode 791system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode 792system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing 793system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle 794system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking 795system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst 796system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running 797system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking 798system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename 799system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full 800system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full 801system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full 802system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers 803system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed 804system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made 805system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups 806system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups 807system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed 808system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing 809system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed 810system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed 811system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer 812system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. 813system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. 814system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. 815system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. 816system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) 817system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ 818system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued 819system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued 820system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling 821system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph 822system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed 823system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle 824system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle 825system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle |
| 344system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 826system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 345system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle | 827system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle 828system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle 829system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle 830system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle 831system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle 832system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle 833system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle 834system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle 835system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle |
| 354system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 836system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 837system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 838system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle | 839system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle |
| 358system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 840system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 359system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available | 841system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available |
| 360system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 362system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 380system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available | 842system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available 843system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 844system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 845system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 846system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 847system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 848system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 849system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 862system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 863system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 864system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 865system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 866system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 867system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 868system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 869system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available |
| 388system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available 389system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available | 870system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available 871system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available |
| 390system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 391system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 392system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued | 872system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 873system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 874system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued |
| 393system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued 394system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued 395system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued 396system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued 397system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued 398system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued 399system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued 400system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued 422system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued 423system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued | 875system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued 876system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued 877system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued 878system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued 879system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued 880system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued 881system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued 882system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued 883system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued 884system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued 885system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued 886system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued 887system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued 888system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued 889system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued 890system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued 891system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued 892system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued 893system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued 894system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued 895system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued 896system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued 897system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued 898system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued 899system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued 900system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued 901system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued 902system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued 903system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued 904system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued 905system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued |
| 424system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 906system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 907system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 426system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued 427system.cpu.iq.rate 0.263501 # Inst issue rate 428system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested 429system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) 430system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads 431system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes 432system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses 433system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads 434system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes 435system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses 436system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses 437system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses 438system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores | 908system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued 909system.cpu.iq.rate 0.261620 # Inst issue rate 910system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested 911system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) 912system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads 913system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes 914system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses 915system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads 916system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes 917system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses 918system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses 919system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses 920system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores |
| 439system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 921system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 440system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed 441system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed 442system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations 443system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed | 922system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed 923system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed 924system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations 925system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed |
| 444system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 445system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 926system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 927system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 446system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled 447system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked | 928system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled 929system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked |
| 448system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 930system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 449system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing 450system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking 451system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking 452system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ 453system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch 454system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions 455system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions 456system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions 457system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall 458system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall 459system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations 460system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly 461system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly 462system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute 463system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions 464system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed 465system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute | 931system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing 932system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking 933system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking 934system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ 935system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch 936system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions 937system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions 938system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions 939system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall 940system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall 941system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations 942system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly 943system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly 944system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute 945system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions 946system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed 947system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute |
| 466system.cpu.iew.exec_swp 0 # number of swp insts executed | 948system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 467system.cpu.iew.exec_nop 221132 # number of nop insts executed 468system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed 469system.cpu.iew.exec_branches 11557425 # Number of branches executed 470system.cpu.iew.exec_stores 12211932 # Number of stores executed 471system.cpu.iew.exec_rate 0.257596 # Inst execution rate 472system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit 473system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back 474system.cpu.iew.wb_producers 47248258 # num instructions producing a value 475system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value | 949system.cpu.iew.exec_nop 221659 # number of nop insts executed 950system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed 951system.cpu.iew.exec_branches 11560329 # Number of branches executed 952system.cpu.iew.exec_stores 12210910 # Number of stores executed 953system.cpu.iew.exec_rate 0.255996 # Inst execution rate 954system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit 955system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back 956system.cpu.iew.wb_producers 47268053 # num instructions producing a value 957system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value |
| 476system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 958system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 477system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle 478system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back | 959system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle 960system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back |
| 479system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 961system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 480system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit | 962system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit |
| 481system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards | 963system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards |
| 482system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted 483system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle | 964system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted 965system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle 966system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle 967system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle |
| 486system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 968system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 487system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle | 969system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle 970system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle 971system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle 972system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle 973system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle 974system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle 975system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle 976system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle 977system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle |
| 496system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 978system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 979system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 980system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle 500system.cpu.commit.committedInsts 60458107 # Number of instructions committed 501system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed | 981system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle 982system.cpu.commit.committedInsts 60458274 # Number of instructions committed 983system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed |
| 502system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 984system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 503system.cpu.commit.refs 27386657 # Number of memory references committed 504system.cpu.commit.loads 15654563 # Number of loads committed 505system.cpu.commit.membars 403601 # Number of memory barriers committed 506system.cpu.commit.branches 9961339 # Number of branches committed | 985system.cpu.commit.refs 27386690 # Number of memory references committed 986system.cpu.commit.loads 15654575 # Number of loads committed 987system.cpu.commit.membars 403596 # Number of memory barriers committed 988system.cpu.commit.branches 9961373 # Number of branches committed |
| 507system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. | 989system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. |
| 508system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. 509system.cpu.commit.function_calls 991261 # Number of function calls committed. 510system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached | 990system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. 991system.cpu.commit.function_calls 991268 # Number of function calls committed. 992system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached |
| 511system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 993system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 512system.cpu.rob.rob_reads 242323943 # The number of ROB reads 513system.cpu.rob.rob_writes 202004834 # The number of ROB writes 514system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself 515system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling 516system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 517system.cpu.committedInsts 60307726 # Number of Instructions Simulated 518system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated 519system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated 520system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction 521system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads 522system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle 523system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads 524system.cpu.int_regfile_reads 550297300 # number of integer regfile reads 525system.cpu.int_regfile_writes 88455600 # number of integer regfile writes 526system.cpu.fp_regfile_reads 8347 # number of floating regfile reads 527system.cpu.fp_regfile_writes 2910 # number of floating regfile writes 528system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads 529system.cpu.misc_regfile_writes 831893 # number of misc regfile writes 530system.cpu.icache.replacements 979954 # number of replacements 531system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use 532system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. 533system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. 534system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. 535system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. 536system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor 537system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy 538system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy 539system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits 540system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits 541system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits 542system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits 543system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits 544system.cpu.icache.overall_hits::total 11267650 # number of overall hits 545system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses 546system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses 547system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses 548system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses 549system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses 550system.cpu.icache.overall_misses::total 1060047 # number of overall misses 551system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles 552system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles 553system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles 554system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles 555system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles 556system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles 557system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) 558system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) 559system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses 560system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses 561system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses 562system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses 563system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses 564system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses 565system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses 566system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses 567system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses 568system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses 569system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency 570system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency 571system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency 572system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency 573system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency 574system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency 575system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked 576system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked 577system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked 578system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 579system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked 580system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked | 994system.cpu.rob.rob_reads 243879966 # The number of ROB reads 995system.cpu.rob.rob_writes 201882555 # The number of ROB writes 996system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself 997system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling 998system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 999system.cpu.committedInsts 60307893 # Number of Instructions Simulated 1000system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated 1001system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated 1002system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction 1003system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads 1004system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle 1005system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads 1006system.cpu.int_regfile_reads 550704700 # number of integer regfile reads 1007system.cpu.int_regfile_writes 88578312 # number of integer regfile writes 1008system.cpu.fp_regfile_reads 8302 # number of floating regfile reads 1009system.cpu.fp_regfile_writes 2882 # number of floating regfile writes 1010system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads 1011system.cpu.misc_regfile_writes 831896 # number of misc regfile writes 1012system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) 1013system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution 1016system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution 1017system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution 1018system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution 1019system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution 1020system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution 1021system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution 1022system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution 1023system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) 1024system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) 1025system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) 1026system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) 1027system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) 1028system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) 1029system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) 1030system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) 1031system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) 1032system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) 1033system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) 1034system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) 1035system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) 1036system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1037system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) 1038system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1039system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) 1040system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1041system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) 1042system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1043system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) 1044system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1045system.cpu.icache.replacements 980157 # number of replacements 1046system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use 1047system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. 1048system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. 1049system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. 1050system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. 1051system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor 1052system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy 1053system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy 1054system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits 1055system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits 1056system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits 1057system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits 1058system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits 1059system.cpu.icache.overall_hits::total 11196212 # number of overall hits 1060system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses 1061system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses 1062system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses 1063system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses 1064system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses 1065system.cpu.icache.overall_misses::total 1060409 # number of overall misses 1066system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles 1067system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles 1068system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles 1069system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles 1070system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles 1071system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles 1072system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) 1073system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) 1074system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses 1075system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses 1076system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses 1077system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses 1078system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses 1079system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses 1080system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses 1081system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses 1082system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses 1083system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses 1084system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency 1085system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency 1086system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency 1087system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency 1088system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency 1089system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency 1090system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked 1091system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1092system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked 1093system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1094system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked 1095system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 581system.cpu.icache.fast_writes 0 # number of fast writes performed 582system.cpu.icache.cache_copies 0 # number of cache copies performed | 1096system.cpu.icache.fast_writes 0 # number of fast writes performed 1097system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 583system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits 584system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits 585system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits 586system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits 587system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits 588system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits 589system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses 590system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses 591system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses 592system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses 593system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses 594system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses 595system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles 596system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles 597system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles 602system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles 603system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles 604system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles 605system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses 606system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses 607system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses 608system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses 609system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses 610system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses 611system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency 613system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency 615system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency | 1098system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits 1099system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits 1100system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits 1101system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits 1102system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits 1103system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits 1104system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # number of ReadReq MSHR misses 1105system.cpu.icache.ReadReq_mshr_misses::total 980711 # number of ReadReq MSHR misses 1106system.cpu.icache.demand_mshr_misses::cpu.inst 980711 # number of demand (read+write) MSHR misses 1107system.cpu.icache.demand_mshr_misses::total 980711 # number of demand (read+write) MSHR misses 1108system.cpu.icache.overall_mshr_misses::cpu.inst 980711 # number of overall MSHR misses 1109system.cpu.icache.overall_mshr_misses::total 980711 # number of overall MSHR misses 1110system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583440602 # number of ReadReq MSHR miss cycles 1111system.cpu.icache.ReadReq_mshr_miss_latency::total 11583440602 # number of ReadReq MSHR miss cycles 1112system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583440602 # number of demand (read+write) MSHR miss cycles 1113system.cpu.icache.demand_mshr_miss_latency::total 11583440602 # number of demand (read+write) MSHR miss cycles 1114system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583440602 # number of overall MSHR miss cycles 1115system.cpu.icache.overall_mshr_miss_latency::total 11583440602 # number of overall MSHR miss cycles 1116system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles 1117system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles 1118system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles 1119system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles 1120system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses 1121system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # mshr miss rate for ReadReq accesses 1122system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for demand accesses 1123system.cpu.icache.demand_mshr_miss_rate::total 0.080015 # mshr miss rate for demand accesses 1124system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for overall accesses 1125system.cpu.icache.overall_mshr_miss_rate::total 0.080015 # mshr miss rate for overall accesses 1126system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11811.268153 # average ReadReq mshr miss latency 1127system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11811.268153 # average ReadReq mshr miss latency 1128system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency 1129system.cpu.icache.demand_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency 1130system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11811.268153 # average overall mshr miss latency 1131system.cpu.icache.overall_avg_mshr_miss_latency::total 11811.268153 # average overall mshr miss latency |
| 617system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 618system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 619system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 620system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 621system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1132system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1133system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1134system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1135system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1136system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 622system.cpu.l2cache.replacements 64333 # number of replacements 623system.cpu.l2cache.tagsinuse 51339.387704 # Cycle average of tags in use 624system.cpu.l2cache.total_refs 1885585 # Total number of references to valid blocks. 625system.cpu.l2cache.sampled_refs 129729 # Sample count of references to valid blocks. 626system.cpu.l2cache.avg_refs 14.534799 # Average number of references to valid blocks. 627system.cpu.l2cache.warmup_cycle 2523139741500 # Cycle when the warmup percentage was hit. 628system.cpu.l2cache.occ_blocks::writebacks 36938.518996 # Average occupied blocks per requestor 629system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.781617 # Average occupied blocks per requestor 630system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor 631system.cpu.l2cache.occ_blocks::cpu.inst 8154.357820 # Average occupied blocks per requestor 632system.cpu.l2cache.occ_blocks::cpu.data 6219.728923 # Average occupied blocks per requestor 633system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy 634system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy | 1137system.cpu.l2cache.replacements 64365 # number of replacements 1138system.cpu.l2cache.tagsinuse 51350.135703 # Cycle average of tags in use 1139system.cpu.l2cache.total_refs 1885273 # Total number of references to valid blocks. 1140system.cpu.l2cache.sampled_refs 129757 # Sample count of references to valid blocks. 1141system.cpu.l2cache.avg_refs 14.529259 # Average number of references to valid blocks. 1142system.cpu.l2cache.warmup_cycle 2499221448500 # Cycle when the warmup percentage was hit. 1143system.cpu.l2cache.occ_blocks::writebacks 36903.083753 # Average occupied blocks per requestor 1144system.cpu.l2cache.occ_blocks::cpu.dtb.walker 33.180761 # Average occupied blocks per requestor 1145system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000367 # Average occupied blocks per requestor 1146system.cpu.l2cache.occ_blocks::cpu.inst 8167.882252 # Average occupied blocks per requestor 1147system.cpu.l2cache.occ_blocks::cpu.data 6245.988569 # Average occupied blocks per requestor 1148system.cpu.l2cache.occ_percent::writebacks 0.563096 # Average percentage of cache occupancy 1149system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000506 # Average percentage of cache occupancy |
| 635system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 1150system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 636system.cpu.l2cache.occ_percent::cpu.inst 0.124426 # Average percentage of cache occupancy 637system.cpu.l2cache.occ_percent::cpu.data 0.094906 # Average percentage of cache occupancy 638system.cpu.l2cache.occ_percent::total 0.783377 # Average percentage of cache occupancy 639system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52369 # number of ReadReq hits 640system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10535 # number of ReadReq hits 641system.cpu.l2cache.ReadReq_hits::cpu.inst 967038 # number of ReadReq hits 642system.cpu.l2cache.ReadReq_hits::cpu.data 387148 # number of ReadReq hits 643system.cpu.l2cache.ReadReq_hits::total 1417090 # number of ReadReq hits 644system.cpu.l2cache.Writeback_hits::writebacks 607758 # number of Writeback hits 645system.cpu.l2cache.Writeback_hits::total 607758 # number of Writeback hits 646system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits 647system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits 648system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits 649system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits 650system.cpu.l2cache.ReadExReq_hits::cpu.data 112914 # number of ReadExReq hits 651system.cpu.l2cache.ReadExReq_hits::total 112914 # number of ReadExReq hits 652system.cpu.l2cache.demand_hits::cpu.dtb.walker 52369 # number of demand (read+write) hits 653system.cpu.l2cache.demand_hits::cpu.itb.walker 10535 # number of demand (read+write) hits 654system.cpu.l2cache.demand_hits::cpu.inst 967038 # number of demand (read+write) hits 655system.cpu.l2cache.demand_hits::cpu.data 500062 # number of demand (read+write) hits 656system.cpu.l2cache.demand_hits::total 1530004 # number of demand (read+write) hits 657system.cpu.l2cache.overall_hits::cpu.dtb.walker 52369 # number of overall hits 658system.cpu.l2cache.overall_hits::cpu.itb.walker 10535 # number of overall hits 659system.cpu.l2cache.overall_hits::cpu.inst 967038 # number of overall hits 660system.cpu.l2cache.overall_hits::cpu.data 500062 # number of overall hits 661system.cpu.l2cache.overall_hits::total 1530004 # number of overall hits 662system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses | 1151system.cpu.l2cache.occ_percent::cpu.inst 0.124632 # Average percentage of cache occupancy 1152system.cpu.l2cache.occ_percent::cpu.data 0.095306 # Average percentage of cache occupancy 1153system.cpu.l2cache.occ_percent::total 0.783541 # Average percentage of cache occupancy 1154system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52156 # number of ReadReq hits 1155system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10569 # number of ReadReq hits 1156system.cpu.l2cache.ReadReq_hits::cpu.inst 967205 # number of ReadReq hits 1157system.cpu.l2cache.ReadReq_hits::cpu.data 387072 # number of ReadReq hits 1158system.cpu.l2cache.ReadReq_hits::total 1417002 # number of ReadReq hits 1159system.cpu.l2cache.Writeback_hits::writebacks 607669 # number of Writeback hits 1160system.cpu.l2cache.Writeback_hits::total 607669 # number of Writeback hits 1161system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits 1162system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits 1163system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits 1164system.cpu.l2cache.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits 1165system.cpu.l2cache.ReadExReq_hits::cpu.data 112874 # number of ReadExReq hits 1166system.cpu.l2cache.ReadExReq_hits::total 112874 # number of ReadExReq hits 1167system.cpu.l2cache.demand_hits::cpu.dtb.walker 52156 # number of demand (read+write) hits 1168system.cpu.l2cache.demand_hits::cpu.itb.walker 10569 # number of demand (read+write) hits 1169system.cpu.l2cache.demand_hits::cpu.inst 967205 # number of demand (read+write) hits 1170system.cpu.l2cache.demand_hits::cpu.data 499946 # number of demand (read+write) hits 1171system.cpu.l2cache.demand_hits::total 1529876 # number of demand (read+write) hits 1172system.cpu.l2cache.overall_hits::cpu.dtb.walker 52156 # number of overall hits 1173system.cpu.l2cache.overall_hits::cpu.itb.walker 10569 # number of overall hits 1174system.cpu.l2cache.overall_hits::cpu.inst 967205 # number of overall hits 1175system.cpu.l2cache.overall_hits::cpu.data 499946 # number of overall hits 1176system.cpu.l2cache.overall_hits::total 1529876 # number of overall hits 1177system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses |
| 663system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 1178system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 664system.cpu.l2cache.ReadReq_misses::cpu.inst 12333 # number of ReadReq misses 665system.cpu.l2cache.ReadReq_misses::cpu.data 10696 # number of ReadReq misses 666system.cpu.l2cache.ReadReq_misses::total 23072 # number of ReadReq misses 667system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses 668system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses | 1179system.cpu.l2cache.ReadReq_misses::cpu.inst 12345 # number of ReadReq misses 1180system.cpu.l2cache.ReadReq_misses::cpu.data 10738 # number of ReadReq misses 1181system.cpu.l2cache.ReadReq_misses::total 23130 # number of ReadReq misses 1182system.cpu.l2cache.UpgradeReq_misses::cpu.data 2912 # number of UpgradeReq misses 1183system.cpu.l2cache.UpgradeReq_misses::total 2912 # number of UpgradeReq misses |
| 669system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 670system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses | 1184system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1185system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses |
| 671system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses 672system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses 673system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses | 1186system.cpu.l2cache.ReadExReq_misses::cpu.data 133181 # number of ReadExReq misses 1187system.cpu.l2cache.ReadExReq_misses::total 133181 # number of ReadExReq misses 1188system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses |
| 674system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 1189system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 675system.cpu.l2cache.demand_misses::cpu.inst 12333 # number of demand (read+write) misses 676system.cpu.l2cache.demand_misses::cpu.data 143900 # number of demand (read+write) misses 677system.cpu.l2cache.demand_misses::total 156276 # number of demand (read+write) misses 678system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses | 1190system.cpu.l2cache.demand_misses::cpu.inst 12345 # number of demand (read+write) misses 1191system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses 1192system.cpu.l2cache.demand_misses::total 156311 # number of demand (read+write) misses 1193system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses |
| 679system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 1194system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 680system.cpu.l2cache.overall_misses::cpu.inst 12333 # number of overall misses 681system.cpu.l2cache.overall_misses::cpu.data 143900 # number of overall misses 682system.cpu.l2cache.overall_misses::total 156276 # number of overall misses 683system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2953500 # number of ReadReq miss cycles 684system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles 685system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695709500 # number of ReadReq miss cycles 686system.cpu.l2cache.ReadReq_miss_latency::cpu.data 628176999 # number of ReadReq miss cycles 687system.cpu.l2cache.ReadReq_miss_latency::total 1326957999 # number of ReadReq miss cycles 688system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles 689system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6755691500 # number of ReadExReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::total 6755691500 # number of ReadExReq miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2953500 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::cpu.inst 695709500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.demand_miss_latency::cpu.data 7383868499 # number of demand (read+write) miss cycles 696system.cpu.l2cache.demand_miss_latency::total 8082649499 # number of demand (read+write) miss cycles 697system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2953500 # number of overall miss cycles 698system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles 699system.cpu.l2cache.overall_miss_latency::cpu.inst 695709500 # number of overall miss cycles 700system.cpu.l2cache.overall_miss_latency::cpu.data 7383868499 # number of overall miss cycles 701system.cpu.l2cache.overall_miss_latency::total 8082649499 # number of overall miss cycles 702system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52410 # number of ReadReq accesses(hits+misses) 703system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10537 # number of ReadReq accesses(hits+misses) 704system.cpu.l2cache.ReadReq_accesses::cpu.inst 979371 # number of ReadReq accesses(hits+misses) 705system.cpu.l2cache.ReadReq_accesses::cpu.data 397844 # number of ReadReq accesses(hits+misses) 706system.cpu.l2cache.ReadReq_accesses::total 1440162 # number of ReadReq accesses(hits+misses) 707system.cpu.l2cache.Writeback_accesses::writebacks 607758 # number of Writeback accesses(hits+misses) 708system.cpu.l2cache.Writeback_accesses::total 607758 # number of Writeback accesses(hits+misses) 709system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses) 710system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses) 711system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) 712system.cpu.l2cache.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::cpu.data 246118 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.ReadExReq_accesses::total 246118 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52410 # number of demand (read+write) accesses 716system.cpu.l2cache.demand_accesses::cpu.itb.walker 10537 # number of demand (read+write) accesses 717system.cpu.l2cache.demand_accesses::cpu.inst 979371 # number of demand (read+write) accesses 718system.cpu.l2cache.demand_accesses::cpu.data 643962 # number of demand (read+write) accesses 719system.cpu.l2cache.demand_accesses::total 1686280 # number of demand (read+write) accesses 720system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52410 # number of overall (read+write) accesses 721system.cpu.l2cache.overall_accesses::cpu.itb.walker 10537 # number of overall (read+write) accesses 722system.cpu.l2cache.overall_accesses::cpu.inst 979371 # number of overall (read+write) accesses 723system.cpu.l2cache.overall_accesses::cpu.data 643962 # number of overall (read+write) accesses 724system.cpu.l2cache.overall_accesses::total 1686280 # number of overall (read+write) accesses 725system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000782 # miss rate for ReadReq accesses 726system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses 727system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012593 # miss rate for ReadReq accesses 728system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026885 # miss rate for ReadReq accesses 729system.cpu.l2cache.ReadReq_miss_rate::total 0.016020 # miss rate for ReadReq accesses 730system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986500 # miss rate for UpgradeReq accesses 731system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986500 # miss rate for UpgradeReq accesses 732system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.176471 # miss rate for SCUpgradeReq accesses 733system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.176471 # miss rate for SCUpgradeReq accesses 734system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541220 # miss rate for ReadExReq accesses 735system.cpu.l2cache.ReadExReq_miss_rate::total 0.541220 # miss rate for ReadExReq accesses 736system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000782 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012593 # miss rate for demand accesses 739system.cpu.l2cache.demand_miss_rate::cpu.data 0.223460 # miss rate for demand accesses 740system.cpu.l2cache.demand_miss_rate::total 0.092675 # miss rate for demand accesses 741system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000782 # miss rate for overall accesses 742system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses 743system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012593 # miss rate for overall accesses 744system.cpu.l2cache.overall_miss_rate::cpu.data 0.223460 # miss rate for overall accesses 745system.cpu.l2cache.overall_miss_rate::total 0.092675 # miss rate for overall accesses 746system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72036.585366 # average ReadReq miss latency 747system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency 748system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56410.402984 # average ReadReq miss latency 749system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58730.085920 # average ReadReq miss latency 750system.cpu.l2cache.ReadReq_avg_miss_latency::total 57513.782897 # average ReadReq miss latency 751system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency 752system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency 753system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50716.881625 # average ReadExReq miss latency 754system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50716.881625 # average ReadExReq miss latency 755system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency 756system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 757system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency 758system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency 759system.cpu.l2cache.demand_avg_miss_latency::total 51720.350527 # average overall miss latency 760system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72036.585366 # average overall miss latency 761system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency 762system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56410.402984 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51312.498256 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::total 51720.350527 # average overall miss latency | 1195system.cpu.l2cache.overall_misses::cpu.inst 12345 # number of overall misses 1196system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses 1197system.cpu.l2cache.overall_misses::total 156311 # number of overall misses 1198system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4040500 # number of ReadReq miss cycles 1199system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130000 # number of ReadReq miss cycles 1200system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 909082500 # number of ReadReq miss cycles 1201system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805516497 # number of ReadReq miss cycles 1202system.cpu.l2cache.ReadReq_miss_latency::total 1718769497 # number of ReadReq miss cycles 1203system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 409500 # number of UpgradeReq miss cycles 1204system.cpu.l2cache.UpgradeReq_miss_latency::total 409500 # number of UpgradeReq miss cycles 1205system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9052113500 # number of ReadExReq miss cycles 1206system.cpu.l2cache.ReadExReq_miss_latency::total 9052113500 # number of ReadExReq miss cycles 1207system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4040500 # number of demand (read+write) miss cycles 1208system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130000 # number of demand (read+write) miss cycles 1209system.cpu.l2cache.demand_miss_latency::cpu.inst 909082500 # number of demand (read+write) miss cycles 1210system.cpu.l2cache.demand_miss_latency::cpu.data 9857629997 # number of demand (read+write) miss cycles 1211system.cpu.l2cache.demand_miss_latency::total 10770882997 # number of demand (read+write) miss cycles 1212system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4040500 # number of overall miss cycles 1213system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130000 # number of overall miss cycles 1214system.cpu.l2cache.overall_miss_latency::cpu.inst 909082500 # number of overall miss cycles 1215system.cpu.l2cache.overall_miss_latency::cpu.data 9857629997 # number of overall miss cycles 1216system.cpu.l2cache.overall_miss_latency::total 10770882997 # number of overall miss cycles 1217system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52201 # number of ReadReq accesses(hits+misses) 1218system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10571 # number of ReadReq accesses(hits+misses) 1219system.cpu.l2cache.ReadReq_accesses::cpu.inst 979550 # number of ReadReq accesses(hits+misses) 1220system.cpu.l2cache.ReadReq_accesses::cpu.data 397810 # number of ReadReq accesses(hits+misses) 1221system.cpu.l2cache.ReadReq_accesses::total 1440132 # number of ReadReq accesses(hits+misses) 1222system.cpu.l2cache.Writeback_accesses::writebacks 607669 # number of Writeback accesses(hits+misses) 1223system.cpu.l2cache.Writeback_accesses::total 607669 # number of Writeback accesses(hits+misses) 1224system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2958 # number of UpgradeReq accesses(hits+misses) 1225system.cpu.l2cache.UpgradeReq_accesses::total 2958 # number of UpgradeReq accesses(hits+misses) 1226system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 15 # number of SCUpgradeReq accesses(hits+misses) 1227system.cpu.l2cache.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses) 1228system.cpu.l2cache.ReadExReq_accesses::cpu.data 246055 # number of ReadExReq accesses(hits+misses) 1229system.cpu.l2cache.ReadExReq_accesses::total 246055 # number of ReadExReq accesses(hits+misses) 1230system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52201 # number of demand (read+write) accesses 1231system.cpu.l2cache.demand_accesses::cpu.itb.walker 10571 # number of demand (read+write) accesses 1232system.cpu.l2cache.demand_accesses::cpu.inst 979550 # number of demand (read+write) accesses 1233system.cpu.l2cache.demand_accesses::cpu.data 643865 # number of demand (read+write) accesses 1234system.cpu.l2cache.demand_accesses::total 1686187 # number of demand (read+write) accesses 1235system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52201 # number of overall (read+write) accesses 1236system.cpu.l2cache.overall_accesses::cpu.itb.walker 10571 # number of overall (read+write) accesses 1237system.cpu.l2cache.overall_accesses::cpu.inst 979550 # number of overall (read+write) accesses 1238system.cpu.l2cache.overall_accesses::cpu.data 643865 # number of overall (read+write) accesses 1239system.cpu.l2cache.overall_accesses::total 1686187 # number of overall (read+write) accesses 1240system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000862 # miss rate for ReadReq accesses 1241system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses 1242system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012603 # miss rate for ReadReq accesses 1243system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026993 # miss rate for ReadReq accesses 1244system.cpu.l2cache.ReadReq_miss_rate::total 0.016061 # miss rate for ReadReq accesses 1245system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984449 # miss rate for UpgradeReq accesses 1246system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984449 # miss rate for UpgradeReq accesses 1247system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.200000 # miss rate for SCUpgradeReq accesses 1248system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses 1249system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541265 # miss rate for ReadExReq accesses 1250system.cpu.l2cache.ReadExReq_miss_rate::total 0.541265 # miss rate for ReadExReq accesses 1251system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000862 # miss rate for demand accesses 1252system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses 1253system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012603 # miss rate for demand accesses 1254system.cpu.l2cache.demand_miss_rate::cpu.data 0.223524 # miss rate for demand accesses 1255system.cpu.l2cache.demand_miss_rate::total 0.092701 # miss rate for demand accesses 1256system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000862 # miss rate for overall accesses 1257system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses 1258system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012603 # miss rate for overall accesses 1259system.cpu.l2cache.overall_miss_rate::cpu.data 0.223524 # miss rate for overall accesses 1260system.cpu.l2cache.overall_miss_rate::total 0.092701 # miss rate for overall accesses 1261system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89788.888889 # average ReadReq miss latency 1262system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65000 # average ReadReq miss latency 1263system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73639.732685 # average ReadReq miss latency 1264system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75015.505401 # average ReadReq miss latency 1265system.cpu.l2cache.ReadReq_avg_miss_latency::total 74309.100605 # average ReadReq miss latency 1266system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 140.625000 # average UpgradeReq miss latency 1267system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 140.625000 # average UpgradeReq miss latency 1268system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67968.505267 # average ReadExReq miss latency 1269system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67968.505267 # average ReadExReq miss latency 1270system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89788.888889 # average overall miss latency 1271system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65000 # average overall miss latency 1272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73639.732685 # average overall miss latency 1273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68494.291907 # average overall miss latency 1274system.cpu.l2cache.demand_avg_miss_latency::total 68906.749986 # average overall miss latency 1275system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89788.888889 # average overall miss latency 1276system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65000 # average overall miss latency 1277system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73639.732685 # average overall miss latency 1278system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68494.291907 # average overall miss latency 1279system.cpu.l2cache.overall_avg_miss_latency::total 68906.749986 # average overall miss latency |
| 765system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 766system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 769system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 770system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 771system.cpu.l2cache.fast_writes 0 # number of fast writes performed 772system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1280system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1281system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1282system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1283system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1284system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1285system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1286system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1287system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 773system.cpu.l2cache.writebacks::writebacks 59090 # number of writebacks 774system.cpu.l2cache.writebacks::total 59090 # number of writebacks 775system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits 776system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 60 # number of ReadReq MSHR hits 777system.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 778system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits 779system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits 780system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 781system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits 782system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits 783system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits 784system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses | 1288system.cpu.l2cache.writebacks::writebacks 59115 # number of writebacks 1289system.cpu.l2cache.writebacks::total 59115 # number of writebacks 1290system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 1291system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 1292system.cpu.l2cache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 1293system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 1294system.cpu.l2cache.demand_mshr_hits::cpu.data 68 # number of demand (read+write) MSHR hits 1295system.cpu.l2cache.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits 1296system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 1297system.cpu.l2cache.overall_mshr_hits::cpu.data 68 # number of overall MSHR hits 1298system.cpu.l2cache.overall_mshr_hits::total 79 # number of overall MSHR hits 1299system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses |
| 785system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 1300system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 786system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12321 # number of ReadReq MSHR misses 787system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10636 # number of ReadReq MSHR misses 788system.cpu.l2cache.ReadReq_mshr_misses::total 23000 # number of ReadReq MSHR misses 789system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses 790system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses | 1301system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12334 # number of ReadReq MSHR misses 1302system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10670 # number of ReadReq MSHR misses 1303system.cpu.l2cache.ReadReq_mshr_misses::total 23051 # number of ReadReq MSHR misses 1304system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2912 # number of UpgradeReq MSHR misses 1305system.cpu.l2cache.UpgradeReq_mshr_misses::total 2912 # number of UpgradeReq MSHR misses |
| 791system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 792system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses | 1306system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1307system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses |
| 793system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133204 # number of ReadExReq MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_misses::total 133204 # number of ReadExReq MSHR misses 795system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses | 1308system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133181 # number of ReadExReq MSHR misses 1309system.cpu.l2cache.ReadExReq_mshr_misses::total 133181 # number of ReadExReq MSHR misses 1310system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses |
| 796system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 1311system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 797system.cpu.l2cache.demand_mshr_misses::cpu.inst 12321 # number of demand (read+write) MSHR misses 798system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses 799system.cpu.l2cache.demand_mshr_misses::total 156204 # number of demand (read+write) MSHR misses 800system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses | 1312system.cpu.l2cache.demand_mshr_misses::cpu.inst 12334 # number of demand (read+write) MSHR misses 1313system.cpu.l2cache.demand_mshr_misses::cpu.data 143851 # number of demand (read+write) MSHR misses 1314system.cpu.l2cache.demand_mshr_misses::total 156232 # number of demand (read+write) MSHR misses 1315system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses |
| 801system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 1316system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 802system.cpu.l2cache.overall_mshr_misses::cpu.inst 12321 # number of overall MSHR misses 803system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses 804system.cpu.l2cache.overall_mshr_misses::total 156204 # number of overall MSHR misses 805system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2441041 # number of ReadReq MSHR miss cycles 806system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93251 # number of ReadReq MSHR miss cycles 807system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541729027 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 493322234 # number of ReadReq MSHR miss cycles 809system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1037585553 # number of ReadReq MSHR miss cycles 810system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles 811system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles | 1317system.cpu.l2cache.overall_mshr_misses::cpu.inst 12334 # number of overall MSHR misses 1318system.cpu.l2cache.overall_mshr_misses::cpu.data 143851 # number of overall MSHR misses 1319system.cpu.l2cache.overall_mshr_misses::total 156232 # number of overall MSHR misses 1320system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3481250 # number of ReadReq MSHR miss cycles 1321system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles 1322system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 755022750 # number of ReadReq MSHR miss cycles 1323system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668946247 # number of ReadReq MSHR miss cycles 1324system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1427555997 # number of ReadReq MSHR miss cycles 1325system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29123912 # number of UpgradeReq MSHR miss cycles 1326system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29123912 # number of UpgradeReq MSHR miss cycles |
| 812system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 813system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles | 1327system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1328system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles |
| 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5095490217 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5095490217 # number of ReadExReq MSHR miss cycles 816system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2441041 # number of demand (read+write) MSHR miss cycles 817system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93251 # number of demand (read+write) MSHR miss cycles 818system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541729027 # number of demand (read+write) MSHR miss cycles 819system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5588812451 # number of demand (read+write) MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::total 6133075770 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2441041 # number of overall MSHR miss cycles 822system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541729027 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5588812451 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 6133075770 # number of overall MSHR miss cycles 826system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles 827system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002521767 # number of ReadReq MSHR uncacheable cycles 828system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007602597 # number of ReadReq MSHR uncacheable cycles 829system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911564456 # number of WriteReq MSHR uncacheable cycles 830system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911564456 # number of WriteReq MSHR uncacheable cycles 831system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5080830 # number of overall MSHR uncacheable cycles 832system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914086223 # number of overall MSHR uncacheable cycles 833system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919167053 # number of overall MSHR uncacheable cycles 834system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for ReadReq accesses 835system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses 836system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for ReadReq accesses 837system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026734 # mshr miss rate for ReadReq accesses 838system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015970 # mshr miss rate for ReadReq accesses 839system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986500 # mshr miss rate for UpgradeReq accesses 840system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986500 # mshr miss rate for UpgradeReq accesses 841system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses 842system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses 843system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541220 # mshr miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541220 # mshr miss rate for ReadExReq accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for demand accesses 849system.cpu.l2cache.demand_mshr_miss_rate::total 0.092632 # mshr miss rate for demand accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for overall accesses 854system.cpu.l2cache.overall_mshr_miss_rate::total 0.092632 # mshr miss rate for overall accesses 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency 857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43967.943105 # average ReadReq mshr miss latency 858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46382.308575 # average ReadReq mshr miss latency 859system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45112.415348 # average ReadReq mshr miss latency 860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 861system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency | 1329system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7387753007 # number of ReadExReq MSHR miss cycles 1330system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7387753007 # number of ReadExReq MSHR miss cycles 1331system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3481250 # number of demand (read+write) MSHR miss cycles 1332system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles 1333system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 755022750 # number of demand (read+write) MSHR miss cycles 1334system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8056699254 # number of demand (read+write) MSHR miss cycles 1335system.cpu.l2cache.demand_mshr_miss_latency::total 8815309004 # number of demand (read+write) MSHR miss cycles 1336system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3481250 # number of overall MSHR miss cycles 1337system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles 1338system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 755022750 # number of overall MSHR miss cycles 1339system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8056699254 # number of overall MSHR miss cycles 1340system.cpu.l2cache.overall_mshr_miss_latency::total 8815309004 # number of overall MSHR miss cycles 1341system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 7078250 # number of ReadReq MSHR uncacheable cycles 1342system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166940694000 # number of ReadReq MSHR uncacheable cycles 1343system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166947772250 # number of ReadReq MSHR uncacheable cycles 1344system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26398880620 # number of WriteReq MSHR uncacheable cycles 1345system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26398880620 # number of WriteReq MSHR uncacheable cycles 1346system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7078250 # number of overall MSHR uncacheable cycles 1347system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193339574620 # number of overall MSHR uncacheable cycles 1348system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193346652870 # number of overall MSHR uncacheable cycles 1349system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for ReadReq accesses 1350system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses 1351system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for ReadReq accesses 1352system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026822 # mshr miss rate for ReadReq accesses 1353system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016006 # mshr miss rate for ReadReq accesses 1354system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984449 # mshr miss rate for UpgradeReq accesses 1355system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984449 # mshr miss rate for UpgradeReq accesses 1356system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for SCUpgradeReq accesses 1357system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses 1358system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541265 # mshr miss rate for ReadExReq accesses 1359system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541265 # mshr miss rate for ReadExReq accesses 1360system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for demand accesses 1361system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses 1362system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for demand accesses 1363system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for demand accesses 1364system.cpu.l2cache.demand_mshr_miss_rate::total 0.092654 # mshr miss rate for demand accesses 1365system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000862 # mshr miss rate for overall accesses 1366system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses 1367system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012591 # mshr miss rate for overall accesses 1368system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223418 # mshr miss rate for overall accesses 1369system.cpu.l2cache.overall_mshr_miss_rate::total 0.092654 # mshr miss rate for overall accesses 1370system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average ReadReq mshr miss latency 1371system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency 1372system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61214.751905 # average ReadReq mshr miss latency 1373system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.118744 # average ReadReq mshr miss latency 1374system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61930.328272 # average ReadReq mshr miss latency 1375system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.343407 # average UpgradeReq mshr miss latency 1376system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.343407 # average UpgradeReq mshr miss latency |
| 862system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 863system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1377system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1378system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 864system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38253.282311 # average ReadExReq mshr miss latency 865system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38253.282311 # average ReadExReq mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency 869system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency 870system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency 872system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency 873system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency 874system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency 875system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency | 1379system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55471.523768 # average ReadExReq mshr miss latency 1380system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55471.523768 # average ReadExReq mshr miss latency 1381system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency 1382system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1383system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency 1384system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency 1385system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency 1386system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77361.111111 # average overall mshr miss latency 1387system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency 1388system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61214.751905 # average overall mshr miss latency 1389system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56007.252324 # average overall mshr miss latency 1390system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56424.477725 # average overall mshr miss latency |
| 876system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 877system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 878system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 879system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 880system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 881system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 882system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 883system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 884system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1391system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1392system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1393system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1394system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1395system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1396system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1397system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1398system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1399system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 885system.cpu.dcache.replacements 643450 # number of replacements 886system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use 887system.cpu.dcache.total_refs 21511687 # Total number of references to valid blocks. 888system.cpu.dcache.sampled_refs 643962 # Sample count of references to valid blocks. 889system.cpu.dcache.avg_refs 33.405212 # Average number of references to valid blocks. 890system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. 891system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor 892system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy 893system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy 894system.cpu.dcache.ReadReq_hits::cpu.data 13758946 # number of ReadReq hits 895system.cpu.dcache.ReadReq_hits::total 13758946 # number of ReadReq hits 896system.cpu.dcache.WriteReq_hits::cpu.data 7259114 # number of WriteReq hits 897system.cpu.dcache.WriteReq_hits::total 7259114 # number of WriteReq hits 898system.cpu.dcache.LoadLockedReq_hits::cpu.data 242919 # number of LoadLockedReq hits 899system.cpu.dcache.LoadLockedReq_hits::total 242919 # number of LoadLockedReq hits 900system.cpu.dcache.StoreCondReq_hits::cpu.data 247600 # number of StoreCondReq hits 901system.cpu.dcache.StoreCondReq_hits::total 247600 # number of StoreCondReq hits 902system.cpu.dcache.demand_hits::cpu.data 21018060 # number of demand (read+write) hits 903system.cpu.dcache.demand_hits::total 21018060 # number of demand (read+write) hits 904system.cpu.dcache.overall_hits::cpu.data 21018060 # number of overall hits 905system.cpu.dcache.overall_hits::total 21018060 # number of overall hits 906system.cpu.dcache.ReadReq_misses::cpu.data 736156 # number of ReadReq misses 907system.cpu.dcache.ReadReq_misses::total 736156 # number of ReadReq misses 908system.cpu.dcache.WriteReq_misses::cpu.data 2963249 # number of WriteReq misses 909system.cpu.dcache.WriteReq_misses::total 2963249 # number of WriteReq misses | 1400system.cpu.dcache.replacements 643353 # number of replacements 1401system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use 1402system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. 1403system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. 1404system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. 1405system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. 1406system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor 1407system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy 1408system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy 1409system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits 1410system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits 1411system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits 1412system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits 1413system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits 1414system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits 1415system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits 1416system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits 1417system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits 1418system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits 1419system.cpu.dcache.overall_hits::cpu.data 21012027 # number of overall hits 1420system.cpu.dcache.overall_hits::total 21012027 # number of overall hits 1421system.cpu.dcache.ReadReq_misses::cpu.data 737498 # number of ReadReq misses 1422system.cpu.dcache.ReadReq_misses::total 737498 # number of ReadReq misses 1423system.cpu.dcache.WriteReq_misses::cpu.data 2963942 # number of WriteReq misses 1424system.cpu.dcache.WriteReq_misses::total 2963942 # number of WriteReq misses |
| 910system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses 911system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses | 1425system.cpu.dcache.LoadLockedReq_misses::cpu.data 13539 # number of LoadLockedReq misses 1426system.cpu.dcache.LoadLockedReq_misses::total 13539 # number of LoadLockedReq misses |
| 912system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses 913system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses 914system.cpu.dcache.demand_misses::cpu.data 3699405 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 3699405 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 3699405 # number of overall misses 917system.cpu.dcache.overall_misses::total 3699405 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 9739284500 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 9739284500 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 104713593229 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles 925system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 114452877729 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 114452877729 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 114452877729 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 114452877729 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 14495102 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 14495102 # number of ReadReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::cpu.data 10222363 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) 934system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) 935system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) | 1427system.cpu.dcache.StoreCondReq_misses::cpu.data 15 # number of StoreCondReq misses 1428system.cpu.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses 1429system.cpu.dcache.demand_misses::cpu.data 3701440 # number of demand (read+write) misses 1430system.cpu.dcache.demand_misses::total 3701440 # number of demand (read+write) misses 1431system.cpu.dcache.overall_misses::cpu.data 3701440 # number of overall misses 1432system.cpu.dcache.overall_misses::total 3701440 # number of overall misses 1433system.cpu.dcache.ReadReq_miss_latency::cpu.data 10068067500 # number of ReadReq miss cycles 1434system.cpu.dcache.ReadReq_miss_latency::total 10068067500 # number of ReadReq miss cycles 1435system.cpu.dcache.WriteReq_miss_latency::cpu.data 132595635732 # number of WriteReq miss cycles 1436system.cpu.dcache.WriteReq_miss_latency::total 132595635732 # number of WriteReq miss cycles 1437system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 183801000 # number of LoadLockedReq miss cycles 1438system.cpu.dcache.LoadLockedReq_miss_latency::total 183801000 # number of LoadLockedReq miss cycles 1439system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 231000 # number of StoreCondReq miss cycles 1440system.cpu.dcache.StoreCondReq_miss_latency::total 231000 # number of StoreCondReq miss cycles 1441system.cpu.dcache.demand_miss_latency::cpu.data 142663703232 # number of demand (read+write) miss cycles 1442system.cpu.dcache.demand_miss_latency::total 142663703232 # number of demand (read+write) miss cycles 1443system.cpu.dcache.overall_miss_latency::cpu.data 142663703232 # number of overall miss cycles 1444system.cpu.dcache.overall_miss_latency::total 142663703232 # number of overall miss cycles 1445system.cpu.dcache.ReadReq_accesses::cpu.data 14491081 # number of ReadReq accesses(hits+misses) 1446system.cpu.dcache.ReadReq_accesses::total 14491081 # number of ReadReq accesses(hits+misses) 1447system.cpu.dcache.WriteReq_accesses::cpu.data 10222386 # number of WriteReq accesses(hits+misses) 1448system.cpu.dcache.WriteReq_accesses::total 10222386 # number of WriteReq accesses(hits+misses) 1449system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256393 # number of LoadLockedReq accesses(hits+misses) 1450system.cpu.dcache.LoadLockedReq_accesses::total 256393 # number of LoadLockedReq accesses(hits+misses) |
| 936system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) 937system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) | 1451system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) 1452system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) |
| 938system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses 939system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses 940system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses 941system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses 942system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses 943system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses 944system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses 945system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses 946system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses 947system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses 948system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses 949system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses 950system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses 951system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses 952system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses 953system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses 954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency 955system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency 956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency 957system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency 958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency 959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency 960system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency 961system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked | 1453system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses 1454system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses 1455system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses 1456system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses 1457system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses 1458system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses 1459system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses 1460system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses 1461system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses 1462system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses 1463system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses 1464system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses 1465system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses 1466system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses 1467system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses 1468system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses 1469system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency 1470system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency 1471system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency 1472system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency 1473system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency 1474system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency 1475system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency 1476system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency 1477system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency 1478system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency 1479system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency 1480system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency 1481system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked 1482system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked 1483system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked 1484system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked 1485system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked 1486system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked |
| 972system.cpu.dcache.fast_writes 0 # number of fast writes performed 973system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1487system.cpu.dcache.fast_writes 0 # number of fast writes performed 1488system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 974system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks 975system.cpu.dcache.writebacks::total 607758 # number of writebacks 976system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits 977system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits 978system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits 979system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits 980system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits 981system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits 982system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits 983system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits 984system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits 985system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits 986system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses 987system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses 988system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses 990system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses 991system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses 992system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses 993system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses 994system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses 995system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses 996system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses 997system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses 998system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles 1002system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles 1003system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles 1004system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles 1005system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles 1006system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles 1007system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles 1008system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles 1009system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles 1010system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles 1011system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles 1012system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles 1013system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles 1014system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles 1015system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles 1016system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses 1017system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses 1018system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses 1019system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses 1020system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses 1021system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses 1022system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses 1023system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses 1024system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses 1025system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses 1026system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses 1027system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses 1028system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency 1029system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency 1030system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency 1031system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency 1032system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency 1033system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency 1034system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency 1035system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency 1036system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency 1037system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency 1038system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency 1039system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency | 1489system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks 1490system.cpu.dcache.writebacks::total 607669 # number of writebacks 1491system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits 1492system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits 1493system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits 1494system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits 1495system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits 1496system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits 1497system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits 1498system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits 1499system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits 1500system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits 1501system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses 1502system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses 1503system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses 1504system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses 1505system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses 1506system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses 1507system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses 1508system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses 1509system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses 1510system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses 1511system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses 1512system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses 1513system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles 1514system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles 1515system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles 1516system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles 1517system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles 1518system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles 1519system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles 1520system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles 1521system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles 1522system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles 1523system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles 1524system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles 1525system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles 1526system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles 1527system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles 1528system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles 1529system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles 1530system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles 1531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses 1532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses 1533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses 1534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses 1535system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses 1536system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses 1537system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses 1538system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses 1539system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses 1540system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses 1541system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses 1542system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses 1543system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency 1544system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency 1545system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency 1546system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency 1547system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency 1548system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency 1549system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency 1550system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency 1551system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency 1552system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency 1553system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency 1554system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency |
| 1040system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1041system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1042system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1043system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1044system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1045system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1047system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1053system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1054system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1055system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1056system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1057system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1058system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1059system.iocache.fast_writes 0 # number of fast writes performed 1060system.iocache.cache_copies 0 # number of cache copies performed | 1555system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1556system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1557system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1558system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1559system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1560system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1561system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1562system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 1568system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1569system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1570system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1571system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1572system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1573system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1574system.iocache.fast_writes 0 # number of fast writes performed 1575system.iocache.cache_copies 0 # number of cache copies performed |
| 1061system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles 1062system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles 1063system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles 1064system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles | 1576system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles 1577system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles 1578system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles 1579system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles |
| 1065system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1066system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1067system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1068system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1069system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1070system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1580system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1581system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1582system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1583system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1584system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1585system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1071system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed | 1586system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed |
| 1072 1073---------- End Simulation Statistics ---------- | 1587 1588---------- End Simulation Statistics ---------- |