| stats.txt (9265:8fe936e937bd) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.537930 # Number of seconds simulated 4sim_ticks 2537929870500 # Number of ticks simulated 5final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 62423 # Simulator instruction rate (inst/s) 8host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.537930 # Number of seconds simulated 4sim_ticks 2537929870500 # Number of ticks simulated 5final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 62423 # Simulator instruction rate (inst/s) 8host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) |
| 64system.l2c.replacements 64349 # number of replacements 65system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use 66system.l2c.total_refs 1931844 # Total number of references to valid blocks. 67system.l2c.sampled_refs 129748 # Sample count of references to valid blocks. 68system.l2c.avg_refs 14.889201 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits 87system.l2c.Writeback_hits::total 609524 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits 90system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits 91system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits 92system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits 93system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits 94system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits 96system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits 97system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits 98system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits 99system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits 100system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits 101system.l2c.overall_hits::cpu.inst 977692 # number of overall hits 102system.l2c.overall_hits::cpu.data 502174 # number of overall hits 103system.l2c.overall_hits::total 1576793 # number of overall hits 104system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 106system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses 107system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses 108system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses 109system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses 110system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses 111system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 112system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 113system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses 114system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses 115system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses 116system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 117system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses 119system.l2c.demand_misses::total 156282 # number of demand (read+write) misses 120system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses 121system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses 122system.l2c.overall_misses::cpu.inst 12366 # number of overall misses 123system.l2c.overall_misses::cpu.data 143849 # number of overall misses 124system.l2c.overall_misses::total 156282 # number of overall misses 125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles 126system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles 127system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles 128system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles 129system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles 130system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles 131system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles 132system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles 133system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles 134system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles 135system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles 136system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles 137system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles 138system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles 139system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles 140system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles 141system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles 142system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles 143system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles 144system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles 145system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles 146system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) 147system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) 148system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) 149system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) 150system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) 151system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) 152system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) 153system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) 154system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) 155system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) 156system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) 158system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) 159system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses 162system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses 163system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses 164system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses 167system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses 168system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses 169system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses 173system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses 178system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses 179system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses 180system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses 181system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses 182system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses 184system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses 185system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses 186system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses 187system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses 189system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses 190system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency 195system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency 196system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency 197system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency 198system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency 199system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency 200system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency 201system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency 202system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency 203system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency 204system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency 205system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency 206system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency 207system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency 208system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency 209system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency 210system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency 211system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 214system.l2c.blocked::no_targets 0 # number of cycles access was blocked 215system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.l2c.fast_writes 0 # number of fast writes performed 218system.l2c.cache_copies 0 # number of cache copies performed 219system.l2c.writebacks::writebacks 59057 # number of writebacks 220system.l2c.writebacks::total 59057 # number of writebacks 221system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 222system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 223system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 224system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 225system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 226system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 227system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 228system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 229system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits 230system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses 231system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 232system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses 235system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses 236system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses 237system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 238system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 239system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses 240system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses 241system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses 242system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 243system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses 244system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses 245system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses 246system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses 247system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 248system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses 249system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses 250system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses 251system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles 252system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles 253system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles 254system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles 255system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles 256system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles 257system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles 258system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 259system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 260system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles 261system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles 262system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles 263system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles 264system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles 265system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles 266system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles 267system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles 268system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles 269system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles 270system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles 271system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles 272system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles 273system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles 274system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles 275system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles 276system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles 277system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles 278system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles 279system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles 280system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses 281system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses 282system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses 283system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses 284system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses 285system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses 286system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses 287system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses 288system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses 289system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses 290system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses 291system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses 292system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses 293system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses 294system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses 295system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses 296system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses 297system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses 298system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses 299system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses 300system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses 301system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency 302system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency 303system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency 304system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency 305system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency 306system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency 307system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency 308system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 309system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 310system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency 311system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency 312system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency 313system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency 314system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency 315system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency 316system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency 317system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency 318system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency 319system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency 320system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency 321system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency 322system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 323system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 324system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 325system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 326system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 327system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 328system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 329system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 330system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 64system.cpu.l2cache.replacements 64349 # number of replacements 65system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use 66system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks. 67system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks. 68system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks. 69system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. 70system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor 71system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor 72system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor 73system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor 74system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor 75system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy 76system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy 77system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 78system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy 79system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy 80system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy 81system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits 82system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits 83system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits 84system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits 85system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits 86system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits 87system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits 88system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits 89system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits 90system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits 91system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits 92system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits 93system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits 94system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits 95system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits 96system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits 97system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits 98system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits 99system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits 100system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits 101system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits 102system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits 103system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits 104system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses 105system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 106system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses 107system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses 108system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses 109system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses 110system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses 111system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 112system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 113system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses 114system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses 115system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses 116system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 117system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses 118system.cpu.l2cache.demand_misses::cpu.data 143849 # number of demand (read+write) misses 119system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses 120system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses 121system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 122system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses 123system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses 124system.cpu.l2cache.overall_misses::total 156282 # number of overall misses 125system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles 126system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles 127system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles 128system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles 129system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles 130system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles 131system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles 132system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles 133system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles 134system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles 135system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles 136system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles 137system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles 138system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles 139system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles 140system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles 141system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles 142system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles 143system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles 144system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles 145system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles 146system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses) 147system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses) 148system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses) 149system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses) 150system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses) 151system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses) 152system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses) 153system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses) 154system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses) 155system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses) 156system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses) 157system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses) 158system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses) 159system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses 160system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses 161system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses 162system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses 163system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses 164system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses 165system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses 166system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses 167system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses 168system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses 169system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses 170system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses 171system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses 172system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses 173system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses 174system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses 175system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses 176system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses 177system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses 178system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses 179system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses 180system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses 181system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses 182system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses 183system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses 184system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses 185system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses 186system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses 187system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses 188system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses 189system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses 190system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency 191system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency 192system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency 193system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency 194system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency 195system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency 196system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency 197system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency 198system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency 199system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency 200system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency 201system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency 202system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency 203system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency 204system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency 205system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency 206system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency 207system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency 208system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency 209system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency 210system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency 211system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 215system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.cpu.l2cache.fast_writes 0 # number of fast writes performed 218system.cpu.l2cache.cache_copies 0 # number of cache copies performed 219system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks 220system.cpu.l2cache.writebacks::total 59057 # number of writebacks 221system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits 222system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 223system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 224system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits 225system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 226system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 227system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits 228system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 229system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits 230system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses 231system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 232system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses 233system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses 234system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses 235system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses 236system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses 237system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 238system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 239system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses 240system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses 241system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses 242system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 243system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses 244system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses 245system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses 246system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses 247system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 248system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses 249system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses 250system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses 251system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles 252system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles 253system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles 254system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles 255system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles 256system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles 257system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles 258system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 259system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 260system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles 261system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles 262system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles 263system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles 264system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles 265system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles 266system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles 267system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles 268system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles 269system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles 270system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles 271system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles 272system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles 273system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles 274system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles 275system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles 276system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles 277system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles 278system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles 279system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles 280system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses 281system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses 282system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses 283system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses 284system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses 285system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses 286system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses 287system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses 288system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses 289system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses 290system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses 291system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses 292system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses 293system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses 294system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses 295system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses 296system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses 297system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses 298system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses 299system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses 300system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses 301system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency 302system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency 303system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency 304system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency 305system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency 306system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency 307system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency 308system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 309system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency 310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency 311system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency 312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency 313system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency 314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency 315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency 316system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency 317system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency 318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency 319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency 320system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency 321system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency 322system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 323system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 324system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 325system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 326system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 327system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 328system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 329system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 330system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 0 # Number of DMA write transactions. 337system.cpu.dtb.inst_hits 0 # ITB inst hits 338system.cpu.dtb.inst_misses 0 # ITB inst misses --- 595 unchanged lines hidden --- | 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 0 # Number of DMA write transactions. 337system.cpu.dtb.inst_hits 0 # ITB inst hits 338system.cpu.dtb.inst_misses 0 # ITB inst misses --- 595 unchanged lines hidden --- |