| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.500827 # Number of seconds simulated 4sim_ticks 2500827052500 # Number of ticks simulated 5final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.502550 # Number of seconds simulated 4sim_ticks 2502549875500 # Number of ticks simulated 5final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 90125 # Simulator instruction rate (inst/s) 8host_op_rate 116367 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3783000939 # Simulator tick rate (ticks/s) 10host_mem_usage 386964 # Number of bytes of host memory used 11host_seconds 661.07 # Real time elapsed on the host 12sim_insts 59579144 # Number of instructions simulated 13sim_ops 76926734 # Number of ops (including micro ops) simulated | 7host_inst_rate 90191 # Simulator instruction rate (inst/s) 8host_op_rate 116452 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3788406278 # Simulator tick rate (ticks/s) 10host_mem_usage 386884 # Number of bytes of host memory used 11host_seconds 660.58 # Real time elapsed on the host 12sim_insts 59578267 # Number of instructions simulated 13sim_ops 76925839 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory 19system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) |
| 14system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 16system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 17system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 18system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 19system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 20system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) 25system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) | 52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) |
| 26system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory 27system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory 28system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory 31system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory 32system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory 33system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory 34system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory 35system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 36system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory 37system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 45system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory 46system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) 64system.l2c.replacements 64425 # number of replacements 65system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use 66system.l2c.total_refs 2029411 # Total number of references to valid blocks. 67system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. 68system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy | 64system.l2c.replacements 64431 # number of replacements 65system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use 66system.l2c.total_refs 2028510 # Total number of references to valid blocks. 67system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. 68system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy |
| 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 78system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits 87system.l2c.Writeback_hits::total 675876 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits 90system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits 91system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits 92system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits 93system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits 94system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits 96system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits 97system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits 98system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits 99system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits 100system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits 101system.l2c.overall_hits::cpu.inst 977061 # number of overall hits 102system.l2c.overall_hits::cpu.data 497363 # number of overall hits 103system.l2c.overall_hits::total 1608896 # number of overall hits 104system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses | 78system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits 87system.l2c.Writeback_hits::total 675442 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits 90system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits 91system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits 92system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits 93system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits 94system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits 96system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits 97system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits 98system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits 99system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits 100system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits 101system.l2c.overall_hits::cpu.inst 977935 # number of overall hits 102system.l2c.overall_hits::cpu.data 496445 # number of overall hits 103system.l2c.overall_hits::total 1608169 # number of overall hits 104system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses |
| 105system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses | 105system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses |
| 106system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses 107system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses 108system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses 109system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses 110system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses 111system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses 112system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses 113system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses 114system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses 115system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses | 106system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses 107system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses 108system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses 109system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses 110system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses 111system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 112system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 113system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses 114system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses 115system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses |
| 116system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses | 116system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses |
| 117system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses 119system.l2c.demand_misses::total 156375 # number of demand (read+write) misses 120system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses | 117system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses 118system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses 119system.l2c.demand_misses::total 156364 # number of demand (read+write) misses 120system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses |
| 121system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses | 121system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses |
| 122system.l2c.overall_misses::cpu.inst 12370 # number of overall misses 123system.l2c.overall_misses::cpu.data 143952 # number of overall misses 124system.l2c.overall_misses::total 156375 # number of overall misses 125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles 126system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles 127system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles 128system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles 129system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles 130system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles 131system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles 132system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles 133system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles 134system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles 135system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles 136system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles 137system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles 138system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles 139system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles 140system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles 141system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles 142system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles 143system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles 144system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles 145system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles 146system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) 147system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) 148system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) 149system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) 150system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) 151system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) 152system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) 153system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) 154system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) 155system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) 156system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) 157system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) 158system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) 159system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses 161system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses 162system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses 163system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses 164system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses 167system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses 168system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses 169system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses | 122system.l2c.overall_misses::cpu.inst 12384 # number of overall misses 123system.l2c.overall_misses::cpu.data 143920 # number of overall misses 124system.l2c.overall_misses::total 156364 # number of overall misses 125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles 126system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles 127system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles 128system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles 129system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles 130system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles 131system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles 132system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles 133system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles 134system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles 135system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles 136system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles 137system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles 138system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles 139system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles 140system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles 141system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles 142system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles 143system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles 144system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) 145system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) 146system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) 147system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) 148system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) 149system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) 150system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) 151system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) 152system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) 153system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) 154system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) 155system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) 156system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) 157system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses 158system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses 159system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses 160system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses 161system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses 162system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses 163system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses 164system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses 165system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses 166system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses 167system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses |
| 170system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses | 168system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses |
| 171system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses 173system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses 174system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses 175system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses 176system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses 177system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses 178system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses 179system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses 180system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses | 169system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses 172system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses 173system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses 174system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses 175system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses 176system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses 177system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses 178system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses |
| 181system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses | 179system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses |
| 182system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses 184system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses 185system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses | 180system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses 181system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses 182system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses 183system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses |
| 186system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses | 184system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses |
| 187system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses 189system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses 190system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency 194system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency 195system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency 196system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency 197system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency 198system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency 199system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency 200system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency 201system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency 202system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency 203system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency 204system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency 205system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency 206system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency 207system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency 208system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency 209system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency 210system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency | 185system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses 186system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses 187system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses 188system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency 189system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency 190system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency 193system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency 194system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency 195system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency 196system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency 197system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency 198system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 199system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency 200system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency 201system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency 202system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency 203system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency 204system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency 205system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency 206system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency |
| 211system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 214system.l2c.blocked::no_targets 0 # number of cycles access was blocked 215system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.l2c.fast_writes 0 # number of fast writes performed 218system.l2c.cache_copies 0 # number of cache copies performed | 207system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 208system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 209system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 210system.l2c.blocked::no_targets 0 # number of cycles access was blocked 211system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 212system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213system.l2c.fast_writes 0 # number of fast writes performed 214system.l2c.cache_copies 0 # number of cache copies performed |
| 219system.l2c.writebacks::writebacks 59134 # number of writebacks 220system.l2c.writebacks::total 59134 # number of writebacks 221system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits | 215system.l2c.writebacks::writebacks 59159 # number of writebacks 216system.l2c.writebacks::total 59159 # number of writebacks 217system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits |
| 222system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits | 218system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits |
| 223system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 224system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits | 219system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits 220system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits |
| 225system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits | 221system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits |
| 226system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 227system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits | 222system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits 223system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits |
| 228system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits | 224system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits |
| 229system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits 230system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses | 225system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits 226system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses |
| 231system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses | 227system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses |
| 232system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses 233system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses 234system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses 235system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses 236system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses 237system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses 238system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses 239system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses 240system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses 241system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses | 228system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses 229system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses 230system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses 231system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses 232system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses 233system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 234system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 235system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses 236system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses 237system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses |
| 242system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses | 238system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses |
| 243system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses 244system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses 245system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses 246system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses | 239system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses 240system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses 241system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses 242system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses |
| 247system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses | 243system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses |
| 248system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses 249system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses 250system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses 251system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles 252system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles 253system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles 254system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles 255system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles 256system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles 257system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles 258system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles 259system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles 260system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles 261system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles 262system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles 263system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles 264system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles 265system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles 266system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles 267system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles 268system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles 269system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles 270system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles 271system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles 272system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles 273system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles 274system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles 275system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles 276system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles 277system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles 278system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles 279system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles 280system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses | 244system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses 245system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses 246system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses 247system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles 248system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles 249system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles 250system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles 251system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles 252system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles 253system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles 254system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles 255system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles 256system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles 257system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles 258system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles 259system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles 260system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles 261system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles 262system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles 263system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles 264system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles 265system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles 266system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles 267system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles 268system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles 269system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles 270system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles 271system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles 272system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles 273system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles 274system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles 275system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles 276system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses |
| 281system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses | 277system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses |
| 282system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses 283system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses 284system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses 285system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses 286system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses 287system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses 288system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses 289system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses 290system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses 291system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses | 278system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses 279system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses 280system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses 281system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses 282system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses 283system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses 284system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses 285system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses 286system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses 287system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses |
| 292system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses | 288system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses |
| 293system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses 294system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses 295system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses 296system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses | 289system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses 290system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses 291system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses 292system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses |
| 297system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses | 293system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses |
| 298system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses 299system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses 300system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses 301system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency 302system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency 303system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency 304system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency 305system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency 306system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency 307system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency | 294system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses 295system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses 296system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses 297system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency 298system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency 299system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency 300system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency 301system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency 302system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency 303system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency |
| 308system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 309system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency | 304system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency 305system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency |
| 310system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency 311system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency 312system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency 313system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency 314system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency 315system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency 316system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency 317system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency 318system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency 319system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency 320system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency 321system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency | 306system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency 307system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency 308system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency 309system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 310system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency 311system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency 312system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency 313system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency 314system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency 315system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency 316system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency 317system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency |
| 322system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 323system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 324system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 325system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 326system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 327system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 328system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 329system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 330system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 0 # Number of DMA write transactions. 337system.cpu.dtb.inst_hits 0 # ITB inst hits 338system.cpu.dtb.inst_misses 0 # ITB inst misses | 318system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 319system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 320system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 321system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 322system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 323system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 324system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 325system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 326system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 328system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 329system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 330system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 331system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 332system.cf0.dma_write_txs 0 # Number of DMA write transactions. 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 339system.cpu.dtb.read_hits 51785537 # DTB read hits 340system.cpu.dtb.read_misses 81591 # DTB read misses 341system.cpu.dtb.write_hits 11872923 # DTB write hits 342system.cpu.dtb.write_misses 18231 # DTB write misses | 335system.cpu.dtb.read_hits 51771660 # DTB read hits 336system.cpu.dtb.read_misses 81258 # DTB read misses 337system.cpu.dtb.write_hits 11880398 # DTB write hits 338system.cpu.dtb.write_misses 17961 # DTB write misses |
| 343system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 344system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 345system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 346system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 339system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 347system.cpu.dtb.flush_entries 4506 # Number of entries that have been flushed from TLB 348system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions 349system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch | 343system.cpu.dtb.flush_entries 4471 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch |
| 350system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 351system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions 352system.cpu.dtb.read_accesses 51867128 # DTB read accesses 353system.cpu.dtb.write_accesses 11891154 # DTB write accesses | 347system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 51852918 # DTB read accesses 349system.cpu.dtb.write_accesses 11898359 # DTB write accesses |
| 354system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 355system.cpu.dtb.hits 63658460 # DTB hits 356system.cpu.dtb.misses 99822 # DTB misses 357system.cpu.dtb.accesses 63758282 # DTB accesses 358system.cpu.itb.inst_hits 13022422 # ITB inst hits 359system.cpu.itb.inst_misses 12153 # ITB inst misses | 351system.cpu.dtb.hits 63652058 # DTB hits 352system.cpu.dtb.misses 99219 # DTB misses 353system.cpu.dtb.accesses 63751277 # DTB accesses 354system.cpu.itb.inst_hits 13142261 # ITB inst hits 355system.cpu.itb.inst_misses 12247 # ITB inst misses |
| 360system.cpu.itb.read_hits 0 # DTB read hits 361system.cpu.itb.read_misses 0 # DTB read misses 362system.cpu.itb.write_hits 0 # DTB write hits 363system.cpu.itb.write_misses 0 # DTB write misses 364system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 366system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 367system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 356system.cpu.itb.read_hits 0 # DTB read hits 357system.cpu.itb.read_misses 0 # DTB read misses 358system.cpu.itb.write_hits 0 # DTB write hits 359system.cpu.itb.write_misses 0 # DTB write misses 360system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 361system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 363system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 368system.cpu.itb.flush_entries 2627 # Number of entries that have been flushed from TLB | 364system.cpu.itb.flush_entries 2634 # Number of entries that have been flushed from TLB |
| 369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 365system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 372system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions | 368system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions |
| 373system.cpu.itb.read_accesses 0 # DTB read accesses 374system.cpu.itb.write_accesses 0 # DTB write accesses | 369system.cpu.itb.read_accesses 0 # DTB read accesses 370system.cpu.itb.write_accesses 0 # DTB write accesses |
| 375system.cpu.itb.inst_accesses 13034575 # ITB inst accesses 376system.cpu.itb.hits 13022422 # DTB hits 377system.cpu.itb.misses 12153 # DTB misses 378system.cpu.itb.accesses 13034575 # DTB accesses 379system.cpu.numCycles 408047924 # number of cpu cycles simulated | 371system.cpu.itb.inst_accesses 13154508 # ITB inst accesses 372system.cpu.itb.hits 13142261 # DTB hits 373system.cpu.itb.misses 12247 # DTB misses 374system.cpu.itb.accesses 13154508 # DTB accesses 375system.cpu.numCycles 413642740 # number of cpu cycles simulated |
| 380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 382system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups 383system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted 384system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect 385system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups 386system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits | 378system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups 379system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted 380system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect 381system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups 382system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits |
| 387system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 383system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 388system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. 389system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. 390system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss 391system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed 392system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered 393system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken 394system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked 395system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing 396system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb 397system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked 398system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 399system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps 400system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions 401system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR 402system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched 403system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed 404system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed 405system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) | 384system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. 385system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. 386system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss 387system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed 388system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered 389system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken 390system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked 391system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing 392system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb 393system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked 394system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 395system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps 396system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions 397system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR 398system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched 399system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed 400system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed 401system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) |
| 408system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 404system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 409system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) 417system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) | 405system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) |
| 418system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 414system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 421system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle 423system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle 424system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle 425system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked 426system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running 427system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking 428system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing 429system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch 430system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction 431system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode 432system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode 433system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing 434system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle 435system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking 436system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst 437system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running 438system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking 439system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename 440system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full 441system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full 443system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers 444system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed 445system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made 446system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups 447system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups 448system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed 449system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing 450system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed 451system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed 452system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer 453system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. 454system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. 455system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. 456system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. 457system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) 458system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ 459system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued 460system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued 461system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling 462system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph 463system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed 464system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle | 417system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle 419system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle 420system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle 421system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked 422system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running 423system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking 424system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing 425system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch 426system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction 427system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode 428system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode 429system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing 430system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle 431system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking 432system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst 433system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running 434system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking 435system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename 436system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full 437system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full 438system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full 439system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers 440system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed 441system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made 442system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups 443system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups 444system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed 445system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing 446system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed 447system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed 448system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer 449system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. 450system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. 451system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. 452system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. 453system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) 454system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ 455system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued 456system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued 457system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling 458system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph 459system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed 460system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle |
| 467system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 463system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 468system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle 473system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle | 464system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle |
| 477system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 473system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 480system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle | 476system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle |
| 481system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 477system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 482system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available 483system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available 511system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available | 478system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available 479system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available 480system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available 484system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available 507system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available 508system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available |
| 513system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 514system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued | 509system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 510system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 511system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued |
| 516system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued 517system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued 518system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued 545system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued 546system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued | 512system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued 513system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued 514system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued 518system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued 541system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued 542system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued |
| 547system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 548system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 543system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 544system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 549system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued 550system.cpu.iq.rate 0.305615 # Inst issue rate 551system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested 552system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) 553system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads 554system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes 555system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses 556system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads 557system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes 558system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses 559system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses 560system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses 561system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores | 545system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued 546system.cpu.iq.rate 0.301258 # Inst issue rate 547system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested 548system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) 549system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads 550system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes 551system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses 552system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads 553system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes 554system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses 555system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses 556system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses 557system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores |
| 562system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 558system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 563system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed 564system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed 565system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations 566system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed | 559system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed 560system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed 561system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations 562system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed |
| 567system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 568system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 563system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 564system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 569system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled 570system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked | 565system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled 566system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked |
| 571system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 567system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 572system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing 573system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking 574system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking 575system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ 576system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch 577system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions 578system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions 579system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions 580system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall 581system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall 582system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations 583system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly 584system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly 585system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute 586system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions 587system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed 588system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute | 568system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing 569system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking 570system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking 571system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ 572system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch 573system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions 574system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions 575system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions 576system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall 577system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall 578system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations 579system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly 580system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly 581system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute 582system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions 583system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed 584system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute |
| 589system.cpu.iew.exec_swp 0 # number of swp insts executed | 585system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 590system.cpu.iew.exec_nop 254480 # number of nop insts executed 591system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed 592system.cpu.iew.exec_branches 11392260 # Number of branches executed 593system.cpu.iew.exec_stores 12383469 # Number of stores executed 594system.cpu.iew.exec_rate 0.298278 # Inst execution rate 595system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit 596system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back 597system.cpu.iew.wb_producers 46962413 # num instructions producing a value 598system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value | 586system.cpu.iew.exec_nop 256054 # number of nop insts executed 587system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed 588system.cpu.iew.exec_branches 11412736 # Number of branches executed 589system.cpu.iew.exec_stores 12391364 # Number of stores executed 590system.cpu.iew.exec_rate 0.293583 # Inst execution rate 591system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit 592system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back 593system.cpu.iew.wb_producers 46459932 # num instructions producing a value 594system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value |
| 599system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 595system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 600system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle 601system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back | 596system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle 597system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back |
| 602system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 598system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 603system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions 604system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions 605system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit 606system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards 607system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted 608system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle | 599system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions 600system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions 601system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit 602system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards 603system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted 604system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle |
| 611system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 607system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 612system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle |
| 621system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 617system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 624system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle 625system.cpu.commit.committedInsts 59729525 # Number of instructions committed 626system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed | 620system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle 621system.cpu.commit.committedInsts 59728648 # Number of instructions committed 622system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed |
| 627system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 623system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 628system.cpu.commit.refs 27513492 # Number of memory references committed 629system.cpu.commit.loads 15715290 # Number of loads committed 630system.cpu.commit.membars 413064 # Number of memory barriers committed 631system.cpu.commit.branches 9904425 # Number of branches committed | 624system.cpu.commit.refs 27513345 # Number of memory references committed 625system.cpu.commit.loads 15715170 # Number of loads committed 626system.cpu.commit.membars 413057 # Number of memory barriers committed 627system.cpu.commit.branches 9904308 # Number of branches committed |
| 632system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. | 628system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. |
| 633system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. 634system.cpu.commit.function_calls 995959 # Number of function calls committed. 635system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached | 629system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. 630system.cpu.commit.function_calls 995953 # Number of function calls committed. 631system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached |
| 636system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 632system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 637system.cpu.rob.rob_reads 240802540 # The number of ROB reads 638system.cpu.rob.rob_writes 206662154 # The number of ROB writes 639system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself 640system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling 641system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 642system.cpu.committedInsts 59579144 # Number of Instructions Simulated 643system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated 644system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated 645system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction 646system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads 647system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle 648system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads 649system.cpu.int_regfile_reads 552215109 # number of integer regfile reads 650system.cpu.int_regfile_writes 88113131 # number of integer regfile writes 651system.cpu.fp_regfile_reads 8314 # number of floating regfile reads 652system.cpu.fp_regfile_writes 2878 # number of floating regfile writes 653system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads 654system.cpu.misc_regfile_writes 912736 # number of misc regfile writes 655system.cpu.icache.replacements 990445 # number of replacements 656system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use 657system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. 658system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. 659system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. 660system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. 661system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor 662system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy 663system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy 664system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits 665system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits 666system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits 667system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits 668system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits 669system.cpu.icache.overall_hits::total 11943122 # number of overall hits 670system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses 671system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses 672system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses 673system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses 674system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses 675system.cpu.icache.overall_misses::total 1075156 # number of overall misses 676system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles 677system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles 678system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles 679system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles 680system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles 681system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles 682system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) 683system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) 684system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses 685system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses 686system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses 687system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses 688system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses 689system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses 690system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses 691system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses 692system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses 693system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses 694system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency 695system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency 696system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency 697system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency 698system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency 699system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency 700system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked | 633system.cpu.rob.rob_reads 246021016 # The number of ROB reads 634system.cpu.rob.rob_writes 206855771 # The number of ROB writes 635system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself 636system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling 637system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 638system.cpu.committedInsts 59578267 # Number of Instructions Simulated 639system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated 640system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated 641system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction 642system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads 643system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle 644system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads 645system.cpu.int_regfile_reads 551124722 # number of integer regfile reads 646system.cpu.int_regfile_writes 87730818 # number of integer regfile writes 647system.cpu.fp_regfile_reads 8186 # number of floating regfile reads 648system.cpu.fp_regfile_writes 2858 # number of floating regfile writes 649system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads 650system.cpu.misc_regfile_writes 912697 # number of misc regfile writes 651system.cpu.icache.replacements 991190 # number of replacements 652system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use 653system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. 654system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. 655system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. 656system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. 657system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor 658system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy 659system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy 660system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits 661system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits 662system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits 663system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits 664system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits 665system.cpu.icache.overall_hits::total 12061455 # number of overall hits 666system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses 667system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses 668system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses 669system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses 670system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses 671system.cpu.icache.overall_misses::total 1076423 # number of overall misses 672system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles 673system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles 674system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles 675system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles 676system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles 677system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles 678system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) 679system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) 680system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses 681system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses 682system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses 683system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses 684system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses 685system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses 686system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses 687system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses 688system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses 689system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses 690system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency 691system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency 692system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency 693system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency 694system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency 695system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency 696system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked |
| 701system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 697system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 702system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked | 698system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked |
| 703system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 699system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 704system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked | 700system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked |
| 705system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 706system.cpu.icache.fast_writes 0 # number of fast writes performed 707system.cpu.icache.cache_copies 0 # number of cache copies performed | 701system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 702system.cpu.icache.fast_writes 0 # number of fast writes performed 703system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 708system.cpu.icache.writebacks::writebacks 67776 # number of writebacks 709system.cpu.icache.writebacks::total 67776 # number of writebacks 710system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits 711system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits 712system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits 713system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits 714system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits 715system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits 716system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses 717system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses 718system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses 719system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses 720system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses 721system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses 722system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles 723system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles 724system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles 725system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles 726system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles 727system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles 729system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles 730system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles 731system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles 732system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses 733system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses 734system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses 735system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses 736system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses 737system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses 738system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency 740system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency 742system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency | 704system.cpu.icache.writebacks::writebacks 67899 # number of writebacks 705system.cpu.icache.writebacks::total 67899 # number of writebacks 706system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits 707system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits 708system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits 709system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits 710system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits 711system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits 712system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses 713system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses 714system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses 715system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses 716system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses 717system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses 718system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles 719system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles 720system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles 721system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles 722system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles 723system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles 724system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles 725system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles 726system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles 727system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles 728system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses 729system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses 730system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses 731system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses 732system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses 733system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses 734system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency 735system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency 736system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency 737system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency 738system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency 739system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency |
| 744system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 745system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 746system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 747system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 748system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 740system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 741system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 742system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 743system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 744system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 749system.cpu.dcache.replacements 644124 # number of replacements 750system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use 751system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. 752system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. 753system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. 754system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. 755system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor 756system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy 757system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy 758system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits 759system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits 760system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits 761system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits 762system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits 763system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits 764system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits 765system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits 766system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits 767system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits 768system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits 769system.cpu.dcache.overall_hits::total 21203803 # number of overall hits 770system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses 771system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses 772system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses 773system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses 774system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses 775system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses 776system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses 777system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses 778system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses 779system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses 780system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses 781system.cpu.dcache.overall_misses::total 3698116 # number of overall misses 782system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles 783system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles 784system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles 785system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles 786system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles 787system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles 788system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles 789system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles 790system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles 791system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles 792system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles 793system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles 794system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) 795system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) | 745system.cpu.dcache.replacements 643139 # number of replacements 746system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use 747system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits 760system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits 762system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits 765system.cpu.dcache.overall_hits::total 21161261 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses 772system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses 773system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses 774system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses 775system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses 776system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses 777system.cpu.dcache.overall_misses::total 3758563 # number of overall misses 778system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles 779system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles 780system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles 781system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles 782system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles 783system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles 784system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles 785system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles 786system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles 787system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles 788system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles 789system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles 790system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) 791system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) |
| 796system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) 797system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) | 792system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) 793system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) |
| 798system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) 799system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) 800system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) 801system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) 802system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses 803system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses 804system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses 805system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses 806system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses 807system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses 808system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses 809system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses 810system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses 811system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses 812system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses 813system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses 814system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses 815system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses 816system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses 817system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses 818system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency 819system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency 820system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency 821system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency 822system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency 823system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency 824system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency 825system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency 826system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency 827system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency 828system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency 829system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency 830system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked 831system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked 832system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked 833system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked 834system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked 835system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked | 794system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) 795system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) 796system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) 797system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) 798system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses 799system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses 800system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses 801system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses 802system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses 803system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses 804system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses 805system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses 806system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses 807system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses 808system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses 809system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses 810system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses 811system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses 812system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses 813system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses 814system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency 815system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency 816system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency 817system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency 818system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency 819system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency 820system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency 821system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency 822system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency 823system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency 824system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency 825system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency 826system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked 827system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked 828system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked 829system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked 830system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked 831system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked |
| 836system.cpu.dcache.fast_writes 0 # number of fast writes performed 837system.cpu.dcache.cache_copies 0 # number of cache copies performed | 832system.cpu.dcache.fast_writes 0 # number of fast writes performed 833system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 838system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks 839system.cpu.dcache.writebacks::total 608100 # number of writebacks 840system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits 841system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits 842system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits 843system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits 844system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits 845system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits 846system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits 847system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits 848system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits 849system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits 850system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses 851system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses 852system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses 853system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses 854system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses 855system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses 856system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses 857system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses 858system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses 859system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses 860system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses 861system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses 862system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles 863system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles 864system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles 865system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles 866system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles 867system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles 868system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles 869system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles 870system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles 871system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles 872system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles 873system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles 874system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles 875system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles 876system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles 877system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles 878system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles 879system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles 880system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses 881system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses 882system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses 883system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses 884system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses 885system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses 886system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses 887system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses 888system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses 889system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses 890system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses 891system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses 892system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency 893system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency 894system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency 895system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency 896system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency 897system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency 898system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency 899system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency 900system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency 901system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency 902system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency 903system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency | 834system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks 835system.cpu.dcache.writebacks::total 607543 # number of writebacks 836system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits 837system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits 838system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits 839system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits 840system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits 841system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits 842system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits 843system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits 844system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits 845system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits 846system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses 847system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses 848system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses 849system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses 850system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses 851system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses 852system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses 853system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses 854system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses 855system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses 856system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses 857system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses 858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles 859system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles 860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles 861system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles 862system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles 863system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles 864system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles 865system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles 866system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles 867system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles 868system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles 869system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles 870system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles 871system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles 872system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles 873system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles 874system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles 875system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles 876system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses 877system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses 878system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses 879system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses 880system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses 881system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses 882system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses 883system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses 884system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses 885system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses 886system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses 887system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses 888system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency 889system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency 890system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency 891system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency 892system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency 893system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency 894system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency 895system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency 896system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency 897system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency 898system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency 899system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency |
| 904system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 905system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 906system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 907system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 908system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 909system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 910system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 911system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 917system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.iocache.blocked::no_targets 0 # number of cycles access was blocked 921system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.iocache.fast_writes 0 # number of fast writes performed 924system.iocache.cache_copies 0 # number of cache copies performed | 900system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 901system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 902system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 903system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 904system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 905system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 906system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 907system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 913system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 914system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 915system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 916system.iocache.blocked::no_targets 0 # number of cycles access was blocked 917system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 918system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 919system.iocache.fast_writes 0 # number of fast writes performed 920system.iocache.cache_copies 0 # number of cache copies performed |
| 925system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles 926system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles 927system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles 928system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles | 921system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles 922system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles 923system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles 924system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles |
| 929system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 930system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 931system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 932system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 933system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 934system.cpu.kern.inst.arm 0 # number of arm instructions executed | 925system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 926system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 927system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 928system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 929system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 930system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 935system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed | 931system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed |
| 936 937---------- End Simulation Statistics ---------- | 932 933---------- End Simulation Statistics ---------- |