| stats.txt (9005:f681719e2e99) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.501686 # Number of seconds simulated 4sim_ticks 2501685689500 # Number of ticks simulated 5final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.501686 # Number of seconds simulated 4sim_ticks 2501685689500 # Number of ticks simulated 5final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 62639 # Simulator instruction rate (inst/s) 8host_op_rate 80877 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2630163340 # Simulator tick rate (ticks/s) 10host_mem_usage 384244 # Number of bytes of host memory used 11host_seconds 951.15 # Real time elapsed on the host | 7host_inst_rate 57858 # Simulator instruction rate (inst/s) 8host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2429415836 # Simulator tick rate (ticks/s) 10host_mem_usage 387132 # Number of bytes of host memory used 11host_seconds 1029.75 # Real time elapsed on the host |
| 12sim_insts 59579009 # Number of instructions simulated 13sim_ops 76926775 # Number of ops (including micro ops) simulated | 12sim_insts 59579009 # Number of instructions simulated 13sim_ops 76926775 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 129658608 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9585736 # Number of bytes written to this memory 17system.physmem.num_reads 14980335 # Number of read requests responded to by this memory 18system.physmem.num_writes 856669 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) 24system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) | 14system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 16system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 17system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 18system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 19system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 20system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) 25system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) 26system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory 27system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory 28system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory 31system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory 32system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory 33system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory 34system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory 35system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 36system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory 37system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 45system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory 46system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) 58system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) |
| 33system.l2c.replacements 119797 # number of replacements 34system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use 35system.l2c.total_refs 1834134 # Total number of references to valid blocks. 36system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. 37system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor --- 93 unchanged lines hidden (view full) --- 134system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses 135system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses 136system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses 137system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses 138system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses 139system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses 140system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses 141system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses | 64system.l2c.replacements 119797 # number of replacements 65system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use 66system.l2c.total_refs 1834134 # Total number of references to valid blocks. 67system.l2c.sampled_refs 150735 # Sample count of references to valid blocks. 68system.l2c.avg_refs 12.167937 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor --- 93 unchanged lines hidden (view full) --- 165system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses 166system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses 167system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses 168system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses 169system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses 170system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses 171system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses 172system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses |
| 173system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses |
|
| 142system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses | 174system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses |
| 175system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses |
|
| 143system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses | 176system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses |
| 177system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses |
|
| 144system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses | 178system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses |
| 179system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses |
|
| 145system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses 146system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses 147system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses 148system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses | 180system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses 181system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses 182system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses 183system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses |
| 184system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses |
|
| 149system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses 150system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses 151system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses 152system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses | 185system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses 186system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses 187system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses 188system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses |
| 189system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses |
|
| 153system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency 154system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency 155system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency 156system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency | 190system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency 191system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency 192system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency 193system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency |
| 194system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency |
|
| 157system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency | 195system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency |
| 196system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency |
|
| 158system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency | 197system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency |
| 198system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency |
|
| 159system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency | 199system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency |
| 200system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency |
|
| 160system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency 161system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency 162system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency 163system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency | 201system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency 202system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency 203system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency 204system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency |
| 205system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency |
|
| 164system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency 165system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency 166system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency 167system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency | 206system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency 207system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency 208system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency 209system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency |
| 210system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency |
|
| 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed --- 60 unchanged lines hidden (view full) --- 236system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles 237system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles 238system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles 239system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles 240system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses 241system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses 242system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses 243system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses | 211system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 214system.l2c.blocked::no_targets 0 # number of cycles access was blocked 215system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.l2c.fast_writes 0 # number of fast writes performed 218system.l2c.cache_copies 0 # number of cache copies performed --- 60 unchanged lines hidden (view full) --- 279system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles 280system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles 281system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles 282system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles 283system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses 284system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses 285system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses 286system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses |
| 287system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses |
|
| 244system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses | 288system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses |
| 289system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses |
|
| 245system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses | 290system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses |
| 291system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses |
|
| 246system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses | 292system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses |
| 293system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses |
|
| 247system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses 248system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses 249system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses 250system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses | 294system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses 295system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses 296system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses 297system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses |
| 298system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses |
|
| 251system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses 252system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses 253system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses 254system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses | 299system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses 300system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses 301system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses 302system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses |
| 303system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses |
|
| 255system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency 256system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency 257system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency 258system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency | 304system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency 305system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency 306system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency 307system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency |
| 308system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency |
|
| 259system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency | 309system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency |
| 310system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency |
|
| 260system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency | 311system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency |
| 312system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency |
|
| 261system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency | 313system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency |
| 314system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency |
|
| 262system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency 263system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency 264system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency 265system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency | 315system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency 316system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency 317system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency 318system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency |
| 319system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency |
|
| 266system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency 267system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency 268system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency 269system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency | 320system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency 321system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency 322system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency 323system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency |
| 324system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency |
|
| 270system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 271system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency | 325system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 326system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 327system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 272system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency | 328system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 329system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 273system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 274system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency | 330system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 331system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 332system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 275system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 276system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 277system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 278system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 279system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 280system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 281system.cf0.dma_write_txs 0 # Number of DMA write transactions. 282system.cpu.dtb.inst_hits 0 # ITB inst hits --- 343 unchanged lines hidden (view full) --- 626system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles 627system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) 628system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) 629system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses 630system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses 631system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses 632system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses 633system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses | 333system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 334system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 335system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 336system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 337system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 338system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 339system.cf0.dma_write_txs 0 # Number of DMA write transactions. 340system.cpu.dtb.inst_hits 0 # ITB inst hits --- 343 unchanged lines hidden (view full) --- 684system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles 685system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses) 686system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses) 687system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses 688system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses 689system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses 690system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses 691system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses |
| 692system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses |
|
| 634system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses | 693system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses |
| 694system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses |
|
| 635system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses | 695system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses |
| 696system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses |
|
| 636system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency | 697system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency |
| 698system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency |
|
| 637system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency | 699system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency |
| 700system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency |
|
| 638system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency | 701system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency |
| 702system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency |
|
| 639system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked 640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 641system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked 642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 643system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked 644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 645system.cpu.icache.fast_writes 0 # number of fast writes performed 646system.cpu.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 664system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles 667system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles 668system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles 669system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles 670system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles 671system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses | 703system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked 704system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 705system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked 706system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 707system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked 708system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 709system.cpu.icache.fast_writes 0 # number of fast writes performed 710system.cpu.icache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 728system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles 729system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles 730system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles 731system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles 732system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles 733system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles 734system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles 735system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses |
| 736system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses |
|
| 672system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses | 737system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses |
| 738system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses |
|
| 673system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses | 739system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses |
| 740system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses |
|
| 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency | 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency |
| 742system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency |
|
| 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency | 743system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency |
| 744system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency |
|
| 676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency | 745system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency |
| 746system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency |
|
| 677system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency | 747system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency |
| 748system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 678system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency | 749system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency |
| 750system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 680system.cpu.dcache.replacements 645895 # number of replacements 681system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use 682system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks. 683system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks. 684system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks. 685system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. 686system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 730system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses) 731system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses) 732system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses) 733system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses 734system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses 735system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses 736system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses 737system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses | 751system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 752system.cpu.dcache.replacements 645895 # number of replacements 753system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use 754system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks. 755system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks. 756system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks. 757system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit. 758system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor --- 43 unchanged lines hidden (view full) --- 802system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses) 803system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses) 804system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses) 805system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses 806system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses 807system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses 808system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses 809system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses |
| 810system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses |
|
| 738system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses | 811system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses |
| 812system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses |
|
| 739system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses | 813system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses |
| 814system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses |
|
| 740system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses | 815system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses |
| 816system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses |
|
| 741system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses | 817system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses |
| 818system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses |
|
| 742system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses | 819system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses |
| 820system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses |
|
| 743system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency | 821system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency |
| 822system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency |
|
| 744system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency | 823system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency |
| 824system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency |
|
| 745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency | 825system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency |
| 826system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency |
|
| 746system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency | 827system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency |
| 828system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency |
|
| 747system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency | 829system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency |
| 830system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency |
|
| 748system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency | 831system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency |
| 832system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency |
|
| 749system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked 750system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked 751system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked 752system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked 753system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked 754system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked 755system.cpu.dcache.fast_writes 0 # number of fast writes performed 756system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 35 unchanged lines hidden (view full) --- 792system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles 793system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles 794system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles 795system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles 796system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles 797system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles 798system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles 799system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses | 833system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked 834system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked 835system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked 836system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked 837system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked 838system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked 839system.cpu.dcache.fast_writes 0 # number of fast writes performed 840system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 35 unchanged lines hidden (view full) --- 876system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles 877system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles 878system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles 879system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles 880system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles 881system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles 882system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles 883system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses |
| 884system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses |
|
| 800system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses | 885system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses |
| 886system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses |
|
| 801system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses | 887system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses |
| 888system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses |
|
| 802system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses | 889system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses |
| 890system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses |
|
| 803system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses | 891system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses |
| 892system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses |
|
| 804system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses | 893system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses |
| 894system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses |
|
| 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency | 895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency |
| 896system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency |
|
| 806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency | 897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency |
| 898system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency |
|
| 807system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency | 899system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency |
| 900system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency |
|
| 808system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency | 901system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency |
| 902system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency |
|
| 809system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency | 903system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency |
| 904system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency |
|
| 810system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency | 905system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency |
| 906system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency |
|
| 811system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency | 907system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency |
| 908system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 812system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency | 909system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency |
| 910system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency |
|
| 813system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency | 911system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency |
| 912system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 814system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 815system.iocache.replacements 0 # number of replacements 816system.iocache.tagsinuse 0 # Cycle average of tags in use 817system.iocache.total_refs 0 # Total number of references to valid blocks. 818system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 819system.iocache.avg_refs nan # Average number of references to valid blocks. 820system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 821system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 826system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 827system.iocache.fast_writes 0 # number of fast writes performed 828system.iocache.cache_copies 0 # number of cache copies performed 829system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles 830system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles 831system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles 832system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles 833system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency | 913system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 914system.iocache.replacements 0 # number of replacements 915system.iocache.tagsinuse 0 # Cycle average of tags in use 916system.iocache.total_refs 0 # Total number of references to valid blocks. 917system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 918system.iocache.avg_refs nan # Average number of references to valid blocks. 919system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 920system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 925system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.iocache.fast_writes 0 # number of fast writes performed 927system.iocache.cache_copies 0 # number of cache copies performed 928system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles 929system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles 930system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles 931system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles 932system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency |
| 933system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency |
|
| 834system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency | 934system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |
| 935system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency |
|
| 835system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 836system.cpu.kern.inst.arm 0 # number of arm instructions executed 837system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed 838 839---------- End Simulation Statistics ---------- | 936system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 937system.cpu.kern.inst.arm 0 # number of arm instructions executed 938system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed 939 940---------- End Simulation Statistics ---------- |