| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.501676 # Number of seconds simulated 4sim_ticks 2501676293500 # Number of ticks simulated 5final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.501676 # Number of seconds simulated 4sim_ticks 2501676293500 # Number of ticks simulated 5final_tick 2501676293500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93944 # Simulator instruction rate (inst/s) 8host_op_rate 121345 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3953091411 # Simulator tick rate (ticks/s) 10host_mem_usage 381372 # Number of bytes of host memory used 11host_seconds 632.84 # Real time elapsed on the host | 7host_inst_rate 32202 # Simulator instruction rate (inst/s) 8host_op_rate 41595 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1355039119 # Simulator tick rate (ticks/s) 10host_mem_usage 388344 # Number of bytes of host memory used 11host_seconds 1846.20 # Real time elapsed on the host |
| 12sim_insts 59451291 # Number of instructions simulated 13sim_ops 76792341 # Number of ops (including micro ops) simulated | 12sim_insts 59451291 # Number of instructions simulated 13sim_ops 76792341 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) 22system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) | |
| 23system.physmem.bytes_read 129652968 # Number of bytes read from this memory 24system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory 25system.physmem.bytes_written 9585096 # Number of bytes written to this memory 26system.physmem.num_reads 14979455 # Number of read requests responded to by this memory 27system.physmem.num_writes 856659 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read 129652968 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1121024 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9585096 # Number of bytes written to this memory 17system.physmem.num_reads 14979455 # Number of read requests responded to by this memory 18system.physmem.num_writes 856659 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 51826437 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 448109 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 3831469 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 55657906 # Total bandwidth to/from this memory (bytes/s) |
| 24system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) |
|
| 33system.l2c.replacements 119784 # number of replacements 34system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use 35system.l2c.total_refs 1826145 # Total number of references to valid blocks. 36system.l2c.sampled_refs 150763 # Sample count of references to valid blocks. 37system.l2c.avg_refs 12.112687 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor --- 123 unchanged lines hidden (view full) --- 164system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency 165system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency 166system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency 167system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 33system.l2c.replacements 119784 # number of replacements 34system.l2c.tagsinuse 25999.615357 # Cycle average of tags in use 35system.l2c.total_refs 1826145 # Total number of references to valid blocks. 36system.l2c.sampled_refs 150763 # Sample count of references to valid blocks. 37system.l2c.avg_refs 12.112687 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 14272.421964 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 65.344146 # Average occupied blocks per requestor --- 123 unchanged lines hidden (view full) --- 164system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369 # average overall miss latency 165system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077 # average overall miss latency 166system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438 # average overall miss latency 167system.l2c.overall_avg_miss_latency::cpu.data 52470.529965 # average overall miss latency 168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 171system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 172system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed 176system.l2c.writebacks::writebacks 102641 # number of writebacks 177system.l2c.writebacks::total 102641 # number of writebacks 178system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 179system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 180system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 181system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits --- 451 unchanged lines hidden (view full) --- 633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked | 174system.l2c.fast_writes 0 # number of fast writes performed 175system.l2c.cache_copies 0 # number of cache copies performed 176system.l2c.writebacks::writebacks 102641 # number of writebacks 177system.l2c.writebacks::total 102641 # number of writebacks 178system.l2c.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits 179system.l2c.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits 180system.l2c.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits 181system.l2c.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits --- 451 unchanged lines hidden (view full) --- 633system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14727.471384 # average ReadReq miss latency 634system.cpu.icache.demand_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 14727.471384 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 3199983 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 416 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 7692.266827 # average number of cycles each access was blocked |
| 641system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 641system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.writebacks::writebacks 59844 # number of writebacks 645system.cpu.icache.writebacks::total 59844 # number of writebacks 646system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits 647system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits 648system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits 649system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits --- 158 unchanged lines hidden (view full) --- 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 809system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 811system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 812system.iocache.replacements 0 # number of replacements 813system.iocache.tagsinuse 0 # Cycle average of tags in use 814system.iocache.total_refs 0 # Total number of references to valid blocks. 815system.iocache.sampled_refs 0 # Sample count of references to valid blocks. | 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.writebacks::writebacks 59844 # number of writebacks 645system.cpu.icache.writebacks::total 59844 # number of writebacks 646system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91810 # number of ReadReq MSHR hits 647system.cpu.icache.ReadReq_mshr_hits::total 91810 # number of ReadReq MSHR hits 648system.cpu.icache.demand_mshr_hits::cpu.inst 91810 # number of demand (read+write) MSHR hits 649system.cpu.icache.demand_mshr_hits::total 91810 # number of demand (read+write) MSHR hits --- 158 unchanged lines hidden (view full) --- 808system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 809system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 810system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 811system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 812system.iocache.replacements 0 # number of replacements 813system.iocache.tagsinuse 0 # Cycle average of tags in use 814system.iocache.total_refs 0 # Total number of references to valid blocks. 815system.iocache.sampled_refs 0 # Sample count of references to valid blocks. |
| 816system.iocache.avg_refs no_value # Average number of references to valid blocks. | 816system.iocache.avg_refs nan # Average number of references to valid blocks. |
| 817system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 818system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 817system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 818system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 819system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 820system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 821system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 822system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 823system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 822system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 823system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 824system.iocache.fast_writes 0 # number of fast writes performed 825system.iocache.cache_copies 0 # number of cache copies performed 826system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles 827system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles 828system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles 829system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles 830system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 831system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 832system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 833system.cpu.kern.inst.arm 0 # number of arm instructions executed 834system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed 835 836---------- End Simulation Statistics ---------- | 824system.iocache.fast_writes 0 # number of fast writes performed 825system.iocache.cache_copies 0 # number of cache copies performed 826system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of ReadReq MSHR uncacheable cycles 827system.iocache.ReadReq_mshr_uncacheable_latency::total 1296055922339 # number of ReadReq MSHR uncacheable cycles 828system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296055922339 # number of overall MSHR uncacheable cycles 829system.iocache.overall_mshr_uncacheable_latency::total 1296055922339 # number of overall MSHR uncacheable cycles 830system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 831system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 832system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 833system.cpu.kern.inst.arm 0 # number of arm instructions executed 834system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed 835 836---------- End Simulation Statistics ---------- |