| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.827853 # Number of seconds simulated 4sim_ticks 2827853096000 # Number of ticks simulated 5final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.829113 # Number of seconds simulated 4sim_ticks 2829112944500 # Number of ticks simulated 5final_tick 2829112944500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 94322 # Simulator instruction rate (inst/s) 8host_op_rate 114411 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2357194570 # Simulator tick rate (ticks/s) 10host_mem_usage 589152 # Number of bytes of host memory used 11host_seconds 1199.67 # Real time elapsed on the host 12sim_insts 113155640 # Number of instructions simulated 13sim_ops 137255479 # Number of ops (including micro ops) simulated | 7host_inst_rate 77107 # Simulator instruction rate (inst/s) 8host_op_rate 93526 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1927521729 # Simulator tick rate (ticks/s) 10host_mem_usage 584852 # Number of bytes of host memory used 11host_seconds 1467.75 # Real time elapsed on the host 12sim_insts 113173049 # Number of instructions simulated 13sim_ops 137272583 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 896 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1316512 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9473064 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 10791880 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1316512 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1316512 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8091648 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 8109172 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 14 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22822 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 148537 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 171395 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 126432 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 130813 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 317 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 465344 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3348422 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_read::total 3814581 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 465344 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 465344 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2860136 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6194 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2866330 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2860136 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 317 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 465344 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3354616 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) |
| 54system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 176441 # Number of read requests accepted 56system.physmem.writeReqs 135743 # Number of write requests accepted 57system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one | 54system.physmem.bw_total::total 6680911 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 171396 # Number of read requests accepted 56system.physmem.writeReqs 130813 # Number of write requests accepted 57system.physmem.readBursts 171396 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 130813 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10959744 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8121728 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10791944 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8109172 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one |
| 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 11743 # Per bank write bursts 68system.physmem.perBankRdBursts::1 11227 # Per bank write bursts 69system.physmem.perBankRdBursts::2 11041 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10652 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13485 # Per bank write bursts 72system.physmem.perBankRdBursts::5 11002 # Per bank write bursts 73system.physmem.perBankRdBursts::6 11432 # Per bank write bursts 74system.physmem.perBankRdBursts::7 11844 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10383 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10947 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10471 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9569 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10361 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11110 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10361 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10660 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8764 # Per bank write bursts 84system.physmem.perBankWrBursts::1 8604 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8676 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8310 # Per bank write bursts 87system.physmem.perBankWrBursts::4 8074 # Per bank write bursts 88system.physmem.perBankWrBursts::5 8230 # Per bank write bursts 89system.physmem.perBankWrBursts::6 8228 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8800 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7938 # Per bank write bursts 92system.physmem.perBankWrBursts::9 8472 # Per bank write bursts 93system.physmem.perBankWrBursts::10 8080 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7388 # Per bank write bursts 95system.physmem.perBankWrBursts::12 8035 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8487 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7854 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7901 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 10680 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10044 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10837 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10904 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13724 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10680 # Per bank write bursts 73system.physmem.perBankRdBursts::6 11438 # Per bank write bursts 74system.physmem.perBankRdBursts::7 11401 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10103 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10404 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10359 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9493 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10229 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11052 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10015 # Per bank write bursts 82system.physmem.perBankRdBursts::15 9883 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8063 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7694 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8368 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8157 # Per bank write bursts 87system.physmem.perBankWrBursts::4 8127 # Per bank write bursts 88system.physmem.perBankWrBursts::5 8035 # Per bank write bursts 89system.physmem.perBankWrBursts::6 8542 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8476 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7684 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7982 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7772 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7097 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7777 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8429 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7462 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7237 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 101system.physmem.totGap 2827852861000 # Total gap between requests | 100system.physmem.numWrRetry 78 # Number of times write queue was full causing retry 101system.physmem.totGap 2829112709500 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) |
| 106system.physmem.readPktSize::4 2996 # Read request sizes (log2) | 106system.physmem.readPktSize::4 3002 # Read request sizes (log2) |
| 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 172889 # Read request sizes (log2) | 108system.physmem.readPktSize::6 167838 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 131362 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 126432 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 150032 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 14994 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 5338 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 866 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads 270system.physmem.totQLat 2116192000 # Total ticks spent queuing 271system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 275system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s | 163system.physmem.wrQLenPdf::15 1809 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2587 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5567 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6032 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6526 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6397 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6800 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 7150 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7716 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7672 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 8616 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9083 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7704 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7368 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 7357 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7214 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 6760 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 6858 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 546 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 532 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 455 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 387 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 299 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 279 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 274 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 291 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 258 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 257 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 253 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 314 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 246 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 250 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 238 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 199 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 224 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 155 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 167 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 208 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 168 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 201 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 169 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 207 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61260 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 311.483382 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 183.687105 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 329.840241 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 22553 36.82% 36.82% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14650 23.91% 60.73% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6334 10.34% 71.07% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3752 6.12% 77.19% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2675 4.37% 81.56% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1648 2.69% 84.25% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1058 1.73% 85.98% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1036 1.69% 87.67% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7554 12.33% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61260 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6323 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.072592 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 535.871052 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6321 99.97% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6323 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6323 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 20.069904 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 18.255220 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 14.875839 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 5596 88.50% 88.50% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 82 1.30% 89.80% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 53 0.84% 90.64% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 37 0.59% 91.22% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 252 3.99% 95.21% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 36 0.57% 95.78% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 9 0.14% 95.92% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 12 0.19% 96.11% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 7 0.11% 96.22% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 4 0.06% 96.28% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 6 0.09% 96.38% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 6 0.09% 96.47% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 139 2.20% 98.67% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 10 0.16% 98.83% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 5 0.08% 98.91% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 3 0.05% 98.96% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 3 0.05% 99.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 2 0.03% 99.04% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 3 0.05% 99.08% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.10% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.02% 99.11% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::108-111 12 0.19% 99.30% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 4 0.06% 99.37% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 15 0.24% 99.60% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 4 0.06% 99.67% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.02% 99.68% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 3 0.05% 99.73% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 1 0.02% 99.75% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 1 0.02% 99.76% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 2 0.03% 99.79% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 99.84% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::180-183 1 0.02% 99.86% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::188-191 1 0.02% 99.89% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::192-195 4 0.06% 99.95% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::196-199 1 0.02% 99.97% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::200-203 2 0.03% 100.00% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::total 6323 # Writes before turning the bus around for reads 277system.physmem.totQLat 4766161750 # Total ticks spent queuing 278system.physmem.totMemAccLat 7977024250 # Total ticks spent from burst creation until serviced by the DRAM 279system.physmem.totBusLat 856230000 # Total ticks spent in databus transfers 280system.physmem.avgQLat 27832.09 # Average queueing delay per DRAM burst 281system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst 282system.physmem.avgMemAccLat 46581.98 # Average memory access latency per DRAM burst 283system.physmem.avgRdBW 3.87 # Average DRAM read bandwidth in MiByte/s 284system.physmem.avgWrBW 2.87 # Average achieved write bandwidth in MiByte/s 285system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s 286system.physmem.avgWrBWSys 2.87 # Average system write bandwidth in MiByte/s |
| 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.05 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 287system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 288system.physmem.busUtil 0.05 # Data bus utilization in percentage 289system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 290system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 284system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 285system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing 286system.physmem.readRowHits 145153 # Number of row buffer hits during reads 287system.physmem.writeRowHits 97985 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes 290system.physmem.avgGap 9058288.90 # Average gap between requests 291system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) 300system.physmem_0.averagePower 669.386141 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states 302system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 304system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 306system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) 314system.physmem_1.averagePower 669.308944 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states 316system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 318system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 320system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 291system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 292system.physmem.avgWrQLen 22.57 # Average write queue length when enqueuing 293system.physmem.readRowHits 141751 # Number of row buffer hits during reads 294system.physmem.writeRowHits 95137 # Number of row buffer hits during writes 295system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads 296system.physmem.writeRowHitRate 74.96 # Row buffer hit rate for writes 297system.physmem.avgGap 9361444.26 # Average gap between requests 298system.physmem.pageHitRate 79.45 # Row buffer hit rate, read and write combined 299system.physmem_0.actEnergy 229201140 # Energy for activate commands per rank (pJ) 300system.physmem_0.preEnergy 121823295 # Energy for precharge commands per rank (pJ) 301system.physmem_0.readEnergy 640515120 # Energy for read commands per rank (pJ) 302system.physmem_0.writeEnergy 341711640 # Energy for write commands per rank (pJ) 303system.physmem_0.refreshEnergy 5262547680.000001 # Energy for refresh commands per rank (pJ) 304system.physmem_0.actBackEnergy 4339877970 # Energy for active background per rank (pJ) 305system.physmem_0.preBackEnergy 323354400 # Energy for precharge background per rank (pJ) 306system.physmem_0.actPowerDownEnergy 10814226390 # Energy for active power-down per rank (pJ) 307system.physmem_0.prePowerDownEnergy 7334392800 # Energy for precharge power-down per rank (pJ) 308system.physmem_0.selfRefreshEnergy 667253476395 # Energy for self refresh per rank (pJ) 309system.physmem_0.totalEnergy 696663805260 # Total energy per rank (pJ) 310system.physmem_0.averagePower 246.248141 # Core power per rank (mW) 311system.physmem_0.totalIdleTime 2818581671250 # Total Idle time Per DRAM Rank 312system.physmem_0.memoryStateTime::IDLE 598120000 # Time in different power states 313system.physmem_0.memoryStateTime::REF 2237496000 # Time in different power states 314system.physmem_0.memoryStateTime::SREF 2775932271000 # Time in different power states 315system.physmem_0.memoryStateTime::PRE_PDN 19100075750 # Time in different power states 316system.physmem_0.memoryStateTime::ACT 7529604250 # Time in different power states 317system.physmem_0.memoryStateTime::ACT_PDN 23715377500 # Time in different power states 318system.physmem_1.actEnergy 208195260 # Energy for activate commands per rank (pJ) 319system.physmem_1.preEnergy 110658405 # Energy for precharge commands per rank (pJ) 320system.physmem_1.readEnergy 582181320 # Energy for read commands per rank (pJ) 321system.physmem_1.writeEnergy 320716800 # Energy for write commands per rank (pJ) 322system.physmem_1.refreshEnergy 5105199840.000001 # Energy for refresh commands per rank (pJ) 323system.physmem_1.actBackEnergy 4092887280 # Energy for active background per rank (pJ) 324system.physmem_1.preBackEnergy 324388800 # Energy for precharge background per rank (pJ) 325system.physmem_1.actPowerDownEnergy 10096669920 # Energy for active power-down per rank (pJ) 326system.physmem_1.prePowerDownEnergy 7288782240 # Energy for precharge power-down per rank (pJ) 327system.physmem_1.selfRefreshEnergy 667807505910 # Energy for self refresh per rank (pJ) 328system.physmem_1.totalEnergy 695939317005 # Total energy per rank (pJ) 329system.physmem_1.averagePower 245.992058 # Core power per rank (mW) 330system.physmem_1.totalIdleTime 2819287837500 # Total Idle time Per DRAM Rank 331system.physmem_1.memoryStateTime::IDLE 611681500 # Time in different power states 332system.physmem_1.memoryStateTime::REF 2171134000 # Time in different power states 333system.physmem_1.memoryStateTime::SREF 2778164795750 # Time in different power states 334system.physmem_1.memoryStateTime::PRE_PDN 18981177000 # Time in different power states 335system.physmem_1.memoryStateTime::ACT 7042291500 # Time in different power states 336system.physmem_1.memoryStateTime::ACT_PDN 22141864750 # Time in different power states 337system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 321system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 327system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) | 338system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 339system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 340system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 341system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 342system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 343system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 344system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 345system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 346system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 349system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) |
| 333system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 334system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 335system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 350system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 351system.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 352system.bridge.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 336system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 353system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 354system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 355system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 356system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 357system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 358system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 342system.cpu.branchPred.lookups 46859222 # Number of BP lookups 343system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits | 359system.cpu.branchPred.lookups 46887151 # Number of BP lookups 360system.cpu.branchPred.condPredicted 24003532 # Number of conditional branches predicted 361system.cpu.branchPred.condIncorrect 1173792 # Number of conditional branches incorrect 362system.cpu.branchPred.BTBLookups 29506695 # Number of BTB lookups 363system.cpu.branchPred.BTBHits 13539046 # Number of BTB hits |
| 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 364system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 348system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. 351system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. 352system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. 353system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. 354system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. | 365system.cpu.branchPred.BTBHitPct 45.884658 # BTB Hit Percentage 366system.cpu.branchPred.usedRAS 11754270 # Number of times the RAS was used to get a target. 367system.cpu.branchPred.RASInCorrect 34776 # Number of incorrect RAS predictions. 368system.cpu.branchPred.indirectLookups 7941183 # Number of indirect predictor lookups. 369system.cpu.branchPred.indirectHits 7796256 # Number of indirect target hits. 370system.cpu.branchPred.indirectMisses 144927 # Number of indirect misses. 371system.cpu.branchPredindirectMispredicted 60295 # Number of mispredicted indirect branches. |
| 355system.cpu_clk_domain.clock 500 # Clock period in ticks | 372system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 356system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 373system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 374system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 395system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 398system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 399system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 400system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 401system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 402system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 386system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 387system.cpu.dtb.walker.walks 72426 # Table walker walks requested 388system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors 389system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate 390system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate 391system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting 392system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution 431system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated 432system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated 433system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated 434system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst | 403system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 404system.cpu.dtb.walker.walks 71256 # Table walker walks requested 405system.cpu.dtb.walker.walksShort 71256 # Table walker walks initiated with short descriptors 406system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29049 # Level at which table walker walks with short descriptors terminate 407system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23358 # Level at which table walker walks with short descriptors terminate 408system.cpu.dtb.walker.walksSquashedBefore 18849 # Table walks squashed before starting 409system.cpu.dtb.walker.walkWaitTime::samples 52407 # Table walker wait (enqueue to first request) latency 410system.cpu.dtb.walker.walkWaitTime::mean 389.146488 # Table walker wait (enqueue to first request) latency 411system.cpu.dtb.walker.walkWaitTime::stdev 2289.126746 # Table walker wait (enqueue to first request) latency 412system.cpu.dtb.walker.walkWaitTime::0-4095 50564 96.48% 96.48% # Table walker wait (enqueue to first request) latency 413system.cpu.dtb.walker.walkWaitTime::4096-8191 708 1.35% 97.83% # Table walker wait (enqueue to first request) latency 414system.cpu.dtb.walker.walkWaitTime::8192-12287 582 1.11% 98.94% # Table walker wait (enqueue to first request) latency 415system.cpu.dtb.walker.walkWaitTime::12288-16383 319 0.61% 99.55% # Table walker wait (enqueue to first request) latency 416system.cpu.dtb.walker.walkWaitTime::16384-20479 67 0.13% 99.68% # Table walker wait (enqueue to first request) latency 417system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.90% # Table walker wait (enqueue to first request) latency 418system.cpu.dtb.walker.walkWaitTime::24576-28671 32 0.06% 99.96% # Table walker wait (enqueue to first request) latency 419system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 420system.cpu.dtb.walker.walkWaitTime::32768-36863 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency 421system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency 422system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency 423system.cpu.dtb.walker.walkWaitTime::45056-49151 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency 424system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 425system.cpu.dtb.walker.walkWaitTime::total 52407 # Table walker wait (enqueue to first request) latency 426system.cpu.dtb.walker.walkCompletionTime::samples 16824 # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::mean 9444.513790 # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walkCompletionTime::gmean 7664.409790 # Table walker service (enqueue to completion) latency 429system.cpu.dtb.walker.walkCompletionTime::stdev 6506.438101 # Table walker service (enqueue to completion) latency 430system.cpu.dtb.walker.walkCompletionTime::0-8191 8278 49.20% 49.20% # Table walker service (enqueue to completion) latency 431system.cpu.dtb.walker.walkCompletionTime::8192-16383 6918 41.12% 90.32% # Table walker service (enqueue to completion) latency 432system.cpu.dtb.walker.walkCompletionTime::16384-24575 1373 8.16% 98.48% # Table walker service (enqueue to completion) latency 433system.cpu.dtb.walker.walkCompletionTime::24576-32767 165 0.98% 99.47% # Table walker service (enqueue to completion) latency 434system.cpu.dtb.walker.walkCompletionTime::32768-40959 22 0.13% 99.60% # Table walker service (enqueue to completion) latency 435system.cpu.dtb.walker.walkCompletionTime::40960-49151 59 0.35% 99.95% # Table walker service (enqueue to completion) latency 436system.cpu.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency 437system.cpu.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.96% # Table walker service (enqueue to completion) latency 438system.cpu.dtb.walker.walkCompletionTime::65536-73727 1 0.01% 99.96% # Table walker service (enqueue to completion) latency 439system.cpu.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 440system.cpu.dtb.walker.walkCompletionTime::98304-106495 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 441system.cpu.dtb.walker.walkCompletionTime::114688-122879 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 442system.cpu.dtb.walker.walkCompletionTime::total 16824 # Table walker service (enqueue to completion) latency 443system.cpu.dtb.walker.walksPending::samples 118987489224 # Table walker pending requests distribution 444system.cpu.dtb.walker.walksPending::mean 0.630928 # Table walker pending requests distribution 445system.cpu.dtb.walker.walksPending::stdev 0.488775 # Table walker pending requests distribution 446system.cpu.dtb.walker.walksPending::0-1 118941247224 99.96% 99.96% # Table walker pending requests distribution 447system.cpu.dtb.walker.walksPending::2-3 32120500 0.03% 99.99% # Table walker pending requests distribution 448system.cpu.dtb.walker.walksPending::4-5 6765500 0.01% 99.99% # Table walker pending requests distribution 449system.cpu.dtb.walker.walksPending::6-7 4407000 0.00% 100.00% # Table walker pending requests distribution 450system.cpu.dtb.walker.walksPending::8-9 968000 0.00% 100.00% # Table walker pending requests distribution 451system.cpu.dtb.walker.walksPending::10-11 470000 0.00% 100.00% # Table walker pending requests distribution 452system.cpu.dtb.walker.walksPending::12-13 1161500 0.00% 100.00% # Table walker pending requests distribution 453system.cpu.dtb.walker.walksPending::14-15 338000 0.00% 100.00% # Table walker pending requests distribution 454system.cpu.dtb.walker.walksPending::16-17 11500 0.00% 100.00% # Table walker pending requests distribution 455system.cpu.dtb.walker.walksPending::total 118987489224 # Table walker pending requests distribution 456system.cpu.dtb.walker.walkPageSizes::4K 6321 82.34% 82.34% # Table walker page sizes translated 457system.cpu.dtb.walker.walkPageSizes::1M 1356 17.66% 100.00% # Table walker page sizes translated 458system.cpu.dtb.walker.walkPageSizes::total 7677 # Table walker page sizes translated 459system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71256 # Table walker requests started/completed, data/inst |
| 435system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 460system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 436system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst | 461system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71256 # Table walker requests started/completed, data/inst 462system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7677 # Table walker requests started/completed, data/inst |
| 438system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 463system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 439system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst | 464system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7677 # Table walker requests started/completed, data/inst 465system.cpu.dtb.walker.walkRequestOrigin::total 78933 # Table walker requests started/completed, data/inst |
| 441system.cpu.dtb.inst_hits 0 # ITB inst hits 442system.cpu.dtb.inst_misses 0 # ITB inst misses | 466system.cpu.dtb.inst_hits 0 # ITB inst hits 467system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 443system.cpu.dtb.read_hits 25423365 # DTB read hits 444system.cpu.dtb.read_misses 62664 # DTB read misses 445system.cpu.dtb.write_hits 19868926 # DTB write hits 446system.cpu.dtb.write_misses 9762 # DTB write misses | 468system.cpu.dtb.read_hits 25423703 # DTB read hits 469system.cpu.dtb.read_misses 61573 # DTB read misses 470system.cpu.dtb.write_hits 19869711 # DTB write hits 471system.cpu.dtb.write_misses 9683 # DTB write misses |
| 447system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 448system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 449system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 450system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 472system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 473system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 474system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 475system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 451system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB 452system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions 453system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch | 476system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB 477system.cpu.dtb.align_faults 365 # Number of TLB faults due to alignment restrictions 478system.cpu.dtb.prefetch_faults 2214 # Number of TLB faults due to prefetch |
| 454system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 479system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 455system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions 456system.cpu.dtb.read_accesses 25486029 # DTB read accesses 457system.cpu.dtb.write_accesses 19878688 # DTB write accesses | 480system.cpu.dtb.perms_faults 1309 # Number of TLB faults due to permissions restrictions 481system.cpu.dtb.read_accesses 25485276 # DTB read accesses 482system.cpu.dtb.write_accesses 19879394 # DTB write accesses |
| 458system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 483system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 459system.cpu.dtb.hits 45292291 # DTB hits 460system.cpu.dtb.misses 72426 # DTB misses 461system.cpu.dtb.accesses 45364717 # DTB accesses 462system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 484system.cpu.dtb.hits 45293414 # DTB hits 485system.cpu.dtb.misses 71256 # DTB misses 486system.cpu.dtb.accesses 45364670 # DTB accesses 487system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 463system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 484system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 486system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 487system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 488system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 489system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 490system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 491system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 488system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 489system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 490system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 492system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 493system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 494system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 495system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 509system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 510system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 511system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 512system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 513system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 514system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 515system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 516system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 492system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 493system.cpu.itb.walker.walks 12855 # Table walker walks requested 494system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors 495system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate 496system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate 497system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting 498system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution 529system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution 530system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution 531system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution 532system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated 533system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated 534system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated | 517system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 518system.cpu.itb.walker.walks 12694 # Table walker walks requested 519system.cpu.itb.walker.walksShort 12694 # Table walker walks initiated with short descriptors 520system.cpu.itb.walker.walksShortTerminationLevel::Level1 3385 # Level at which table walker walks with short descriptors terminate 521system.cpu.itb.walker.walksShortTerminationLevel::Level2 7744 # Level at which table walker walks with short descriptors terminate 522system.cpu.itb.walker.walksSquashedBefore 1565 # Table walks squashed before starting 523system.cpu.itb.walker.walkWaitTime::samples 11129 # Table walker wait (enqueue to first request) latency 524system.cpu.itb.walker.walkWaitTime::mean 587.519094 # Table walker wait (enqueue to first request) latency 525system.cpu.itb.walker.walkWaitTime::stdev 2554.039533 # Table walker wait (enqueue to first request) latency 526system.cpu.itb.walker.walkWaitTime::0-4095 10635 95.56% 95.56% # Table walker wait (enqueue to first request) latency 527system.cpu.itb.walker.walkWaitTime::4096-8191 121 1.09% 96.65% # Table walker wait (enqueue to first request) latency 528system.cpu.itb.walker.walkWaitTime::8192-12287 223 2.00% 98.65% # Table walker wait (enqueue to first request) latency 529system.cpu.itb.walker.walkWaitTime::12288-16383 105 0.94% 99.60% # Table walker wait (enqueue to first request) latency 530system.cpu.itb.walker.walkWaitTime::16384-20479 19 0.17% 99.77% # Table walker wait (enqueue to first request) latency 531system.cpu.itb.walker.walkWaitTime::20480-24575 20 0.18% 99.95% # Table walker wait (enqueue to first request) latency 532system.cpu.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency 533system.cpu.itb.walker.walkWaitTime::40960-45055 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu.itb.walker.walkWaitTime::total 11129 # Table walker wait (enqueue to first request) latency 535system.cpu.itb.walker.walkCompletionTime::samples 4883 # Table walker service (enqueue to completion) latency 536system.cpu.itb.walker.walkCompletionTime::mean 9054.884292 # Table walker service (enqueue to completion) latency 537system.cpu.itb.walker.walkCompletionTime::gmean 7027.204830 # Table walker service (enqueue to completion) latency 538system.cpu.itb.walker.walkCompletionTime::stdev 11165.478993 # Table walker service (enqueue to completion) latency 539system.cpu.itb.walker.walkCompletionTime::0-65535 4881 99.96% 99.96% # Table walker service (enqueue to completion) latency 540system.cpu.itb.walker.walkCompletionTime::65536-131071 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 541system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 542system.cpu.itb.walker.walkCompletionTime::total 4883 # Table walker service (enqueue to completion) latency 543system.cpu.itb.walker.walksPending::samples 24497265712 # Table walker pending requests distribution 544system.cpu.itb.walker.walksPending::mean 0.701353 # Table walker pending requests distribution 545system.cpu.itb.walker.walksPending::stdev 0.457724 # Table walker pending requests distribution 546system.cpu.itb.walker.walksPending::0 7316690500 29.87% 29.87% # Table walker pending requests distribution 547system.cpu.itb.walker.walksPending::1 17179912712 70.13% 100.00% # Table walker pending requests distribution 548system.cpu.itb.walker.walksPending::2 662500 0.00% 100.00% # Table walker pending requests distribution 549system.cpu.itb.walker.walksPending::total 24497265712 # Table walker pending requests distribution 550system.cpu.itb.walker.walkPageSizes::4K 2983 89.90% 89.90% # Table walker page sizes translated 551system.cpu.itb.walker.walkPageSizes::1M 335 10.10% 100.00% # Table walker page sizes translated 552system.cpu.itb.walker.walkPageSizes::total 3318 # Table walker page sizes translated |
| 535system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 553system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 536system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst 537system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst | 554system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12694 # Table walker requests started/completed, data/inst 555system.cpu.itb.walker.walkRequestOrigin_Requested::total 12694 # Table walker requests started/completed, data/inst |
| 538system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 556system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 539system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst 540system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst 541system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst 542system.cpu.itb.inst_hits 66060204 # ITB inst hits 543system.cpu.itb.inst_misses 12855 # ITB inst misses | 557system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3318 # Table walker requests started/completed, data/inst 558system.cpu.itb.walker.walkRequestOrigin_Completed::total 3318 # Table walker requests started/completed, data/inst 559system.cpu.itb.walker.walkRequestOrigin::total 16012 # Table walker requests started/completed, data/inst 560system.cpu.itb.inst_hits 65985862 # ITB inst hits 561system.cpu.itb.inst_misses 12694 # ITB inst misses |
| 544system.cpu.itb.read_hits 0 # DTB read hits 545system.cpu.itb.read_misses 0 # DTB read misses 546system.cpu.itb.write_hits 0 # DTB write hits 547system.cpu.itb.write_misses 0 # DTB write misses 548system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 549system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 550system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 551system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 562system.cpu.itb.read_hits 0 # DTB read hits 563system.cpu.itb.read_misses 0 # DTB read misses 564system.cpu.itb.write_hits 0 # DTB write hits 565system.cpu.itb.write_misses 0 # DTB write misses 566system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 567system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 568system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 569system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 552system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB | 570system.cpu.itb.flush_entries 3015 # Number of entries that have been flushed from TLB |
| 553system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 554system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 555system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 571system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 572system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 573system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 556system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions | 574system.cpu.itb.perms_faults 2167 # Number of TLB faults due to permissions restrictions |
| 557system.cpu.itb.read_accesses 0 # DTB read accesses 558system.cpu.itb.write_accesses 0 # DTB write accesses | 575system.cpu.itb.read_accesses 0 # DTB read accesses 576system.cpu.itb.write_accesses 0 # DTB write accesses |
| 559system.cpu.itb.inst_accesses 66073059 # ITB inst accesses 560system.cpu.itb.hits 66060204 # DTB hits 561system.cpu.itb.misses 12855 # DTB misses 562system.cpu.itb.accesses 66073059 # DTB accesses | 577system.cpu.itb.inst_accesses 65998556 # ITB inst accesses 578system.cpu.itb.hits 65985862 # DTB hits 579system.cpu.itb.misses 12694 # DTB misses 580system.cpu.itb.accesses 65998556 # DTB accesses |
| 563system.cpu.numPwrStateTransitions 6076 # Number of power state transitions 564system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state | 581system.cpu.numPwrStateTransitions 6076 # Number of power state transitions 582system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state |
| 565system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state | 583system.cpu.pwrStateClkGateDist::mean 887100825.703094 # Distribution of time spent in the clock gated state 584system.cpu.pwrStateClkGateDist::stdev 17420756349.556362 # Distribution of time spent in the clock gated state |
| 567system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 572system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 573system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 585system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state 586system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state 587system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 588system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 589system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 590system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 591system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 574system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state | 592system.cpu.pwrStateClkGateDist::max_value 499972215488 # Distribution of time spent in the clock gated state |
| 575system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state | 593system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state |
| 576system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states 577system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states 578system.cpu.numCycles 264351157 # number of cpu cycles simulated | 594system.cpu.pwrStateResidencyTicks::ON 134100636014 # Cumulative time (in ticks) in various power states 595system.cpu.pwrStateResidencyTicks::CLK_GATED 2695012308486 # Cumulative time (in ticks) in various power states 596system.cpu.numCycles 268201326 # number of cpu cycles simulated |
| 579system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 580system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 597system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 598system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 581system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss 582system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed 583system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered 584system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken 585system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked 586system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing 587system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb 588system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 589system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps 590system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions 591system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR 592system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched 593system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed 594system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed 595system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) | 599system.cpu.fetch.icacheStallCycles 105037035 # Number of cycles fetch is stalled on an Icache miss 600system.cpu.fetch.Insts 183958233 # Number of instructions fetch has processed 601system.cpu.fetch.Branches 46887151 # Number of branches that fetch encountered 602system.cpu.fetch.predictedBranches 33089572 # Number of branches that fetch has predicted taken 603system.cpu.fetch.Cycles 151917777 # Number of cycles fetch has run and was not squashing or blocked 604system.cpu.fetch.SquashCycles 6065436 # Number of cycles fetch has spent squashing 605system.cpu.fetch.TlbCycles 178887 # Number of cycles fetch has spent waiting for tlb 606system.cpu.fetch.MiscStallCycles 8852 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 607system.cpu.fetch.PendingTrapStallCycles 338530 # Number of stall cycles due to pending traps 608system.cpu.fetch.PendingQuiesceStallCycles 869885 # Number of stall cycles due to pending quiesce instructions 609system.cpu.fetch.IcacheWaitRetryStallCycles 153 # Number of stall cycles due to full MSHR 610system.cpu.fetch.CacheLines 65984793 # Number of cache lines fetched 611system.cpu.fetch.IcacheSquashes 962400 # Number of outstanding Icache misses that were squashed 612system.cpu.fetch.ItlbSquashes 5953 # Number of outstanding ITLB misses that were squashed 613system.cpu.fetch.rateDist::samples 261383837 # Number of instructions fetched each cycle (Total) 614system.cpu.fetch.rateDist::mean 0.858435 # Number of instructions fetched each cycle (Total) 615system.cpu.fetch.rateDist::stdev 1.227931 # Number of instructions fetched each cycle (Total) |
| 598system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 616system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 599system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) | 617system.cpu.fetch.rateDist::0 162469808 62.16% 62.16% # Number of instructions fetched each cycle (Total) 618system.cpu.fetch.rateDist::1 29156945 11.15% 73.31% # Number of instructions fetched each cycle (Total) 619system.cpu.fetch.rateDist::2 14047249 5.37% 78.69% # Number of instructions fetched each cycle (Total) 620system.cpu.fetch.rateDist::3 55709835 21.31% 100.00% # Number of instructions fetched each cycle (Total) |
| 603system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 621system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 622system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 623system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 606system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) 607system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle 608system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle 609system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle 610system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked 611system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running 612system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking 613system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing 614system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch 615system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction 616system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode 617system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode 618system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing 619system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle 620system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking 621system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst 622system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running 623system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking 624system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename 625system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename 626system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full 627system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full 628system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full 629system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full 630system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed 631system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made 632system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups 633system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups 634system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed 635system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing 636system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed 637system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed 638system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer 639system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. 640system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. 641system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. 642system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. 643system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) 644system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ 645system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued 646system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued 647system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling 648system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph 649system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed 650system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle | 624system.cpu.fetch.rateDist::total 261383837 # Number of instructions fetched each cycle (Total) 625system.cpu.fetch.branchRate 0.174821 # Number of branch fetches per cycle 626system.cpu.fetch.rate 0.685896 # Number of inst fetches per cycle 627system.cpu.decode.IdleCycles 78154489 # Number of cycles decode is idle 628system.cpu.decode.BlockedCycles 112430645 # Number of cycles decode is blocked 629system.cpu.decode.RunCycles 64386105 # Number of cycles decode is running 630system.cpu.decode.UnblockCycles 3839531 # Number of cycles decode is unblocking 631system.cpu.decode.SquashCycles 2573067 # Number of cycles decode is squashing 632system.cpu.decode.BranchResolved 3403885 # Number of times decode resolved a branch 633system.cpu.decode.BranchMispred 467719 # Number of times decode detected a branch misprediction 634system.cpu.decode.DecodedInsts 157074107 # Number of instructions handled by decode 635system.cpu.decode.SquashedInsts 3510025 # Number of squashed instructions handled by decode 636system.cpu.rename.SquashCycles 2573067 # Number of cycles rename is squashing 637system.cpu.rename.IdleCycles 83905287 # Number of cycles rename is idle 638system.cpu.rename.BlockCycles 11250556 # Number of cycles rename is blocking 639system.cpu.rename.serializeStallCycles 76371084 # count of cycles rename stalled for serializing inst 640system.cpu.rename.RunCycles 62477293 # Number of cycles rename is running 641system.cpu.rename.UnblockCycles 24806550 # Number of cycles rename is unblocking 642system.cpu.rename.RenamedInsts 146503885 # Number of instructions processed by rename 643system.cpu.rename.SquashedInsts 915767 # Number of squashed instructions processed by rename 644system.cpu.rename.ROBFullEvents 476463 # Number of times rename has blocked due to ROB full 645system.cpu.rename.IQFullEvents 65809 # Number of times rename has blocked due to IQ full 646system.cpu.rename.LQFullEvents 19068 # Number of times rename has blocked due to LQ full 647system.cpu.rename.SQFullEvents 22053632 # Number of times rename has blocked due to SQ full 648system.cpu.rename.RenamedOperands 150297963 # Number of destination operands rename has renamed 649system.cpu.rename.RenameLookups 677315873 # Number of register rename lookups that rename has made 650system.cpu.rename.int_rename_lookups 164027698 # Number of integer rename lookups 651system.cpu.rename.fp_rename_lookups 11061 # Number of floating rename lookups 652system.cpu.rename.CommittedMaps 141834071 # Number of HB maps that are committed 653system.cpu.rename.UndoneMaps 8463886 # Number of HB maps that are undone due to squashing 654system.cpu.rename.serializingInsts 2844043 # count of serializing insts renamed 655system.cpu.rename.tempSerializingInsts 2648878 # count of temporary serializing insts renamed 656system.cpu.rename.skidInsts 13862484 # count of insts added to the skid buffer 657system.cpu.memDep0.insertedLoads 26350148 # Number of loads inserted to the mem dependence unit. 658system.cpu.memDep0.insertedStores 21217553 # Number of stores inserted to the mem dependence unit. 659system.cpu.memDep0.conflictingLoads 1695311 # Number of conflicting loads. 660system.cpu.memDep0.conflictingStores 2061783 # Number of conflicting stores. 661system.cpu.iq.iqInstsAdded 143296271 # Number of instructions added to the IQ (excludes non-spec) 662system.cpu.iq.iqNonSpecInstsAdded 2116715 # Number of non-speculative instructions added to the IQ 663system.cpu.iq.iqInstsIssued 143117357 # Number of instructions issued 664system.cpu.iq.iqSquashedInstsIssued 261040 # Number of squashed instructions issued 665system.cpu.iq.iqSquashedInstsExamined 8140399 # Number of squashed instructions iterated over during squash; mainly for profiling 666system.cpu.iq.iqSquashedOperandsExamined 14276109 # Number of squashed operands that are examined and possibly removed from graph 667system.cpu.iq.iqSquashedNonSpecRemoved 121662 # Number of squashed non-spec instructions that were removed 668system.cpu.iq.issued_per_cycle::samples 261383837 # Number of insts issued each cycle 669system.cpu.iq.issued_per_cycle::mean 0.547537 # Number of insts issued each cycle 670system.cpu.iq.issued_per_cycle::stdev 0.874444 # Number of insts issued each cycle |
| 653system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 671system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 654system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle | 672system.cpu.iq.issued_per_cycle::0 173081384 66.22% 66.22% # Number of insts issued each cycle 673system.cpu.iq.issued_per_cycle::1 45405843 17.37% 83.59% # Number of insts issued each cycle 674system.cpu.iq.issued_per_cycle::2 31801280 12.17% 95.76% # Number of insts issued each cycle 675system.cpu.iq.issued_per_cycle::3 10272399 3.93% 99.69% # Number of insts issued each cycle 676system.cpu.iq.issued_per_cycle::4 822898 0.31% 100.00% # Number of insts issued each cycle |
| 659system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 677system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 678system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 679system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 680system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 681system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 682system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 683system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 666system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle | 684system.cpu.iq.issued_per_cycle::total 261383837 # Number of insts issued each cycle |
| 667system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 685system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 668system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available 669system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available 670system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available 672system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available 676system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available 693system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available 694system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available 696system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available 697system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available 698system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available | 686system.cpu.iq.fu_full::IntAlu 7335509 32.77% 32.77% # attempts to use FU when none available 687system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 688system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 689system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 690system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 691system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 692system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available 693system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available 694system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available 696system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available 697system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available 698system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available 699system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available 700system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available 701system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available 702system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available 703system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available 704system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available 705system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available 706system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available 707system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available 708system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available 709system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available 710system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available 711system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available 712system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available 713system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 714system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 715system.cpu.iq.fu_full::MemRead 5621614 25.12% 57.89% # attempts to use FU when none available 716system.cpu.iq.fu_full::MemWrite 9424915 42.11% 100.00% # attempts to use FU when none available |
| 699system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 700system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 701system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued | 717system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 718system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 719system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued |
| 702system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued 703system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued | 720system.cpu.iq.FU_type_0::IntAlu 95907816 67.01% 67.02% # Type of FU issued 721system.cpu.iq.FU_type_0::IntMult 114378 0.08% 67.09% # Type of FU issued |
| 704system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 706system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 707system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 708system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 709system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 710system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 719system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued | 722system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 727system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 728system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 737system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 738system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 739system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 740system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 741system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 742system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 743system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 744system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued |
| 727system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued | 745system.cpu.iq.FU_type_0::SimdFloatMisc 8550 0.01% 67.10% # Type of FU issued |
| 728system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 730system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued | 746system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 747system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 748system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued |
| 731system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued 732system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued | 749system.cpu.iq.FU_type_0::MemRead 26140422 18.27% 85.37% # Type of FU issued 750system.cpu.iq.FU_type_0::MemWrite 20943854 14.63% 100.00% # Type of FU issued |
| 733system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 734system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 751system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 752system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 735system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued 736system.cpu.iq.rate 0.541351 # Inst issue rate 737system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested 738system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) 739system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads 740system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes 741system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses 742system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads 743system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes 744system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses 745system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses 746system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses 747system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores | 753system.cpu.iq.FU_type_0::total 143117357 # Type of FU issued 754system.cpu.iq.rate 0.533619 # Inst issue rate 755system.cpu.iq.fu_busy_cnt 22382070 # FU busy when requested 756system.cpu.iq.fu_busy_rate 0.156390 # FU busy rate (busy events/executed inst) 757system.cpu.iq.int_inst_queue_reads 570225766 # Number of integer instruction queue reads 758system.cpu.iq.int_inst_queue_writes 153558624 # Number of integer instruction queue writes 759system.cpu.iq.int_inst_queue_wakeup_accesses 140063898 # Number of integer instruction queue wakeup accesses 760system.cpu.iq.fp_inst_queue_reads 35895 # Number of floating instruction queue reads 761system.cpu.iq.fp_inst_queue_writes 13316 # Number of floating instruction queue writes 762system.cpu.iq.fp_inst_queue_wakeup_accesses 11500 # Number of floating instruction queue wakeup accesses 763system.cpu.iq.int_alu_accesses 165473596 # Number of integer alu accesses 764system.cpu.iq.fp_alu_accesses 23494 # Number of floating point alu accesses 765system.cpu.iew.lsq.thread0.forwLoads 325086 # Number of loads that had data forwarded from stores |
| 748system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 766system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 749system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed 750system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed 751system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations 752system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed | 767system.cpu.iew.lsq.thread0.squashedLoads 1430934 # Number of loads squashed 768system.cpu.iew.lsq.thread0.ignoredResponses 704 # Number of memory responses ignored because the instruction is squashed 769system.cpu.iew.lsq.thread0.memOrderViolation 18603 # Number of memory ordering violations 770system.cpu.iew.lsq.thread0.squashedStores 620075 # Number of stores squashed |
| 753system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 754system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 771system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 772system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 755system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled 756system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked | 773system.cpu.iew.lsq.thread0.rescheduledLoads 88534 # Number of loads that were rescheduled 774system.cpu.iew.lsq.thread0.cacheBlocked 6404 # Number of times an access to memory failed due to the cache being blocked |
| 757system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 775system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 758system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing 759system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking 760system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking 761system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ | 776system.cpu.iew.iewSquashCycles 2573067 # Number of cycles IEW is squashing 777system.cpu.iew.iewBlockCycles 1155549 # Number of cycles IEW is blocking 778system.cpu.iew.iewUnblockCycles 418674 # Number of cycles IEW is unblocking 779system.cpu.iew.iewDispatchedInsts 145593643 # Number of instructions dispatched to IQ |
| 762system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 780system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 763system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions 764system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions 765system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions 766system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall 767system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall 768system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations 769system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly 770system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly 771system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute 772system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions 773system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed 774system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute | 781system.cpu.iew.iewDispLoadInsts 26350148 # Number of dispatched load instructions 782system.cpu.iew.iewDispStoreInsts 21217553 # Number of dispatched store instructions 783system.cpu.iew.iewDispNonSpecInsts 1093742 # Number of dispatched non-speculative instructions 784system.cpu.iew.iewIQFullEvents 17678 # Number of times the IQ has become full, causing a stall 785system.cpu.iew.iewLSQFullEvents 382838 # Number of times the LSQ has become full, causing a stall 786system.cpu.iew.memOrderViolationEvents 18603 # Number of memory order violations 787system.cpu.iew.predictedTakenIncorrect 276771 # Number of branches that were predicted taken incorrectly 788system.cpu.iew.predictedNotTakenIncorrect 470806 # Number of branches that were predicted not taken incorrectly 789system.cpu.iew.branchMispredicts 747577 # Number of branch mispredicts detected at execute 790system.cpu.iew.iewExecutedInsts 142219738 # Number of executed instructions 791system.cpu.iew.iewExecLoadInsts 25746846 # Number of load instructions executed 792system.cpu.iew.iewExecSquashedInsts 826473 # Number of squashed instructions skipped in execute |
| 775system.cpu.iew.exec_swp 0 # number of swp insts executed | 793system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 776system.cpu.iew.exec_nop 180805 # number of nop insts executed 777system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed 778system.cpu.iew.exec_branches 26509940 # Number of branches executed 779system.cpu.iew.exec_stores 20830689 # Number of stores executed 780system.cpu.iew.exec_rate 0.537948 # Inst execution rate 781system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit 782system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back 783system.cpu.iew.wb_producers 63261975 # num instructions producing a value 784system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value 785system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle 786system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back 787system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit 788system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards 789system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted 790system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle | 794system.cpu.iew.exec_nop 180657 # number of nop insts executed 795system.cpu.iew.exec_refs 46578356 # number of memory reference insts executed 796system.cpu.iew.exec_branches 26518178 # Number of branches executed 797system.cpu.iew.exec_stores 20831510 # Number of stores executed 798system.cpu.iew.exec_rate 0.530272 # Inst execution rate 799system.cpu.iew.wb_sent 141851208 # cumulative count of insts sent to commit 800system.cpu.iew.wb_count 140075398 # cumulative count of insts written-back 801system.cpu.iew.wb_producers 63278837 # num instructions producing a value 802system.cpu.iew.wb_consumers 95827539 # num instructions consuming a value 803system.cpu.iew.wb_rate 0.522277 # insts written-back per cycle 804system.cpu.iew.wb_fanout 0.660341 # average fanout of values written-back 805system.cpu.commit.commitSquashedInsts 7356149 # The number of squashed insts skipped by commit 806system.cpu.commit.commitNonSpecStalls 1995053 # The number of times commit has been forced to stall to communicate backwards 807system.cpu.commit.branchMispredicts 714141 # The number of times a branch was mispredicted 808system.cpu.commit.committed_per_cycle::samples 258490005 # Number of insts commited each cycle 809system.cpu.commit.committed_per_cycle::mean 0.531655 # Number of insts commited each cycle 810system.cpu.commit.committed_per_cycle::stdev 1.132637 # Number of insts commited each cycle |
| 793system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 811system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 794system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle | 812system.cpu.commit.committed_per_cycle::0 184915208 71.54% 71.54% # Number of insts commited each cycle 813system.cpu.commit.committed_per_cycle::1 43409459 16.79% 88.33% # Number of insts commited each cycle 814system.cpu.commit.committed_per_cycle::2 15465173 5.98% 94.31% # Number of insts commited each cycle 815system.cpu.commit.committed_per_cycle::3 4364887 1.69% 96.00% # Number of insts commited each cycle 816system.cpu.commit.committed_per_cycle::4 6512039 2.52% 98.52% # Number of insts commited each cycle 817system.cpu.commit.committed_per_cycle::5 1543037 0.60% 99.12% # Number of insts commited each cycle 818system.cpu.commit.committed_per_cycle::6 797927 0.31% 99.43% # Number of insts commited each cycle 819system.cpu.commit.committed_per_cycle::7 416081 0.16% 99.59% # Number of insts commited each cycle 820system.cpu.commit.committed_per_cycle::8 1066194 0.41% 100.00% # Number of insts commited each cycle |
| 803system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 821system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 822system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 823system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 806system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle 807system.cpu.commit.committedInsts 113310545 # Number of instructions committed 808system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed | 824system.cpu.commit.committed_per_cycle::total 258490005 # Number of insts commited each cycle 825system.cpu.commit.committedInsts 113327954 # Number of instructions committed 826system.cpu.commit.committedOps 137427488 # Number of ops (including micro ops) committed |
| 809system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 827system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 810system.cpu.commit.refs 45513412 # Number of memory references committed 811system.cpu.commit.loads 24916720 # Number of loads committed 812system.cpu.commit.membars 814165 # Number of memory barriers committed 813system.cpu.commit.branches 26044798 # Number of branches committed | 828system.cpu.commit.refs 45516692 # Number of memory references committed 829system.cpu.commit.loads 24919214 # Number of loads committed 830system.cpu.commit.membars 814556 # Number of memory barriers committed 831system.cpu.commit.branches 26054279 # Number of branches committed |
| 814system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. | 832system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. |
| 815system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. 816system.cpu.commit.function_calls 4891928 # Number of function calls committed. | 833system.cpu.commit.int_insts 120246700 # Number of committed integer instructions. 834system.cpu.commit.function_calls 4895002 # Number of function calls committed. |
| 817system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 835system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 818system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction 819system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction | 836system.cpu.commit.op_class_0::IntAlu 91789332 66.79% 66.79% # Class of committed instruction 837system.cpu.commit.op_class_0::IntMult 112915 0.08% 66.87% # Class of committed instruction |
| 820system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 835system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction | 838system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 842system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 843system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 844system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 853system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 854system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 855system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 856system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 857system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 858system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 859system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 860system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction |
| 843system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction | 861system.cpu.commit.op_class_0::SimdFloatMisc 8549 0.01% 66.88% # Class of committed instruction |
| 844system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 846system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction | 862system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 863system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 864system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction |
| 847system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction 848system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction | 865system.cpu.commit.op_class_0::MemRead 24919214 18.13% 85.01% # Class of committed instruction 866system.cpu.commit.op_class_0::MemWrite 20597478 14.99% 100.00% # Class of committed instruction |
| 849system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 850system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 867system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 868system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 851system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction 852system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached 853system.cpu.rob.rob_reads 376774257 # The number of ROB reads 854system.cpu.rob.rob_writes 292425270 # The number of ROB writes 855system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself 856system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling 857system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 858system.cpu.committedInsts 113155640 # Number of Instructions Simulated 859system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated 860system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction 861system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads 862system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle 863system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads 864system.cpu.int_regfile_reads 155596461 # number of integer regfile reads 865system.cpu.int_regfile_writes 88540193 # number of integer regfile writes 866system.cpu.fp_regfile_reads 9674 # number of floating regfile reads | 869system.cpu.commit.op_class_0::total 137427488 # Class of committed instruction 870system.cpu.commit.bw_lim_events 1066194 # number cycles where commit BW limit reached 871system.cpu.rob.rob_reads 379949809 # The number of ROB reads 872system.cpu.rob.rob_writes 292448043 # The number of ROB writes 873system.cpu.timesIdled 895006 # Number of times that the entire CPU went into an idle state and unscheduled itself 874system.cpu.idleCycles 6817489 # Total number of cycles that the CPU has spent unscheduled due to idling 875system.cpu.quiesceCycles 5390024564 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 876system.cpu.committedInsts 113173049 # Number of Instructions Simulated 877system.cpu.committedOps 137272583 # Number of Ops (including micro ops) Simulated 878system.cpu.cpi 2.369834 # CPI: Cycles Per Instruction 879system.cpu.cpi_total 2.369834 # CPI: Total CPI of All Threads 880system.cpu.ipc 0.421971 # IPC: Instructions Per Cycle 881system.cpu.ipc_total 0.421971 # IPC: Total IPC of All Threads 882system.cpu.int_regfile_reads 155600043 # number of integer regfile reads 883system.cpu.int_regfile_writes 88544133 # number of integer regfile writes 884system.cpu.fp_regfile_reads 9688 # number of floating regfile reads |
| 867system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 885system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 868system.cpu.cc_regfile_reads 502394909 # number of cc regfile reads 869system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes 870system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads 871system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes 872system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 873system.cpu.dcache.tags.replacements 839084 # number of replacements 874system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use 875system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. 876system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. 877system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. 878system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. 879system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor 880system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy 881system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy | 886system.cpu.cc_regfile_reads 502437138 # number of cc regfile reads 887system.cpu.cc_regfile_writes 53153343 # number of cc regfile writes 888system.cpu.misc_regfile_reads 452546223 # number of misc regfile reads 889system.cpu.misc_regfile_writes 1521066 # number of misc regfile writes 890system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 891system.cpu.dcache.tags.replacements 835143 # number of replacements 892system.cpu.dcache.tags.tagsinuse 511.950856 # Cycle average of tags in use 893system.cpu.dcache.tags.total_refs 40081033 # Total number of references to valid blocks. 894system.cpu.dcache.tags.sampled_refs 835655 # Sample count of references to valid blocks. 895system.cpu.dcache.tags.avg_refs 47.963613 # Average number of references to valid blocks. 896system.cpu.dcache.tags.warmup_cycle 291735500 # Cycle when the warmup percentage was hit. 897system.cpu.dcache.tags.occ_blocks::cpu.data 511.950856 # Average occupied blocks per requestor 898system.cpu.dcache.tags.occ_percent::cpu.data 0.999904 # Average percentage of cache occupancy 899system.cpu.dcache.tags.occ_percent::total 0.999904 # Average percentage of cache occupancy |
| 882system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 900system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 883system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id | 901system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 902system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id 903system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id |
| 886system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 904system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 887system.cpu.dcache.tags.tag_accesses 179200286 # Number of tag accesses 888system.cpu.dcache.tags.data_accesses 179200286 # Number of data accesses 889system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 890system.cpu.dcache.ReadReq_hits::cpu.data 23273566 # number of ReadReq hits 891system.cpu.dcache.ReadReq_hits::total 23273566 # number of ReadReq hits 892system.cpu.dcache.WriteReq_hits::cpu.data 15547100 # number of WriteReq hits 893system.cpu.dcache.WriteReq_hits::total 15547100 # number of WriteReq hits 894system.cpu.dcache.SoftPFReq_hits::cpu.data 345314 # number of SoftPFReq hits 895system.cpu.dcache.SoftPFReq_hits::total 345314 # number of SoftPFReq hits 896system.cpu.dcache.LoadLockedReq_hits::cpu.data 441102 # number of LoadLockedReq hits 897system.cpu.dcache.LoadLockedReq_hits::total 441102 # number of LoadLockedReq hits 898system.cpu.dcache.StoreCondReq_hits::cpu.data 459566 # number of StoreCondReq hits 899system.cpu.dcache.StoreCondReq_hits::total 459566 # number of StoreCondReq hits 900system.cpu.dcache.demand_hits::cpu.data 38820666 # number of demand (read+write) hits 901system.cpu.dcache.demand_hits::total 38820666 # number of demand (read+write) hits 902system.cpu.dcache.overall_hits::cpu.data 39165980 # number of overall hits 903system.cpu.dcache.overall_hits::total 39165980 # number of overall hits 904system.cpu.dcache.ReadReq_misses::cpu.data 709196 # number of ReadReq misses 905system.cpu.dcache.ReadReq_misses::total 709196 # number of ReadReq misses 906system.cpu.dcache.WriteReq_misses::cpu.data 3610101 # number of WriteReq misses 907system.cpu.dcache.WriteReq_misses::total 3610101 # number of WriteReq misses 908system.cpu.dcache.SoftPFReq_misses::cpu.data 177382 # number of SoftPFReq misses 909system.cpu.dcache.SoftPFReq_misses::total 177382 # number of SoftPFReq misses 910system.cpu.dcache.LoadLockedReq_misses::cpu.data 26835 # number of LoadLockedReq misses 911system.cpu.dcache.LoadLockedReq_misses::total 26835 # number of LoadLockedReq misses 912system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 913system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 914system.cpu.dcache.demand_misses::cpu.data 4319297 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 4319297 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 4496679 # number of overall misses 917system.cpu.dcache.overall_misses::total 4496679 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 10317292500 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 10317292500 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 150336233192 # number of WriteReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369753500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 369753500 # number of LoadLockedReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 213000 # number of StoreCondReq miss cycles 925system.cpu.dcache.StoreCondReq_miss_latency::total 213000 # number of StoreCondReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 160653525692 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 160653525692 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 160653525692 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 160653525692 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 23982762 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 23982762 # number of ReadReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::cpu.data 19157201 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 19157201 # number of WriteReq accesses(hits+misses) 934system.cpu.dcache.SoftPFReq_accesses::cpu.data 522696 # number of SoftPFReq accesses(hits+misses) 935system.cpu.dcache.SoftPFReq_accesses::total 522696 # number of SoftPFReq accesses(hits+misses) 936system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467937 # number of LoadLockedReq accesses(hits+misses) 937system.cpu.dcache.LoadLockedReq_accesses::total 467937 # number of LoadLockedReq accesses(hits+misses) 938system.cpu.dcache.StoreCondReq_accesses::cpu.data 459571 # number of StoreCondReq accesses(hits+misses) 939system.cpu.dcache.StoreCondReq_accesses::total 459571 # number of StoreCondReq accesses(hits+misses) 940system.cpu.dcache.demand_accesses::cpu.data 43139963 # number of demand (read+write) accesses 941system.cpu.dcache.demand_accesses::total 43139963 # number of demand (read+write) accesses 942system.cpu.dcache.overall_accesses::cpu.data 43662659 # number of overall (read+write) accesses 943system.cpu.dcache.overall_accesses::total 43662659 # number of overall (read+write) accesses 944system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses 945system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses 946system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188446 # miss rate for WriteReq accesses 947system.cpu.dcache.WriteReq_miss_rate::total 0.188446 # miss rate for WriteReq accesses 948system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339360 # miss rate for SoftPFReq accesses 949system.cpu.dcache.SoftPFReq_miss_rate::total 0.339360 # miss rate for SoftPFReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057347 # miss rate for LoadLockedReq accesses 951system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057347 # miss rate for LoadLockedReq accesses 952system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 953system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 954system.cpu.dcache.demand_miss_rate::cpu.data 0.100123 # miss rate for demand accesses 955system.cpu.dcache.demand_miss_rate::total 0.100123 # miss rate for demand accesses 956system.cpu.dcache.overall_miss_rate::cpu.data 0.102987 # miss rate for overall accesses 957system.cpu.dcache.overall_miss_rate::total 0.102987 # miss rate for overall accesses 958system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815 # average ReadReq miss latency 959system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815 # average ReadReq miss latency 960system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838 # average WriteReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838 # average WriteReq miss latency 962system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716 # average LoadLockedReq miss latency 963system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716 # average LoadLockedReq miss latency 964system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42600 # average StoreCondReq miss latency 965system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42600 # average StoreCondReq miss latency 966system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827 # average overall miss latency 967system.cpu.dcache.demand_avg_miss_latency::total 37194.368827 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124 # average overall miss latency 969system.cpu.dcache.overall_avg_miss_latency::total 35727.150124 # average overall miss latency 970system.cpu.dcache.blocked_cycles::no_mshrs 590933 # number of cycles access was blocked | 905system.cpu.dcache.tags.tag_accesses 179197279 # Number of tag accesses 906system.cpu.dcache.tags.data_accesses 179197279 # Number of data accesses 907system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 908system.cpu.dcache.ReadReq_hits::cpu.data 23277440 # number of ReadReq hits 909system.cpu.dcache.ReadReq_hits::total 23277440 # number of ReadReq hits 910system.cpu.dcache.WriteReq_hits::cpu.data 15552456 # number of WriteReq hits 911system.cpu.dcache.WriteReq_hits::total 15552456 # number of WriteReq hits 912system.cpu.dcache.SoftPFReq_hits::cpu.data 346215 # number of SoftPFReq hits 913system.cpu.dcache.SoftPFReq_hits::total 346215 # number of SoftPFReq hits 914system.cpu.dcache.LoadLockedReq_hits::cpu.data 441873 # number of LoadLockedReq hits 915system.cpu.dcache.LoadLockedReq_hits::total 441873 # number of LoadLockedReq hits 916system.cpu.dcache.StoreCondReq_hits::cpu.data 460172 # number of StoreCondReq hits 917system.cpu.dcache.StoreCondReq_hits::total 460172 # number of StoreCondReq hits 918system.cpu.dcache.demand_hits::cpu.data 38829896 # number of demand (read+write) hits 919system.cpu.dcache.demand_hits::total 38829896 # number of demand (read+write) hits 920system.cpu.dcache.overall_hits::cpu.data 39176111 # number of overall hits 921system.cpu.dcache.overall_hits::total 39176111 # number of overall hits 922system.cpu.dcache.ReadReq_misses::cpu.data 703989 # number of ReadReq misses 923system.cpu.dcache.ReadReq_misses::total 703989 # number of ReadReq misses 924system.cpu.dcache.WriteReq_misses::cpu.data 3604729 # number of WriteReq misses 925system.cpu.dcache.WriteReq_misses::total 3604729 # number of WriteReq misses 926system.cpu.dcache.SoftPFReq_misses::cpu.data 176925 # number of SoftPFReq misses 927system.cpu.dcache.SoftPFReq_misses::total 176925 # number of SoftPFReq misses 928system.cpu.dcache.LoadLockedReq_misses::cpu.data 26598 # number of LoadLockedReq misses 929system.cpu.dcache.LoadLockedReq_misses::total 26598 # number of LoadLockedReq misses 930system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 931system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 932system.cpu.dcache.demand_misses::cpu.data 4308718 # number of demand (read+write) misses 933system.cpu.dcache.demand_misses::total 4308718 # number of demand (read+write) misses 934system.cpu.dcache.overall_misses::cpu.data 4485643 # number of overall misses 935system.cpu.dcache.overall_misses::total 4485643 # number of overall misses 936system.cpu.dcache.ReadReq_miss_latency::cpu.data 11027261000 # number of ReadReq miss cycles 937system.cpu.dcache.ReadReq_miss_latency::total 11027261000 # number of ReadReq miss cycles 938system.cpu.dcache.WriteReq_miss_latency::cpu.data 167170360202 # number of WriteReq miss cycles 939system.cpu.dcache.WriteReq_miss_latency::total 167170360202 # number of WriteReq miss cycles 940system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 370603000 # number of LoadLockedReq miss cycles 941system.cpu.dcache.LoadLockedReq_miss_latency::total 370603000 # number of LoadLockedReq miss cycles 942system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 196000 # number of StoreCondReq miss cycles 943system.cpu.dcache.StoreCondReq_miss_latency::total 196000 # number of StoreCondReq miss cycles 944system.cpu.dcache.demand_miss_latency::cpu.data 178197621202 # number of demand (read+write) miss cycles 945system.cpu.dcache.demand_miss_latency::total 178197621202 # number of demand (read+write) miss cycles 946system.cpu.dcache.overall_miss_latency::cpu.data 178197621202 # number of overall miss cycles 947system.cpu.dcache.overall_miss_latency::total 178197621202 # number of overall miss cycles 948system.cpu.dcache.ReadReq_accesses::cpu.data 23981429 # number of ReadReq accesses(hits+misses) 949system.cpu.dcache.ReadReq_accesses::total 23981429 # number of ReadReq accesses(hits+misses) 950system.cpu.dcache.WriteReq_accesses::cpu.data 19157185 # number of WriteReq accesses(hits+misses) 951system.cpu.dcache.WriteReq_accesses::total 19157185 # number of WriteReq accesses(hits+misses) 952system.cpu.dcache.SoftPFReq_accesses::cpu.data 523140 # number of SoftPFReq accesses(hits+misses) 953system.cpu.dcache.SoftPFReq_accesses::total 523140 # number of SoftPFReq accesses(hits+misses) 954system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468471 # number of LoadLockedReq accesses(hits+misses) 955system.cpu.dcache.LoadLockedReq_accesses::total 468471 # number of LoadLockedReq accesses(hits+misses) 956system.cpu.dcache.StoreCondReq_accesses::cpu.data 460176 # number of StoreCondReq accesses(hits+misses) 957system.cpu.dcache.StoreCondReq_accesses::total 460176 # number of StoreCondReq accesses(hits+misses) 958system.cpu.dcache.demand_accesses::cpu.data 43138614 # number of demand (read+write) accesses 959system.cpu.dcache.demand_accesses::total 43138614 # number of demand (read+write) accesses 960system.cpu.dcache.overall_accesses::cpu.data 43661754 # number of overall (read+write) accesses 961system.cpu.dcache.overall_accesses::total 43661754 # number of overall (read+write) accesses 962system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029356 # miss rate for ReadReq accesses 963system.cpu.dcache.ReadReq_miss_rate::total 0.029356 # miss rate for ReadReq accesses 964system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188166 # miss rate for WriteReq accesses 965system.cpu.dcache.WriteReq_miss_rate::total 0.188166 # miss rate for WriteReq accesses 966system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338198 # miss rate for SoftPFReq accesses 967system.cpu.dcache.SoftPFReq_miss_rate::total 0.338198 # miss rate for SoftPFReq accesses 968system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056776 # miss rate for LoadLockedReq accesses 969system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056776 # miss rate for LoadLockedReq accesses 970system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 971system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 972system.cpu.dcache.demand_miss_rate::cpu.data 0.099881 # miss rate for demand accesses 973system.cpu.dcache.demand_miss_rate::total 0.099881 # miss rate for demand accesses 974system.cpu.dcache.overall_miss_rate::cpu.data 0.102736 # miss rate for overall accesses 975system.cpu.dcache.overall_miss_rate::total 0.102736 # miss rate for overall accesses 976system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15663.967761 # average ReadReq miss latency 977system.cpu.dcache.ReadReq_avg_miss_latency::total 15663.967761 # average ReadReq miss latency 978system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46375.292068 # average WriteReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::total 46375.292068 # average WriteReq miss latency 980system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13933.491240 # average LoadLockedReq miss latency 981system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13933.491240 # average LoadLockedReq miss latency 982system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 49000 # average StoreCondReq miss latency 983system.cpu.dcache.StoreCondReq_avg_miss_latency::total 49000 # average StoreCondReq miss latency 984system.cpu.dcache.demand_avg_miss_latency::cpu.data 41357.457416 # average overall miss latency 985system.cpu.dcache.demand_avg_miss_latency::total 41357.457416 # average overall miss latency 986system.cpu.dcache.overall_avg_miss_latency::cpu.data 39726.215662 # average overall miss latency 987system.cpu.dcache.overall_avg_miss_latency::total 39726.215662 # average overall miss latency 988system.cpu.dcache.blocked_cycles::no_mshrs 633494 # number of cycles access was blocked |
| 971system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 989system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 972system.cpu.dcache.blocked::no_mshrs 7520 # number of cycles access was blocked | 990system.cpu.dcache.blocked::no_mshrs 7037 # number of cycles access was blocked |
| 973system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 991system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 974system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.581516 # average number of cycles each access was blocked | 992system.cpu.dcache.avg_blocked_cycles::no_mshrs 90.023305 # average number of cycles each access was blocked |
| 975system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 993system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 976system.cpu.dcache.writebacks::writebacks 696178 # number of writebacks 977system.cpu.dcache.writebacks::total 696178 # number of writebacks 978system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295013 # number of ReadReq MSHR hits 979system.cpu.dcache.ReadReq_mshr_hits::total 295013 # number of ReadReq MSHR hits 980system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309632 # number of WriteReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::total 3309632 # number of WriteReq MSHR hits 982system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18459 # number of LoadLockedReq MSHR hits 983system.cpu.dcache.LoadLockedReq_mshr_hits::total 18459 # number of LoadLockedReq MSHR hits 984system.cpu.dcache.demand_mshr_hits::cpu.data 3604645 # number of demand (read+write) MSHR hits 985system.cpu.dcache.demand_mshr_hits::total 3604645 # number of demand (read+write) MSHR hits 986system.cpu.dcache.overall_mshr_hits::cpu.data 3604645 # number of overall MSHR hits 987system.cpu.dcache.overall_mshr_hits::total 3604645 # number of overall MSHR hits 988system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414183 # number of ReadReq MSHR misses 989system.cpu.dcache.ReadReq_mshr_misses::total 414183 # number of ReadReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300469 # number of WriteReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::total 300469 # number of WriteReq MSHR misses 992system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119358 # number of SoftPFReq MSHR misses 993system.cpu.dcache.SoftPFReq_mshr_misses::total 119358 # number of SoftPFReq MSHR misses 994system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8376 # number of LoadLockedReq MSHR misses 995system.cpu.dcache.LoadLockedReq_mshr_misses::total 8376 # number of LoadLockedReq MSHR misses 996system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 997system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 998system.cpu.dcache.demand_mshr_misses::cpu.data 714652 # number of demand (read+write) MSHR misses 999system.cpu.dcache.demand_mshr_misses::total 714652 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.overall_mshr_misses::cpu.data 834010 # number of overall MSHR misses 1001system.cpu.dcache.overall_mshr_misses::total 834010 # number of overall MSHR misses | 994system.cpu.dcache.writebacks::writebacks 694028 # number of writebacks 995system.cpu.dcache.writebacks::total 694028 # number of writebacks 996system.cpu.dcache.ReadReq_mshr_hits::cpu.data 292192 # number of ReadReq MSHR hits 997system.cpu.dcache.ReadReq_mshr_hits::total 292192 # number of ReadReq MSHR hits 998system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3305480 # number of WriteReq MSHR hits 999system.cpu.dcache.WriteReq_mshr_hits::total 3305480 # number of WriteReq MSHR hits 1000system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18304 # number of LoadLockedReq MSHR hits 1001system.cpu.dcache.LoadLockedReq_mshr_hits::total 18304 # number of LoadLockedReq MSHR hits 1002system.cpu.dcache.demand_mshr_hits::cpu.data 3597672 # number of demand (read+write) MSHR hits 1003system.cpu.dcache.demand_mshr_hits::total 3597672 # number of demand (read+write) MSHR hits 1004system.cpu.dcache.overall_mshr_hits::cpu.data 3597672 # number of overall MSHR hits 1005system.cpu.dcache.overall_mshr_hits::total 3597672 # number of overall MSHR hits 1006system.cpu.dcache.ReadReq_mshr_misses::cpu.data 411797 # number of ReadReq MSHR misses 1007system.cpu.dcache.ReadReq_mshr_misses::total 411797 # number of ReadReq MSHR misses 1008system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299249 # number of WriteReq MSHR misses 1009system.cpu.dcache.WriteReq_mshr_misses::total 299249 # number of WriteReq MSHR misses 1010system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119132 # number of SoftPFReq MSHR misses 1011system.cpu.dcache.SoftPFReq_mshr_misses::total 119132 # number of SoftPFReq MSHR misses 1012system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8294 # number of LoadLockedReq MSHR misses 1013system.cpu.dcache.LoadLockedReq_mshr_misses::total 8294 # number of LoadLockedReq MSHR misses 1014system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 1015system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 1016system.cpu.dcache.demand_mshr_misses::cpu.data 711046 # number of demand (read+write) MSHR misses 1017system.cpu.dcache.demand_mshr_misses::total 711046 # number of demand (read+write) MSHR misses 1018system.cpu.dcache.overall_mshr_misses::cpu.data 830178 # number of overall MSHR misses 1019system.cpu.dcache.overall_mshr_misses::total 830178 # number of overall MSHR misses |
| 1002system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1003system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable 1004system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1005system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1006system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1007system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses | 1020system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1021system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable 1022system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1023system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1024system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1025system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses |
| 1008system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890415000 # number of ReadReq MSHR miss cycles 1009system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890415000 # number of ReadReq MSHR miss cycles 1010system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13426039479 # number of WriteReq MSHR miss cycles 1011system.cpu.dcache.WriteReq_mshr_miss_latency::total 13426039479 # number of WriteReq MSHR miss cycles 1012system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1622684000 # number of SoftPFReq MSHR miss cycles 1013system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1622684000 # number of SoftPFReq MSHR miss cycles 1014system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 130358500 # number of LoadLockedReq MSHR miss cycles 1015system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles 1016system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles 1017system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles 1021system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles 1022system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles 1023system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles 1024system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles 1025system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles 1026system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses 1027system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses 1028system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses 1029system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses 1030system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses 1031system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses 1032system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses 1033system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses 1034system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1035system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1036system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses 1037system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses 1038system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses 1039system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses 1040system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency 1041system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency 1042system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency 1043system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # average WriteReq mshr miss latency 1044system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454 # average SoftPFReq mshr miss latency 1045system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454 # average SoftPFReq mshr miss latency 1046system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721 # average LoadLockedReq mshr miss latency 1047system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721 # average LoadLockedReq mshr miss latency 1048system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41600 # average StoreCondReq mshr miss latency 1049system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41600 # average StoreCondReq mshr miss latency 1050system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709 # average overall mshr miss latency 1051system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709 # average overall mshr miss latency 1052system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632 # average overall mshr miss latency 1053system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632 # average overall mshr miss latency 1054system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182 # average ReadReq mshr uncacheable latency 1055system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182 # average ReadReq mshr uncacheable latency 1056system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098 # average overall mshr uncacheable latency 1057system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098 # average overall mshr uncacheable latency 1058system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1059system.cpu.icache.tags.replacements 1887810 # number of replacements 1060system.cpu.icache.tags.tagsinuse 511.341026 # Cycle average of tags in use 1061system.cpu.icache.tags.total_refs 64075895 # Total number of references to valid blocks. 1062system.cpu.icache.tags.sampled_refs 1888322 # Sample count of references to valid blocks. 1063system.cpu.icache.tags.avg_refs 33.932716 # Average number of references to valid blocks. 1064system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit. 1065system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor 1066system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy 1067system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy | 1026system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6168747500 # number of ReadReq MSHR miss cycles 1027system.cpu.dcache.ReadReq_mshr_miss_latency::total 6168747500 # number of ReadReq MSHR miss cycles 1028system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14918046982 # number of WriteReq MSHR miss cycles 1029system.cpu.dcache.WriteReq_mshr_miss_latency::total 14918046982 # number of WriteReq MSHR miss cycles 1030system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1646074000 # number of SoftPFReq MSHR miss cycles 1031system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1646074000 # number of SoftPFReq MSHR miss cycles 1032system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126955500 # number of LoadLockedReq MSHR miss cycles 1033system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126955500 # number of LoadLockedReq MSHR miss cycles 1034system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 192000 # number of StoreCondReq MSHR miss cycles 1035system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 192000 # number of StoreCondReq MSHR miss cycles 1036system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086794482 # number of demand (read+write) MSHR miss cycles 1037system.cpu.dcache.demand_mshr_miss_latency::total 21086794482 # number of demand (read+write) MSHR miss cycles 1038system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22732868482 # number of overall MSHR miss cycles 1039system.cpu.dcache.overall_mshr_miss_latency::total 22732868482 # number of overall MSHR miss cycles 1040system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6281936500 # number of ReadReq MSHR uncacheable cycles 1041system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6281936500 # number of ReadReq MSHR uncacheable cycles 1042system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6281936500 # number of overall MSHR uncacheable cycles 1043system.cpu.dcache.overall_mshr_uncacheable_latency::total 6281936500 # number of overall MSHR uncacheable cycles 1044system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017171 # mshr miss rate for ReadReq accesses 1045system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017171 # mshr miss rate for ReadReq accesses 1046system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015621 # mshr miss rate for WriteReq accesses 1047system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015621 # mshr miss rate for WriteReq accesses 1048system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227725 # mshr miss rate for SoftPFReq accesses 1049system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227725 # mshr miss rate for SoftPFReq accesses 1050system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017704 # mshr miss rate for LoadLockedReq accesses 1051system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017704 # mshr miss rate for LoadLockedReq accesses 1052system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1053system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 1054system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016483 # mshr miss rate for demand accesses 1055system.cpu.dcache.demand_mshr_miss_rate::total 0.016483 # mshr miss rate for demand accesses 1056system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019014 # mshr miss rate for overall accesses 1057system.cpu.dcache.overall_mshr_miss_rate::total 0.019014 # mshr miss rate for overall accesses 1058system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14980.069063 # average ReadReq mshr miss latency 1059system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14980.069063 # average ReadReq mshr miss latency 1060system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49851.618492 # average WriteReq mshr miss latency 1061system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49851.618492 # average WriteReq mshr miss latency 1062system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13817.227949 # average SoftPFReq mshr miss latency 1063system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13817.227949 # average SoftPFReq mshr miss latency 1064system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15306.908609 # average LoadLockedReq mshr miss latency 1065system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15306.908609 # average LoadLockedReq mshr miss latency 1066system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 48000 # average StoreCondReq mshr miss latency 1067system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 48000 # average StoreCondReq mshr miss latency 1068system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29656.020120 # average overall mshr miss latency 1069system.cpu.dcache.demand_avg_mshr_miss_latency::total 29656.020120 # average overall mshr miss latency 1070system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27383.125645 # average overall mshr miss latency 1071system.cpu.dcache.overall_avg_mshr_miss_latency::total 27383.125645 # average overall mshr miss latency 1072system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201816.317024 # average ReadReq mshr uncacheable latency 1073system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201816.317024 # average ReadReq mshr uncacheable latency 1074system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106997.606922 # average overall mshr uncacheable latency 1075system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106997.606922 # average overall mshr uncacheable latency 1076system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1077system.cpu.icache.tags.replacements 1888653 # number of replacements 1078system.cpu.icache.tags.tagsinuse 511.315245 # Cycle average of tags in use 1079system.cpu.icache.tags.total_refs 64000443 # Total number of references to valid blocks. 1080system.cpu.icache.tags.sampled_refs 1889165 # Sample count of references to valid blocks. 1081system.cpu.icache.tags.avg_refs 33.877635 # Average number of references to valid blocks. 1082system.cpu.icache.tags.warmup_cycle 14109307500 # Cycle when the warmup percentage was hit. 1083system.cpu.icache.tags.occ_blocks::cpu.inst 511.315245 # Average occupied blocks per requestor 1084system.cpu.icache.tags.occ_percent::cpu.inst 0.998663 # Average percentage of cache occupancy 1085system.cpu.icache.tags.occ_percent::total 0.998663 # Average percentage of cache occupancy |
| 1068system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1086system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1069system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1070system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 1071system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id 1072system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id | 1087system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 1088system.cpu.icache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 1089system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id 1090system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id |
| 1073system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1091system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1074system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses 1075system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses 1076system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1077system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits 1078system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits 1079system.cpu.icache.demand_hits::cpu.inst 64075895 # number of demand (read+write) hits 1080system.cpu.icache.demand_hits::total 64075895 # number of demand (read+write) hits 1081system.cpu.icache.overall_hits::cpu.inst 64075895 # number of overall hits 1082system.cpu.icache.overall_hits::total 64075895 # number of overall hits 1083system.cpu.icache.ReadReq_misses::cpu.inst 1980206 # number of ReadReq misses 1084system.cpu.icache.ReadReq_misses::total 1980206 # number of ReadReq misses 1085system.cpu.icache.demand_misses::cpu.inst 1980206 # number of demand (read+write) misses 1086system.cpu.icache.demand_misses::total 1980206 # number of demand (read+write) misses 1087system.cpu.icache.overall_misses::cpu.inst 1980206 # number of overall misses 1088system.cpu.icache.overall_misses::total 1980206 # number of overall misses 1089system.cpu.icache.ReadReq_miss_latency::cpu.inst 26984355494 # number of ReadReq miss cycles 1090system.cpu.icache.ReadReq_miss_latency::total 26984355494 # number of ReadReq miss cycles 1091system.cpu.icache.demand_miss_latency::cpu.inst 26984355494 # number of demand (read+write) miss cycles 1092system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles 1093system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles 1094system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles 1095system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) 1096system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) 1097system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses 1098system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses 1099system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses 1100system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses 1101system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses 1102system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses 1103system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses 1104system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses 1105system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses 1106system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses 1107system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency 1108system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency 1109system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency 1110system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency 1111system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency 1112system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency 1113system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked | 1092system.cpu.icache.tags.tag_accesses 67870984 # Number of tag accesses 1093system.cpu.icache.tags.data_accesses 67870984 # Number of data accesses 1094system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1095system.cpu.icache.ReadReq_hits::cpu.inst 64000443 # number of ReadReq hits 1096system.cpu.icache.ReadReq_hits::total 64000443 # number of ReadReq hits 1097system.cpu.icache.demand_hits::cpu.inst 64000443 # number of demand (read+write) hits 1098system.cpu.icache.demand_hits::total 64000443 # number of demand (read+write) hits 1099system.cpu.icache.overall_hits::cpu.inst 64000443 # number of overall hits 1100system.cpu.icache.overall_hits::total 64000443 # number of overall hits 1101system.cpu.icache.ReadReq_misses::cpu.inst 1981341 # number of ReadReq misses 1102system.cpu.icache.ReadReq_misses::total 1981341 # number of ReadReq misses 1103system.cpu.icache.demand_misses::cpu.inst 1981341 # number of demand (read+write) misses 1104system.cpu.icache.demand_misses::total 1981341 # number of demand (read+write) misses 1105system.cpu.icache.overall_misses::cpu.inst 1981341 # number of overall misses 1106system.cpu.icache.overall_misses::total 1981341 # number of overall misses 1107system.cpu.icache.ReadReq_miss_latency::cpu.inst 27584584993 # number of ReadReq miss cycles 1108system.cpu.icache.ReadReq_miss_latency::total 27584584993 # number of ReadReq miss cycles 1109system.cpu.icache.demand_miss_latency::cpu.inst 27584584993 # number of demand (read+write) miss cycles 1110system.cpu.icache.demand_miss_latency::total 27584584993 # number of demand (read+write) miss cycles 1111system.cpu.icache.overall_miss_latency::cpu.inst 27584584993 # number of overall miss cycles 1112system.cpu.icache.overall_miss_latency::total 27584584993 # number of overall miss cycles 1113system.cpu.icache.ReadReq_accesses::cpu.inst 65981784 # number of ReadReq accesses(hits+misses) 1114system.cpu.icache.ReadReq_accesses::total 65981784 # number of ReadReq accesses(hits+misses) 1115system.cpu.icache.demand_accesses::cpu.inst 65981784 # number of demand (read+write) accesses 1116system.cpu.icache.demand_accesses::total 65981784 # number of demand (read+write) accesses 1117system.cpu.icache.overall_accesses::cpu.inst 65981784 # number of overall (read+write) accesses 1118system.cpu.icache.overall_accesses::total 65981784 # number of overall (read+write) accesses 1119system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.030029 # miss rate for ReadReq accesses 1120system.cpu.icache.ReadReq_miss_rate::total 0.030029 # miss rate for ReadReq accesses 1121system.cpu.icache.demand_miss_rate::cpu.inst 0.030029 # miss rate for demand accesses 1122system.cpu.icache.demand_miss_rate::total 0.030029 # miss rate for demand accesses 1123system.cpu.icache.overall_miss_rate::cpu.inst 0.030029 # miss rate for overall accesses 1124system.cpu.icache.overall_miss_rate::total 0.030029 # miss rate for overall accesses 1125system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13922.179470 # average ReadReq miss latency 1126system.cpu.icache.ReadReq_avg_miss_latency::total 13922.179470 # average ReadReq miss latency 1127system.cpu.icache.demand_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency 1128system.cpu.icache.demand_avg_miss_latency::total 13922.179470 # average overall miss latency 1129system.cpu.icache.overall_avg_miss_latency::cpu.inst 13922.179470 # average overall miss latency 1130system.cpu.icache.overall_avg_miss_latency::total 13922.179470 # average overall miss latency 1131system.cpu.icache.blocked_cycles::no_mshrs 3020 # number of cycles access was blocked |
| 1114system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1132system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1115system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked | 1133system.cpu.icache.blocked::no_mshrs 145 # number of cycles access was blocked |
| 1116system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1134system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1117system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked | 1135system.cpu.icache.avg_blocked_cycles::no_mshrs 20.827586 # average number of cycles each access was blocked |
| 1118system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1136system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1119system.cpu.icache.writebacks::writebacks 1887810 # number of writebacks 1120system.cpu.icache.writebacks::total 1887810 # number of writebacks 1121system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91852 # number of ReadReq MSHR hits 1122system.cpu.icache.ReadReq_mshr_hits::total 91852 # number of ReadReq MSHR hits 1123system.cpu.icache.demand_mshr_hits::cpu.inst 91852 # number of demand (read+write) MSHR hits 1124system.cpu.icache.demand_mshr_hits::total 91852 # number of demand (read+write) MSHR hits 1125system.cpu.icache.overall_mshr_hits::cpu.inst 91852 # number of overall MSHR hits 1126system.cpu.icache.overall_mshr_hits::total 91852 # number of overall MSHR hits 1127system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888354 # number of ReadReq MSHR misses 1128system.cpu.icache.ReadReq_mshr_misses::total 1888354 # number of ReadReq MSHR misses 1129system.cpu.icache.demand_mshr_misses::cpu.inst 1888354 # number of demand (read+write) MSHR misses 1130system.cpu.icache.demand_mshr_misses::total 1888354 # number of demand (read+write) MSHR misses 1131system.cpu.icache.overall_mshr_misses::cpu.inst 1888354 # number of overall MSHR misses 1132system.cpu.icache.overall_mshr_misses::total 1888354 # number of overall MSHR misses 1133system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1134system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1135system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1136system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1137system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24226536497 # number of ReadReq MSHR miss cycles 1138system.cpu.icache.ReadReq_mshr_miss_latency::total 24226536497 # number of ReadReq MSHR miss cycles 1139system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24226536497 # number of demand (read+write) MSHR miss cycles 1140system.cpu.icache.demand_mshr_miss_latency::total 24226536497 # number of demand (read+write) MSHR miss cycles 1141system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24226536497 # number of overall MSHR miss cycles 1142system.cpu.icache.overall_mshr_miss_latency::total 24226536497 # number of overall MSHR miss cycles 1143system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 229048500 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 229048500 # number of ReadReq MSHR uncacheable cycles 1145system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 229048500 # number of overall MSHR uncacheable cycles 1146system.cpu.icache.overall_mshr_uncacheable_latency::total 229048500 # number of overall MSHR uncacheable cycles 1147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for ReadReq accesses 1148system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028587 # mshr miss rate for ReadReq accesses 1149system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for demand accesses 1150system.cpu.icache.demand_mshr_miss_rate::total 0.028587 # mshr miss rate for demand accesses 1151system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for overall accesses 1152system.cpu.icache.overall_mshr_miss_rate::total 0.028587 # mshr miss rate for overall accesses 1153system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437 # average ReadReq mshr miss latency 1154system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437 # average ReadReq mshr miss latency 1155system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency 1156system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency 1157system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency 1158system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency 1159system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average ReadReq mshr uncacheable latency 1160system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773 # average ReadReq mshr uncacheable latency 1161system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average overall mshr uncacheable latency 1162system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773 # average overall mshr uncacheable latency 1163system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1164system.cpu.l2cache.tags.replacements 103423 # number of replacements 1165system.cpu.l2cache.tags.tagsinuse 65159.012032 # Cycle average of tags in use 1166system.cpu.l2cache.tags.total_refs 5300281 # Total number of references to valid blocks. 1167system.cpu.l2cache.tags.sampled_refs 168782 # Sample count of references to valid blocks. 1168system.cpu.l2cache.tags.avg_refs 31.403118 # Average number of references to valid blocks. 1169system.cpu.l2cache.tags.warmup_cycle 93779484000 # Cycle when the warmup percentage was hit. 1170system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.961762 # Average occupied blocks per requestor 1171system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.729813 # Average occupied blocks per requestor 1172system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609 # Average occupied blocks per requestor 1173system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848 # Average occupied blocks per requestor 1174system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy 1175system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy 1176system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155301 # Average percentage of cache occupancy 1177system.cpu.l2cache.tags.occ_percent::cpu.data 0.838738 # Average percentage of cache occupancy 1178system.cpu.l2cache.tags.occ_percent::total 0.994248 # Average percentage of cache occupancy 1179system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1180system.cpu.l2cache.tags.occ_task_id_blocks::1024 65345 # Occupied blocks per task id 1181system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5571 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59599 # Occupied blocks per task id 1185system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id 1186system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997086 # Percentage of cache occupancy per task id 1187system.cpu.l2cache.tags.tag_accesses 43992446 # Number of tag accesses 1188system.cpu.l2cache.tags.data_accesses 43992446 # Number of data accesses 1189system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1190system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54341 # number of ReadReq hits 1191system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10212 # number of ReadReq hits 1192system.cpu.l2cache.ReadReq_hits::total 64553 # number of ReadReq hits 1193system.cpu.l2cache.WritebackDirty_hits::writebacks 696178 # number of WritebackDirty hits 1194system.cpu.l2cache.WritebackDirty_hits::total 696178 # number of WritebackDirty hits 1195system.cpu.l2cache.WritebackClean_hits::writebacks 1850381 # number of WritebackClean hits 1196system.cpu.l2cache.WritebackClean_hits::total 1850381 # number of WritebackClean hits 1197system.cpu.l2cache.UpgradeReq_hits::cpu.data 2757 # number of UpgradeReq hits 1198system.cpu.l2cache.UpgradeReq_hits::total 2757 # number of UpgradeReq hits 1199system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1200system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1201system.cpu.l2cache.ReadExReq_hits::cpu.data 158824 # number of ReadExReq hits 1202system.cpu.l2cache.ReadExReq_hits::total 158824 # number of ReadExReq hits 1203system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868353 # number of ReadCleanReq hits 1204system.cpu.l2cache.ReadCleanReq_hits::total 1868353 # number of ReadCleanReq hits 1205system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527348 # number of ReadSharedReq hits 1206system.cpu.l2cache.ReadSharedReq_hits::total 527348 # number of ReadSharedReq hits 1207system.cpu.l2cache.demand_hits::cpu.dtb.walker 54341 # number of demand (read+write) hits 1208system.cpu.l2cache.demand_hits::cpu.itb.walker 10212 # number of demand (read+write) hits 1209system.cpu.l2cache.demand_hits::cpu.inst 1868353 # number of demand (read+write) hits 1210system.cpu.l2cache.demand_hits::cpu.data 686172 # number of demand (read+write) hits 1211system.cpu.l2cache.demand_hits::total 2619078 # number of demand (read+write) hits 1212system.cpu.l2cache.overall_hits::cpu.dtb.walker 54341 # number of overall hits 1213system.cpu.l2cache.overall_hits::cpu.itb.walker 10212 # number of overall hits 1214system.cpu.l2cache.overall_hits::cpu.inst 1868353 # number of overall hits 1215system.cpu.l2cache.overall_hits::cpu.data 686172 # number of overall hits 1216system.cpu.l2cache.overall_hits::total 2619078 # number of overall hits 1217system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses 1218system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1219system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses 1220system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses 1221system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses | 1137system.cpu.icache.writebacks::writebacks 1888653 # number of writebacks 1138system.cpu.icache.writebacks::total 1888653 # number of writebacks 1139system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92140 # number of ReadReq MSHR hits 1140system.cpu.icache.ReadReq_mshr_hits::total 92140 # number of ReadReq MSHR hits 1141system.cpu.icache.demand_mshr_hits::cpu.inst 92140 # number of demand (read+write) MSHR hits 1142system.cpu.icache.demand_mshr_hits::total 92140 # number of demand (read+write) MSHR hits 1143system.cpu.icache.overall_mshr_hits::cpu.inst 92140 # number of overall MSHR hits 1144system.cpu.icache.overall_mshr_hits::total 92140 # number of overall MSHR hits 1145system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889201 # number of ReadReq MSHR misses 1146system.cpu.icache.ReadReq_mshr_misses::total 1889201 # number of ReadReq MSHR misses 1147system.cpu.icache.demand_mshr_misses::cpu.inst 1889201 # number of demand (read+write) MSHR misses 1148system.cpu.icache.demand_mshr_misses::total 1889201 # number of demand (read+write) MSHR misses 1149system.cpu.icache.overall_mshr_misses::cpu.inst 1889201 # number of overall MSHR misses 1150system.cpu.icache.overall_mshr_misses::total 1889201 # number of overall MSHR misses 1151system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable 1152system.cpu.icache.ReadReq_mshr_uncacheable::total 3009 # number of ReadReq MSHR uncacheable 1153system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses 1154system.cpu.icache.overall_mshr_uncacheable_misses::total 3009 # number of overall MSHR uncacheable misses 1155system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24719841497 # number of ReadReq MSHR miss cycles 1156system.cpu.icache.ReadReq_mshr_miss_latency::total 24719841497 # number of ReadReq MSHR miss cycles 1157system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24719841497 # number of demand (read+write) MSHR miss cycles 1158system.cpu.icache.demand_mshr_miss_latency::total 24719841497 # number of demand (read+write) MSHR miss cycles 1159system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24719841497 # number of overall MSHR miss cycles 1160system.cpu.icache.overall_mshr_miss_latency::total 24719841497 # number of overall MSHR miss cycles 1161system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 246809500 # number of ReadReq MSHR uncacheable cycles 1162system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 246809500 # number of ReadReq MSHR uncacheable cycles 1163system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 246809500 # number of overall MSHR uncacheable cycles 1164system.cpu.icache.overall_mshr_uncacheable_latency::total 246809500 # number of overall MSHR uncacheable cycles 1165system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for ReadReq accesses 1166system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028632 # mshr miss rate for ReadReq accesses 1167system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for demand accesses 1168system.cpu.icache.demand_mshr_miss_rate::total 0.028632 # mshr miss rate for demand accesses 1169system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028632 # mshr miss rate for overall accesses 1170system.cpu.icache.overall_mshr_miss_rate::total 0.028632 # mshr miss rate for overall accesses 1171system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13084.812837 # average ReadReq mshr miss latency 1172system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13084.812837 # average ReadReq mshr miss latency 1173system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency 1174system.cpu.icache.demand_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency 1175system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13084.812837 # average overall mshr miss latency 1176system.cpu.icache.overall_avg_mshr_miss_latency::total 13084.812837 # average overall mshr miss latency 1177system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average ReadReq mshr uncacheable latency 1178system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82023.762047 # average ReadReq mshr uncacheable latency 1179system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82023.762047 # average overall mshr uncacheable latency 1180system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82023.762047 # average overall mshr uncacheable latency 1181system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1182system.cpu.l2cache.tags.replacements 98099 # number of replacements 1183system.cpu.l2cache.tags.tagsinuse 65152.234049 # Cycle average of tags in use 1184system.cpu.l2cache.tags.total_refs 5297886 # Total number of references to valid blocks. 1185system.cpu.l2cache.tags.sampled_refs 163487 # Sample count of references to valid blocks. 1186system.cpu.l2cache.tags.avg_refs 32.405549 # Average number of references to valid blocks. 1187system.cpu.l2cache.tags.warmup_cycle 91189853000 # Cycle when the warmup percentage was hit. 1188system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 7.921050 # Average occupied blocks per requestor 1189system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 4.702137 # Average occupied blocks per requestor 1190system.cpu.l2cache.tags.occ_blocks::cpu.inst 10408.149180 # Average occupied blocks per requestor 1191system.cpu.l2cache.tags.occ_blocks::cpu.data 54731.461682 # Average occupied blocks per requestor 1192system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000121 # Average percentage of cache occupancy 1193system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000072 # Average percentage of cache occupancy 1194system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158816 # Average percentage of cache occupancy 1195system.cpu.l2cache.tags.occ_percent::cpu.data 0.835136 # Average percentage of cache occupancy 1196system.cpu.l2cache.tags.occ_percent::total 0.994144 # Average percentage of cache occupancy 1197system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1198system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id 1199system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1200system.cpu.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id 1201system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5397 # Occupied blocks per task id 1202system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59667 # Occupied blocks per task id 1203system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1204system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id 1205system.cpu.l2cache.tags.tag_accesses 43918819 # Number of tag accesses 1206system.cpu.l2cache.tags.data_accesses 43918819 # Number of data accesses 1207system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1208system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52413 # number of ReadReq hits 1209system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10038 # number of ReadReq hits 1210system.cpu.l2cache.ReadReq_hits::total 62451 # number of ReadReq hits 1211system.cpu.l2cache.WritebackDirty_hits::writebacks 694028 # number of WritebackDirty hits 1212system.cpu.l2cache.WritebackDirty_hits::total 694028 # number of WritebackDirty hits 1213system.cpu.l2cache.WritebackClean_hits::writebacks 1850699 # number of WritebackClean hits 1214system.cpu.l2cache.WritebackClean_hits::total 1850699 # number of WritebackClean hits 1215system.cpu.l2cache.UpgradeReq_hits::cpu.data 2792 # number of UpgradeReq hits 1216system.cpu.l2cache.UpgradeReq_hits::total 2792 # number of UpgradeReq hits 1217system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1218system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1219system.cpu.l2cache.ReadExReq_hits::cpu.data 161486 # number of ReadExReq hits 1220system.cpu.l2cache.ReadExReq_hits::total 161486 # number of ReadExReq hits 1221system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1869293 # number of ReadCleanReq hits 1222system.cpu.l2cache.ReadCleanReq_hits::total 1869293 # number of ReadCleanReq hits 1223system.cpu.l2cache.ReadSharedReq_hits::cpu.data 525699 # number of ReadSharedReq hits 1224system.cpu.l2cache.ReadSharedReq_hits::total 525699 # number of ReadSharedReq hits 1225system.cpu.l2cache.demand_hits::cpu.dtb.walker 52413 # number of demand (read+write) hits 1226system.cpu.l2cache.demand_hits::cpu.itb.walker 10038 # number of demand (read+write) hits 1227system.cpu.l2cache.demand_hits::cpu.inst 1869293 # number of demand (read+write) hits 1228system.cpu.l2cache.demand_hits::cpu.data 687185 # number of demand (read+write) hits 1229system.cpu.l2cache.demand_hits::total 2618929 # number of demand (read+write) hits 1230system.cpu.l2cache.overall_hits::cpu.dtb.walker 52413 # number of overall hits 1231system.cpu.l2cache.overall_hits::cpu.itb.walker 10038 # number of overall hits 1232system.cpu.l2cache.overall_hits::cpu.inst 1869293 # number of overall hits 1233system.cpu.l2cache.overall_hits::cpu.data 687185 # number of overall hits 1234system.cpu.l2cache.overall_hits::total 2618929 # number of overall hits 1235system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 14 # number of ReadReq misses 1236system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1237system.cpu.l2cache.ReadReq_misses::total 21 # number of ReadReq misses 1238system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses 1239system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses |
| 1222system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1223system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 1240system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1241system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 1224system.cpu.l2cache.ReadExReq_misses::cpu.data 139010 # number of ReadExReq misses 1225system.cpu.l2cache.ReadExReq_misses::total 139010 # number of ReadExReq misses 1226system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19937 # number of ReadCleanReq misses 1227system.cpu.l2cache.ReadCleanReq_misses::total 19937 # number of ReadCleanReq misses 1228system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14436 # number of ReadSharedReq misses 1229system.cpu.l2cache.ReadSharedReq_misses::total 14436 # number of ReadSharedReq misses 1230system.cpu.l2cache.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses 1231system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1232system.cpu.l2cache.demand_misses::cpu.inst 19937 # number of demand (read+write) misses 1233system.cpu.l2cache.demand_misses::cpu.data 153446 # number of demand (read+write) misses 1234system.cpu.l2cache.demand_misses::total 173405 # number of demand (read+write) misses 1235system.cpu.l2cache.overall_misses::cpu.dtb.walker 16 # number of overall misses 1236system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1237system.cpu.l2cache.overall_misses::cpu.inst 19937 # number of overall misses 1238system.cpu.l2cache.overall_misses::cpu.data 153446 # number of overall misses 1239system.cpu.l2cache.overall_misses::total 173405 # number of overall misses 1240system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1497500 # number of ReadReq miss cycles 1241system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 502000 # number of ReadReq miss cycles 1242system.cpu.l2cache.ReadReq_miss_latency::total 1999500 # number of ReadReq miss cycles 1243system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles 1244system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles 1245system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 167000 # number of SCUpgradeReq miss cycles 1246system.cpu.l2cache.SCUpgradeReq_miss_latency::total 167000 # number of SCUpgradeReq miss cycles 1247system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11275740500 # number of ReadExReq miss cycles 1248system.cpu.l2cache.ReadExReq_miss_latency::total 11275740500 # number of ReadExReq miss cycles 1249system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1659086000 # number of ReadCleanReq miss cycles 1250system.cpu.l2cache.ReadCleanReq_miss_latency::total 1659086000 # number of ReadCleanReq miss cycles 1251system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1242944500 # number of ReadSharedReq miss cycles 1252system.cpu.l2cache.ReadSharedReq_miss_latency::total 1242944500 # number of ReadSharedReq miss cycles 1253system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1497500 # number of demand (read+write) miss cycles 1254system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 502000 # number of demand (read+write) miss cycles 1255system.cpu.l2cache.demand_miss_latency::cpu.inst 1659086000 # number of demand (read+write) miss cycles 1256system.cpu.l2cache.demand_miss_latency::cpu.data 12518685000 # number of demand (read+write) miss cycles 1257system.cpu.l2cache.demand_miss_latency::total 14179770500 # number of demand (read+write) miss cycles 1258system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1497500 # number of overall miss cycles 1259system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 502000 # number of overall miss cycles 1260system.cpu.l2cache.overall_miss_latency::cpu.inst 1659086000 # number of overall miss cycles 1261system.cpu.l2cache.overall_miss_latency::cpu.data 12518685000 # number of overall miss cycles 1262system.cpu.l2cache.overall_miss_latency::total 14179770500 # number of overall miss cycles 1263system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54357 # number of ReadReq accesses(hits+misses) 1264system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10218 # number of ReadReq accesses(hits+misses) 1265system.cpu.l2cache.ReadReq_accesses::total 64575 # number of ReadReq accesses(hits+misses) 1266system.cpu.l2cache.WritebackDirty_accesses::writebacks 696178 # number of WritebackDirty accesses(hits+misses) 1267system.cpu.l2cache.WritebackDirty_accesses::total 696178 # number of WritebackDirty accesses(hits+misses) 1268system.cpu.l2cache.WritebackClean_accesses::writebacks 1850381 # number of WritebackClean accesses(hits+misses) 1269system.cpu.l2cache.WritebackClean_accesses::total 1850381 # number of WritebackClean accesses(hits+misses) 1270system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) 1271system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) 1272system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1273system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1274system.cpu.l2cache.ReadExReq_accesses::cpu.data 297834 # number of ReadExReq accesses(hits+misses) 1275system.cpu.l2cache.ReadExReq_accesses::total 297834 # number of ReadExReq accesses(hits+misses) 1276system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888290 # number of ReadCleanReq accesses(hits+misses) 1277system.cpu.l2cache.ReadCleanReq_accesses::total 1888290 # number of ReadCleanReq accesses(hits+misses) 1278system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541784 # number of ReadSharedReq accesses(hits+misses) 1279system.cpu.l2cache.ReadSharedReq_accesses::total 541784 # number of ReadSharedReq accesses(hits+misses) 1280system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54357 # number of demand (read+write) accesses 1281system.cpu.l2cache.demand_accesses::cpu.itb.walker 10218 # number of demand (read+write) accesses 1282system.cpu.l2cache.demand_accesses::cpu.inst 1888290 # number of demand (read+write) accesses 1283system.cpu.l2cache.demand_accesses::cpu.data 839618 # number of demand (read+write) accesses 1284system.cpu.l2cache.demand_accesses::total 2792483 # number of demand (read+write) accesses 1285system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54357 # number of overall (read+write) accesses 1286system.cpu.l2cache.overall_accesses::cpu.itb.walker 10218 # number of overall (read+write) accesses 1287system.cpu.l2cache.overall_accesses::cpu.inst 1888290 # number of overall (read+write) accesses 1288system.cpu.l2cache.overall_accesses::cpu.data 839618 # number of overall (read+write) accesses 1289system.cpu.l2cache.overall_accesses::total 2792483 # number of overall (read+write) accesses 1290system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000294 # miss rate for ReadReq accesses 1291system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000587 # miss rate for ReadReq accesses 1292system.cpu.l2cache.ReadReq_miss_rate::total 0.000341 # miss rate for ReadReq accesses 1293system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003974 # miss rate for UpgradeReq accesses 1294system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003974 # miss rate for UpgradeReq accesses 1295system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1296system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 1297system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.466737 # miss rate for ReadExReq accesses 1298system.cpu.l2cache.ReadExReq_miss_rate::total 0.466737 # miss rate for ReadExReq accesses 1299system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010558 # miss rate for ReadCleanReq accesses 1300system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010558 # miss rate for ReadCleanReq accesses 1301system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026645 # miss rate for ReadSharedReq accesses 1302system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026645 # miss rate for ReadSharedReq accesses 1303system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000294 # miss rate for demand accesses 1304system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000587 # miss rate for demand accesses 1305system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010558 # miss rate for demand accesses 1306system.cpu.l2cache.demand_miss_rate::cpu.data 0.182757 # miss rate for demand accesses 1307system.cpu.l2cache.demand_miss_rate::total 0.062097 # miss rate for demand accesses 1308system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000294 # miss rate for overall accesses 1309system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000587 # miss rate for overall accesses 1310system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010558 # miss rate for overall accesses 1311system.cpu.l2cache.overall_miss_rate::cpu.data 0.182757 # miss rate for overall accesses 1312system.cpu.l2cache.overall_miss_rate::total 0.062097 # miss rate for overall accesses 1313system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000 # average ReadReq miss latency 1314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667 # average ReadReq miss latency 1315system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636 # average ReadReq miss latency 1316system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636 # average UpgradeReq miss latency 1317system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636 # average UpgradeReq miss latency 1318system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83500 # average SCUpgradeReq miss latency 1319system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83500 # average SCUpgradeReq miss latency 1320system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669 # average ReadExReq miss latency 1321system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669 # average ReadExReq miss latency 1322system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760 # average ReadCleanReq miss latency 1323system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760 # average ReadCleanReq miss latency 1324system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429 # average ReadSharedReq miss latency 1325system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429 # average ReadSharedReq miss latency 1326system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency 1327system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency 1328system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency 1329system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency 1330system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461 # average overall miss latency 1331system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency 1332system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency 1333system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency 1334system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency 1335system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461 # average overall miss latency | 1242system.cpu.l2cache.ReadExReq_misses::cpu.data 135095 # number of ReadExReq misses 1243system.cpu.l2cache.ReadExReq_misses::total 135095 # number of ReadExReq misses 1244system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19848 # number of ReadCleanReq misses 1245system.cpu.l2cache.ReadCleanReq_misses::total 19848 # number of ReadCleanReq misses 1246system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13395 # number of ReadSharedReq misses 1247system.cpu.l2cache.ReadSharedReq_misses::total 13395 # number of ReadSharedReq misses 1248system.cpu.l2cache.demand_misses::cpu.dtb.walker 14 # number of demand (read+write) misses 1249system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1250system.cpu.l2cache.demand_misses::cpu.inst 19848 # number of demand (read+write) misses 1251system.cpu.l2cache.demand_misses::cpu.data 148490 # number of demand (read+write) misses 1252system.cpu.l2cache.demand_misses::total 168359 # number of demand (read+write) misses 1253system.cpu.l2cache.overall_misses::cpu.dtb.walker 14 # number of overall misses 1254system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1255system.cpu.l2cache.overall_misses::cpu.inst 19848 # number of overall misses 1256system.cpu.l2cache.overall_misses::cpu.data 148490 # number of overall misses 1257system.cpu.l2cache.overall_misses::total 168359 # number of overall misses 1258system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3912000 # number of ReadReq miss cycles 1259system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 1698000 # number of ReadReq miss cycles 1260system.cpu.l2cache.ReadReq_miss_latency::total 5610000 # number of ReadReq miss cycles 1261system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 143500 # number of UpgradeReq miss cycles 1262system.cpu.l2cache.UpgradeReq_miss_latency::total 143500 # number of UpgradeReq miss cycles 1263system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 164000 # number of SCUpgradeReq miss cycles 1264system.cpu.l2cache.SCUpgradeReq_miss_latency::total 164000 # number of SCUpgradeReq miss cycles 1265system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12742200000 # number of ReadExReq miss cycles 1266system.cpu.l2cache.ReadExReq_miss_latency::total 12742200000 # number of ReadExReq miss cycles 1267system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2140966000 # number of ReadCleanReq miss cycles 1268system.cpu.l2cache.ReadCleanReq_miss_latency::total 2140966000 # number of ReadCleanReq miss cycles 1269system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1561950000 # number of ReadSharedReq miss cycles 1270system.cpu.l2cache.ReadSharedReq_miss_latency::total 1561950000 # number of ReadSharedReq miss cycles 1271system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3912000 # number of demand (read+write) miss cycles 1272system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 1698000 # number of demand (read+write) miss cycles 1273system.cpu.l2cache.demand_miss_latency::cpu.inst 2140966000 # number of demand (read+write) miss cycles 1274system.cpu.l2cache.demand_miss_latency::cpu.data 14304150000 # number of demand (read+write) miss cycles 1275system.cpu.l2cache.demand_miss_latency::total 16450726000 # number of demand (read+write) miss cycles 1276system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3912000 # number of overall miss cycles 1277system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 1698000 # number of overall miss cycles 1278system.cpu.l2cache.overall_miss_latency::cpu.inst 2140966000 # number of overall miss cycles 1279system.cpu.l2cache.overall_miss_latency::cpu.data 14304150000 # number of overall miss cycles 1280system.cpu.l2cache.overall_miss_latency::total 16450726000 # number of overall miss cycles 1281system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52427 # number of ReadReq accesses(hits+misses) 1282system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10045 # number of ReadReq accesses(hits+misses) 1283system.cpu.l2cache.ReadReq_accesses::total 62472 # number of ReadReq accesses(hits+misses) 1284system.cpu.l2cache.WritebackDirty_accesses::writebacks 694028 # number of WritebackDirty accesses(hits+misses) 1285system.cpu.l2cache.WritebackDirty_accesses::total 694028 # number of WritebackDirty accesses(hits+misses) 1286system.cpu.l2cache.WritebackClean_accesses::writebacks 1850699 # number of WritebackClean accesses(hits+misses) 1287system.cpu.l2cache.WritebackClean_accesses::total 1850699 # number of WritebackClean accesses(hits+misses) 1288system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2797 # number of UpgradeReq accesses(hits+misses) 1289system.cpu.l2cache.UpgradeReq_accesses::total 2797 # number of UpgradeReq accesses(hits+misses) 1290system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 1291system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 1292system.cpu.l2cache.ReadExReq_accesses::cpu.data 296581 # number of ReadExReq accesses(hits+misses) 1293system.cpu.l2cache.ReadExReq_accesses::total 296581 # number of ReadExReq accesses(hits+misses) 1294system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1889141 # number of ReadCleanReq accesses(hits+misses) 1295system.cpu.l2cache.ReadCleanReq_accesses::total 1889141 # number of ReadCleanReq accesses(hits+misses) 1296system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 539094 # number of ReadSharedReq accesses(hits+misses) 1297system.cpu.l2cache.ReadSharedReq_accesses::total 539094 # number of ReadSharedReq accesses(hits+misses) 1298system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52427 # number of demand (read+write) accesses 1299system.cpu.l2cache.demand_accesses::cpu.itb.walker 10045 # number of demand (read+write) accesses 1300system.cpu.l2cache.demand_accesses::cpu.inst 1889141 # number of demand (read+write) accesses 1301system.cpu.l2cache.demand_accesses::cpu.data 835675 # number of demand (read+write) accesses 1302system.cpu.l2cache.demand_accesses::total 2787288 # number of demand (read+write) accesses 1303system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52427 # number of overall (read+write) accesses 1304system.cpu.l2cache.overall_accesses::cpu.itb.walker 10045 # number of overall (read+write) accesses 1305system.cpu.l2cache.overall_accesses::cpu.inst 1889141 # number of overall (read+write) accesses 1306system.cpu.l2cache.overall_accesses::cpu.data 835675 # number of overall (read+write) accesses 1307system.cpu.l2cache.overall_accesses::total 2787288 # number of overall (read+write) accesses 1308system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000267 # miss rate for ReadReq accesses 1309system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000697 # miss rate for ReadReq accesses 1310system.cpu.l2cache.ReadReq_miss_rate::total 0.000336 # miss rate for ReadReq accesses 1311system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.001788 # miss rate for UpgradeReq accesses 1312system.cpu.l2cache.UpgradeReq_miss_rate::total 0.001788 # miss rate for UpgradeReq accesses 1313system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1314system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 1315system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455508 # miss rate for ReadExReq accesses 1316system.cpu.l2cache.ReadExReq_miss_rate::total 0.455508 # miss rate for ReadExReq accesses 1317system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010506 # miss rate for ReadCleanReq accesses 1318system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010506 # miss rate for ReadCleanReq accesses 1319system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024847 # miss rate for ReadSharedReq accesses 1320system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024847 # miss rate for ReadSharedReq accesses 1321system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000267 # miss rate for demand accesses 1322system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000697 # miss rate for demand accesses 1323system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010506 # miss rate for demand accesses 1324system.cpu.l2cache.demand_miss_rate::cpu.data 0.177689 # miss rate for demand accesses 1325system.cpu.l2cache.demand_miss_rate::total 0.060402 # miss rate for demand accesses 1326system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000267 # miss rate for overall accesses 1327system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000697 # miss rate for overall accesses 1328system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010506 # miss rate for overall accesses 1329system.cpu.l2cache.overall_miss_rate::cpu.data 0.177689 # miss rate for overall accesses 1330system.cpu.l2cache.overall_miss_rate::total 0.060402 # miss rate for overall accesses 1331system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 279428.571429 # average ReadReq miss latency 1332system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 242571.428571 # average ReadReq miss latency 1333system.cpu.l2cache.ReadReq_avg_miss_latency::total 267142.857143 # average ReadReq miss latency 1334system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 28700 # average UpgradeReq miss latency 1335system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 28700 # average UpgradeReq miss latency 1336system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82000 # average SCUpgradeReq miss latency 1337system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82000 # average SCUpgradeReq miss latency 1338system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94320.293127 # average ReadExReq miss latency 1339system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94320.293127 # average ReadExReq miss latency 1340system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107868.097541 # average ReadCleanReq miss latency 1341system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107868.097541 # average ReadCleanReq miss latency 1342system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 116606.942889 # average ReadSharedReq miss latency 1343system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 116606.942889 # average ReadSharedReq miss latency 1344system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency 1345system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency 1346system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency 1347system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency 1348system.cpu.l2cache.demand_avg_miss_latency::total 97712.186459 # average overall miss latency 1349system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 279428.571429 # average overall miss latency 1350system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 242571.428571 # average overall miss latency 1351system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107868.097541 # average overall miss latency 1352system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96330.729342 # average overall miss latency 1353system.cpu.l2cache.overall_avg_miss_latency::total 97712.186459 # average overall miss latency |
| 1336system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1337system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1338system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1339system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1340system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1341system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1354system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1355system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1356system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1357system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1358system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1359system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1342system.cpu.l2cache.writebacks::writebacks 95172 # number of writebacks 1343system.cpu.l2cache.writebacks::total 95172 # number of writebacks 1344system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits 1345system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits 1346system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits 1347system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits 1348system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits 1349system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits 1350system.cpu.l2cache.demand_mshr_hits::total 135 # number of demand (read+write) MSHR hits 1351system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits 1352system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits 1353system.cpu.l2cache.overall_mshr_hits::total 135 # number of overall MSHR hits 1354system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 16 # number of ReadReq MSHR misses 1355system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1356system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses 1357system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses 1358system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses | 1360system.cpu.l2cache.writebacks::writebacks 90242 # number of writebacks 1361system.cpu.l2cache.writebacks::total 90242 # number of writebacks 1362system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 25 # number of ReadCleanReq MSHR hits 1363system.cpu.l2cache.ReadCleanReq_mshr_hits::total 25 # number of ReadCleanReq MSHR hits 1364system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits 1365system.cpu.l2cache.ReadSharedReq_mshr_hits::total 113 # number of ReadSharedReq MSHR hits 1366system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1367system.cpu.l2cache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits 1368system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits 1369system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits 1370system.cpu.l2cache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits 1371system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits 1372system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 14 # number of ReadReq MSHR misses 1373system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1374system.cpu.l2cache.ReadReq_mshr_misses::total 21 # number of ReadReq MSHR misses 1375system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses 1376system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses |
| 1359system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1360system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1377system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1378system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1361system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139010 # number of ReadExReq MSHR misses 1362system.cpu.l2cache.ReadExReq_mshr_misses::total 139010 # number of ReadExReq MSHR misses 1363system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19914 # number of ReadCleanReq MSHR misses 1364system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19914 # number of ReadCleanReq MSHR misses 1365system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14324 # number of ReadSharedReq MSHR misses 1366system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14324 # number of ReadSharedReq MSHR misses 1367system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 16 # number of demand (read+write) MSHR misses 1368system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1369system.cpu.l2cache.demand_mshr_misses::cpu.inst 19914 # number of demand (read+write) MSHR misses 1370system.cpu.l2cache.demand_mshr_misses::cpu.data 153334 # number of demand (read+write) MSHR misses 1371system.cpu.l2cache.demand_mshr_misses::total 173270 # number of demand (read+write) MSHR misses 1372system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 16 # number of overall MSHR misses 1373system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1374system.cpu.l2cache.overall_mshr_misses::cpu.inst 19914 # number of overall MSHR misses 1375system.cpu.l2cache.overall_mshr_misses::cpu.data 153334 # number of overall MSHR misses 1376system.cpu.l2cache.overall_mshr_misses::total 173270 # number of overall MSHR misses 1377system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable | 1379system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135095 # number of ReadExReq MSHR misses 1380system.cpu.l2cache.ReadExReq_mshr_misses::total 135095 # number of ReadExReq MSHR misses 1381system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19823 # number of ReadCleanReq MSHR misses 1382system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19823 # number of ReadCleanReq MSHR misses 1383system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13282 # number of ReadSharedReq MSHR misses 1384system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13282 # number of ReadSharedReq MSHR misses 1385system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 14 # number of demand (read+write) MSHR misses 1386system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1387system.cpu.l2cache.demand_mshr_misses::cpu.inst 19823 # number of demand (read+write) MSHR misses 1388system.cpu.l2cache.demand_mshr_misses::cpu.data 148377 # number of demand (read+write) MSHR misses 1389system.cpu.l2cache.demand_mshr_misses::total 168221 # number of demand (read+write) MSHR misses 1390system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 14 # number of overall MSHR misses 1391system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1392system.cpu.l2cache.overall_mshr_misses::cpu.inst 19823 # number of overall MSHR misses 1393system.cpu.l2cache.overall_mshr_misses::cpu.data 148377 # number of overall MSHR misses 1394system.cpu.l2cache.overall_mshr_misses::total 168221 # number of overall MSHR misses 1395system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3009 # number of ReadReq MSHR uncacheable |
| 1378system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable | 1396system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable |
| 1379system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34130 # number of ReadReq MSHR uncacheable | 1397system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34136 # number of ReadReq MSHR uncacheable |
| 1380system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1381system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable | 1398system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1399system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable |
| 1382system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses | 1400system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3009 # number of overall MSHR uncacheable misses |
| 1383system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses | 1401system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses |
| 1384system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61714 # number of overall MSHR uncacheable misses 1385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1337500 # number of ReadReq MSHR miss cycles 1386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles 1387system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1779500 # number of ReadReq MSHR miss cycles 1388system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 210500 # number of UpgradeReq MSHR miss cycles 1389system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 210500 # number of UpgradeReq MSHR miss cycles 1390system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 147000 # number of SCUpgradeReq MSHR miss cycles 1391system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 147000 # number of SCUpgradeReq MSHR miss cycles 1392system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9885640500 # number of ReadExReq MSHR miss cycles 1393system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9885640500 # number of ReadExReq MSHR miss cycles 1394system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1458480000 # number of ReadCleanReq MSHR miss cycles 1395system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1458480000 # number of ReadCleanReq MSHR miss cycles 1396system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1091561500 # number of ReadSharedReq MSHR miss cycles 1397system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1091561500 # number of ReadSharedReq MSHR miss cycles 1398system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1337500 # number of demand (read+write) MSHR miss cycles 1399system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles 1400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1458480000 # number of demand (read+write) MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10977202000 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::total 12437461500 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1337500 # number of overall MSHR miss cycles 1404system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles 1405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1458480000 # number of overall MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10977202000 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::total 12437461500 # number of overall MSHR miss cycles 1408system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191510500 # number of ReadReq MSHR uncacheable cycles 1409system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5890404500 # number of ReadReq MSHR uncacheable cycles 1410system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6081915000 # number of ReadReq MSHR uncacheable cycles 1411system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191510500 # number of overall MSHR uncacheable cycles 1412system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5890404500 # number of overall MSHR uncacheable cycles 1413system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6081915000 # number of overall MSHR uncacheable cycles 1414system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for ReadReq accesses 1415system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for ReadReq accesses 1416system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000341 # mshr miss rate for ReadReq accesses 1417system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003974 # mshr miss rate for UpgradeReq accesses 1418system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003974 # mshr miss rate for UpgradeReq accesses 1419system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1420system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 1421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466737 # mshr miss rate for ReadExReq accesses 1422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466737 # mshr miss rate for ReadExReq accesses 1423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for ReadCleanReq accesses 1424system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010546 # mshr miss rate for ReadCleanReq accesses 1425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026439 # mshr miss rate for ReadSharedReq accesses 1426system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026439 # mshr miss rate for ReadSharedReq accesses 1427system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for demand accesses 1428system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for demand accesses 1429system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for demand accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::total 0.062049 # mshr miss rate for demand accesses 1432system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for overall accesses 1433system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses 1434system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses 1437system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency 1438system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency 1439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency 1440system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency 1441system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency 1442system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency 1443system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency 1444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency 1445system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency 1446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency 1447system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency 1448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency 1449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency 1450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency 1451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency 1452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency 1455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency 1456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency 1457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency 1460system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency 1461system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency 1462system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency 1463system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency 1464system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency 1465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency 1466system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter. 1467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1469system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1402system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61720 # number of overall MSHR uncacheable misses 1403system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3772000 # number of ReadReq MSHR miss cycles 1404system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 1628000 # number of ReadReq MSHR miss cycles 1405system.cpu.l2cache.ReadReq_mshr_miss_latency::total 5400000 # number of ReadReq MSHR miss cycles 1406system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 93500 # number of UpgradeReq MSHR miss cycles 1407system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 93500 # number of UpgradeReq MSHR miss cycles 1408system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 144000 # number of SCUpgradeReq MSHR miss cycles 1409system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 144000 # number of SCUpgradeReq MSHR miss cycles 1410system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11391250000 # number of ReadExReq MSHR miss cycles 1411system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11391250000 # number of ReadExReq MSHR miss cycles 1412system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1940936500 # number of ReadCleanReq MSHR miss cycles 1413system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1940936500 # number of ReadCleanReq MSHR miss cycles 1414system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1418400000 # number of ReadSharedReq MSHR miss cycles 1415system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1418400000 # number of ReadSharedReq MSHR miss cycles 1416system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3772000 # number of demand (read+write) MSHR miss cycles 1417system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 1628000 # number of demand (read+write) MSHR miss cycles 1418system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1940936500 # number of demand (read+write) MSHR miss cycles 1419system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12809650000 # number of demand (read+write) MSHR miss cycles 1420system.cpu.l2cache.demand_mshr_miss_latency::total 14755986500 # number of demand (read+write) MSHR miss cycles 1421system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3772000 # number of overall MSHR miss cycles 1422system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 1628000 # number of overall MSHR miss cycles 1423system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1940936500 # number of overall MSHR miss cycles 1424system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12809650000 # number of overall MSHR miss cycles 1425system.cpu.l2cache.overall_mshr_miss_latency::total 14755986500 # number of overall MSHR miss cycles 1426system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209196500 # number of ReadReq MSHR uncacheable cycles 1427system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5892839000 # number of ReadReq MSHR uncacheable cycles 1428system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6102035500 # number of ReadReq MSHR uncacheable cycles 1429system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209196500 # number of overall MSHR uncacheable cycles 1430system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5892839000 # number of overall MSHR uncacheable cycles 1431system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6102035500 # number of overall MSHR uncacheable cycles 1432system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for ReadReq accesses 1433system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for ReadReq accesses 1434system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000336 # mshr miss rate for ReadReq accesses 1435system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.001788 # mshr miss rate for UpgradeReq accesses 1436system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.001788 # mshr miss rate for UpgradeReq accesses 1437system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1438system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1439system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455508 # mshr miss rate for ReadExReq accesses 1440system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455508 # mshr miss rate for ReadExReq accesses 1441system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for ReadCleanReq accesses 1442system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010493 # mshr miss rate for ReadCleanReq accesses 1443system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024638 # mshr miss rate for ReadSharedReq accesses 1444system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024638 # mshr miss rate for ReadSharedReq accesses 1445system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for demand accesses 1446system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for demand accesses 1447system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for demand accesses 1448system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for demand accesses 1449system.cpu.l2cache.demand_mshr_miss_rate::total 0.060353 # mshr miss rate for demand accesses 1450system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000267 # mshr miss rate for overall accesses 1451system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000697 # mshr miss rate for overall accesses 1452system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010493 # mshr miss rate for overall accesses 1453system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177553 # mshr miss rate for overall accesses 1454system.cpu.l2cache.overall_mshr_miss_rate::total 0.060353 # mshr miss rate for overall accesses 1455system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average ReadReq mshr miss latency 1456system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average ReadReq mshr miss latency 1457system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 257142.857143 # average ReadReq mshr miss latency 1458system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18700 # average UpgradeReq mshr miss latency 1459system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18700 # average UpgradeReq mshr miss latency 1460system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72000 # average SCUpgradeReq mshr miss latency 1461system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72000 # average SCUpgradeReq mshr miss latency 1462system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84320.293127 # average ReadExReq mshr miss latency 1463system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84320.293127 # average ReadExReq mshr miss latency 1464system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97913.358220 # average ReadCleanReq mshr miss latency 1465system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97913.358220 # average ReadCleanReq mshr miss latency 1466system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 106791.145912 # average ReadSharedReq mshr miss latency 1467system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 106791.145912 # average ReadSharedReq mshr miss latency 1468system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency 1469system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency 1470system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency 1471system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency 1472system.cpu.l2cache.demand_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency 1473system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 269428.571429 # average overall mshr miss latency 1474system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 232571.428571 # average overall mshr miss latency 1475system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97913.358220 # average overall mshr miss latency 1476system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86331.776488 # average overall mshr miss latency 1477system.cpu.l2cache.overall_avg_mshr_miss_latency::total 87717.862217 # average overall mshr miss latency 1478system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average ReadReq mshr uncacheable latency 1479system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189315.995759 # average ReadReq mshr uncacheable latency 1480system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178756.605929 # average ReadReq mshr uncacheable latency 1481system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69523.595879 # average overall mshr uncacheable latency 1482system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100370.271329 # average overall mshr uncacheable latency 1483system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98866.420933 # average overall mshr uncacheable latency 1484system.cpu.toL2Bus.snoop_filter.tot_requests 5483646 # Total number of requests made to the snoop filter. 1485system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758798 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1486system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45074 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1487system.cpu.toL2Bus.snoop_filter.tot_snoops 178 # Total number of snoops made to the snoop filter. 1488system.cpu.toL2Bus.snoop_filter.hit_single_snoops 178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1489system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1473system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution | 1490system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1491system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1492system.cpu.toL2Bus.trans_dist::ReadResp 2557224 # Transaction distribution |
| 1475system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution | 1493system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1494system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution |
| 1477system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution 1484system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution 1485system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution 1486system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution 1487system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution 1488system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) 1489system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) 1490system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) 1491system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) 1493system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.snoops 139207 # Total snoops (count) 1499system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) 1500system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram 1501system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram | 1495system.cpu.toL2Bus.trans_dist::WritebackDirty 784270 # Transaction distribution 1496system.cpu.toL2Bus.trans_dist::WritebackClean 1888653 # Transaction distribution 1497system.cpu.toL2Bus.trans_dist::CleanEvict 148972 # Transaction distribution 1498system.cpu.toL2Bus.trans_dist::UpgradeReq 2797 # Transaction distribution 1499system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1500system.cpu.toL2Bus.trans_dist::UpgradeResp 2801 # Transaction distribution 1501system.cpu.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution 1502system.cpu.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution 1503system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889201 # Transaction distribution 1504system.cpu.toL2Bus.trans_dist::ReadSharedReq 539301 # Transaction distribution 1505system.cpu.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution 1506system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5673012 # Packet count per connected master and slave (bytes) 1507system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629673 # Packet count per connected master and slave (bytes) 1508system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28918 # Packet count per connected master and slave (bytes) 1509system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128192 # Packet count per connected master and slave (bytes) 1510system.cpu.toL2Bus.pkt_count::total 8459795 # Packet count per connected master and slave (bytes) 1511system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241826896 # Cumulative packet size per connected master and slave (bytes) 1512system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98094045 # Cumulative packet size per connected master and slave (bytes) 1513system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40180 # Cumulative packet size per connected master and slave (bytes) 1514system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209708 # Cumulative packet size per connected master and slave (bytes) 1515system.cpu.toL2Bus.pkt_size::total 340170829 # Cumulative packet size per connected master and slave (bytes) 1516system.cpu.toL2Bus.snoops 135300 # Total snoops (count) 1517system.cpu.toL2Bus.snoopTraffic 5917976 # Total snoop traffic (bytes) 1518system.cpu.toL2Bus.snoop_fanout::samples 2986955 # Request fanout histogram 1519system.cpu.toL2Bus.snoop_fanout::mean 0.025939 # Request fanout histogram 1520system.cpu.toL2Bus.snoop_fanout::stdev 0.158953 # Request fanout histogram |
| 1503system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1521system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1504system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram | 1522system.cpu.toL2Bus.snoop_fanout::0 2909477 97.41% 97.41% # Request fanout histogram 1523system.cpu.toL2Bus.snoop_fanout::1 77478 2.59% 100.00% # Request fanout histogram |
| 1506system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1509system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1524system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1525system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1526system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1527system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1510system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram 1511system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) | 1528system.cpu.toL2Bus.snoop_fanout::total 2986955 # Request fanout histogram 1529system.cpu.toL2Bus.reqLayer0.occupancy 5400390498 # Layer occupancy (ticks) |
| 1512system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1530system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1513system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) | 1531system.cpu.toL2Bus.snoopLayer0.occupancy 295626 # Layer occupancy (ticks) |
| 1514system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1532system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1515system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) | 1533system.cpu.toL2Bus.respLayer0.occupancy 2837677759 # Layer occupancy (ticks) |
| 1516system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1534system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1517system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) | 1535system.cpu.toL2Bus.respLayer1.occupancy 1300010143 # Layer occupancy (ticks) |
| 1518system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1536system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1519system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) | 1537system.cpu.toL2Bus.respLayer2.occupancy 18878489 # Layer occupancy (ticks) |
| 1520system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1538system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1521system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) | 1539system.cpu.toL2Bus.respLayer3.occupancy 75816896 # Layer occupancy (ticks) |
| 1522system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1540system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1523system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1524system.iobus.trans_dist::ReadReq 30182 # Transaction distribution 1525system.iobus.trans_dist::ReadResp 30182 # Transaction distribution | 1541system.iobus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1542system.iobus.trans_dist::ReadReq 30169 # Transaction distribution 1543system.iobus.trans_dist::ReadResp 30169 # Transaction distribution |
| 1526system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1527system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1528system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1540system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1541system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1542system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1543system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) | 1544system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1545system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1546system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1551system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1558system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1559system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1560system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1561system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1562system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1563system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1564system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1565system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) |
| 1548system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) | 1566system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) 1567system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) 1568system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) |
| 1551system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1563system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) | 1569system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1574system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1575system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1576system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1581system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1582system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1583system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1584system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1585system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1586system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1587system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1588system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1571system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) 1574system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) | 1589system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) 1590system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) 1591system.iobus.pkt_size::total 2480117 # Cumulative packet size per connected master and slave (bytes) 1592system.iobus.reqLayer0.occupancy 43090000 # Layer occupancy (ticks) |
| 1575system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1593system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1576system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) | 1594system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) |
| 1577system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1595system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1578system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) | 1596system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) |
| 1579system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1597system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1580system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) | 1598system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) |
| 1581system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1599system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1582system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) | 1600system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) |
| 1583system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1601system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1584system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) | 1602system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) |
| 1585system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1603system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1586system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) | 1604system.iobus.reqLayer8.occupancy 649000 # Layer occupancy (ticks) |
| 1587system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1588system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1589system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1590system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1591system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1592system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 1593system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1594system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1600system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1601system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1602system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1603system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1604system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1605system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1606system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1607system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1605system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1606system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1607system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1608system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1609system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1610system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 1611system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1612system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1618system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1619system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1620system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1621system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1622system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1623system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1624system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1625system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1608system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) | 1626system.iobus.reqLayer23.occupancy 6166500 # Layer occupancy (ticks) |
| 1609system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1627system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1610system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) | 1628system.iobus.reqLayer24.occupancy 33827500 # Layer occupancy (ticks) |
| 1611system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1629system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1612system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) | 1630system.iobus.reqLayer25.occupancy 187658622 # Layer occupancy (ticks) |
| 1613system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1614system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1615system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1631system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1632system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1633system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1616system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) | 1634system.iobus.respLayer3.occupancy 36712000 # Layer occupancy (ticks) |
| 1617system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1635system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1618system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1619system.iocache.tags.replacements 36423 # number of replacements 1620system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use | 1636system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1637system.iocache.tags.replacements 36410 # number of replacements 1638system.iocache.tags.tagsinuse 1.001835 # Cycle average of tags in use |
| 1621system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1639system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1622system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. | 1640system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. |
| 1623system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1641system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1624system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. 1625system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor 1626system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy 1627system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy | 1642system.iocache.tags.warmup_cycle 253680812000 # Cycle when the warmup percentage was hit. 1643system.iocache.tags.occ_blocks::realview.ide 1.001835 # Average occupied blocks per requestor 1644system.iocache.tags.occ_percent::realview.ide 0.062615 # Average percentage of cache occupancy 1645system.iocache.tags.occ_percent::total 0.062615 # Average percentage of cache occupancy |
| 1628system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1629system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1630system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1646system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1647system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1648system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1631system.iocache.tags.tag_accesses 328113 # Number of tag accesses 1632system.iocache.tags.data_accesses 328113 # Number of data accesses 1633system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1634system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses 1635system.iocache.ReadReq_misses::total 233 # number of ReadReq misses | 1649system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1650system.iocache.tags.data_accesses 327996 # Number of data accesses 1651system.iocache.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1652system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1653system.iocache.ReadReq_misses::total 220 # number of ReadReq misses |
| 1636system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1637system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1654system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1655system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1638system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses 1639system.iocache.demand_misses::total 36457 # number of demand (read+write) misses 1640system.iocache.overall_misses::realview.ide 36457 # number of overall misses 1641system.iocache.overall_misses::total 36457 # number of overall misses 1642system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles 1643system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles 1644system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles 1645system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles 1646system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles 1647system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles 1648system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles 1649system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles 1650system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) 1651system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) | 1656system.iocache.demand_misses::realview.ide 36444 # number of demand (read+write) misses 1657system.iocache.demand_misses::total 36444 # number of demand (read+write) misses 1658system.iocache.overall_misses::realview.ide 36444 # number of overall misses 1659system.iocache.overall_misses::total 36444 # number of overall misses 1660system.iocache.ReadReq_miss_latency::realview.ide 35726876 # number of ReadReq miss cycles 1661system.iocache.ReadReq_miss_latency::total 35726876 # number of ReadReq miss cycles 1662system.iocache.WriteLineReq_miss_latency::realview.ide 4357072746 # number of WriteLineReq miss cycles 1663system.iocache.WriteLineReq_miss_latency::total 4357072746 # number of WriteLineReq miss cycles 1664system.iocache.demand_miss_latency::realview.ide 4392799622 # number of demand (read+write) miss cycles 1665system.iocache.demand_miss_latency::total 4392799622 # number of demand (read+write) miss cycles 1666system.iocache.overall_miss_latency::realview.ide 4392799622 # number of overall miss cycles 1667system.iocache.overall_miss_latency::total 4392799622 # number of overall miss cycles 1668system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1669system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) |
| 1652system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1653system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1670system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1671system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1654system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses 1655system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses 1656system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses 1657system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses | 1672system.iocache.demand_accesses::realview.ide 36444 # number of demand (read+write) accesses 1673system.iocache.demand_accesses::total 36444 # number of demand (read+write) accesses 1674system.iocache.overall_accesses::realview.ide 36444 # number of overall (read+write) accesses 1675system.iocache.overall_accesses::total 36444 # number of overall (read+write) accesses |
| 1658system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1659system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1660system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1661system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1662system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1663system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1664system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1665system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1676system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1677system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1678system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1679system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1680system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1681system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1682system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1683system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1666system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency 1667system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency 1668system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency 1669system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency 1670system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency 1671system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency 1672system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency 1673system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency 1674system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1684system.iocache.ReadReq_avg_miss_latency::realview.ide 162394.890909 # average ReadReq miss latency 1685system.iocache.ReadReq_avg_miss_latency::total 162394.890909 # average ReadReq miss latency 1686system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120281.381018 # average WriteLineReq miss latency 1687system.iocache.WriteLineReq_avg_miss_latency::total 120281.381018 # average WriteLineReq miss latency 1688system.iocache.demand_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency 1689system.iocache.demand_avg_miss_latency::total 120535.605916 # average overall miss latency 1690system.iocache.overall_avg_miss_latency::realview.ide 120535.605916 # average overall miss latency 1691system.iocache.overall_avg_miss_latency::total 120535.605916 # average overall miss latency 1692system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked |
| 1675system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1693system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1676system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1694system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 1677system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1695system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1678system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1696system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked |
| 1679system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1680system.iocache.writebacks::writebacks 36190 # number of writebacks 1681system.iocache.writebacks::total 36190 # number of writebacks | 1697system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1698system.iocache.writebacks::writebacks 36190 # number of writebacks 1699system.iocache.writebacks::total 36190 # number of writebacks |
| 1682system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses 1683system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses | 1700system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1701system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses |
| 1684system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1685system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1702system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1703system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1686system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses 1687system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses 1688system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses 1689system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses 1690system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles 1691system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles 1692system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles 1693system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles 1694system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles 1695system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles 1696system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles 1697system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles | 1704system.iocache.demand_mshr_misses::realview.ide 36444 # number of demand (read+write) MSHR misses 1705system.iocache.demand_mshr_misses::total 36444 # number of demand (read+write) MSHR misses 1706system.iocache.overall_mshr_misses::realview.ide 36444 # number of overall MSHR misses 1707system.iocache.overall_mshr_misses::total 36444 # number of overall MSHR misses 1708system.iocache.ReadReq_mshr_miss_latency::realview.ide 24726876 # number of ReadReq MSHR miss cycles 1709system.iocache.ReadReq_mshr_miss_latency::total 24726876 # number of ReadReq MSHR miss cycles 1710system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2543825241 # number of WriteLineReq MSHR miss cycles 1711system.iocache.WriteLineReq_mshr_miss_latency::total 2543825241 # number of WriteLineReq MSHR miss cycles 1712system.iocache.demand_mshr_miss_latency::realview.ide 2568552117 # number of demand (read+write) MSHR miss cycles 1713system.iocache.demand_mshr_miss_latency::total 2568552117 # number of demand (read+write) MSHR miss cycles 1714system.iocache.overall_mshr_miss_latency::realview.ide 2568552117 # number of overall MSHR miss cycles 1715system.iocache.overall_mshr_miss_latency::total 2568552117 # number of overall MSHR miss cycles |
| 1698system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1699system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1700system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1701system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1702system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1703system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1704system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1705system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1716system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1717system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1718system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1719system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1720system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1721system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1722system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1723system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1706system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency 1707system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency 1708system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency 1709system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency 1710system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency 1711system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency 1712system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency 1713system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency 1714system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. 1715system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1716system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1724system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112394.890909 # average ReadReq mshr miss latency 1725system.iocache.ReadReq_avg_mshr_miss_latency::total 112394.890909 # average ReadReq mshr miss latency 1726system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70224.857581 # average WriteLineReq mshr miss latency 1727system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70224.857581 # average WriteLineReq mshr miss latency 1728system.iocache.demand_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency 1729system.iocache.demand_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency 1730system.iocache.overall_avg_mshr_miss_latency::realview.ide 70479.423691 # average overall mshr miss latency 1731system.iocache.overall_avg_mshr_miss_latency::total 70479.423691 # average overall mshr miss latency 1732system.membus.snoop_filter.tot_requests 339259 # Total number of requests made to the snoop filter. 1733system.membus.snoop_filter.hit_single_requests 139343 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1734system.membus.snoop_filter.hit_multi_requests 469 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1717system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1718system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1719system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1735system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1736system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1737system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1720system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1721system.membus.trans_dist::ReadReq 34130 # Transaction distribution 1722system.membus.trans_dist::ReadResp 68622 # Transaction distribution | 1738system.membus.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1739system.membus.trans_dist::ReadReq 34136 # Transaction distribution 1740system.membus.trans_dist::ReadResp 67481 # Transaction distribution |
| 1723system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1724system.membus.trans_dist::WriteResp 27584 # Transaction distribution | 1741system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1742system.membus.trans_dist::WriteResp 27584 # Transaction distribution |
| 1725system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution 1726system.membus.trans_dist::CleanEvict 8484 # Transaction distribution 1727system.membus.trans_dist::UpgradeReq 130 # Transaction distribution | 1743system.membus.trans_dist::WritebackDirty 126432 # Transaction distribution 1744system.membus.trans_dist::CleanEvict 8077 # Transaction distribution 1745system.membus.trans_dist::UpgradeReq 126 # Transaction distribution |
| 1728system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1729system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1746system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1747system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1730system.membus.trans_dist::ReadExReq 138891 # Transaction distribution 1731system.membus.trans_dist::ReadExResp 138891 # Transaction distribution 1732system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution | 1748system.membus.trans_dist::ReadExReq 134974 # Transaction distribution 1749system.membus.trans_dist::ReadExResp 134974 # Transaction distribution 1750system.membus.trans_dist::ReadSharedReq 33346 # Transaction distribution |
| 1733system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1734system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1735system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1736system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) | 1751system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1752system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1753system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1754system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
| 1737system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) 1738system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) 1739system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) 1740system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) 1741system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) | 1755system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450027 # Packet count per connected master and slave (bytes) 1756system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557589 # Packet count per connected master and slave (bytes) 1757system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72869 # Packet count per connected master and slave (bytes) 1758system.membus.pkt_count_system.iocache.mem_side::total 72869 # Packet count per connected master and slave (bytes) 1759system.membus.pkt_count::total 630458 # Packet count per connected master and slave (bytes) |
| 1742system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1743system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) 1744system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) | 1760system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1761system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) 1762system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
| 1745system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) 1746system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) | 1763system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16583932 # Cumulative packet size per connected master and slave (bytes) 1764system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16747309 # Cumulative packet size per connected master and slave (bytes) |
| 1747system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1748system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1765system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1766system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1749system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) 1750system.membus.snoops 497 # Total snoops (count) 1751system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) 1752system.membus.snoop_fanout::samples 271454 # Request fanout histogram 1753system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram 1754system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram | 1767system.membus.pkt_size::total 19064429 # Cumulative packet size per connected master and slave (bytes) 1768system.membus.snoops 484 # Total snoops (count) 1769system.membus.snoopTraffic 30848 # Total snoop traffic (bytes) 1770system.membus.snoop_fanout::samples 266392 # Request fanout histogram 1771system.membus.snoop_fanout::mean 0.019141 # Request fanout histogram 1772system.membus.snoop_fanout::stdev 0.137021 # Request fanout histogram |
| 1755system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1773system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1756system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram 1757system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram | 1774system.membus.snoop_fanout::0 261293 98.09% 98.09% # Request fanout histogram 1775system.membus.snoop_fanout::1 5099 1.91% 100.00% # Request fanout histogram |
| 1758system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1759system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1760system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1761system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1776system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1777system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1778system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1779system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1762system.membus.snoop_fanout::total 271454 # Request fanout histogram 1763system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) | 1780system.membus.snoop_fanout::total 266392 # Request fanout histogram 1781system.membus.reqLayer0.occupancy 84425500 # Layer occupancy (ticks) |
| 1764system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1765system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1766system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1782system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1783system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1784system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1767system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) | 1785system.membus.reqLayer2.occupancy 1729999 # Layer occupancy (ticks) |
| 1768system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1786system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1769system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) | 1787system.membus.reqLayer5.occupancy 876952960 # Layer occupancy (ticks) |
| 1770system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1788system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1771system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) | 1789system.membus.respLayer2.occupancy 984786250 # Layer occupancy (ticks) |
| 1772system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1790system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1773system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) | 1791system.membus.respLayer3.occupancy 1178374 # Layer occupancy (ticks) |
| 1774system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1792system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1775system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1776system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1777system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1778system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1779system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1780system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1781system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 1793system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1794system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1795system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1796system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1797system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1798system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1799system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 1782system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1783system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1784system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1785system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1786system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1787system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1800system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1801system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1802system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1803system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1804system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1805system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1788system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1789system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 1806system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1807system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 1790system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1791system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1792system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1793system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1794system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1795system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1796system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1797system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1813system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1814system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1815system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1816system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1817system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1818system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1819system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1820system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1808system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1809system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1810system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1811system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1812system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1813system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1814system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1815system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1831system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1832system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1833system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1834system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1835system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1836system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1837system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1838system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1821system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1822system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1823system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1824system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1825system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1826system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1827system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 1839system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1840system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1841system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1842system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1843system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1844system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1845system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 1828system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1829system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1830system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1831system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1846system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1847system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1848system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1849system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1832system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1833system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1834system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1835system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1836system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1837system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1838system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1839system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1840system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1841system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1842system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1843system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states | 1850system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1851system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1852system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1853system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1854system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1855system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1856system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1857system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1858system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1859system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1860system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states 1861system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2829112944500 # Cumulative time (in ticks) in various power states |
| 1844system.cpu.kern.inst.arm 0 # number of arm instructions executed 1845system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed 1846 1847---------- End Simulation Statistics ---------- | 1862system.cpu.kern.inst.arm 0 # number of arm instructions executed 1863system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed 1864 1865---------- End Simulation Statistics ---------- |