| stats.txt (11589:af2f7fef4875) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.832894 # Number of seconds simulated 4sim_ticks 2832894126500 # Number of ticks simulated 5final_tick 2832894126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.827853 # Number of seconds simulated 4sim_ticks 2827853096000 # Number of ticks simulated 5final_tick 2827853096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 136161 # Simulator instruction rate (inst/s) 8host_op_rate 165152 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3410188815 # Simulator tick rate (ticks/s) 10host_mem_usage 579068 # Number of bytes of host memory used 11host_seconds 830.71 # Real time elapsed on the host 12sim_insts 113111333 # Number of instructions simulated 13sim_ops 137193850 # Number of ops (including micro ops) simulated | 7host_inst_rate 94322 # Simulator instruction rate (inst/s) 8host_op_rate 114411 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2357194570 # Simulator tick rate (ticks/s) 10host_mem_usage 589152 # Number of bytes of host memory used 11host_seconds 1199.67 # Real time elapsed on the host 12sim_insts 113155640 # Number of instructions simulated 13sim_ops 137255479 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1321536 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9400296 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1322240 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9790440 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 22system.physmem.bytes_read::total 10724584 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1321536 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1321536 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8031104 # Number of bytes written to this memory | 22system.physmem.bytes_read::total 11115048 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1322240 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1322240 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8407168 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 27system.physmem.bytes_written::total 8048628 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22896 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 147400 # Number of read requests responded to by this memory | 27system.physmem.bytes_written::total 8424692 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22907 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 153496 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 170339 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 125486 # Number of write requests responded to by this memory | 33system.physmem.num_reads::total 176440 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 131362 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::total 129867 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 466497 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3318266 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.num_writes::total 135743 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 362 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 467577 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3462146 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::total 3785734 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 466497 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 466497 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2834947 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2841133 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2834947 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 466497 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3324452 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_read::total 3930561 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 467577 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 467577 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2972986 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2979183 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2972986 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 362 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 467577 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3468343 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) | 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) |
| 54system.physmem.bw_total::total 6626867 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170340 # Number of read requests accepted 56system.physmem.writeReqs 129867 # Number of write requests accepted 57system.physmem.readBursts 170340 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 129867 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10892352 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8061056 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10724648 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8048628 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one | 54system.physmem.bw_total::total 6909744 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 176441 # Number of read requests accepted 56system.physmem.writeReqs 135743 # Number of write requests accepted 57system.physmem.readBursts 176441 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 135743 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 11282432 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8437824 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 11115112 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8424692 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one |
| 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 67system.physmem.perBankRdBursts::0 11036 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10507 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10862 # Per bank write bursts 70system.physmem.perBankRdBursts::3 11068 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13101 # Per bank write bursts 72system.physmem.perBankRdBursts::5 10327 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10639 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10985 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10460 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10167 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10435 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9511 # Per bank write bursts 79system.physmem.perBankRdBursts::12 9930 # Per bank write bursts 80system.physmem.perBankRdBursts::13 10756 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10401 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10008 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8291 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7865 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8399 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8558 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7751 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7713 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7781 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8111 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7871 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7662 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7844 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7196 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7582 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8119 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7846 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7365 # Per bank write bursts | 67system.physmem.perBankRdBursts::0 11743 # Per bank write bursts 68system.physmem.perBankRdBursts::1 11227 # Per bank write bursts 69system.physmem.perBankRdBursts::2 11041 # Per bank write bursts 70system.physmem.perBankRdBursts::3 10652 # Per bank write bursts 71system.physmem.perBankRdBursts::4 13485 # Per bank write bursts 72system.physmem.perBankRdBursts::5 11002 # Per bank write bursts 73system.physmem.perBankRdBursts::6 11432 # Per bank write bursts 74system.physmem.perBankRdBursts::7 11844 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10383 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10947 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10471 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9569 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10361 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11110 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10361 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10660 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8764 # Per bank write bursts 84system.physmem.perBankWrBursts::1 8604 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8676 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8310 # Per bank write bursts 87system.physmem.perBankWrBursts::4 8074 # Per bank write bursts 88system.physmem.perBankWrBursts::5 8230 # Per bank write bursts 89system.physmem.perBankWrBursts::6 8228 # Per bank write bursts 90system.physmem.perBankWrBursts::7 8800 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7938 # Per bank write bursts 92system.physmem.perBankWrBursts::9 8472 # Per bank write bursts 93system.physmem.perBankWrBursts::10 8080 # Per bank write bursts 94system.physmem.perBankWrBursts::11 7388 # Per bank write bursts 95system.physmem.perBankWrBursts::12 8035 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8487 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7854 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7901 # Per bank write bursts |
| 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 100system.physmem.numWrRetry 17 # Number of times write queue was full causing retry 101system.physmem.totGap 2832893894500 # Total gap between requests | 100system.physmem.numWrRetry 4 # Number of times write queue was full causing retry 101system.physmem.totGap 2827852861000 # Total gap between requests |
| 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 2996 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) | 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 2996 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 108system.physmem.readPktSize::6 166788 # Read request sizes (log2) | 108system.physmem.readPktSize::6 172889 # Read request sizes (log2) |
| 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) | 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 115system.physmem.writePktSize::6 125486 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 150867 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 16439 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see | 115system.physmem.writePktSize::6 131362 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 155219 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 17999 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 2225 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 829 # What read queue length does an incoming req see |
| 120system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::15 1883 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6675 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6069 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 7147 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6554 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6489 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6585 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7283 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 7048 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7591 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8460 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7511 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7926 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8975 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7507 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7208 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1140 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 304 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 257 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 130 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 79 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 55 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 81 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 48 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 79 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 62108 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 305.167515 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 180.813202 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 324.494619 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 23016 37.06% 37.06% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 15104 24.32% 61.38% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6524 10.50% 71.88% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3665 5.90% 77.78% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2528 4.07% 81.85% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1637 2.64% 84.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1479 2.38% 86.87% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1102 1.77% 88.64% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7053 11.36% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 62108 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.706936 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 569.623530 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.507001 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.506831 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 14.607971 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5435 88.49% 88.49% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 129 2.10% 90.59% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 31 0.50% 91.09% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 49 0.80% 91.89% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 32 0.52% 92.41% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 17 0.28% 92.69% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 48 0.78% 93.47% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 14 0.23% 93.70% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 140 2.28% 95.98% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 11 0.18% 96.16% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 8 0.13% 96.29% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 8 0.13% 96.42% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 65 1.06% 97.48% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 1 0.02% 97.49% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 21 0.34% 97.83% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 93 1.51% 99.35% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 3 0.05% 99.40% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::88-91 1 0.02% 99.41% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::92-95 1 0.02% 99.43% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.45% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 2 0.03% 99.48% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::112-115 3 0.05% 99.53% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.54% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 11 0.18% 99.72% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::132-135 1 0.02% 99.74% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::136-139 1 0.02% 99.76% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::148-151 1 0.02% 99.92% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 1 0.02% 99.93% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::176-179 2 0.03% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::208-211 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads 270system.physmem.totQLat 2108320500 # Total ticks spent queuing 271system.physmem.totMemAccLat 5299439250 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 850965000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 12387.82 # Average queueing delay per DRAM burst | 163system.physmem.wrQLenPdf::15 2095 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2964 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 5951 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6509 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 6942 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6801 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 7294 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 7733 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 8218 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 8271 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 9582 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 9943 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 8295 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 8200 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8031 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7326 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7196 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7152 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 364 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 327 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 266 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 134 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 125 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 139 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 130 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 109 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 104 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 98 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 70 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 57 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 31 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 10 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 64990 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 303.434251 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 179.571710 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 325.070143 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 24166 37.18% 37.18% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 15993 24.61% 61.79% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6821 10.50% 72.29% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3792 5.83% 78.12% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2758 4.24% 82.37% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1633 2.51% 84.88% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1086 1.67% 86.55% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1085 1.67% 88.22% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7656 11.78% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 64990 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6662 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 26.461423 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 559.657587 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6661 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6662 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6662 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 19.790003 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.288798 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 12.351415 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5875 88.19% 88.19% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 70 1.05% 89.24% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 75 1.13% 90.36% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 36 0.54% 90.90% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 259 3.89% 94.79% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 62 0.93% 95.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 25 0.38% 96.10% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 19 0.29% 96.38% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 9 0.14% 96.52% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 7 0.11% 96.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 3 0.05% 96.67% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 4 0.06% 96.73% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 160 2.40% 99.13% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 6 0.09% 99.22% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 8 0.12% 99.34% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 2 0.03% 99.37% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.47% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 10 0.15% 99.70% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 1 0.02% 99.71% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.02% 99.73% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 8 0.12% 99.85% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::144-147 1 0.02% 99.88% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::156-159 1 0.02% 99.89% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::160-163 1 0.02% 99.91% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::168-171 2 0.03% 99.94% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 6662 # Writes before turning the bus around for reads 270system.physmem.totQLat 2116192000 # Total ticks spent queuing 271system.physmem.totMemAccLat 5421592000 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 881440000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 12004.17 # Average queueing delay per DRAM burst |
| 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 275system.physmem.avgMemAccLat 31137.82 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.79 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s | 275system.physmem.avgMemAccLat 30754.17 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.93 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s |
| 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.05 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing | 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.05 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing |
| 285system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing 286system.physmem.readRowHits 139937 # Number of row buffer hits during reads 287system.physmem.writeRowHits 94101 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes 290system.physmem.avgGap 9436468.49 # Average gap between requests 291system.physmem.pageHitRate 79.02 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 243454680 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 132837375 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 690495000 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 417759120 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 83647548450 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1626357251250 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1896519747795 # Total energy per rank (pJ) 300system.physmem_0.averagePower 669.465335 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 2705450093000 # Time in different power states 302system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states | 285system.physmem.avgWrQLen 23.03 # Average write queue length when enqueuing 286system.physmem.readRowHits 145153 # Number of row buffer hits during reads 287system.physmem.writeRowHits 97985 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 74.31 # Row buffer hit rate for writes 290system.physmem.avgGap 9058288.90 # Average gap between requests 291system.physmem.pageHitRate 78.90 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 256087440 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 139730250 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 720922800 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 438605280 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 81077227785 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 1625589296250 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 1892923233405 # Total energy per rank (pJ) 300system.physmem_0.averagePower 669.386141 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 2704185411500 # Time in different power states 302system.physmem_0.memoryStateTime::REF 94428100000 # Time in different power states |
| 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 304system.physmem_0.memoryStateTime::ACT 32840757000 # Time in different power states | 304system.physmem_0.memoryStateTime::ACT 29235954750 # Time in different power states |
| 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 306system.physmem_1.actEnergy 226081800 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 123358125 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 637002600 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 398422800 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 82216233135 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1627612791000 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1896244291380 # Total energy per rank (pJ) 314system.physmem_1.averagePower 669.368099 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 2707556632500 # Time in different power states 316system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states | 306system.physmem_1.actEnergy 235236960 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 128353500 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 654115800 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 415724400 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 184701363600 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 80292349755 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 1626277785750 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 1892704929765 # Total energy per rank (pJ) 314system.physmem_1.averagePower 669.308944 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 2705344853000 # Time in different power states 316system.physmem_1.memoryStateTime::REF 94428100000 # Time in different power states |
| 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 318system.physmem_1.memoryStateTime::ACT 30741160500 # Time in different power states | 318system.physmem_1.memoryStateTime::ACT 28080129500 # Time in different power states |
| 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 320system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 320system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 321system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 327system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) | 321system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 327system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 332system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) |
| 333system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 334system.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 335system.bridge.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 333system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 334system.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 335system.bridge.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 336system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 336system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 342system.cpu.branchPred.lookups 46812529 # Number of BP lookups 343system.cpu.branchPred.condPredicted 23980713 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 1174980 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 29461889 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 13525990 # Number of BTB hits | 342system.cpu.branchPred.lookups 46859222 # Number of BP lookups 343system.cpu.branchPred.condPredicted 23995015 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 1174256 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 29489294 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 13535968 # Number of BTB hits |
| 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 348system.cpu.branchPred.BTBHitPct 45.910125 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 11726513 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 34925 # Number of incorrect RAS predictions. 351system.cpu.branchPred.indirectLookups 7916092 # Number of indirect predictor lookups. 352system.cpu.branchPred.indirectHits 7770128 # Number of indirect target hits. 353system.cpu.branchPred.indirectMisses 145964 # Number of indirect misses. 354system.cpu.branchPredindirectMispredicted 60126 # Number of mispredicted indirect branches. | 348system.cpu.branchPred.BTBHitPct 45.901296 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 11745095 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 35189 # Number of incorrect RAS predictions. 351system.cpu.branchPred.indirectLookups 7931554 # Number of indirect predictor lookups. 352system.cpu.branchPred.indirectHits 7786304 # Number of indirect target hits. 353system.cpu.branchPred.indirectMisses 145250 # Number of indirect misses. 354system.cpu.branchPredindirectMispredicted 60170 # Number of mispredicted indirect branches. |
| 355system.cpu_clk_domain.clock 500 # Clock period in ticks | 355system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 356system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 356system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 386system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 387system.cpu.dtb.walker.walks 72186 # Table walker walks requested 388system.cpu.dtb.walker.walksShort 72186 # Table walker walks initiated with short descriptors 389system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29334 # Level at which table walker walks with short descriptors terminate 390system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23181 # Level at which table walker walks with short descriptors terminate 391system.cpu.dtb.walker.walksSquashedBefore 19671 # Table walks squashed before starting 392system.cpu.dtb.walker.walkWaitTime::samples 52515 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::mean 467.713986 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::stdev 2821.743931 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::0-8191 51203 97.50% 97.50% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::8192-16383 905 1.72% 99.22% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::16384-24575 322 0.61% 99.84% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::24576-32767 40 0.08% 99.91% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::32768-40959 18 0.03% 99.95% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency | 386system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 387system.cpu.dtb.walker.walks 72426 # Table walker walks requested 388system.cpu.dtb.walker.walksShort 72426 # Table walker walks initiated with short descriptors 389system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29716 # Level at which table walker walks with short descriptors terminate 390system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23400 # Level at which table walker walks with short descriptors terminate 391system.cpu.dtb.walker.walksSquashedBefore 19310 # Table walks squashed before starting 392system.cpu.dtb.walker.walkWaitTime::samples 53116 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::mean 407.485503 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::stdev 2469.018740 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::0-8191 51917 97.74% 97.74% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::8192-16383 937 1.76% 99.51% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::16384-24575 190 0.36% 99.86% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::24576-32767 37 0.07% 99.93% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::32768-40959 15 0.03% 99.96% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 403system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 403system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 404system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::total 52515 # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkCompletionTime::samples 17658 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::mean 12583.333333 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::gmean 10066.135653 # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::stdev 8522.119991 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::0-32767 17438 98.75% 98.75% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::32768-65535 214 1.21% 99.97% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::total 17658 # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walksPending::samples 131358619316 # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::mean 0.629965 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::stdev 0.490082 # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::0-1 131298865316 99.95% 99.95% # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::2-3 40695500 0.03% 99.99% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::4-5 8747000 0.01% 99.99% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::6-7 6751500 0.01% 100.00% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::8-9 1053500 0.00% 100.00% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::10-11 584000 0.00% 100.00% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::12-13 1412000 0.00% 100.00% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution | 404system.cpu.dtb.walker.walkWaitTime::total 53116 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 17396 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 9637.387905 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 7803.906851 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 6813.601039 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-16383 15561 89.45% 89.45% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::16384-32767 1740 10.00% 99.45% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::32768-49151 86 0.49% 99.95% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::49152-65535 2 0.01% 99.96% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::245760-262143 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::total 17396 # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walksPending::samples 117727604724 # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::mean 0.629848 # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::stdev 0.489627 # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::0-1 117677681224 99.96% 99.96% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::2-3 34838500 0.03% 99.99% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::4-5 7318000 0.01% 99.99% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::6-7 4585500 0.00% 100.00% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::8-9 935500 0.00% 100.00% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::10-11 533500 0.00% 100.00% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::12-13 1306000 0.00% 100.00% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::14-15 397000 0.00% 100.00% # Table walker pending requests distribution |
| 428system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution | 429system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution |
| 429system.cpu.dtb.walker.walksPending::total 131358619316 # Table walker pending requests distribution 430system.cpu.dtb.walker.walkPageSizes::4K 6349 82.25% 82.25% # Table walker page sizes translated 431system.cpu.dtb.walker.walkPageSizes::1M 1370 17.75% 100.00% # Table walker page sizes translated 432system.cpu.dtb.walker.walkPageSizes::total 7719 # Table walker page sizes translated 433system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72186 # Table walker requests started/completed, data/inst | 430system.cpu.dtb.walker.walksPending::total 117727604724 # Table walker pending requests distribution 431system.cpu.dtb.walker.walkPageSizes::4K 6471 81.85% 81.85% # Table walker page sizes translated 432system.cpu.dtb.walker.walkPageSizes::1M 1435 18.15% 100.00% # Table walker page sizes translated 433system.cpu.dtb.walker.walkPageSizes::total 7906 # Table walker page sizes translated 434system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72426 # Table walker requests started/completed, data/inst |
| 434system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 435system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 435system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72186 # Table walker requests started/completed, data/inst 436system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7719 # Table walker requests started/completed, data/inst | 436system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72426 # Table walker requests started/completed, data/inst 437system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7906 # Table walker requests started/completed, data/inst |
| 437system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 438system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 438system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7719 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin::total 79905 # Table walker requests started/completed, data/inst | 439system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7906 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin::total 80332 # Table walker requests started/completed, data/inst |
| 440system.cpu.dtb.inst_hits 0 # ITB inst hits 441system.cpu.dtb.inst_misses 0 # ITB inst misses | 441system.cpu.dtb.inst_hits 0 # ITB inst hits 442system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 442system.cpu.dtb.read_hits 25413003 # DTB read hits 443system.cpu.dtb.read_misses 62542 # DTB read misses 444system.cpu.dtb.write_hits 19866296 # DTB write hits 445system.cpu.dtb.write_misses 9644 # DTB write misses | 443system.cpu.dtb.read_hits 25423365 # DTB read hits 444system.cpu.dtb.read_misses 62664 # DTB read misses 445system.cpu.dtb.write_hits 19868926 # DTB write hits 446system.cpu.dtb.write_misses 9762 # DTB write misses |
| 446system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 447system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 448system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 449system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 447system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 448system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 449system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 450system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 450system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB 451system.cpu.dtb.align_faults 366 # Number of TLB faults due to alignment restrictions 452system.cpu.dtb.prefetch_faults 2075 # Number of TLB faults due to prefetch | 451system.cpu.dtb.flush_entries 4289 # Number of entries that have been flushed from TLB 452system.cpu.dtb.align_faults 358 # Number of TLB faults due to alignment restrictions 453system.cpu.dtb.prefetch_faults 2236 # Number of TLB faults due to prefetch |
| 453system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 454system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 454system.cpu.dtb.perms_faults 1321 # Number of TLB faults due to permissions restrictions 455system.cpu.dtb.read_accesses 25475545 # DTB read accesses 456system.cpu.dtb.write_accesses 19875940 # DTB write accesses | 455system.cpu.dtb.perms_faults 1258 # Number of TLB faults due to permissions restrictions 456system.cpu.dtb.read_accesses 25486029 # DTB read accesses 457system.cpu.dtb.write_accesses 19878688 # DTB write accesses |
| 457system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 458system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 458system.cpu.dtb.hits 45279299 # DTB hits 459system.cpu.dtb.misses 72186 # DTB misses 460system.cpu.dtb.accesses 45351485 # DTB accesses 461system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 459system.cpu.dtb.hits 45292291 # DTB hits 460system.cpu.dtb.misses 72426 # DTB misses 461system.cpu.dtb.accesses 45364717 # DTB accesses 462system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 462system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 483system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 484system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 485system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 486system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 487system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 488system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 489system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 490system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 463system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 484system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 486system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 487system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 488system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 489system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 490system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 491system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 491system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 492system.cpu.itb.walker.walks 12817 # Table walker walks requested 493system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors 494system.cpu.itb.walker.walksShortTerminationLevel::Level1 3407 # Level at which table walker walks with short descriptors terminate 495system.cpu.itb.walker.walksShortTerminationLevel::Level2 7692 # Level at which table walker walks with short descriptors terminate 496system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting 497system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::mean 742.229030 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::stdev 3116.397220 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::0-4095 10521 94.79% 94.79% # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::4096-8191 119 1.07% 95.86% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::8192-12287 227 2.05% 97.91% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.02% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::16384-20479 47 0.42% 99.44% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.86% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.95% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 512system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 513system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency 514system.cpu.itb.walker.walkCompletionTime::samples 5040 # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::mean 12026.488095 # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::gmean 9684.197840 # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::stdev 7608.176186 # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::0-16383 4071 80.77% 80.77% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::16384-32767 955 18.95% 99.72% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::32768-49151 11 0.22% 99.94% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walkCompletionTime::total 5040 # Table walker service (enqueue to completion) latency 524system.cpu.itb.walker.walksPending::samples 23984374916 # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::mean 0.642154 # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::stdev 0.479545 # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::0 8584682500 35.79% 35.79% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::1 15397812416 64.20% 99.99% # Table walker pending requests distribution 529system.cpu.itb.walker.walksPending::2 1792000 0.01% 100.00% # Table walker pending requests distribution 530system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution 531system.cpu.itb.walker.walksPending::total 23984374916 # Table walker pending requests distribution 532system.cpu.itb.walker.walkPageSizes::4K 2987 89.92% 89.92% # Table walker page sizes translated 533system.cpu.itb.walker.walkPageSizes::1M 335 10.08% 100.00% # Table walker page sizes translated 534system.cpu.itb.walker.walkPageSizes::total 3322 # Table walker page sizes translated | 492system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 493system.cpu.itb.walker.walks 12855 # Table walker walks requested 494system.cpu.itb.walker.walksShort 12855 # Table walker walks initiated with short descriptors 495system.cpu.itb.walker.walksShortTerminationLevel::Level1 3590 # Level at which table walker walks with short descriptors terminate 496system.cpu.itb.walker.walksShortTerminationLevel::Level2 7693 # Level at which table walker walks with short descriptors terminate 497system.cpu.itb.walker.walksSquashedBefore 1572 # Table walks squashed before starting 498system.cpu.itb.walker.walkWaitTime::samples 11283 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::mean 605.778605 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::stdev 2805.757421 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::0-8191 10907 96.67% 96.67% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::8192-16383 327 2.90% 99.57% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::16384-24575 40 0.35% 99.92% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::24576-32767 5 0.04% 99.96% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::81920-90111 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::total 11283 # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkCompletionTime::samples 4887 # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::mean 8961.019030 # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::gmean 7007.167188 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::stdev 7172.888707 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::0-8191 3327 68.08% 68.08% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::8192-16383 829 16.96% 85.04% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::16384-24575 682 13.96% 99.00% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::24576-32767 38 0.78% 99.77% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::32768-40959 1 0.02% 99.80% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::40960-49151 7 0.14% 99.94% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::49152-57343 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::total 4887 # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walksPending::samples 23237381212 # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::mean 0.774797 # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::stdev 0.417824 # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::0 5234024500 22.52% 22.52% # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::1 18002578212 77.47% 100.00% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::2 696500 0.00% 100.00% # Table walker pending requests distribution 529system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution 530system.cpu.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution 531system.cpu.itb.walker.walksPending::total 23237381212 # Table walker pending requests distribution 532system.cpu.itb.walker.walkPageSizes::4K 2980 89.89% 89.89% # Table walker page sizes translated 533system.cpu.itb.walker.walkPageSizes::1M 335 10.11% 100.00% # Table walker page sizes translated 534system.cpu.itb.walker.walkPageSizes::total 3315 # Table walker page sizes translated |
| 535system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 535system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 536system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst 537system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst | 536system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12855 # Table walker requests started/completed, data/inst 537system.cpu.itb.walker.walkRequestOrigin_Requested::total 12855 # Table walker requests started/completed, data/inst |
| 538system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 538system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 539system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3322 # Table walker requests started/completed, data/inst 540system.cpu.itb.walker.walkRequestOrigin_Completed::total 3322 # Table walker requests started/completed, data/inst 541system.cpu.itb.walker.walkRequestOrigin::total 16139 # Table walker requests started/completed, data/inst 542system.cpu.itb.inst_hits 65982481 # ITB inst hits 543system.cpu.itb.inst_misses 12817 # ITB inst misses | 539system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3315 # Table walker requests started/completed, data/inst 540system.cpu.itb.walker.walkRequestOrigin_Completed::total 3315 # Table walker requests started/completed, data/inst 541system.cpu.itb.walker.walkRequestOrigin::total 16170 # Table walker requests started/completed, data/inst 542system.cpu.itb.inst_hits 66060204 # ITB inst hits 543system.cpu.itb.inst_misses 12855 # ITB inst misses |
| 544system.cpu.itb.read_hits 0 # DTB read hits 545system.cpu.itb.read_misses 0 # DTB read misses 546system.cpu.itb.write_hits 0 # DTB write hits 547system.cpu.itb.write_misses 0 # DTB write misses 548system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 549system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 550system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 551system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 544system.cpu.itb.read_hits 0 # DTB read hits 545system.cpu.itb.read_misses 0 # DTB read misses 546system.cpu.itb.write_hits 0 # DTB write hits 547system.cpu.itb.write_misses 0 # DTB write misses 548system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 549system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 550system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 551system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 552system.cpu.itb.flush_entries 3021 # Number of entries that have been flushed from TLB | 552system.cpu.itb.flush_entries 3013 # Number of entries that have been flushed from TLB |
| 553system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 554system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 555system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 553system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 554system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 555system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 556system.cpu.itb.perms_faults 2147 # Number of TLB faults due to permissions restrictions | 556system.cpu.itb.perms_faults 2175 # Number of TLB faults due to permissions restrictions |
| 557system.cpu.itb.read_accesses 0 # DTB read accesses 558system.cpu.itb.write_accesses 0 # DTB write accesses | 557system.cpu.itb.read_accesses 0 # DTB read accesses 558system.cpu.itb.write_accesses 0 # DTB write accesses |
| 559system.cpu.itb.inst_accesses 65995298 # ITB inst accesses 560system.cpu.itb.hits 65982481 # DTB hits 561system.cpu.itb.misses 12817 # DTB misses 562system.cpu.itb.accesses 65995298 # DTB accesses 563system.cpu.numPwrStateTransitions 6074 # Number of power state transitions 564system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::mean 886948130.312150 # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::stdev 17421700028.084686 # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state | 559system.cpu.itb.inst_accesses 66073059 # ITB inst accesses 560system.cpu.itb.hits 66060204 # DTB hits 561system.cpu.itb.misses 12855 # DTB misses 562system.cpu.itb.accesses 66073059 # DTB accesses 563system.cpu.numPwrStateTransitions 6076 # Number of power state transitions 564system.cpu.pwrStateClkGateDist::samples 3038 # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::mean 887319797.866359 # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::stdev 17420812025.908409 # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::underflows 2966 97.63% 97.63% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::1000-5e+10 66 2.17% 99.80% # Distribution of time spent in the clock gated state |
| 569system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state | 569system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state |
| 570system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state | 570system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state |
| 571system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 572system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state | 572system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 573system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state |
| 573system.cpu.pwrStateClkGateDist::max_value 499972891000 # Distribution of time spent in the clock gated state 574system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state 575system.cpu.pwrStateResidencyTicks::ON 139232654742 # Cumulative time (in ticks) in various power states 576system.cpu.pwrStateResidencyTicks::CLK_GATED 2693661471758 # Cumulative time (in ticks) in various power states 577system.cpu.numCycles 278465363 # number of cpu cycles simulated | 574system.cpu.pwrStateClkGateDist::max_value 499973328096 # Distribution of time spent in the clock gated state 575system.cpu.pwrStateClkGateDist::total 3038 # Distribution of time spent in the clock gated state 576system.cpu.pwrStateResidencyTicks::ON 132175550082 # Cumulative time (in ticks) in various power states 577system.cpu.pwrStateResidencyTicks::CLK_GATED 2695677545918 # Cumulative time (in ticks) in various power states 578system.cpu.numCycles 264351157 # number of cpu cycles simulated |
| 578system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 579system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 579system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 580system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 580system.cpu.fetch.icacheStallCycles 104979858 # Number of cycles fetch is stalled on an Icache miss 581system.cpu.fetch.Insts 184015649 # Number of instructions fetch has processed 582system.cpu.fetch.Branches 46812529 # Number of branches that fetch encountered 583system.cpu.fetch.predictedBranches 33022631 # Number of branches that fetch has predicted taken 584system.cpu.fetch.Cycles 161497089 # Number of cycles fetch has run and was not squashing or blocked 585system.cpu.fetch.SquashCycles 6057652 # Number of cycles fetch has spent squashing 586system.cpu.fetch.TlbCycles 189263 # Number of cycles fetch has spent waiting for tlb 587system.cpu.fetch.MiscStallCycles 8972 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 588system.cpu.fetch.PendingTrapStallCycles 337056 # Number of stall cycles due to pending traps 589system.cpu.fetch.PendingQuiesceStallCycles 558097 # Number of stall cycles due to pending quiesce instructions 590system.cpu.fetch.IcacheWaitRetryStallCycles 172 # Number of stall cycles due to full MSHR 591system.cpu.fetch.CacheLines 65981271 # Number of cache lines fetched 592system.cpu.fetch.IcacheSquashes 1027864 # Number of outstanding Icache misses that were squashed 593system.cpu.fetch.ItlbSquashes 6246 # Number of outstanding ITLB misses that were squashed 594system.cpu.fetch.rateDist::samples 270599333 # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::mean 0.829251 # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::stdev 1.216918 # Number of instructions fetched each cycle (Total) | 581system.cpu.fetch.icacheStallCycles 105007140 # Number of cycles fetch is stalled on an Icache miss 582system.cpu.fetch.Insts 184198118 # Number of instructions fetch has processed 583system.cpu.fetch.Branches 46859222 # Number of branches that fetch encountered 584system.cpu.fetch.predictedBranches 33067367 # Number of branches that fetch has predicted taken 585system.cpu.fetch.Cycles 149125653 # Number of cycles fetch has run and was not squashing or blocked 586system.cpu.fetch.SquashCycles 6062128 # Number of cycles fetch has spent squashing 587system.cpu.fetch.TlbCycles 177509 # Number of cycles fetch has spent waiting for tlb 588system.cpu.fetch.MiscStallCycles 8064 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 589system.cpu.fetch.PendingTrapStallCycles 342285 # Number of stall cycles due to pending traps 590system.cpu.fetch.PendingQuiesceStallCycles 500656 # Number of stall cycles due to pending quiesce instructions 591system.cpu.fetch.IcacheWaitRetryStallCycles 149 # Number of stall cycles due to full MSHR 592system.cpu.fetch.CacheLines 66059105 # Number of cache lines fetched 593system.cpu.fetch.IcacheSquashes 1061874 # Number of outstanding Icache misses that were squashed 594system.cpu.fetch.ItlbSquashes 6140 # Number of outstanding ITLB misses that were squashed 595system.cpu.fetch.rateDist::samples 258192520 # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::mean 0.869926 # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::stdev 1.232240 # Number of instructions fetched each cycle (Total) |
| 597system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 598system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 598system.cpu.fetch.rateDist::0 171686790 63.45% 63.45% # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::1 29154260 10.77% 74.22% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::2 14034299 5.19% 79.41% # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::3 55723984 20.59% 100.00% # Number of instructions fetched each cycle (Total) | 599system.cpu.fetch.rateDist::0 159207105 61.66% 61.66% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::1 29153243 11.29% 72.95% # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::2 14041371 5.44% 78.39% # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::3 55790801 21.61% 100.00% # Number of instructions fetched each cycle (Total) |
| 602system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 603system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 604system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 605system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 605system.cpu.fetch.rateDist::total 270599333 # Number of instructions fetched each cycle (Total) 606system.cpu.fetch.branchRate 0.168109 # Number of branch fetches per cycle 607system.cpu.fetch.rate 0.660821 # Number of inst fetches per cycle 608system.cpu.decode.IdleCycles 77964907 # Number of cycles decode is idle 609system.cpu.decode.BlockedCycles 121895477 # Number of cycles decode is blocked 610system.cpu.decode.RunCycles 64303176 # Number of cycles decode is running 611system.cpu.decode.UnblockCycles 3866825 # Number of cycles decode is unblocking 612system.cpu.decode.SquashCycles 2568948 # Number of cycles decode is squashing 613system.cpu.decode.BranchResolved 3406986 # Number of times decode resolved a branch 614system.cpu.decode.BranchMispred 467982 # Number of times decode detected a branch misprediction 615system.cpu.decode.DecodedInsts 156982730 # Number of instructions handled by decode 616system.cpu.decode.SquashedInsts 3511045 # Number of squashed instructions handled by decode 617system.cpu.rename.SquashCycles 2568948 # Number of cycles rename is squashing 618system.cpu.rename.IdleCycles 83721940 # Number of cycles rename is idle 619system.cpu.rename.BlockCycles 11815597 # Number of cycles rename is blocking 620system.cpu.rename.serializeStallCycles 76560081 # count of cycles rename stalled for serializing inst 621system.cpu.rename.RunCycles 62413108 # Number of cycles rename is running 622system.cpu.rename.UnblockCycles 33519659 # Number of cycles rename is unblocking 623system.cpu.rename.RenamedInsts 146432544 # Number of instructions processed by rename 624system.cpu.rename.SquashedInsts 918349 # Number of squashed instructions processed by rename 625system.cpu.rename.ROBFullEvents 465966 # Number of times rename has blocked due to ROB full 626system.cpu.rename.IQFullEvents 65322 # Number of times rename has blocked due to IQ full 627system.cpu.rename.LQFullEvents 18586 # Number of times rename has blocked due to LQ full 628system.cpu.rename.SQFullEvents 30762818 # Number of times rename has blocked due to SQ full 629system.cpu.rename.RenamedOperands 150226924 # Number of destination operands rename has renamed 630system.cpu.rename.RenameLookups 676971311 # Number of register rename lookups that rename has made 631system.cpu.rename.int_rename_lookups 163962292 # Number of integer rename lookups 632system.cpu.rename.fp_rename_lookups 10893 # Number of floating rename lookups 633system.cpu.rename.CommittedMaps 141750491 # Number of HB maps that are committed 634system.cpu.rename.UndoneMaps 8476427 # Number of HB maps that are undone due to squashing 635system.cpu.rename.serializingInsts 2839737 # count of serializing insts renamed 636system.cpu.rename.tempSerializingInsts 2644396 # count of temporary serializing insts renamed 637system.cpu.rename.skidInsts 13885386 # count of insts added to the skid buffer 638system.cpu.memDep0.insertedLoads 26339908 # Number of loads inserted to the mem dependence unit. 639system.cpu.memDep0.insertedStores 21214343 # Number of stores inserted to the mem dependence unit. 640system.cpu.memDep0.conflictingLoads 1703941 # Number of conflicting loads. 641system.cpu.memDep0.conflictingStores 2126584 # Number of conflicting stores. 642system.cpu.iq.iqInstsAdded 143224778 # Number of instructions added to the IQ (excludes non-spec) 643system.cpu.iq.iqNonSpecInstsAdded 2118002 # Number of non-speculative instructions added to the IQ 644system.cpu.iq.iqInstsIssued 143047064 # Number of instructions issued 645system.cpu.iq.iqSquashedInstsIssued 260478 # Number of squashed instructions issued 646system.cpu.iq.iqSquashedInstsExamined 8148926 # Number of squashed instructions iterated over during squash; mainly for profiling 647system.cpu.iq.iqSquashedOperandsExamined 14278560 # Number of squashed operands that are examined and possibly removed from graph 648system.cpu.iq.iqSquashedNonSpecRemoved 121950 # Number of squashed non-spec instructions that were removed 649system.cpu.iq.issued_per_cycle::samples 270599333 # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::mean 0.528631 # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::stdev 0.865147 # Number of insts issued each cycle | 606system.cpu.fetch.rateDist::total 258192520 # Number of instructions fetched each cycle (Total) 607system.cpu.fetch.branchRate 0.177261 # Number of branch fetches per cycle 608system.cpu.fetch.rate 0.696793 # Number of inst fetches per cycle 609system.cpu.decode.IdleCycles 78121728 # Number of cycles decode is idle 610system.cpu.decode.BlockedCycles 109293057 # Number of cycles decode is blocked 611system.cpu.decode.RunCycles 64347286 # Number of cycles decode is running 612system.cpu.decode.UnblockCycles 3858820 # Number of cycles decode is unblocking 613system.cpu.decode.SquashCycles 2571629 # Number of cycles decode is squashing 614system.cpu.decode.BranchResolved 3404933 # Number of times decode resolved a branch 615system.cpu.decode.BranchMispred 467397 # Number of times decode detected a branch misprediction 616system.cpu.decode.DecodedInsts 157054266 # Number of instructions handled by decode 617system.cpu.decode.SquashedInsts 3508469 # Number of squashed instructions handled by decode 618system.cpu.rename.SquashCycles 2571629 # Number of cycles rename is squashing 619system.cpu.rename.IdleCycles 83876272 # Number of cycles rename is idle 620system.cpu.rename.BlockCycles 10707182 # Number of cycles rename is blocking 621system.cpu.rename.serializeStallCycles 75777880 # count of cycles rename stalled for serializing inst 622system.cpu.rename.RunCycles 62454434 # Number of cycles rename is running 623system.cpu.rename.UnblockCycles 22805123 # Number of cycles rename is unblocking 624system.cpu.rename.RenamedInsts 146493829 # Number of instructions processed by rename 625system.cpu.rename.SquashedInsts 914752 # Number of squashed instructions processed by rename 626system.cpu.rename.ROBFullEvents 447933 # Number of times rename has blocked due to ROB full 627system.cpu.rename.IQFullEvents 65579 # Number of times rename has blocked due to IQ full 628system.cpu.rename.LQFullEvents 19295 # Number of times rename has blocked due to LQ full 629system.cpu.rename.SQFullEvents 20059867 # Number of times rename has blocked due to SQ full 630system.cpu.rename.RenamedOperands 150297562 # Number of destination operands rename has renamed 631system.cpu.rename.RenameLookups 677265731 # Number of register rename lookups that rename has made 632system.cpu.rename.int_rename_lookups 164029738 # Number of integer rename lookups 633system.cpu.rename.fp_rename_lookups 11047 # Number of floating rename lookups 634system.cpu.rename.CommittedMaps 141819290 # Number of HB maps that are committed 635system.cpu.rename.UndoneMaps 8478266 # Number of HB maps that are undone due to squashing 636system.cpu.rename.serializingInsts 2841903 # count of serializing insts renamed 637system.cpu.rename.tempSerializingInsts 2646616 # count of temporary serializing insts renamed 638system.cpu.rename.skidInsts 13881588 # count of insts added to the skid buffer 639system.cpu.memDep0.insertedLoads 26350743 # Number of loads inserted to the mem dependence unit. 640system.cpu.memDep0.insertedStores 21216202 # Number of stores inserted to the mem dependence unit. 641system.cpu.memDep0.conflictingLoads 1694356 # Number of conflicting loads. 642system.cpu.memDep0.conflictingStores 2155521 # Number of conflicting stores. 643system.cpu.iq.iqInstsAdded 143287156 # Number of instructions added to the IQ (excludes non-spec) 644system.cpu.iq.iqNonSpecInstsAdded 2116266 # Number of non-speculative instructions added to the IQ 645system.cpu.iq.iqInstsIssued 143106706 # Number of instructions issued 646system.cpu.iq.iqSquashedInstsIssued 261772 # Number of squashed instructions issued 647system.cpu.iq.iqSquashedInstsExamined 8147939 # Number of squashed instructions iterated over during squash; mainly for profiling 648system.cpu.iq.iqSquashedOperandsExamined 14286308 # Number of squashed operands that are examined and possibly removed from graph 649system.cpu.iq.iqSquashedNonSpecRemoved 122067 # Number of squashed non-spec instructions that were removed 650system.cpu.iq.issued_per_cycle::samples 258192520 # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::mean 0.554264 # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::stdev 0.878016 # Number of insts issued each cycle |
| 652system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 653system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 653system.cpu.iq.issued_per_cycle::0 182394036 67.40% 67.40% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::1 45259787 16.73% 84.13% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::2 31866202 11.78% 95.91% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::3 10262392 3.79% 99.70% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::4 816883 0.30% 100.00% # Number of insts issued each cycle | 654system.cpu.iq.issued_per_cycle::0 169987358 65.84% 65.84% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::1 45210540 17.51% 83.35% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::2 31907168 12.36% 95.71% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::3 10268019 3.98% 99.68% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::4 819402 0.32% 100.00% # Number of insts issued each cycle |
| 658system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 659system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 663system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 664system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 665system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 665system.cpu.iq.issued_per_cycle::total 270599333 # Number of insts issued each cycle | 666system.cpu.iq.issued_per_cycle::total 258192520 # Number of insts issued each cycle |
| 666system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 667system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 667system.cpu.iq.fu_full::IntAlu 7342152 32.76% 32.76% # attempts to use FU when none available 668system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 669system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 670system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 672system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available 693system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available 694system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 696system.cpu.iq.fu_full::MemRead 5622313 25.09% 57.86% # attempts to use FU when none available 697system.cpu.iq.fu_full::MemWrite 9444091 42.14% 100.00% # attempts to use FU when none available | 668system.cpu.iq.fu_full::IntAlu 7338606 32.76% 32.76% # attempts to use FU when none available 669system.cpu.iq.fu_full::IntMult 32 0.00% 32.76% # attempts to use FU when none available 670system.cpu.iq.fu_full::IntDiv 0 0.00% 32.76% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.76% # attempts to use FU when none available 672system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.76% # attempts to use FU when none available 673system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.76% # attempts to use FU when none available 674system.cpu.iq.fu_full::FloatMult 0 0.00% 32.76% # attempts to use FU when none available 675system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.76% # attempts to use FU when none available 676system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.76% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.76% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.76% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.76% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.76% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.76% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.76% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdMult 0 0.00% 32.76% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.76% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdShift 0 0.00% 32.76% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.76% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.76% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.76% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.76% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.76% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.76% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.76% # attempts to use FU when none available 693system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.76% # attempts to use FU when none available 694system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.76% # attempts to use FU when none available 695system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.76% # attempts to use FU when none available 696system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.76% # attempts to use FU when none available 697system.cpu.iq.fu_full::MemRead 5623411 25.10% 57.86% # attempts to use FU when none available 698system.cpu.iq.fu_full::MemWrite 9440852 42.14% 100.00% # attempts to use FU when none available |
| 698system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 699system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 700system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued | 699system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 700system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 701system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued |
| 701system.cpu.iq.FU_type_0::IntAlu 95850690 67.01% 67.01% # Type of FU issued 702system.cpu.iq.FU_type_0::IntMult 114288 0.08% 67.09% # Type of FU issued | 702system.cpu.iq.FU_type_0::IntAlu 95896760 67.01% 67.01% # Type of FU issued 703system.cpu.iq.FU_type_0::IntMult 115009 0.08% 67.09% # Type of FU issued |
| 703system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 704system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 706system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 707system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 708system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 709system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 718system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued | 704system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 706system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 707system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 708system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 709system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 710system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 719system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued |
| 726system.cpu.iq.FU_type_0::SimdFloatMisc 8577 0.01% 67.09% # Type of FU issued 727system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued 728system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued 730system.cpu.iq.FU_type_0::MemRead 26130891 18.27% 85.36% # Type of FU issued 731system.cpu.iq.FU_type_0::MemWrite 20940281 14.64% 100.00% # Type of FU issued | 727system.cpu.iq.FU_type_0::SimdFloatMisc 8592 0.01% 67.10% # Type of FU issued 728system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued 729system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued 730system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued 731system.cpu.iq.FU_type_0::MemRead 26141404 18.27% 85.37% # Type of FU issued 732system.cpu.iq.FU_type_0::MemWrite 20942604 14.63% 100.00% # Type of FU issued |
| 732system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 733system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 733system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 734system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 734system.cpu.iq.FU_type_0::total 143047064 # Type of FU issued 735system.cpu.iq.rate 0.513698 # Inst issue rate 736system.cpu.iq.fu_busy_cnt 22408588 # FU busy when requested 737system.cpu.iq.fu_busy_rate 0.156652 # FU busy rate (busy events/executed inst) 738system.cpu.iq.int_inst_queue_reads 579326888 # Number of integer instruction queue reads 739system.cpu.iq.int_inst_queue_writes 153497201 # Number of integer instruction queue writes 740system.cpu.iq.int_inst_queue_wakeup_accesses 139997351 # Number of integer instruction queue wakeup accesses 741system.cpu.iq.fp_inst_queue_reads 35639 # Number of floating instruction queue reads 742system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes 743system.cpu.iq.fp_inst_queue_wakeup_accesses 11369 # Number of floating instruction queue wakeup accesses 744system.cpu.iq.int_alu_accesses 165429916 # Number of integer alu accesses 745system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses 746system.cpu.iew.lsq.thread0.forwLoads 323958 # Number of loads that had data forwarded from stores | 735system.cpu.iq.FU_type_0::total 143106706 # Type of FU issued 736system.cpu.iq.rate 0.541351 # Inst issue rate 737system.cpu.iq.fu_busy_cnt 22402901 # FU busy when requested 738system.cpu.iq.fu_busy_rate 0.156547 # FU busy rate (busy events/executed inst) 739system.cpu.iq.int_inst_queue_reads 567034934 # Number of integer instruction queue reads 740system.cpu.iq.int_inst_queue_writes 153556562 # Number of integer instruction queue writes 741system.cpu.iq.int_inst_queue_wakeup_accesses 140052264 # Number of integer instruction queue wakeup accesses 742system.cpu.iq.fp_inst_queue_reads 35671 # Number of floating instruction queue reads 743system.cpu.iq.fp_inst_queue_writes 13288 # Number of floating instruction queue writes 744system.cpu.iq.fp_inst_queue_wakeup_accesses 11499 # Number of floating instruction queue wakeup accesses 745system.cpu.iq.int_alu_accesses 165483986 # Number of integer alu accesses 746system.cpu.iq.fp_alu_accesses 23284 # Number of floating point alu accesses 747system.cpu.iew.lsq.thread0.forwLoads 324130 # Number of loads that had data forwarded from stores |
| 747system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 748system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 748system.cpu.iew.lsq.thread0.squashedLoads 1433781 # Number of loads squashed 749system.cpu.iew.lsq.thread0.ignoredResponses 712 # Number of memory responses ignored because the instruction is squashed 750system.cpu.iew.lsq.thread0.memOrderViolation 18665 # Number of memory ordering violations 751system.cpu.iew.lsq.thread0.squashedStores 622043 # Number of stores squashed | 749system.cpu.iew.lsq.thread0.squashedLoads 1434023 # Number of loads squashed 750system.cpu.iew.lsq.thread0.ignoredResponses 698 # Number of memory responses ignored because the instruction is squashed 751system.cpu.iew.lsq.thread0.memOrderViolation 18538 # Number of memory ordering violations 752system.cpu.iew.lsq.thread0.squashedStores 619510 # Number of stores squashed |
| 752system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 753system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 753system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 754system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 754system.cpu.iew.lsq.thread0.rescheduledLoads 88844 # Number of loads that were rescheduled 755system.cpu.iew.lsq.thread0.cacheBlocked 6344 # Number of times an access to memory failed due to the cache being blocked | 755system.cpu.iew.lsq.thread0.rescheduledLoads 88631 # Number of loads that were rescheduled 756system.cpu.iew.lsq.thread0.cacheBlocked 6598 # Number of times an access to memory failed due to the cache being blocked |
| 756system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 757system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 757system.cpu.iew.iewSquashCycles 2568948 # Number of cycles IEW is squashing 758system.cpu.iew.iewBlockCycles 1241907 # Number of cycles IEW is blocking 759system.cpu.iew.iewUnblockCycles 544667 # Number of cycles IEW is unblocking 760system.cpu.iew.iewDispatchedInsts 145523405 # Number of instructions dispatched to IQ | 758system.cpu.iew.iewSquashCycles 2571629 # Number of cycles IEW is squashing 759system.cpu.iew.iewBlockCycles 994929 # Number of cycles IEW is blocking 760system.cpu.iew.iewUnblockCycles 316385 # Number of cycles IEW is unblocking 761system.cpu.iew.iewDispatchedInsts 145584227 # Number of instructions dispatched to IQ |
| 761system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 762system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 762system.cpu.iew.iewDispLoadInsts 26339908 # Number of dispatched load instructions 763system.cpu.iew.iewDispStoreInsts 21214343 # Number of dispatched store instructions 764system.cpu.iew.iewDispNonSpecInsts 1094304 # Number of dispatched non-speculative instructions 765system.cpu.iew.iewIQFullEvents 17849 # Number of times the IQ has become full, causing a stall 766system.cpu.iew.iewLSQFullEvents 508298 # Number of times the LSQ has become full, causing a stall 767system.cpu.iew.memOrderViolationEvents 18665 # Number of memory order violations 768system.cpu.iew.predictedTakenIncorrect 277238 # Number of branches that were predicted taken incorrectly 769system.cpu.iew.predictedNotTakenIncorrect 471000 # Number of branches that were predicted not taken incorrectly 770system.cpu.iew.branchMispredicts 748238 # Number of branch mispredicts detected at execute 771system.cpu.iew.iewExecutedInsts 142148555 # Number of executed instructions 772system.cpu.iew.iewExecLoadInsts 25736254 # Number of load instructions executed 773system.cpu.iew.iewExecSquashedInsts 826428 # Number of squashed instructions skipped in execute | 763system.cpu.iew.iewDispLoadInsts 26350743 # Number of dispatched load instructions 764system.cpu.iew.iewDispStoreInsts 21216202 # Number of dispatched store instructions 765system.cpu.iew.iewDispNonSpecInsts 1093451 # Number of dispatched non-speculative instructions 766system.cpu.iew.iewIQFullEvents 17658 # Number of times the IQ has become full, causing a stall 767system.cpu.iew.iewLSQFullEvents 280514 # Number of times the LSQ has become full, causing a stall 768system.cpu.iew.memOrderViolationEvents 18538 # Number of memory order violations 769system.cpu.iew.predictedTakenIncorrect 277676 # Number of branches that were predicted taken incorrectly 770system.cpu.iew.predictedNotTakenIncorrect 470698 # Number of branches that were predicted not taken incorrectly 771system.cpu.iew.branchMispredicts 748374 # Number of branch mispredicts detected at execute 772system.cpu.iew.iewExecutedInsts 142207045 # Number of executed instructions 773system.cpu.iew.iewExecLoadInsts 25746206 # Number of load instructions executed 774system.cpu.iew.iewExecSquashedInsts 827350 # Number of squashed instructions skipped in execute |
| 774system.cpu.iew.exec_swp 0 # number of swp insts executed | 775system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 775system.cpu.iew.exec_nop 180625 # number of nop insts executed 776system.cpu.iew.exec_refs 46564673 # number of memory reference insts executed 777system.cpu.iew.exec_branches 26492434 # Number of branches executed 778system.cpu.iew.exec_stores 20828419 # Number of stores executed 779system.cpu.iew.exec_rate 0.510471 # Inst execution rate 780system.cpu.iew.wb_sent 141779361 # cumulative count of insts sent to commit 781system.cpu.iew.wb_count 140008720 # cumulative count of insts written-back 782system.cpu.iew.wb_producers 63240555 # num instructions producing a value 783system.cpu.iew.wb_consumers 95712709 # num instructions consuming a value 784system.cpu.iew.wb_rate 0.502787 # insts written-back per cycle 785system.cpu.iew.wb_fanout 0.660733 # average fanout of values written-back 786system.cpu.commit.commitSquashedInsts 7366290 # The number of squashed insts skipped by commit 787system.cpu.commit.commitNonSpecStalls 1996052 # The number of times commit has been forced to stall to communicate backwards 788system.cpu.commit.branchMispredicts 715102 # The number of times a branch was mispredicted 789system.cpu.commit.committed_per_cycle::samples 267708008 # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::mean 0.513054 # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::stdev 1.118068 # Number of insts commited each cycle | 776system.cpu.iew.exec_nop 180805 # number of nop insts executed 777system.cpu.iew.exec_refs 46576895 # number of memory reference insts executed 778system.cpu.iew.exec_branches 26509940 # Number of branches executed 779system.cpu.iew.exec_stores 20830689 # Number of stores executed 780system.cpu.iew.exec_rate 0.537948 # Inst execution rate 781system.cpu.iew.wb_sent 141837731 # cumulative count of insts sent to commit 782system.cpu.iew.wb_count 140063763 # cumulative count of insts written-back 783system.cpu.iew.wb_producers 63261975 # num instructions producing a value 784system.cpu.iew.wb_consumers 95760288 # num instructions consuming a value 785system.cpu.iew.wb_rate 0.529840 # insts written-back per cycle 786system.cpu.iew.wb_fanout 0.660628 # average fanout of values written-back 787system.cpu.commit.commitSquashedInsts 7362260 # The number of squashed insts skipped by commit 788system.cpu.commit.commitNonSpecStalls 1994199 # The number of times commit has been forced to stall to communicate backwards 789system.cpu.commit.branchMispredicts 714821 # The number of times a branch was mispredicted 790system.cpu.commit.committed_per_cycle::samples 255299551 # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::mean 0.538232 # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::stdev 1.139550 # Number of insts commited each cycle |
| 792system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 793system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 793system.cpu.commit.committed_per_cycle::0 194252968 72.56% 72.56% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::1 43305040 16.18% 88.74% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::2 15457612 5.77% 94.51% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::3 4371808 1.63% 96.14% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::4 6428406 2.40% 98.55% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::5 1610065 0.60% 99.15% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::6 797962 0.30% 99.45% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::7 411830 0.15% 99.60% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::8 1072317 0.40% 100.00% # Number of insts commited each cycle | 794system.cpu.commit.committed_per_cycle::0 181839086 71.23% 71.23% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::1 43295063 16.96% 88.18% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::2 15470047 6.06% 94.24% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::3 4367483 1.71% 95.95% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::4 6400805 2.51% 98.46% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::5 1643674 0.64% 99.11% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::6 799411 0.31% 99.42% # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::7 417134 0.16% 99.58% # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::8 1066848 0.42% 100.00% # Number of insts commited each cycle |
| 802system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 803system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 803system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 804system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 805system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 805system.cpu.commit.committed_per_cycle::total 267708008 # Number of insts commited each cycle 806system.cpu.commit.committedInsts 113266238 # Number of instructions committed 807system.cpu.commit.committedOps 137348755 # Number of ops (including micro ops) committed | 806system.cpu.commit.committed_per_cycle::total 255299551 # Number of insts commited each cycle 807system.cpu.commit.committedInsts 113310545 # Number of instructions committed 808system.cpu.commit.committedOps 137410384 # Number of ops (including micro ops) committed |
| 808system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 809system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 809system.cpu.commit.refs 45498427 # Number of memory references committed 810system.cpu.commit.loads 24906127 # Number of loads committed 811system.cpu.commit.membars 814995 # Number of memory barriers committed 812system.cpu.commit.branches 26026646 # Number of branches committed 813system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 814system.cpu.commit.int_insts 120175202 # Number of committed integer instructions. 815system.cpu.commit.function_calls 4885014 # Number of function calls committed. | 810system.cpu.commit.refs 45513412 # Number of memory references committed 811system.cpu.commit.loads 24916720 # Number of loads committed 812system.cpu.commit.membars 814165 # Number of memory barriers committed 813system.cpu.commit.branches 26044798 # Number of branches committed 814system.cpu.commit.fp_insts 11492 # Number of committed floating point instructions. 815system.cpu.commit.int_insts 120233477 # Number of committed integer instructions. 816system.cpu.commit.function_calls 4891928 # Number of function calls committed. |
| 816system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 817system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 817system.cpu.commit.op_class_0::IntAlu 91728959 66.79% 66.79% # Class of committed instruction 818system.cpu.commit.op_class_0::IntMult 112792 0.08% 66.87% # Class of committed instruction | 818system.cpu.commit.op_class_0::IntAlu 91774855 66.79% 66.79% # Class of committed instruction 819system.cpu.commit.op_class_0::IntMult 113526 0.08% 66.87% # Class of committed instruction |
| 819system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 820system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 834system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction | 820system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 835system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction |
| 842system.cpu.commit.op_class_0::SimdFloatMisc 8577 0.01% 66.87% # Class of committed instruction 843system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 844system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 846system.cpu.commit.op_class_0::MemRead 24906127 18.13% 85.01% # Class of committed instruction 847system.cpu.commit.op_class_0::MemWrite 20592300 14.99% 100.00% # Class of committed instruction | 843system.cpu.commit.op_class_0::SimdFloatMisc 8591 0.01% 66.88% # Class of committed instruction 844system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 845system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 846system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction 847system.cpu.commit.op_class_0::MemRead 24916720 18.13% 85.01% # Class of committed instruction 848system.cpu.commit.op_class_0::MemWrite 20596692 14.99% 100.00% # Class of committed instruction |
| 848system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 849system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 849system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 850system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 850system.cpu.commit.op_class_0::total 137348755 # Class of committed instruction 851system.cpu.commit.bw_lim_events 1072317 # number cycles where commit BW limit reached 852system.cpu.rob.rob_reads 389160423 # The number of ROB reads 853system.cpu.rob.rob_writes 292308325 # The number of ROB writes 854system.cpu.timesIdled 890756 # Number of times that the entire CPU went into an idle state and unscheduled itself 855system.cpu.idleCycles 7866030 # Total number of cycles that the CPU has spent unscheduled due to idling 856system.cpu.quiesceCycles 5387322891 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 857system.cpu.committedInsts 113111333 # Number of Instructions Simulated 858system.cpu.committedOps 137193850 # Number of Ops (including micro ops) Simulated 859system.cpu.cpi 2.461870 # CPI: Cycles Per Instruction 860system.cpu.cpi_total 2.461870 # CPI: Total CPI of All Threads 861system.cpu.ipc 0.406195 # IPC: Instructions Per Cycle 862system.cpu.ipc_total 0.406195 # IPC: Total IPC of All Threads 863system.cpu.int_regfile_reads 155535200 # number of integer regfile reads 864system.cpu.int_regfile_writes 88495253 # number of integer regfile writes 865system.cpu.fp_regfile_reads 9528 # number of floating regfile reads | 851system.cpu.commit.op_class_0::total 137410384 # Class of committed instruction 852system.cpu.commit.bw_lim_events 1066848 # number cycles where commit BW limit reached 853system.cpu.rob.rob_reads 376774257 # The number of ROB reads 854system.cpu.rob.rob_writes 292425270 # The number of ROB writes 855system.cpu.timesIdled 893722 # Number of times that the entire CPU went into an idle state and unscheduled itself 856system.cpu.idleCycles 6158637 # Total number of cycles that the CPU has spent unscheduled due to idling 857system.cpu.quiesceCycles 5391355036 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 858system.cpu.committedInsts 113155640 # Number of Instructions Simulated 859system.cpu.committedOps 137255479 # Number of Ops (including micro ops) Simulated 860system.cpu.cpi 2.336173 # CPI: Cycles Per Instruction 861system.cpu.cpi_total 2.336173 # CPI: Total CPI of All Threads 862system.cpu.ipc 0.428050 # IPC: Instructions Per Cycle 863system.cpu.ipc_total 0.428050 # IPC: Total IPC of All Threads 864system.cpu.int_regfile_reads 155596461 # number of integer regfile reads 865system.cpu.int_regfile_writes 88540193 # number of integer regfile writes 866system.cpu.fp_regfile_reads 9674 # number of floating regfile reads |
| 866system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 867system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 867system.cpu.cc_regfile_reads 502191757 # number of cc regfile reads 868system.cpu.cc_regfile_writes 53133619 # number of cc regfile writes 869system.cpu.misc_regfile_reads 461629806 # number of misc regfile reads 870system.cpu.misc_regfile_writes 1521804 # number of misc regfile writes 871system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 872system.cpu.dcache.tags.replacements 838109 # number of replacements 873system.cpu.dcache.tags.tagsinuse 511.925913 # Cycle average of tags in use 874system.cpu.dcache.tags.total_refs 40060330 # Total number of references to valid blocks. 875system.cpu.dcache.tags.sampled_refs 838621 # Sample count of references to valid blocks. 876system.cpu.dcache.tags.avg_refs 47.769290 # Average number of references to valid blocks. 877system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 878system.cpu.dcache.tags.occ_blocks::cpu.data 511.925913 # Average occupied blocks per requestor 879system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 880system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy | 868system.cpu.cc_regfile_reads 502394909 # number of cc regfile reads 869system.cpu.cc_regfile_writes 53149715 # number of cc regfile writes 870system.cpu.misc_regfile_reads 449419252 # number of misc regfile reads 871system.cpu.misc_regfile_writes 1520020 # number of misc regfile writes 872system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 873system.cpu.dcache.tags.replacements 839084 # number of replacements 874system.cpu.dcache.tags.tagsinuse 511.954165 # Cycle average of tags in use 875system.cpu.dcache.tags.total_refs 40069527 # Total number of references to valid blocks. 876system.cpu.dcache.tags.sampled_refs 839596 # Sample count of references to valid blocks. 877system.cpu.dcache.tags.avg_refs 47.724771 # Average number of references to valid blocks. 878system.cpu.dcache.tags.warmup_cycle 270911500 # Cycle when the warmup percentage was hit. 879system.cpu.dcache.tags.occ_blocks::cpu.data 511.954165 # Average occupied blocks per requestor 880system.cpu.dcache.tags.occ_percent::cpu.data 0.999910 # Average percentage of cache occupancy 881system.cpu.dcache.tags.occ_percent::total 0.999910 # Average percentage of cache occupancy |
| 881system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 882system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 882system.cpu.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 883system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id | 883system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id |
| 885system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 886system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 886system.cpu.dcache.tags.tag_accesses 179138470 # Number of tag accesses 887system.cpu.dcache.tags.data_accesses 179138470 # Number of data accesses 888system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 889system.cpu.dcache.ReadReq_hits::cpu.data 23266826 # number of ReadReq hits 890system.cpu.dcache.ReadReq_hits::total 23266826 # number of ReadReq hits 891system.cpu.dcache.WriteReq_hits::cpu.data 15542812 # number of WriteReq hits 892system.cpu.dcache.WriteReq_hits::total 15542812 # number of WriteReq hits 893system.cpu.dcache.SoftPFReq_hits::cpu.data 345885 # number of SoftPFReq hits 894system.cpu.dcache.SoftPFReq_hits::total 345885 # number of SoftPFReq hits 895system.cpu.dcache.LoadLockedReq_hits::cpu.data 441505 # number of LoadLockedReq hits 896system.cpu.dcache.LoadLockedReq_hits::total 441505 # number of LoadLockedReq hits 897system.cpu.dcache.StoreCondReq_hits::cpu.data 460387 # number of StoreCondReq hits 898system.cpu.dcache.StoreCondReq_hits::total 460387 # number of StoreCondReq hits 899system.cpu.dcache.demand_hits::cpu.data 38809638 # number of demand (read+write) hits 900system.cpu.dcache.demand_hits::total 38809638 # number of demand (read+write) hits 901system.cpu.dcache.overall_hits::cpu.data 39155523 # number of overall hits 902system.cpu.dcache.overall_hits::total 39155523 # number of overall hits 903system.cpu.dcache.ReadReq_misses::cpu.data 704207 # number of ReadReq misses 904system.cpu.dcache.ReadReq_misses::total 704207 # number of ReadReq misses 905system.cpu.dcache.WriteReq_misses::cpu.data 3608607 # number of WriteReq misses 906system.cpu.dcache.WriteReq_misses::total 3608607 # number of WriteReq misses 907system.cpu.dcache.SoftPFReq_misses::cpu.data 177503 # number of SoftPFReq misses 908system.cpu.dcache.SoftPFReq_misses::total 177503 # number of SoftPFReq misses 909system.cpu.dcache.LoadLockedReq_misses::cpu.data 27219 # number of LoadLockedReq misses 910system.cpu.dcache.LoadLockedReq_misses::total 27219 # number of LoadLockedReq misses | 887system.cpu.dcache.tags.tag_accesses 179200286 # Number of tag accesses 888system.cpu.dcache.tags.data_accesses 179200286 # Number of data accesses 889system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 890system.cpu.dcache.ReadReq_hits::cpu.data 23273566 # number of ReadReq hits 891system.cpu.dcache.ReadReq_hits::total 23273566 # number of ReadReq hits 892system.cpu.dcache.WriteReq_hits::cpu.data 15547100 # number of WriteReq hits 893system.cpu.dcache.WriteReq_hits::total 15547100 # number of WriteReq hits 894system.cpu.dcache.SoftPFReq_hits::cpu.data 345314 # number of SoftPFReq hits 895system.cpu.dcache.SoftPFReq_hits::total 345314 # number of SoftPFReq hits 896system.cpu.dcache.LoadLockedReq_hits::cpu.data 441102 # number of LoadLockedReq hits 897system.cpu.dcache.LoadLockedReq_hits::total 441102 # number of LoadLockedReq hits 898system.cpu.dcache.StoreCondReq_hits::cpu.data 459566 # number of StoreCondReq hits 899system.cpu.dcache.StoreCondReq_hits::total 459566 # number of StoreCondReq hits 900system.cpu.dcache.demand_hits::cpu.data 38820666 # number of demand (read+write) hits 901system.cpu.dcache.demand_hits::total 38820666 # number of demand (read+write) hits 902system.cpu.dcache.overall_hits::cpu.data 39165980 # number of overall hits 903system.cpu.dcache.overall_hits::total 39165980 # number of overall hits 904system.cpu.dcache.ReadReq_misses::cpu.data 709196 # number of ReadReq misses 905system.cpu.dcache.ReadReq_misses::total 709196 # number of ReadReq misses 906system.cpu.dcache.WriteReq_misses::cpu.data 3610101 # number of WriteReq misses 907system.cpu.dcache.WriteReq_misses::total 3610101 # number of WriteReq misses 908system.cpu.dcache.SoftPFReq_misses::cpu.data 177382 # number of SoftPFReq misses 909system.cpu.dcache.SoftPFReq_misses::total 177382 # number of SoftPFReq misses 910system.cpu.dcache.LoadLockedReq_misses::cpu.data 26835 # number of LoadLockedReq misses 911system.cpu.dcache.LoadLockedReq_misses::total 26835 # number of LoadLockedReq misses |
| 911system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 912system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses | 912system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 913system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses |
| 913system.cpu.dcache.demand_misses::cpu.data 4312814 # number of demand (read+write) misses 914system.cpu.dcache.demand_misses::total 4312814 # number of demand (read+write) misses 915system.cpu.dcache.overall_misses::cpu.data 4490317 # number of overall misses 916system.cpu.dcache.overall_misses::total 4490317 # number of overall misses 917system.cpu.dcache.ReadReq_miss_latency::cpu.data 11705123500 # number of ReadReq miss cycles 918system.cpu.dcache.ReadReq_miss_latency::total 11705123500 # number of ReadReq miss cycles 919system.cpu.dcache.WriteReq_miss_latency::cpu.data 232670418192 # number of WriteReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::total 232670418192 # number of WriteReq miss cycles 921system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376308000 # number of LoadLockedReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::total 376308000 # number of LoadLockedReq miss cycles 923system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 275000 # number of StoreCondReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::total 275000 # number of StoreCondReq miss cycles 925system.cpu.dcache.demand_miss_latency::cpu.data 244375541692 # number of demand (read+write) miss cycles 926system.cpu.dcache.demand_miss_latency::total 244375541692 # number of demand (read+write) miss cycles 927system.cpu.dcache.overall_miss_latency::cpu.data 244375541692 # number of overall miss cycles 928system.cpu.dcache.overall_miss_latency::total 244375541692 # number of overall miss cycles 929system.cpu.dcache.ReadReq_accesses::cpu.data 23971033 # number of ReadReq accesses(hits+misses) 930system.cpu.dcache.ReadReq_accesses::total 23971033 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.WriteReq_accesses::cpu.data 19151419 # number of WriteReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::total 19151419 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.SoftPFReq_accesses::cpu.data 523388 # number of SoftPFReq accesses(hits+misses) 934system.cpu.dcache.SoftPFReq_accesses::total 523388 # number of SoftPFReq accesses(hits+misses) 935system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468724 # number of LoadLockedReq accesses(hits+misses) 936system.cpu.dcache.LoadLockedReq_accesses::total 468724 # number of LoadLockedReq accesses(hits+misses) 937system.cpu.dcache.StoreCondReq_accesses::cpu.data 460392 # number of StoreCondReq accesses(hits+misses) 938system.cpu.dcache.StoreCondReq_accesses::total 460392 # number of StoreCondReq accesses(hits+misses) 939system.cpu.dcache.demand_accesses::cpu.data 43122452 # number of demand (read+write) accesses 940system.cpu.dcache.demand_accesses::total 43122452 # number of demand (read+write) accesses 941system.cpu.dcache.overall_accesses::cpu.data 43645840 # number of overall (read+write) accesses 942system.cpu.dcache.overall_accesses::total 43645840 # number of overall (read+write) accesses 943system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029377 # miss rate for ReadReq accesses 944system.cpu.dcache.ReadReq_miss_rate::total 0.029377 # miss rate for ReadReq accesses 945system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188425 # miss rate for WriteReq accesses 946system.cpu.dcache.WriteReq_miss_rate::total 0.188425 # miss rate for WriteReq accesses 947system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339142 # miss rate for SoftPFReq accesses 948system.cpu.dcache.SoftPFReq_miss_rate::total 0.339142 # miss rate for SoftPFReq accesses 949system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058070 # miss rate for LoadLockedReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058070 # miss rate for LoadLockedReq accesses | 914system.cpu.dcache.demand_misses::cpu.data 4319297 # number of demand (read+write) misses 915system.cpu.dcache.demand_misses::total 4319297 # number of demand (read+write) misses 916system.cpu.dcache.overall_misses::cpu.data 4496679 # number of overall misses 917system.cpu.dcache.overall_misses::total 4496679 # number of overall misses 918system.cpu.dcache.ReadReq_miss_latency::cpu.data 10317292500 # number of ReadReq miss cycles 919system.cpu.dcache.ReadReq_miss_latency::total 10317292500 # number of ReadReq miss cycles 920system.cpu.dcache.WriteReq_miss_latency::cpu.data 150336233192 # number of WriteReq miss cycles 921system.cpu.dcache.WriteReq_miss_latency::total 150336233192 # number of WriteReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 369753500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.LoadLockedReq_miss_latency::total 369753500 # number of LoadLockedReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 213000 # number of StoreCondReq miss cycles 925system.cpu.dcache.StoreCondReq_miss_latency::total 213000 # number of StoreCondReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 160653525692 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 160653525692 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 160653525692 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 160653525692 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 23982762 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 23982762 # number of ReadReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::cpu.data 19157201 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 19157201 # number of WriteReq accesses(hits+misses) 934system.cpu.dcache.SoftPFReq_accesses::cpu.data 522696 # number of SoftPFReq accesses(hits+misses) 935system.cpu.dcache.SoftPFReq_accesses::total 522696 # number of SoftPFReq accesses(hits+misses) 936system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467937 # number of LoadLockedReq accesses(hits+misses) 937system.cpu.dcache.LoadLockedReq_accesses::total 467937 # number of LoadLockedReq accesses(hits+misses) 938system.cpu.dcache.StoreCondReq_accesses::cpu.data 459571 # number of StoreCondReq accesses(hits+misses) 939system.cpu.dcache.StoreCondReq_accesses::total 459571 # number of StoreCondReq accesses(hits+misses) 940system.cpu.dcache.demand_accesses::cpu.data 43139963 # number of demand (read+write) accesses 941system.cpu.dcache.demand_accesses::total 43139963 # number of demand (read+write) accesses 942system.cpu.dcache.overall_accesses::cpu.data 43662659 # number of overall (read+write) accesses 943system.cpu.dcache.overall_accesses::total 43662659 # number of overall (read+write) accesses 944system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses 945system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses 946system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188446 # miss rate for WriteReq accesses 947system.cpu.dcache.WriteReq_miss_rate::total 0.188446 # miss rate for WriteReq accesses 948system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339360 # miss rate for SoftPFReq accesses 949system.cpu.dcache.SoftPFReq_miss_rate::total 0.339360 # miss rate for SoftPFReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057347 # miss rate for LoadLockedReq accesses 951system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057347 # miss rate for LoadLockedReq accesses |
| 951system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 952system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses | 952system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 953system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses |
| 953system.cpu.dcache.demand_miss_rate::cpu.data 0.100013 # miss rate for demand accesses 954system.cpu.dcache.demand_miss_rate::total 0.100013 # miss rate for demand accesses 955system.cpu.dcache.overall_miss_rate::cpu.data 0.102881 # miss rate for overall accesses 956system.cpu.dcache.overall_miss_rate::total 0.102881 # miss rate for overall accesses 957system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16621.708532 # average ReadReq miss latency 958system.cpu.dcache.ReadReq_avg_miss_latency::total 16621.708532 # average ReadReq miss latency 959system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64476.519109 # average WriteReq miss latency 960system.cpu.dcache.WriteReq_avg_miss_latency::total 64476.519109 # average WriteReq miss latency 961system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13825.195635 # average LoadLockedReq miss latency 962system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13825.195635 # average LoadLockedReq miss latency 963system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55000 # average StoreCondReq miss latency 964system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55000 # average StoreCondReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 56662.666577 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 56662.666577 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 54422.781664 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 54422.781664 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 867732 # number of cycles access was blocked | 954system.cpu.dcache.demand_miss_rate::cpu.data 0.100123 # miss rate for demand accesses 955system.cpu.dcache.demand_miss_rate::total 0.100123 # miss rate for demand accesses 956system.cpu.dcache.overall_miss_rate::cpu.data 0.102987 # miss rate for overall accesses 957system.cpu.dcache.overall_miss_rate::total 0.102987 # miss rate for overall accesses 958system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14547.871815 # average ReadReq miss latency 959system.cpu.dcache.ReadReq_avg_miss_latency::total 14547.871815 # average ReadReq miss latency 960system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41643.220838 # average WriteReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::total 41643.220838 # average WriteReq miss latency 962system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13778.777716 # average LoadLockedReq miss latency 963system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13778.777716 # average LoadLockedReq miss latency 964system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 42600 # average StoreCondReq miss latency 965system.cpu.dcache.StoreCondReq_avg_miss_latency::total 42600 # average StoreCondReq miss latency 966system.cpu.dcache.demand_avg_miss_latency::cpu.data 37194.368827 # average overall miss latency 967system.cpu.dcache.demand_avg_miss_latency::total 37194.368827 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::cpu.data 35727.150124 # average overall miss latency 969system.cpu.dcache.overall_avg_miss_latency::total 35727.150124 # average overall miss latency 970system.cpu.dcache.blocked_cycles::no_mshrs 590933 # number of cycles access was blocked |
| 970system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 971system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 971system.cpu.dcache.blocked::no_mshrs 6871 # number of cycles access was blocked | 972system.cpu.dcache.blocked::no_mshrs 7520 # number of cycles access was blocked |
| 972system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 973system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 126.289041 # average number of cycles each access was blocked | 974system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.581516 # average number of cycles each access was blocked |
| 974system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 975system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 975system.cpu.dcache.writebacks::writebacks 696134 # number of writebacks 976system.cpu.dcache.writebacks::total 696134 # number of writebacks 977system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290642 # number of ReadReq MSHR hits 978system.cpu.dcache.ReadReq_mshr_hits::total 290642 # number of ReadReq MSHR hits 979system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3308599 # number of WriteReq MSHR hits 980system.cpu.dcache.WriteReq_mshr_hits::total 3308599 # number of WriteReq MSHR hits 981system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18782 # number of LoadLockedReq MSHR hits 982system.cpu.dcache.LoadLockedReq_mshr_hits::total 18782 # number of LoadLockedReq MSHR hits 983system.cpu.dcache.demand_mshr_hits::cpu.data 3599241 # number of demand (read+write) MSHR hits 984system.cpu.dcache.demand_mshr_hits::total 3599241 # number of demand (read+write) MSHR hits 985system.cpu.dcache.overall_mshr_hits::cpu.data 3599241 # number of overall MSHR hits 986system.cpu.dcache.overall_mshr_hits::total 3599241 # number of overall MSHR hits 987system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413565 # number of ReadReq MSHR misses 988system.cpu.dcache.ReadReq_mshr_misses::total 413565 # number of ReadReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300008 # number of WriteReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::total 300008 # number of WriteReq MSHR misses 991system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119442 # number of SoftPFReq MSHR misses 992system.cpu.dcache.SoftPFReq_mshr_misses::total 119442 # number of SoftPFReq MSHR misses 993system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8437 # number of LoadLockedReq MSHR misses 994system.cpu.dcache.LoadLockedReq_mshr_misses::total 8437 # number of LoadLockedReq MSHR misses | 976system.cpu.dcache.writebacks::writebacks 696178 # number of writebacks 977system.cpu.dcache.writebacks::total 696178 # number of writebacks 978system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295013 # number of ReadReq MSHR hits 979system.cpu.dcache.ReadReq_mshr_hits::total 295013 # number of ReadReq MSHR hits 980system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309632 # number of WriteReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::total 3309632 # number of WriteReq MSHR hits 982system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18459 # number of LoadLockedReq MSHR hits 983system.cpu.dcache.LoadLockedReq_mshr_hits::total 18459 # number of LoadLockedReq MSHR hits 984system.cpu.dcache.demand_mshr_hits::cpu.data 3604645 # number of demand (read+write) MSHR hits 985system.cpu.dcache.demand_mshr_hits::total 3604645 # number of demand (read+write) MSHR hits 986system.cpu.dcache.overall_mshr_hits::cpu.data 3604645 # number of overall MSHR hits 987system.cpu.dcache.overall_mshr_hits::total 3604645 # number of overall MSHR hits 988system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414183 # number of ReadReq MSHR misses 989system.cpu.dcache.ReadReq_mshr_misses::total 414183 # number of ReadReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300469 # number of WriteReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::total 300469 # number of WriteReq MSHR misses 992system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119358 # number of SoftPFReq MSHR misses 993system.cpu.dcache.SoftPFReq_mshr_misses::total 119358 # number of SoftPFReq MSHR misses 994system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8376 # number of LoadLockedReq MSHR misses 995system.cpu.dcache.LoadLockedReq_mshr_misses::total 8376 # number of LoadLockedReq MSHR misses |
| 995system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 996system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses | 996system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 997system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses |
| 997system.cpu.dcache.demand_mshr_misses::cpu.data 713573 # number of demand (read+write) MSHR misses 998system.cpu.dcache.demand_mshr_misses::total 713573 # number of demand (read+write) MSHR misses 999system.cpu.dcache.overall_mshr_misses::cpu.data 833015 # number of overall MSHR misses 1000system.cpu.dcache.overall_mshr_misses::total 833015 # number of overall MSHR misses 1001system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1002system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 1003system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1004system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1005system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1006system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 1007system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6383877500 # number of ReadReq MSHR miss cycles 1008system.cpu.dcache.ReadReq_mshr_miss_latency::total 6383877500 # number of ReadReq MSHR miss cycles 1009system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19987260971 # number of WriteReq MSHR miss cycles 1010system.cpu.dcache.WriteReq_mshr_miss_latency::total 19987260971 # number of WriteReq MSHR miss cycles 1011system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1693165000 # number of SoftPFReq MSHR miss cycles 1012system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1693165000 # number of SoftPFReq MSHR miss cycles 1013system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126972500 # number of LoadLockedReq MSHR miss cycles 1014system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126972500 # number of LoadLockedReq MSHR miss cycles 1015system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270000 # number of StoreCondReq MSHR miss cycles 1016system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270000 # number of StoreCondReq MSHR miss cycles 1017system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26371138471 # number of demand (read+write) MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::total 26371138471 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064303471 # number of overall MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::total 28064303471 # number of overall MSHR miss cycles 1021system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276254500 # number of ReadReq MSHR uncacheable cycles 1022system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276254500 # number of ReadReq MSHR uncacheable cycles 1023system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276254500 # number of overall MSHR uncacheable cycles 1024system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276254500 # number of overall MSHR uncacheable cycles 1025system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017253 # mshr miss rate for ReadReq accesses 1026system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses 1027system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015665 # mshr miss rate for WriteReq accesses 1028system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015665 # mshr miss rate for WriteReq accesses 1029system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228209 # mshr miss rate for SoftPFReq accesses 1030system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228209 # mshr miss rate for SoftPFReq accesses 1031system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018000 # mshr miss rate for LoadLockedReq accesses 1032system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018000 # mshr miss rate for LoadLockedReq accesses | 998system.cpu.dcache.demand_mshr_misses::cpu.data 714652 # number of demand (read+write) MSHR misses 999system.cpu.dcache.demand_mshr_misses::total 714652 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.overall_mshr_misses::cpu.data 834010 # number of overall MSHR misses 1001system.cpu.dcache.overall_mshr_misses::total 834010 # number of overall MSHR misses 1002system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1003system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable 1004system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1005system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1006system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1007system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses 1008system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890415000 # number of ReadReq MSHR miss cycles 1009system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890415000 # number of ReadReq MSHR miss cycles 1010system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13426039479 # number of WriteReq MSHR miss cycles 1011system.cpu.dcache.WriteReq_mshr_miss_latency::total 13426039479 # number of WriteReq MSHR miss cycles 1012system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1622684000 # number of SoftPFReq MSHR miss cycles 1013system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1622684000 # number of SoftPFReq MSHR miss cycles 1014system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 130358500 # number of LoadLockedReq MSHR miss cycles 1015system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 130358500 # number of LoadLockedReq MSHR miss cycles 1016system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 208000 # number of StoreCondReq MSHR miss cycles 1017system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 208000 # number of StoreCondReq MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19316454479 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.demand_mshr_miss_latency::total 19316454479 # number of demand (read+write) MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20939138479 # number of overall MSHR miss cycles 1021system.cpu.dcache.overall_mshr_miss_latency::total 20939138479 # number of overall MSHR miss cycles 1022system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279502000 # number of ReadReq MSHR uncacheable cycles 1023system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279502000 # number of ReadReq MSHR uncacheable cycles 1024system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6279502000 # number of overall MSHR uncacheable cycles 1025system.cpu.dcache.overall_mshr_uncacheable_latency::total 6279502000 # number of overall MSHR uncacheable cycles 1026system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017270 # mshr miss rate for ReadReq accesses 1027system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017270 # mshr miss rate for ReadReq accesses 1028system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015684 # mshr miss rate for WriteReq accesses 1029system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015684 # mshr miss rate for WriteReq accesses 1030system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228351 # mshr miss rate for SoftPFReq accesses 1031system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228351 # mshr miss rate for SoftPFReq accesses 1032system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017900 # mshr miss rate for LoadLockedReq accesses 1033system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017900 # mshr miss rate for LoadLockedReq accesses |
| 1033system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1034system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses | 1034system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1035system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses |
| 1035system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016548 # mshr miss rate for demand accesses 1036system.cpu.dcache.demand_mshr_miss_rate::total 0.016548 # mshr miss rate for demand accesses 1037system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019086 # mshr miss rate for overall accesses 1038system.cpu.dcache.overall_mshr_miss_rate::total 0.019086 # mshr miss rate for overall accesses 1039system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15436.213171 # average ReadReq mshr miss latency 1040system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15436.213171 # average ReadReq mshr miss latency 1041system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66622.426639 # average WriteReq mshr miss latency 1042system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66622.426639 # average WriteReq mshr miss latency 1043system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14175.624990 # average SoftPFReq mshr miss latency 1044system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14175.624990 # average SoftPFReq mshr miss latency 1045system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15049.484414 # average LoadLockedReq mshr miss latency 1046system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15049.484414 # average LoadLockedReq mshr miss latency 1047system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54000 # average StoreCondReq mshr miss latency 1048system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54000 # average StoreCondReq mshr miss latency 1049system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36956.469024 # average overall mshr miss latency 1050system.cpu.dcache.demand_avg_mshr_miss_latency::total 36956.469024 # average overall mshr miss latency 1051system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33690.033758 # average overall mshr miss latency 1052system.cpu.dcache.overall_avg_mshr_miss_latency::total 33690.033758 # average overall mshr miss latency 1053system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201620.819814 # average ReadReq mshr uncacheable latency 1054system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201620.819814 # average ReadReq mshr uncacheable latency 1055system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.365671 # average overall mshr uncacheable latency 1056system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.365671 # average overall mshr uncacheable latency 1057system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1058system.cpu.icache.tags.replacements 1886431 # number of replacements 1059system.cpu.icache.tags.tagsinuse 511.154202 # Cycle average of tags in use 1060system.cpu.icache.tags.total_refs 64000082 # Total number of references to valid blocks. 1061system.cpu.icache.tags.sampled_refs 1886943 # Sample count of references to valid blocks. 1062system.cpu.icache.tags.avg_refs 33.917337 # Average number of references to valid blocks. 1063system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. 1064system.cpu.icache.tags.occ_blocks::cpu.inst 511.154202 # Average occupied blocks per requestor 1065system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1066system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy | 1036system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016566 # mshr miss rate for demand accesses 1037system.cpu.dcache.demand_mshr_miss_rate::total 0.016566 # mshr miss rate for demand accesses 1038system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019101 # mshr miss rate for overall accesses 1039system.cpu.dcache.overall_mshr_miss_rate::total 0.019101 # mshr miss rate for overall accesses 1040system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14221.769121 # average ReadReq mshr miss latency 1041system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14221.769121 # average ReadReq mshr miss latency 1042system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44683.609554 # average WriteReq mshr miss latency 1043system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44683.609554 # average WriteReq mshr miss latency 1044system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13595.100454 # average SoftPFReq mshr miss latency 1045system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13595.100454 # average SoftPFReq mshr miss latency 1046system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15563.335721 # average LoadLockedReq mshr miss latency 1047system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15563.335721 # average LoadLockedReq mshr miss latency 1048system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 41600 # average StoreCondReq mshr miss latency 1049system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 41600 # average StoreCondReq mshr miss latency 1050system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27029.175709 # average overall mshr miss latency 1051system.cpu.dcache.demand_avg_mshr_miss_latency::total 27029.175709 # average overall mshr miss latency 1052system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25106.579632 # average overall mshr miss latency 1053system.cpu.dcache.overall_avg_mshr_miss_latency::total 25106.579632 # average overall mshr miss latency 1054system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201738.105182 # average ReadReq mshr uncacheable latency 1055system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201738.105182 # average ReadReq mshr uncacheable latency 1056system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106956.141098 # average overall mshr uncacheable latency 1057system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106956.141098 # average overall mshr uncacheable latency 1058system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1059system.cpu.icache.tags.replacements 1887810 # number of replacements 1060system.cpu.icache.tags.tagsinuse 511.341026 # Cycle average of tags in use 1061system.cpu.icache.tags.total_refs 64075895 # Total number of references to valid blocks. 1062system.cpu.icache.tags.sampled_refs 1888322 # Sample count of references to valid blocks. 1063system.cpu.icache.tags.avg_refs 33.932716 # Average number of references to valid blocks. 1064system.cpu.icache.tags.warmup_cycle 13715039500 # Cycle when the warmup percentage was hit. 1065system.cpu.icache.tags.occ_blocks::cpu.inst 511.341026 # Average occupied blocks per requestor 1066system.cpu.icache.tags.occ_percent::cpu.inst 0.998713 # Average percentage of cache occupancy 1067system.cpu.icache.tags.occ_percent::total 0.998713 # Average percentage of cache occupancy |
| 1067system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1068system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1068system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id 1069system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id 1070system.cpu.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id 1071system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id | 1069system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1070system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 1071system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id 1072system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 1072system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1073system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1073system.cpu.icache.tags.tag_accesses 67865267 # Number of tag accesses 1074system.cpu.icache.tags.data_accesses 67865267 # Number of data accesses 1075system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1076system.cpu.icache.ReadReq_hits::cpu.inst 64000082 # number of ReadReq hits 1077system.cpu.icache.ReadReq_hits::total 64000082 # number of ReadReq hits 1078system.cpu.icache.demand_hits::cpu.inst 64000082 # number of demand (read+write) hits 1079system.cpu.icache.demand_hits::total 64000082 # number of demand (read+write) hits 1080system.cpu.icache.overall_hits::cpu.inst 64000082 # number of overall hits 1081system.cpu.icache.overall_hits::total 64000082 # number of overall hits 1082system.cpu.icache.ReadReq_misses::cpu.inst 1978185 # number of ReadReq misses 1083system.cpu.icache.ReadReq_misses::total 1978185 # number of ReadReq misses 1084system.cpu.icache.demand_misses::cpu.inst 1978185 # number of demand (read+write) misses 1085system.cpu.icache.demand_misses::total 1978185 # number of demand (read+write) misses 1086system.cpu.icache.overall_misses::cpu.inst 1978185 # number of overall misses 1087system.cpu.icache.overall_misses::total 1978185 # number of overall misses 1088system.cpu.icache.ReadReq_miss_latency::cpu.inst 28158737492 # number of ReadReq miss cycles 1089system.cpu.icache.ReadReq_miss_latency::total 28158737492 # number of ReadReq miss cycles 1090system.cpu.icache.demand_miss_latency::cpu.inst 28158737492 # number of demand (read+write) miss cycles 1091system.cpu.icache.demand_miss_latency::total 28158737492 # number of demand (read+write) miss cycles 1092system.cpu.icache.overall_miss_latency::cpu.inst 28158737492 # number of overall miss cycles 1093system.cpu.icache.overall_miss_latency::total 28158737492 # number of overall miss cycles 1094system.cpu.icache.ReadReq_accesses::cpu.inst 65978267 # number of ReadReq accesses(hits+misses) 1095system.cpu.icache.ReadReq_accesses::total 65978267 # number of ReadReq accesses(hits+misses) 1096system.cpu.icache.demand_accesses::cpu.inst 65978267 # number of demand (read+write) accesses 1097system.cpu.icache.demand_accesses::total 65978267 # number of demand (read+write) accesses 1098system.cpu.icache.overall_accesses::cpu.inst 65978267 # number of overall (read+write) accesses 1099system.cpu.icache.overall_accesses::total 65978267 # number of overall (read+write) accesses 1100system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029982 # miss rate for ReadReq accesses 1101system.cpu.icache.ReadReq_miss_rate::total 0.029982 # miss rate for ReadReq accesses 1102system.cpu.icache.demand_miss_rate::cpu.inst 0.029982 # miss rate for demand accesses 1103system.cpu.icache.demand_miss_rate::total 0.029982 # miss rate for demand accesses 1104system.cpu.icache.overall_miss_rate::cpu.inst 0.029982 # miss rate for overall accesses 1105system.cpu.icache.overall_miss_rate::total 0.029982 # miss rate for overall accesses 1106system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14234.633006 # average ReadReq miss latency 1107system.cpu.icache.ReadReq_avg_miss_latency::total 14234.633006 # average ReadReq miss latency 1108system.cpu.icache.demand_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency 1109system.cpu.icache.demand_avg_miss_latency::total 14234.633006 # average overall miss latency 1110system.cpu.icache.overall_avg_miss_latency::cpu.inst 14234.633006 # average overall miss latency 1111system.cpu.icache.overall_avg_miss_latency::total 14234.633006 # average overall miss latency 1112system.cpu.icache.blocked_cycles::no_mshrs 5390 # number of cycles access was blocked | 1074system.cpu.icache.tags.tag_accesses 67944454 # Number of tag accesses 1075system.cpu.icache.tags.data_accesses 67944454 # Number of data accesses 1076system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1077system.cpu.icache.ReadReq_hits::cpu.inst 64075895 # number of ReadReq hits 1078system.cpu.icache.ReadReq_hits::total 64075895 # number of ReadReq hits 1079system.cpu.icache.demand_hits::cpu.inst 64075895 # number of demand (read+write) hits 1080system.cpu.icache.demand_hits::total 64075895 # number of demand (read+write) hits 1081system.cpu.icache.overall_hits::cpu.inst 64075895 # number of overall hits 1082system.cpu.icache.overall_hits::total 64075895 # number of overall hits 1083system.cpu.icache.ReadReq_misses::cpu.inst 1980206 # number of ReadReq misses 1084system.cpu.icache.ReadReq_misses::total 1980206 # number of ReadReq misses 1085system.cpu.icache.demand_misses::cpu.inst 1980206 # number of demand (read+write) misses 1086system.cpu.icache.demand_misses::total 1980206 # number of demand (read+write) misses 1087system.cpu.icache.overall_misses::cpu.inst 1980206 # number of overall misses 1088system.cpu.icache.overall_misses::total 1980206 # number of overall misses 1089system.cpu.icache.ReadReq_miss_latency::cpu.inst 26984355494 # number of ReadReq miss cycles 1090system.cpu.icache.ReadReq_miss_latency::total 26984355494 # number of ReadReq miss cycles 1091system.cpu.icache.demand_miss_latency::cpu.inst 26984355494 # number of demand (read+write) miss cycles 1092system.cpu.icache.demand_miss_latency::total 26984355494 # number of demand (read+write) miss cycles 1093system.cpu.icache.overall_miss_latency::cpu.inst 26984355494 # number of overall miss cycles 1094system.cpu.icache.overall_miss_latency::total 26984355494 # number of overall miss cycles 1095system.cpu.icache.ReadReq_accesses::cpu.inst 66056101 # number of ReadReq accesses(hits+misses) 1096system.cpu.icache.ReadReq_accesses::total 66056101 # number of ReadReq accesses(hits+misses) 1097system.cpu.icache.demand_accesses::cpu.inst 66056101 # number of demand (read+write) accesses 1098system.cpu.icache.demand_accesses::total 66056101 # number of demand (read+write) accesses 1099system.cpu.icache.overall_accesses::cpu.inst 66056101 # number of overall (read+write) accesses 1100system.cpu.icache.overall_accesses::total 66056101 # number of overall (read+write) accesses 1101system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029978 # miss rate for ReadReq accesses 1102system.cpu.icache.ReadReq_miss_rate::total 0.029978 # miss rate for ReadReq accesses 1103system.cpu.icache.demand_miss_rate::cpu.inst 0.029978 # miss rate for demand accesses 1104system.cpu.icache.demand_miss_rate::total 0.029978 # miss rate for demand accesses 1105system.cpu.icache.overall_miss_rate::cpu.inst 0.029978 # miss rate for overall accesses 1106system.cpu.icache.overall_miss_rate::total 0.029978 # miss rate for overall accesses 1107system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13627.044607 # average ReadReq miss latency 1108system.cpu.icache.ReadReq_avg_miss_latency::total 13627.044607 # average ReadReq miss latency 1109system.cpu.icache.demand_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency 1110system.cpu.icache.demand_avg_miss_latency::total 13627.044607 # average overall miss latency 1111system.cpu.icache.overall_avg_miss_latency::cpu.inst 13627.044607 # average overall miss latency 1112system.cpu.icache.overall_avg_miss_latency::total 13627.044607 # average overall miss latency 1113system.cpu.icache.blocked_cycles::no_mshrs 2643 # number of cycles access was blocked |
| 1113system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1114system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1114system.cpu.icache.blocked::no_mshrs 176 # number of cycles access was blocked | 1115system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked |
| 1115system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1116system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1116system.cpu.icache.avg_blocked_cycles::no_mshrs 30.625000 # average number of cycles each access was blocked | 1117system.cpu.icache.avg_blocked_cycles::no_mshrs 21.144000 # average number of cycles each access was blocked |
| 1117system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1118system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1118system.cpu.icache.writebacks::writebacks 1886431 # number of writebacks 1119system.cpu.icache.writebacks::total 1886431 # number of writebacks 1120system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91184 # number of ReadReq MSHR hits 1121system.cpu.icache.ReadReq_mshr_hits::total 91184 # number of ReadReq MSHR hits 1122system.cpu.icache.demand_mshr_hits::cpu.inst 91184 # number of demand (read+write) MSHR hits 1123system.cpu.icache.demand_mshr_hits::total 91184 # number of demand (read+write) MSHR hits 1124system.cpu.icache.overall_mshr_hits::cpu.inst 91184 # number of overall MSHR hits 1125system.cpu.icache.overall_mshr_hits::total 91184 # number of overall MSHR hits 1126system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887001 # number of ReadReq MSHR misses 1127system.cpu.icache.ReadReq_mshr_misses::total 1887001 # number of ReadReq MSHR misses 1128system.cpu.icache.demand_mshr_misses::cpu.inst 1887001 # number of demand (read+write) MSHR misses 1129system.cpu.icache.demand_mshr_misses::total 1887001 # number of demand (read+write) MSHR misses 1130system.cpu.icache.overall_mshr_misses::cpu.inst 1887001 # number of overall MSHR misses 1131system.cpu.icache.overall_mshr_misses::total 1887001 # number of overall MSHR misses | 1119system.cpu.icache.writebacks::writebacks 1887810 # number of writebacks 1120system.cpu.icache.writebacks::total 1887810 # number of writebacks 1121system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91852 # number of ReadReq MSHR hits 1122system.cpu.icache.ReadReq_mshr_hits::total 91852 # number of ReadReq MSHR hits 1123system.cpu.icache.demand_mshr_hits::cpu.inst 91852 # number of demand (read+write) MSHR hits 1124system.cpu.icache.demand_mshr_hits::total 91852 # number of demand (read+write) MSHR hits 1125system.cpu.icache.overall_mshr_hits::cpu.inst 91852 # number of overall MSHR hits 1126system.cpu.icache.overall_mshr_hits::total 91852 # number of overall MSHR hits 1127system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1888354 # number of ReadReq MSHR misses 1128system.cpu.icache.ReadReq_mshr_misses::total 1888354 # number of ReadReq MSHR misses 1129system.cpu.icache.demand_mshr_misses::cpu.inst 1888354 # number of demand (read+write) MSHR misses 1130system.cpu.icache.demand_mshr_misses::total 1888354 # number of demand (read+write) MSHR misses 1131system.cpu.icache.overall_mshr_misses::cpu.inst 1888354 # number of overall MSHR misses 1132system.cpu.icache.overall_mshr_misses::total 1888354 # number of overall MSHR misses |
| 1132system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1133system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1134system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1135system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses | 1133system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1134system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1135system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1136system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses |
| 1136system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25189687497 # number of ReadReq MSHR miss cycles 1137system.cpu.icache.ReadReq_mshr_miss_latency::total 25189687497 # number of ReadReq MSHR miss cycles 1138system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25189687497 # number of demand (read+write) MSHR miss cycles 1139system.cpu.icache.demand_mshr_miss_latency::total 25189687497 # number of demand (read+write) MSHR miss cycles 1140system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25189687497 # number of overall MSHR miss cycles 1141system.cpu.icache.overall_mshr_miss_latency::total 25189687497 # number of overall MSHR miss cycles 1142system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles 1143system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles 1145system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles 1146system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for ReadReq accesses 1147system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028600 # mshr miss rate for ReadReq accesses 1148system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for demand accesses 1149system.cpu.icache.demand_mshr_miss_rate::total 0.028600 # mshr miss rate for demand accesses 1150system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028600 # mshr miss rate for overall accesses 1151system.cpu.icache.overall_mshr_miss_rate::total 0.028600 # mshr miss rate for overall accesses 1152system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.058902 # average ReadReq mshr miss latency 1153system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.058902 # average ReadReq mshr miss latency 1154system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency 1155system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency 1156system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.058902 # average overall mshr miss latency 1157system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.058902 # average overall mshr miss latency 1158system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency 1159system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency 1160system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency 1161system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency 1162system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1163system.cpu.l2cache.tags.replacements 97066 # number of replacements 1164system.cpu.l2cache.tags.tagsinuse 65034.676246 # Cycle average of tags in use 1165system.cpu.l2cache.tags.total_refs 5004762 # Total number of references to valid blocks. 1166system.cpu.l2cache.tags.sampled_refs 162374 # Sample count of references to valid blocks. 1167system.cpu.l2cache.tags.avg_refs 30.822435 # Average number of references to valid blocks. 1168system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1169system.cpu.l2cache.tags.occ_blocks::writebacks 49586.658386 # Average occupied blocks per requestor 1170system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.610418 # Average occupied blocks per requestor 1171system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.677884 # Average occupied blocks per requestor 1172system.cpu.l2cache.tags.occ_blocks::cpu.inst 10386.588269 # Average occupied blocks per requestor 1173system.cpu.l2cache.tags.occ_blocks::cpu.data 5047.141288 # Average occupied blocks per requestor 1174system.cpu.l2cache.tags.occ_percent::writebacks 0.756632 # Average percentage of cache occupancy 1175system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000177 # Average percentage of cache occupancy 1176system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy 1177system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158487 # Average percentage of cache occupancy 1178system.cpu.l2cache.tags.occ_percent::cpu.data 0.077013 # Average percentage of cache occupancy 1179system.cpu.l2cache.tags.occ_percent::total 0.992350 # Average percentage of cache occupancy 1180system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id 1181system.cpu.l2cache.tags.occ_task_id_blocks::1024 65293 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 1185system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2842 # Occupied blocks per task id 1186system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6720 # Occupied blocks per task id 1187system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55568 # Occupied blocks per task id 1188system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id 1189system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996292 # Percentage of cache occupancy per task id 1190system.cpu.l2cache.tags.tag_accesses 44286849 # Number of tag accesses 1191system.cpu.l2cache.tags.data_accesses 44286849 # Number of data accesses 1192system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1193system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 57782 # number of ReadReq hits 1194system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12059 # number of ReadReq hits 1195system.cpu.l2cache.ReadReq_hits::total 69841 # number of ReadReq hits 1196system.cpu.l2cache.WritebackDirty_hits::writebacks 696134 # number of WritebackDirty hits 1197system.cpu.l2cache.WritebackDirty_hits::total 696134 # number of WritebackDirty hits 1198system.cpu.l2cache.WritebackClean_hits::writebacks 1848502 # number of WritebackClean hits 1199system.cpu.l2cache.WritebackClean_hits::total 1848502 # number of WritebackClean hits 1200system.cpu.l2cache.UpgradeReq_hits::cpu.data 60 # number of UpgradeReq hits 1201system.cpu.l2cache.UpgradeReq_hits::total 60 # number of UpgradeReq hits 1202system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1203system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1204system.cpu.l2cache.ReadExReq_hits::cpu.data 161598 # number of ReadExReq hits 1205system.cpu.l2cache.ReadExReq_hits::total 161598 # number of ReadExReq hits 1206system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866971 # number of ReadCleanReq hits 1207system.cpu.l2cache.ReadCleanReq_hits::total 1866971 # number of ReadCleanReq hits 1208system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527952 # number of ReadSharedReq hits 1209system.cpu.l2cache.ReadSharedReq_hits::total 527952 # number of ReadSharedReq hits 1210system.cpu.l2cache.demand_hits::cpu.dtb.walker 57782 # number of demand (read+write) hits 1211system.cpu.l2cache.demand_hits::cpu.itb.walker 12059 # number of demand (read+write) hits 1212system.cpu.l2cache.demand_hits::cpu.inst 1866971 # number of demand (read+write) hits 1213system.cpu.l2cache.demand_hits::cpu.data 689550 # number of demand (read+write) hits 1214system.cpu.l2cache.demand_hits::total 2626362 # number of demand (read+write) hits 1215system.cpu.l2cache.overall_hits::cpu.dtb.walker 57782 # number of overall hits 1216system.cpu.l2cache.overall_hits::cpu.itb.walker 12059 # number of overall hits 1217system.cpu.l2cache.overall_hits::cpu.inst 1866971 # number of overall hits 1218system.cpu.l2cache.overall_hits::cpu.data 689550 # number of overall hits 1219system.cpu.l2cache.overall_hits::total 2626362 # number of overall hits 1220system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses 1221system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses 1222system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses 1223system.cpu.l2cache.UpgradeReq_misses::cpu.data 2746 # number of UpgradeReq misses 1224system.cpu.l2cache.UpgradeReq_misses::total 2746 # number of UpgradeReq misses 1225system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1226system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1227system.cpu.l2cache.ReadExReq_misses::cpu.data 135739 # number of ReadExReq misses 1228system.cpu.l2cache.ReadExReq_misses::total 135739 # number of ReadExReq misses 1229system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19929 # number of ReadCleanReq misses 1230system.cpu.l2cache.ReadCleanReq_misses::total 19929 # number of ReadCleanReq misses 1231system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13357 # number of ReadSharedReq misses 1232system.cpu.l2cache.ReadSharedReq_misses::total 13357 # number of ReadSharedReq misses 1233system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses 1234system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses 1235system.cpu.l2cache.demand_misses::cpu.inst 19929 # number of demand (read+write) misses 1236system.cpu.l2cache.demand_misses::cpu.data 149096 # number of demand (read+write) misses 1237system.cpu.l2cache.demand_misses::total 169053 # number of demand (read+write) misses 1238system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses 1239system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses 1240system.cpu.l2cache.overall_misses::cpu.inst 19929 # number of overall misses 1241system.cpu.l2cache.overall_misses::cpu.data 149096 # number of overall misses 1242system.cpu.l2cache.overall_misses::total 169053 # number of overall misses 1243system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2978500 # number of ReadReq miss cycles 1244system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 929000 # number of ReadReq miss cycles 1245system.cpu.l2cache.ReadReq_miss_latency::total 3907500 # number of ReadReq miss cycles 1246system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2730500 # number of UpgradeReq miss cycles 1247system.cpu.l2cache.UpgradeReq_miss_latency::total 2730500 # number of UpgradeReq miss cycles 1248system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1249system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1250system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17623320500 # number of ReadExReq miss cycles 1251system.cpu.l2cache.ReadExReq_miss_latency::total 17623320500 # number of ReadExReq miss cycles 1252system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2639049500 # number of ReadCleanReq miss cycles 1253system.cpu.l2cache.ReadCleanReq_miss_latency::total 2639049500 # number of ReadCleanReq miss cycles 1254system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1797637500 # number of ReadSharedReq miss cycles 1255system.cpu.l2cache.ReadSharedReq_miss_latency::total 1797637500 # number of ReadSharedReq miss cycles 1256system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2978500 # number of demand (read+write) miss cycles 1257system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 929000 # number of demand (read+write) miss cycles 1258system.cpu.l2cache.demand_miss_latency::cpu.inst 2639049500 # number of demand (read+write) miss cycles 1259system.cpu.l2cache.demand_miss_latency::cpu.data 19420958000 # number of demand (read+write) miss cycles 1260system.cpu.l2cache.demand_miss_latency::total 22063915000 # number of demand (read+write) miss cycles 1261system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2978500 # number of overall miss cycles 1262system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 929000 # number of overall miss cycles 1263system.cpu.l2cache.overall_miss_latency::cpu.inst 2639049500 # number of overall miss cycles 1264system.cpu.l2cache.overall_miss_latency::cpu.data 19420958000 # number of overall miss cycles 1265system.cpu.l2cache.overall_miss_latency::total 22063915000 # number of overall miss cycles 1266system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 57803 # number of ReadReq accesses(hits+misses) 1267system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12066 # number of ReadReq accesses(hits+misses) 1268system.cpu.l2cache.ReadReq_accesses::total 69869 # number of ReadReq accesses(hits+misses) 1269system.cpu.l2cache.WritebackDirty_accesses::writebacks 696134 # number of WritebackDirty accesses(hits+misses) 1270system.cpu.l2cache.WritebackDirty_accesses::total 696134 # number of WritebackDirty accesses(hits+misses) 1271system.cpu.l2cache.WritebackClean_accesses::writebacks 1848502 # number of WritebackClean accesses(hits+misses) 1272system.cpu.l2cache.WritebackClean_accesses::total 1848502 # number of WritebackClean accesses(hits+misses) 1273system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2806 # number of UpgradeReq accesses(hits+misses) 1274system.cpu.l2cache.UpgradeReq_accesses::total 2806 # number of UpgradeReq accesses(hits+misses) | 1137system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24226536497 # number of ReadReq MSHR miss cycles 1138system.cpu.icache.ReadReq_mshr_miss_latency::total 24226536497 # number of ReadReq MSHR miss cycles 1139system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24226536497 # number of demand (read+write) MSHR miss cycles 1140system.cpu.icache.demand_mshr_miss_latency::total 24226536497 # number of demand (read+write) MSHR miss cycles 1141system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24226536497 # number of overall MSHR miss cycles 1142system.cpu.icache.overall_mshr_miss_latency::total 24226536497 # number of overall MSHR miss cycles 1143system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 229048500 # number of ReadReq MSHR uncacheable cycles 1144system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 229048500 # number of ReadReq MSHR uncacheable cycles 1145system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 229048500 # number of overall MSHR uncacheable cycles 1146system.cpu.icache.overall_mshr_uncacheable_latency::total 229048500 # number of overall MSHR uncacheable cycles 1147system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for ReadReq accesses 1148system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028587 # mshr miss rate for ReadReq accesses 1149system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for demand accesses 1150system.cpu.icache.demand_mshr_miss_rate::total 0.028587 # mshr miss rate for demand accesses 1151system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028587 # mshr miss rate for overall accesses 1152system.cpu.icache.overall_mshr_miss_rate::total 0.028587 # mshr miss rate for overall accesses 1153system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12829.446437 # average ReadReq mshr miss latency 1154system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12829.446437 # average ReadReq mshr miss latency 1155system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency 1156system.cpu.icache.demand_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency 1157system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12829.446437 # average overall mshr miss latency 1158system.cpu.icache.overall_avg_mshr_miss_latency::total 12829.446437 # average overall mshr miss latency 1159system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average ReadReq mshr uncacheable latency 1160system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76273.226773 # average ReadReq mshr uncacheable latency 1161system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76273.226773 # average overall mshr uncacheable latency 1162system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76273.226773 # average overall mshr uncacheable latency 1163system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1164system.cpu.l2cache.tags.replacements 103423 # number of replacements 1165system.cpu.l2cache.tags.tagsinuse 65159.012032 # Cycle average of tags in use 1166system.cpu.l2cache.tags.total_refs 5300281 # Total number of references to valid blocks. 1167system.cpu.l2cache.tags.sampled_refs 168782 # Sample count of references to valid blocks. 1168system.cpu.l2cache.tags.avg_refs 31.403118 # Average number of references to valid blocks. 1169system.cpu.l2cache.tags.warmup_cycle 93779484000 # Cycle when the warmup percentage was hit. 1170system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 9.961762 # Average occupied blocks per requestor 1171system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.729813 # Average occupied blocks per requestor 1172system.cpu.l2cache.tags.occ_blocks::cpu.inst 10177.791609 # Average occupied blocks per requestor 1173system.cpu.l2cache.tags.occ_blocks::cpu.data 54967.528848 # Average occupied blocks per requestor 1174system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000152 # Average percentage of cache occupancy 1175system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy 1176system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155301 # Average percentage of cache occupancy 1177system.cpu.l2cache.tags.occ_percent::cpu.data 0.838738 # Average percentage of cache occupancy 1178system.cpu.l2cache.tags.occ_percent::total 0.994248 # Average percentage of cache occupancy 1179system.cpu.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1180system.cpu.l2cache.tags.occ_task_id_blocks::1024 65345 # Occupied blocks per task id 1181system.cpu.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5571 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59599 # Occupied blocks per task id 1185system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id 1186system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997086 # Percentage of cache occupancy per task id 1187system.cpu.l2cache.tags.tag_accesses 43992446 # Number of tag accesses 1188system.cpu.l2cache.tags.data_accesses 43992446 # Number of data accesses 1189system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1190system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54341 # number of ReadReq hits 1191system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10212 # number of ReadReq hits 1192system.cpu.l2cache.ReadReq_hits::total 64553 # number of ReadReq hits 1193system.cpu.l2cache.WritebackDirty_hits::writebacks 696178 # number of WritebackDirty hits 1194system.cpu.l2cache.WritebackDirty_hits::total 696178 # number of WritebackDirty hits 1195system.cpu.l2cache.WritebackClean_hits::writebacks 1850381 # number of WritebackClean hits 1196system.cpu.l2cache.WritebackClean_hits::total 1850381 # number of WritebackClean hits 1197system.cpu.l2cache.UpgradeReq_hits::cpu.data 2757 # number of UpgradeReq hits 1198system.cpu.l2cache.UpgradeReq_hits::total 2757 # number of UpgradeReq hits 1199system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1200system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1201system.cpu.l2cache.ReadExReq_hits::cpu.data 158824 # number of ReadExReq hits 1202system.cpu.l2cache.ReadExReq_hits::total 158824 # number of ReadExReq hits 1203system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1868353 # number of ReadCleanReq hits 1204system.cpu.l2cache.ReadCleanReq_hits::total 1868353 # number of ReadCleanReq hits 1205system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527348 # number of ReadSharedReq hits 1206system.cpu.l2cache.ReadSharedReq_hits::total 527348 # number of ReadSharedReq hits 1207system.cpu.l2cache.demand_hits::cpu.dtb.walker 54341 # number of demand (read+write) hits 1208system.cpu.l2cache.demand_hits::cpu.itb.walker 10212 # number of demand (read+write) hits 1209system.cpu.l2cache.demand_hits::cpu.inst 1868353 # number of demand (read+write) hits 1210system.cpu.l2cache.demand_hits::cpu.data 686172 # number of demand (read+write) hits 1211system.cpu.l2cache.demand_hits::total 2619078 # number of demand (read+write) hits 1212system.cpu.l2cache.overall_hits::cpu.dtb.walker 54341 # number of overall hits 1213system.cpu.l2cache.overall_hits::cpu.itb.walker 10212 # number of overall hits 1214system.cpu.l2cache.overall_hits::cpu.inst 1868353 # number of overall hits 1215system.cpu.l2cache.overall_hits::cpu.data 686172 # number of overall hits 1216system.cpu.l2cache.overall_hits::total 2619078 # number of overall hits 1217system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses 1218system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1219system.cpu.l2cache.ReadReq_misses::total 22 # number of ReadReq misses 1220system.cpu.l2cache.UpgradeReq_misses::cpu.data 11 # number of UpgradeReq misses 1221system.cpu.l2cache.UpgradeReq_misses::total 11 # number of UpgradeReq misses 1222system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1223system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1224system.cpu.l2cache.ReadExReq_misses::cpu.data 139010 # number of ReadExReq misses 1225system.cpu.l2cache.ReadExReq_misses::total 139010 # number of ReadExReq misses 1226system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19937 # number of ReadCleanReq misses 1227system.cpu.l2cache.ReadCleanReq_misses::total 19937 # number of ReadCleanReq misses 1228system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14436 # number of ReadSharedReq misses 1229system.cpu.l2cache.ReadSharedReq_misses::total 14436 # number of ReadSharedReq misses 1230system.cpu.l2cache.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses 1231system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1232system.cpu.l2cache.demand_misses::cpu.inst 19937 # number of demand (read+write) misses 1233system.cpu.l2cache.demand_misses::cpu.data 153446 # number of demand (read+write) misses 1234system.cpu.l2cache.demand_misses::total 173405 # number of demand (read+write) misses 1235system.cpu.l2cache.overall_misses::cpu.dtb.walker 16 # number of overall misses 1236system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1237system.cpu.l2cache.overall_misses::cpu.inst 19937 # number of overall misses 1238system.cpu.l2cache.overall_misses::cpu.data 153446 # number of overall misses 1239system.cpu.l2cache.overall_misses::total 173405 # number of overall misses 1240system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1497500 # number of ReadReq miss cycles 1241system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 502000 # number of ReadReq miss cycles 1242system.cpu.l2cache.ReadReq_miss_latency::total 1999500 # number of ReadReq miss cycles 1243system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles 1244system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles 1245system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 167000 # number of SCUpgradeReq miss cycles 1246system.cpu.l2cache.SCUpgradeReq_miss_latency::total 167000 # number of SCUpgradeReq miss cycles 1247system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11275740500 # number of ReadExReq miss cycles 1248system.cpu.l2cache.ReadExReq_miss_latency::total 11275740500 # number of ReadExReq miss cycles 1249system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1659086000 # number of ReadCleanReq miss cycles 1250system.cpu.l2cache.ReadCleanReq_miss_latency::total 1659086000 # number of ReadCleanReq miss cycles 1251system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1242944500 # number of ReadSharedReq miss cycles 1252system.cpu.l2cache.ReadSharedReq_miss_latency::total 1242944500 # number of ReadSharedReq miss cycles 1253system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1497500 # number of demand (read+write) miss cycles 1254system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 502000 # number of demand (read+write) miss cycles 1255system.cpu.l2cache.demand_miss_latency::cpu.inst 1659086000 # number of demand (read+write) miss cycles 1256system.cpu.l2cache.demand_miss_latency::cpu.data 12518685000 # number of demand (read+write) miss cycles 1257system.cpu.l2cache.demand_miss_latency::total 14179770500 # number of demand (read+write) miss cycles 1258system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1497500 # number of overall miss cycles 1259system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 502000 # number of overall miss cycles 1260system.cpu.l2cache.overall_miss_latency::cpu.inst 1659086000 # number of overall miss cycles 1261system.cpu.l2cache.overall_miss_latency::cpu.data 12518685000 # number of overall miss cycles 1262system.cpu.l2cache.overall_miss_latency::total 14179770500 # number of overall miss cycles 1263system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54357 # number of ReadReq accesses(hits+misses) 1264system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10218 # number of ReadReq accesses(hits+misses) 1265system.cpu.l2cache.ReadReq_accesses::total 64575 # number of ReadReq accesses(hits+misses) 1266system.cpu.l2cache.WritebackDirty_accesses::writebacks 696178 # number of WritebackDirty accesses(hits+misses) 1267system.cpu.l2cache.WritebackDirty_accesses::total 696178 # number of WritebackDirty accesses(hits+misses) 1268system.cpu.l2cache.WritebackClean_accesses::writebacks 1850381 # number of WritebackClean accesses(hits+misses) 1269system.cpu.l2cache.WritebackClean_accesses::total 1850381 # number of WritebackClean accesses(hits+misses) 1270system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) 1271system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) |
| 1275system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1276system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) | 1272system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1273system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) |
| 1277system.cpu.l2cache.ReadExReq_accesses::cpu.data 297337 # number of ReadExReq accesses(hits+misses) 1278system.cpu.l2cache.ReadExReq_accesses::total 297337 # number of ReadExReq accesses(hits+misses) 1279system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886900 # number of ReadCleanReq accesses(hits+misses) 1280system.cpu.l2cache.ReadCleanReq_accesses::total 1886900 # number of ReadCleanReq accesses(hits+misses) 1281system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541309 # number of ReadSharedReq accesses(hits+misses) 1282system.cpu.l2cache.ReadSharedReq_accesses::total 541309 # number of ReadSharedReq accesses(hits+misses) 1283system.cpu.l2cache.demand_accesses::cpu.dtb.walker 57803 # number of demand (read+write) accesses 1284system.cpu.l2cache.demand_accesses::cpu.itb.walker 12066 # number of demand (read+write) accesses 1285system.cpu.l2cache.demand_accesses::cpu.inst 1886900 # number of demand (read+write) accesses 1286system.cpu.l2cache.demand_accesses::cpu.data 838646 # number of demand (read+write) accesses 1287system.cpu.l2cache.demand_accesses::total 2795415 # number of demand (read+write) accesses 1288system.cpu.l2cache.overall_accesses::cpu.dtb.walker 57803 # number of overall (read+write) accesses 1289system.cpu.l2cache.overall_accesses::cpu.itb.walker 12066 # number of overall (read+write) accesses 1290system.cpu.l2cache.overall_accesses::cpu.inst 1886900 # number of overall (read+write) accesses 1291system.cpu.l2cache.overall_accesses::cpu.data 838646 # number of overall (read+write) accesses 1292system.cpu.l2cache.overall_accesses::total 2795415 # number of overall (read+write) accesses 1293system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000363 # miss rate for ReadReq accesses 1294system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000580 # miss rate for ReadReq accesses 1295system.cpu.l2cache.ReadReq_miss_rate::total 0.000401 # miss rate for ReadReq accesses 1296system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.978617 # miss rate for UpgradeReq accesses 1297system.cpu.l2cache.UpgradeReq_miss_rate::total 0.978617 # miss rate for UpgradeReq accesses 1298system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 1299system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 1300system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.456516 # miss rate for ReadExReq accesses 1301system.cpu.l2cache.ReadExReq_miss_rate::total 0.456516 # miss rate for ReadExReq accesses 1302system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010562 # miss rate for ReadCleanReq accesses 1303system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010562 # miss rate for ReadCleanReq accesses 1304system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024675 # miss rate for ReadSharedReq accesses 1305system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024675 # miss rate for ReadSharedReq accesses 1306system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000363 # miss rate for demand accesses 1307system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000580 # miss rate for demand accesses 1308system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010562 # miss rate for demand accesses 1309system.cpu.l2cache.demand_miss_rate::cpu.data 0.177782 # miss rate for demand accesses 1310system.cpu.l2cache.demand_miss_rate::total 0.060475 # miss rate for demand accesses 1311system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000363 # miss rate for overall accesses 1312system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000580 # miss rate for overall accesses 1313system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010562 # miss rate for overall accesses 1314system.cpu.l2cache.overall_miss_rate::cpu.data 0.177782 # miss rate for overall accesses 1315system.cpu.l2cache.overall_miss_rate::total 0.060475 # miss rate for overall accesses 1316system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 141833.333333 # average ReadReq miss latency 1317system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132714.285714 # average ReadReq miss latency 1318system.cpu.l2cache.ReadReq_avg_miss_latency::total 139553.571429 # average ReadReq miss latency 1319system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 994.355426 # average UpgradeReq miss latency 1320system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 994.355426 # average UpgradeReq miss latency 1321system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1322system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1323system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129832.402626 # average ReadExReq miss latency 1324system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129832.402626 # average ReadExReq miss latency 1325system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132422.575142 # average ReadCleanReq miss latency 1326system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132422.575142 # average ReadCleanReq miss latency 1327system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134583.926031 # average ReadSharedReq miss latency 1328system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134583.926031 # average ReadSharedReq miss latency 1329system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 141833.333333 # average overall miss latency 1330system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132714.285714 # average overall miss latency 1331system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132422.575142 # average overall miss latency 1332system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130258.075334 # average overall miss latency 1333system.cpu.l2cache.demand_avg_miss_latency::total 130514.779389 # average overall miss latency 1334system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 141833.333333 # average overall miss latency 1335system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132714.285714 # average overall miss latency 1336system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132422.575142 # average overall miss latency 1337system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130258.075334 # average overall miss latency 1338system.cpu.l2cache.overall_avg_miss_latency::total 130514.779389 # average overall miss latency | 1274system.cpu.l2cache.ReadExReq_accesses::cpu.data 297834 # number of ReadExReq accesses(hits+misses) 1275system.cpu.l2cache.ReadExReq_accesses::total 297834 # number of ReadExReq accesses(hits+misses) 1276system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1888290 # number of ReadCleanReq accesses(hits+misses) 1277system.cpu.l2cache.ReadCleanReq_accesses::total 1888290 # number of ReadCleanReq accesses(hits+misses) 1278system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 541784 # number of ReadSharedReq accesses(hits+misses) 1279system.cpu.l2cache.ReadSharedReq_accesses::total 541784 # number of ReadSharedReq accesses(hits+misses) 1280system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54357 # number of demand (read+write) accesses 1281system.cpu.l2cache.demand_accesses::cpu.itb.walker 10218 # number of demand (read+write) accesses 1282system.cpu.l2cache.demand_accesses::cpu.inst 1888290 # number of demand (read+write) accesses 1283system.cpu.l2cache.demand_accesses::cpu.data 839618 # number of demand (read+write) accesses 1284system.cpu.l2cache.demand_accesses::total 2792483 # number of demand (read+write) accesses 1285system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54357 # number of overall (read+write) accesses 1286system.cpu.l2cache.overall_accesses::cpu.itb.walker 10218 # number of overall (read+write) accesses 1287system.cpu.l2cache.overall_accesses::cpu.inst 1888290 # number of overall (read+write) accesses 1288system.cpu.l2cache.overall_accesses::cpu.data 839618 # number of overall (read+write) accesses 1289system.cpu.l2cache.overall_accesses::total 2792483 # number of overall (read+write) accesses 1290system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000294 # miss rate for ReadReq accesses 1291system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000587 # miss rate for ReadReq accesses 1292system.cpu.l2cache.ReadReq_miss_rate::total 0.000341 # miss rate for ReadReq accesses 1293system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003974 # miss rate for UpgradeReq accesses 1294system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003974 # miss rate for UpgradeReq accesses 1295system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1296system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 1297system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.466737 # miss rate for ReadExReq accesses 1298system.cpu.l2cache.ReadExReq_miss_rate::total 0.466737 # miss rate for ReadExReq accesses 1299system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010558 # miss rate for ReadCleanReq accesses 1300system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010558 # miss rate for ReadCleanReq accesses 1301system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026645 # miss rate for ReadSharedReq accesses 1302system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026645 # miss rate for ReadSharedReq accesses 1303system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000294 # miss rate for demand accesses 1304system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000587 # miss rate for demand accesses 1305system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010558 # miss rate for demand accesses 1306system.cpu.l2cache.demand_miss_rate::cpu.data 0.182757 # miss rate for demand accesses 1307system.cpu.l2cache.demand_miss_rate::total 0.062097 # miss rate for demand accesses 1308system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000294 # miss rate for overall accesses 1309system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000587 # miss rate for overall accesses 1310system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010558 # miss rate for overall accesses 1311system.cpu.l2cache.overall_miss_rate::cpu.data 0.182757 # miss rate for overall accesses 1312system.cpu.l2cache.overall_miss_rate::total 0.062097 # miss rate for overall accesses 1313system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93593.750000 # average ReadReq miss latency 1314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83666.666667 # average ReadReq miss latency 1315system.cpu.l2cache.ReadReq_avg_miss_latency::total 90886.363636 # average ReadReq miss latency 1316system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 29136.363636 # average UpgradeReq miss latency 1317system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 29136.363636 # average UpgradeReq miss latency 1318system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 83500 # average SCUpgradeReq miss latency 1319system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 83500 # average SCUpgradeReq miss latency 1320system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81114.599669 # average ReadExReq miss latency 1321system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81114.599669 # average ReadExReq miss latency 1322system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83216.431760 # average ReadCleanReq miss latency 1323system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83216.431760 # average ReadCleanReq miss latency 1324system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86100.339429 # average ReadSharedReq miss latency 1325system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86100.339429 # average ReadSharedReq miss latency 1326system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency 1327system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency 1328system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency 1329system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency 1330system.cpu.l2cache.demand_avg_miss_latency::total 81772.558461 # average overall miss latency 1331system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93593.750000 # average overall miss latency 1332system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83666.666667 # average overall miss latency 1333system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83216.431760 # average overall miss latency 1334system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81583.651578 # average overall miss latency 1335system.cpu.l2cache.overall_avg_miss_latency::total 81772.558461 # average overall miss latency |
| 1339system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1340system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1341system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1342system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1343system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1344system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1336system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1337system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1338system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1339system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1340system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1341system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1345system.cpu.l2cache.writebacks::writebacks 89296 # number of writebacks 1346system.cpu.l2cache.writebacks::total 89296 # number of writebacks 1347system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1348system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits | 1342system.cpu.l2cache.writebacks::writebacks 95172 # number of writebacks 1343system.cpu.l2cache.writebacks::total 95172 # number of writebacks 1344system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 23 # number of ReadCleanReq MSHR hits 1345system.cpu.l2cache.ReadCleanReq_mshr_hits::total 23 # number of ReadCleanReq MSHR hits |
| 1349system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits 1350system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits | 1346system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits 1347system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits |
| 1351system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits | 1348system.cpu.l2cache.demand_mshr_hits::cpu.inst 23 # number of demand (read+write) MSHR hits |
| 1352system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits | 1349system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits |
| 1353system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits 1354system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits | 1350system.cpu.l2cache.demand_mshr_hits::total 135 # number of demand (read+write) MSHR hits 1351system.cpu.l2cache.overall_mshr_hits::cpu.inst 23 # number of overall MSHR hits |
| 1355system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits | 1352system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits |
| 1356system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits 1357system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses 1358system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses 1359system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses 1360system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2746 # number of UpgradeReq MSHR misses 1361system.cpu.l2cache.UpgradeReq_mshr_misses::total 2746 # number of UpgradeReq MSHR misses 1362system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1363system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1364system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135739 # number of ReadExReq MSHR misses 1365system.cpu.l2cache.ReadExReq_mshr_misses::total 135739 # number of ReadExReq MSHR misses 1366system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19903 # number of ReadCleanReq MSHR misses 1367system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19903 # number of ReadCleanReq MSHR misses 1368system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13245 # number of ReadSharedReq MSHR misses 1369system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13245 # number of ReadSharedReq MSHR misses 1370system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses 1371system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses 1372system.cpu.l2cache.demand_mshr_misses::cpu.inst 19903 # number of demand (read+write) MSHR misses 1373system.cpu.l2cache.demand_mshr_misses::cpu.data 148984 # number of demand (read+write) MSHR misses 1374system.cpu.l2cache.demand_mshr_misses::total 168915 # number of demand (read+write) MSHR misses 1375system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 1376system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1377system.cpu.l2cache.overall_mshr_misses::cpu.inst 19903 # number of overall MSHR misses 1378system.cpu.l2cache.overall_mshr_misses::cpu.data 148984 # number of overall MSHR misses 1379system.cpu.l2cache.overall_mshr_misses::total 168915 # number of overall MSHR misses | 1353system.cpu.l2cache.overall_mshr_hits::total 135 # number of overall MSHR hits 1354system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 16 # number of ReadReq MSHR misses 1355system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1356system.cpu.l2cache.ReadReq_mshr_misses::total 22 # number of ReadReq MSHR misses 1357system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 11 # number of UpgradeReq MSHR misses 1358system.cpu.l2cache.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses 1359system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1360system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1361system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 139010 # number of ReadExReq MSHR misses 1362system.cpu.l2cache.ReadExReq_mshr_misses::total 139010 # number of ReadExReq MSHR misses 1363system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19914 # number of ReadCleanReq MSHR misses 1364system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19914 # number of ReadCleanReq MSHR misses 1365system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14324 # number of ReadSharedReq MSHR misses 1366system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14324 # number of ReadSharedReq MSHR misses 1367system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 16 # number of demand (read+write) MSHR misses 1368system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1369system.cpu.l2cache.demand_mshr_misses::cpu.inst 19914 # number of demand (read+write) MSHR misses 1370system.cpu.l2cache.demand_mshr_misses::cpu.data 153334 # number of demand (read+write) MSHR misses 1371system.cpu.l2cache.demand_mshr_misses::total 173270 # number of demand (read+write) MSHR misses 1372system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 16 # number of overall MSHR misses 1373system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1374system.cpu.l2cache.overall_mshr_misses::cpu.inst 19914 # number of overall MSHR misses 1375system.cpu.l2cache.overall_mshr_misses::cpu.data 153334 # number of overall MSHR misses 1376system.cpu.l2cache.overall_mshr_misses::total 173270 # number of overall MSHR misses |
| 1380system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable | 1377system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable |
| 1381system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1382system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable 1383system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1384system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable | 1378system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1379system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34130 # number of ReadReq MSHR uncacheable 1380system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1381system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable |
| 1385system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses | 1382system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses |
| 1386system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1387system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses 1388system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2768500 # number of ReadReq MSHR miss cycles 1389system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 859000 # number of ReadReq MSHR miss cycles 1390system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3627500 # number of ReadReq MSHR miss cycles 1391system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 186762000 # number of UpgradeReq MSHR miss cycles 1392system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 186762000 # number of UpgradeReq MSHR miss cycles 1393system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 210500 # number of SCUpgradeReq MSHR miss cycles 1394system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 210500 # number of SCUpgradeReq MSHR miss cycles 1395system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16265930500 # number of ReadExReq MSHR miss cycles 1396system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16265930500 # number of ReadExReq MSHR miss cycles 1397system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2437107003 # number of ReadCleanReq MSHR miss cycles 1398system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2437107003 # number of ReadCleanReq MSHR miss cycles 1399system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1651792000 # number of ReadSharedReq MSHR miss cycles 1400system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1651792000 # number of ReadSharedReq MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2768500 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 859000 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2437107003 # number of demand (read+write) MSHR miss cycles 1404system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17917722500 # number of demand (read+write) MSHR miss cycles 1405system.cpu.l2cache.demand_mshr_miss_latency::total 20358457003 # number of demand (read+write) MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2768500 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 859000 # number of overall MSHR miss cycles 1408system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2437107003 # number of overall MSHR miss cycles 1409system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17917722500 # number of overall MSHR miss cycles 1410system.cpu.l2cache.overall_mshr_miss_latency::total 20358457003 # number of overall MSHR miss cycles 1411system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles 1412system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887129500 # number of ReadReq MSHR uncacheable cycles 1413system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227197000 # number of ReadReq MSHR uncacheable cycles 1414system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles 1415system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887129500 # number of overall MSHR uncacheable cycles 1416system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227197000 # number of overall MSHR uncacheable cycles 1417system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for ReadReq accesses 1418system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for ReadReq accesses 1419system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000401 # mshr miss rate for ReadReq accesses 1420system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.978617 # mshr miss rate for UpgradeReq accesses 1421system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.978617 # mshr miss rate for UpgradeReq accesses 1422system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 1423system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 1424system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.456516 # mshr miss rate for ReadExReq accesses 1425system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.456516 # mshr miss rate for ReadExReq accesses 1426system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for ReadCleanReq accesses 1427system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010548 # mshr miss rate for ReadCleanReq accesses 1428system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024468 # mshr miss rate for ReadSharedReq accesses 1429system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024468 # mshr miss rate for ReadSharedReq accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for demand accesses 1432system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for demand accesses 1433system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for demand accesses 1434system.cpu.l2cache.demand_mshr_miss_rate::total 0.060426 # mshr miss rate for demand accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000363 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000580 # mshr miss rate for overall accesses 1437system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010548 # mshr miss rate for overall accesses 1438system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177648 # mshr miss rate for overall accesses 1439system.cpu.l2cache.overall_mshr_miss_rate::total 0.060426 # mshr miss rate for overall accesses 1440system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average ReadReq mshr miss latency 1441system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average ReadReq mshr miss latency 1442system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129553.571429 # average ReadReq mshr miss latency 1443system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.381646 # average UpgradeReq mshr miss latency 1444system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.381646 # average UpgradeReq mshr miss latency 1445system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70166.666667 # average SCUpgradeReq mshr miss latency 1446system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70166.666667 # average SCUpgradeReq mshr miss latency 1447system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119832.402626 # average ReadExReq mshr miss latency 1448system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119832.402626 # average ReadExReq mshr miss latency 1449system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122449.228910 # average ReadCleanReq mshr miss latency 1450system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122449.228910 # average ReadCleanReq mshr miss latency 1451system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124710.607777 # average ReadSharedReq mshr miss latency 1452system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124710.607777 # average ReadSharedReq mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency 1455system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency 1456system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency 1457system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131833.333333 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122714.285714 # average overall mshr miss latency 1460system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122449.228910 # average overall mshr miss latency 1461system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120266.085620 # average overall mshr miss latency 1462system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120524.861635 # average overall mshr miss latency 1463system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency 1464system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.418260 # average ReadReq mshr uncacheable latency 1465system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182444.538849 # average ReadReq mshr uncacheable latency 1466system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency 1467system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100267.900330 # average overall mshr uncacheable latency 1468system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.217396 # average overall mshr uncacheable latency 1469system.cpu.toL2Bus.snoop_filter.tot_requests 5483160 # Total number of requests made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757544 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1471system.cpu.toL2Bus.snoop_filter.hit_multi_requests 45002 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1472system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. 1473system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1383system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1384system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61714 # number of overall MSHR uncacheable misses 1385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1337500 # number of ReadReq MSHR miss cycles 1386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 442000 # number of ReadReq MSHR miss cycles 1387system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1779500 # number of ReadReq MSHR miss cycles 1388system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 210500 # number of UpgradeReq MSHR miss cycles 1389system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 210500 # number of UpgradeReq MSHR miss cycles 1390system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 147000 # number of SCUpgradeReq MSHR miss cycles 1391system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 147000 # number of SCUpgradeReq MSHR miss cycles 1392system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9885640500 # number of ReadExReq MSHR miss cycles 1393system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9885640500 # number of ReadExReq MSHR miss cycles 1394system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1458480000 # number of ReadCleanReq MSHR miss cycles 1395system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1458480000 # number of ReadCleanReq MSHR miss cycles 1396system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1091561500 # number of ReadSharedReq MSHR miss cycles 1397system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1091561500 # number of ReadSharedReq MSHR miss cycles 1398system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1337500 # number of demand (read+write) MSHR miss cycles 1399system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 442000 # number of demand (read+write) MSHR miss cycles 1400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1458480000 # number of demand (read+write) MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10977202000 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::total 12437461500 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1337500 # number of overall MSHR miss cycles 1404system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 442000 # number of overall MSHR miss cycles 1405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1458480000 # number of overall MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10977202000 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::total 12437461500 # number of overall MSHR miss cycles 1408system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191510500 # number of ReadReq MSHR uncacheable cycles 1409system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5890404500 # number of ReadReq MSHR uncacheable cycles 1410system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6081915000 # number of ReadReq MSHR uncacheable cycles 1411system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191510500 # number of overall MSHR uncacheable cycles 1412system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5890404500 # number of overall MSHR uncacheable cycles 1413system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6081915000 # number of overall MSHR uncacheable cycles 1414system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for ReadReq accesses 1415system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for ReadReq accesses 1416system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000341 # mshr miss rate for ReadReq accesses 1417system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.003974 # mshr miss rate for UpgradeReq accesses 1418system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.003974 # mshr miss rate for UpgradeReq accesses 1419system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1420system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 1421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.466737 # mshr miss rate for ReadExReq accesses 1422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.466737 # mshr miss rate for ReadExReq accesses 1423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for ReadCleanReq accesses 1424system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010546 # mshr miss rate for ReadCleanReq accesses 1425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026439 # mshr miss rate for ReadSharedReq accesses 1426system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026439 # mshr miss rate for ReadSharedReq accesses 1427system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for demand accesses 1428system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for demand accesses 1429system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for demand accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::total 0.062049 # mshr miss rate for demand accesses 1432system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000294 # mshr miss rate for overall accesses 1433system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000587 # mshr miss rate for overall accesses 1434system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010546 # mshr miss rate for overall accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.182624 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::total 0.062049 # mshr miss rate for overall accesses 1437system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average ReadReq mshr miss latency 1438system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average ReadReq mshr miss latency 1439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 80886.363636 # average ReadReq mshr miss latency 1440system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19136.363636 # average UpgradeReq mshr miss latency 1441system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19136.363636 # average UpgradeReq mshr miss latency 1442system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 73500 # average SCUpgradeReq mshr miss latency 1443system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 73500 # average SCUpgradeReq mshr miss latency 1444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71114.599669 # average ReadExReq mshr miss latency 1445system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71114.599669 # average ReadExReq mshr miss latency 1446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73238.927388 # average ReadCleanReq mshr miss latency 1447system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73238.927388 # average ReadCleanReq mshr miss latency 1448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76205.075398 # average ReadSharedReq mshr miss latency 1449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76205.075398 # average ReadSharedReq mshr miss latency 1450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency 1451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency 1452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency 1455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83593.750000 # average overall mshr miss latency 1456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73666.666667 # average overall mshr miss latency 1457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73238.927388 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.136565 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71780.813182 # average overall mshr miss latency 1460system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average ReadReq mshr uncacheable latency 1461system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189237.783917 # average ReadReq mshr uncacheable latency 1462system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 178198.505713 # average ReadReq mshr uncacheable latency 1463system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 63773.060273 # average overall mshr uncacheable latency 1464system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100328.805505 # average overall mshr uncacheable latency 1465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 98550.004861 # average overall mshr uncacheable latency 1466system.cpu.toL2Bus.snoop_filter.tot_requests 5488560 # Total number of requests made to the snoop filter. 1467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2760615 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44763 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1469system.cpu.toL2Bus.snoop_filter.tot_snoops 238 # Total number of snoops made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 238 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1474system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1475system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1476system.cpu.toL2Bus.trans_dist::ReadReq 128619 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::ReadResp 2557060 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::WritebackDirty 821637 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::WritebackClean 1886431 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::CleanEvict 149968 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::UpgradeReq 2806 # Transaction distribution | 1472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1473system.cpu.toL2Bus.trans_dist::ReadReq 129622 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::ReadResp 2559974 # Transaction distribution 1475system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::WritebackDirty 791350 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WritebackClean 1887810 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::CleanEvict 151157 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution |
| 1484system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution | 1481system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution |
| 1485system.cpu.toL2Bus.trans_dist::UpgradeResp 2811 # Transaction distribution 1486system.cpu.toL2Bus.trans_dist::ReadExReq 297337 # Transaction distribution 1487system.cpu.toL2Bus.trans_dist::ReadExResp 297337 # Transaction distribution 1488system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887001 # Transaction distribution 1489system.cpu.toL2Bus.trans_dist::ReadSharedReq 541532 # Transaction distribution 1490system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1491system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5666337 # Packet count per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2638583 # Packet count per connected master and slave (bytes) 1493system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30857 # Packet count per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133499 # Packet count per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_count::total 8469276 # Packet count per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241541168 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98417449 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) 1499system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 231212 # Cumulative packet size per connected master and slave (bytes) 1500system.cpu.toL2Bus.pkt_size::total 340238093 # Cumulative packet size per connected master and slave (bytes) 1501system.cpu.toL2Bus.snoops 194794 # Total snoops (count) 1502system.cpu.toL2Bus.snoopTraffic 8145576 # Total snoop traffic (bytes) 1503system.cpu.toL2Bus.snoop_fanout::samples 3054607 # Request fanout histogram 1504system.cpu.toL2Bus.snoop_fanout::mean 0.024758 # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::stdev 0.155386 # Request fanout histogram | 1482system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::ReadExReq 297834 # Transaction distribution 1484system.cpu.toL2Bus.trans_dist::ReadExResp 297834 # Transaction distribution 1485system.cpu.toL2Bus.trans_dist::ReadCleanReq 1888354 # Transaction distribution 1486system.cpu.toL2Bus.trans_dist::ReadSharedReq 542004 # Transaction distribution 1487system.cpu.toL2Bus.trans_dist::InvalidateReq 4368 # Transaction distribution 1488system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5670459 # Packet count per connected master and slave (bytes) 1489system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2641503 # Packet count per connected master and slave (bytes) 1490system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 29194 # Packet count per connected master and slave (bytes) 1491system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130873 # Packet count per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_count::total 8472029 # Packet count per connected master and slave (bytes) 1493system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241718384 # Cumulative packet size per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98487773 # Cumulative packet size per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40872 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 217428 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size::total 340464457 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.snoops 139207 # Total snoops (count) 1499system.cpu.toL2Bus.snoopTraffic 6232532 # Total snoop traffic (bytes) 1500system.cpu.toL2Bus.snoop_fanout::samples 2995964 # Request fanout histogram 1501system.cpu.toL2Bus.snoop_fanout::mean 0.025358 # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::stdev 0.157210 # Request fanout histogram |
| 1506system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1503system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1507system.cpu.toL2Bus.snoop_fanout::0 2978982 97.52% 97.52% # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::1 75625 2.48% 100.00% # Request fanout histogram | 1504system.cpu.toL2Bus.snoop_fanout::0 2919992 97.46% 97.46% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::1 75972 2.54% 100.00% # Request fanout histogram |
| 1509system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1510system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1511system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1512system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1506system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1509system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1513system.cpu.toL2Bus.snoop_fanout::total 3054607 # Request fanout histogram 1514system.cpu.toL2Bus.reqLayer0.occupancy 5400960498 # Layer occupancy (ticks) | 1510system.cpu.toL2Bus.snoop_fanout::total 2995964 # Request fanout histogram 1511system.cpu.toL2Bus.reqLayer0.occupancy 5405204997 # Layer occupancy (ticks) |
| 1515system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) | 1512system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| 1516system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) | 1513system.cpu.toL2Bus.snoopLayer0.occupancy 383377 # Layer occupancy (ticks) |
| 1517system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1514system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1518system.cpu.toL2Bus.respLayer0.occupancy 2834452098 # Layer occupancy (ticks) | 1515system.cpu.toL2Bus.respLayer0.occupancy 2836467127 # Layer occupancy (ticks) |
| 1519system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1516system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1520system.cpu.toL2Bus.respLayer1.occupancy 1304519551 # Layer occupancy (ticks) | 1517system.cpu.toL2Bus.respLayer1.occupancy 1305988986 # Layer occupancy (ticks) |
| 1521system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1518system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1522system.cpu.toL2Bus.respLayer2.occupancy 18799483 # Layer occupancy (ticks) | 1519system.cpu.toL2Bus.respLayer2.occupancy 18982487 # Layer occupancy (ticks) |
| 1523system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1520system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1524system.cpu.toL2Bus.respLayer3.occupancy 75755880 # Layer occupancy (ticks) | 1521system.cpu.toL2Bus.respLayer3.occupancy 76565899 # Layer occupancy (ticks) |
| 1525system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1522system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1526system.iobus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1527system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1528system.iobus.trans_dist::ReadResp 30172 # Transaction distribution | 1523system.iobus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1524system.iobus.trans_dist::ReadReq 30182 # Transaction distribution 1525system.iobus.trans_dist::ReadResp 30182 # Transaction distribution |
| 1529system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1530system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1531system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1536system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1543system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) | 1526system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1527system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1528system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 1540system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1541system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1542system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1543system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) |
| 1551system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) 1552system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) 1553system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) | 1548system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) |
| 1554system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1566system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) | 1551system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1563system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1574system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) 1575system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) 1576system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) 1577system.iobus.reqLayer0.occupancy 43088500 # Layer occupancy (ticks) | 1571system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) 1574system.iobus.reqLayer0.occupancy 43094500 # Layer occupancy (ticks) |
| 1578system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1575system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1579system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) | 1576system.iobus.reqLayer1.occupancy 101000 # Layer occupancy (ticks) |
| 1580system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1577system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1581system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) | 1578system.iobus.reqLayer2.occupancy 325500 # Layer occupancy (ticks) |
| 1582system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1579system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1583system.iobus.reqLayer3.occupancy 28000 # Layer occupancy (ticks) | 1580system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) |
| 1584system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 1586system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 1581system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1582system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) 1583system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 1587system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) | 1584system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) |
| 1588system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) | 1585system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) |
| 1589system.iobus.reqLayer8.occupancy 651500 # Layer occupancy (ticks) | 1586system.iobus.reqLayer8.occupancy 649500 # Layer occupancy (ticks) |
| 1590system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1591system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1592system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1593system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1594system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1595system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 1596system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1597system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1603system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1604system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1605system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1606system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1607system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1608system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1609system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1610system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) | 1587system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1588system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1589system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1590system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1591system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1592system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 1593system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1594system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) --- 5 unchanged lines hidden (view full) --- 1600system.iobus.reqLayer18.occupancy 9000 # Layer occupancy (ticks) 1601system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1602system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1603system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1604system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1605system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1606system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) 1607system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) |
| 1611system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) | 1608system.iobus.reqLayer23.occupancy 6172500 # Layer occupancy (ticks) |
| 1612system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 1609system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 1613system.iobus.reqLayer24.occupancy 33063500 # Layer occupancy (ticks) | 1610system.iobus.reqLayer24.occupancy 33854000 # Layer occupancy (ticks) |
| 1614system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 1611system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 1615system.iobus.reqLayer25.occupancy 187149991 # Layer occupancy (ticks) | 1612system.iobus.reqLayer25.occupancy 187760330 # Layer occupancy (ticks) |
| 1616system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1617system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1618system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1613system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1614system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1615system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1619system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) | 1616system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) |
| 1620system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1617system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1621system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1622system.iocache.tags.replacements 36413 # number of replacements 1623system.iocache.tags.tagsinuse 1.005857 # Cycle average of tags in use | 1618system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1619system.iocache.tags.replacements 36423 # number of replacements 1620system.iocache.tags.tagsinuse 1.000676 # Cycle average of tags in use |
| 1624system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1621system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1625system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. | 1622system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. |
| 1626system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1623system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1627system.iocache.tags.warmup_cycle 256506730000 # Cycle when the warmup percentage was hit. 1628system.iocache.tags.occ_blocks::realview.ide 1.005857 # Average occupied blocks per requestor 1629system.iocache.tags.occ_percent::realview.ide 0.062866 # Average percentage of cache occupancy 1630system.iocache.tags.occ_percent::total 0.062866 # Average percentage of cache occupancy | 1624system.iocache.tags.warmup_cycle 252706881000 # Cycle when the warmup percentage was hit. 1625system.iocache.tags.occ_blocks::realview.ide 1.000676 # Average occupied blocks per requestor 1626system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy 1627system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy |
| 1631system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1632system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1633system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1628system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1629system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1630system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1634system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1635system.iocache.tags.data_accesses 328023 # Number of data accesses 1636system.iocache.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1637system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1638system.iocache.ReadReq_misses::total 223 # number of ReadReq misses | 1631system.iocache.tags.tag_accesses 328113 # Number of tag accesses 1632system.iocache.tags.data_accesses 328113 # Number of data accesses 1633system.iocache.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1634system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses 1635system.iocache.ReadReq_misses::total 233 # number of ReadReq misses |
| 1639system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1640system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses | 1636system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1637system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
| 1641system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses 1642system.iocache.demand_misses::total 36447 # number of demand (read+write) misses 1643system.iocache.overall_misses::realview.ide 36447 # number of overall misses 1644system.iocache.overall_misses::total 36447 # number of overall misses 1645system.iocache.ReadReq_miss_latency::realview.ide 28156877 # number of ReadReq miss cycles 1646system.iocache.ReadReq_miss_latency::total 28156877 # number of ReadReq miss cycles 1647system.iocache.WriteLineReq_miss_latency::realview.ide 4551348114 # number of WriteLineReq miss cycles 1648system.iocache.WriteLineReq_miss_latency::total 4551348114 # number of WriteLineReq miss cycles 1649system.iocache.demand_miss_latency::realview.ide 4579504991 # number of demand (read+write) miss cycles 1650system.iocache.demand_miss_latency::total 4579504991 # number of demand (read+write) miss cycles 1651system.iocache.overall_miss_latency::realview.ide 4579504991 # number of overall miss cycles 1652system.iocache.overall_miss_latency::total 4579504991 # number of overall miss cycles 1653system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) 1654system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) | 1638system.iocache.demand_misses::realview.ide 36457 # number of demand (read+write) misses 1639system.iocache.demand_misses::total 36457 # number of demand (read+write) misses 1640system.iocache.overall_misses::realview.ide 36457 # number of overall misses 1641system.iocache.overall_misses::total 36457 # number of overall misses 1642system.iocache.ReadReq_miss_latency::realview.ide 28964877 # number of ReadReq miss cycles 1643system.iocache.ReadReq_miss_latency::total 28964877 # number of ReadReq miss cycles 1644system.iocache.WriteLineReq_miss_latency::realview.ide 4277512453 # number of WriteLineReq miss cycles 1645system.iocache.WriteLineReq_miss_latency::total 4277512453 # number of WriteLineReq miss cycles 1646system.iocache.demand_miss_latency::realview.ide 4306477330 # number of demand (read+write) miss cycles 1647system.iocache.demand_miss_latency::total 4306477330 # number of demand (read+write) miss cycles 1648system.iocache.overall_miss_latency::realview.ide 4306477330 # number of overall miss cycles 1649system.iocache.overall_miss_latency::total 4306477330 # number of overall miss cycles 1650system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) 1651system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) |
| 1655system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1656system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) | 1652system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1653system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
| 1657system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses 1658system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses 1659system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses 1660system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses | 1654system.iocache.demand_accesses::realview.ide 36457 # number of demand (read+write) accesses 1655system.iocache.demand_accesses::total 36457 # number of demand (read+write) accesses 1656system.iocache.overall_accesses::realview.ide 36457 # number of overall (read+write) accesses 1657system.iocache.overall_accesses::total 36457 # number of overall (read+write) accesses |
| 1661system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1662system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1663system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1664system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1665system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1666system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1667system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1668system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1658system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1659system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1660system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1661system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1662system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1663system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1664system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1665system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1669system.iocache.ReadReq_avg_miss_latency::realview.ide 126264.022422 # average ReadReq miss latency 1670system.iocache.ReadReq_avg_miss_latency::total 126264.022422 # average ReadReq miss latency 1671system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125644.548200 # average WriteLineReq miss latency 1672system.iocache.WriteLineReq_avg_miss_latency::total 125644.548200 # average WriteLineReq miss latency 1673system.iocache.demand_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency 1674system.iocache.demand_avg_miss_latency::total 125648.338437 # average overall miss latency 1675system.iocache.overall_avg_miss_latency::realview.ide 125648.338437 # average overall miss latency 1676system.iocache.overall_avg_miss_latency::total 125648.338437 # average overall miss latency | 1666system.iocache.ReadReq_avg_miss_latency::realview.ide 124312.776824 # average ReadReq miss latency 1667system.iocache.ReadReq_avg_miss_latency::total 124312.776824 # average ReadReq miss latency 1668system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.039007 # average WriteLineReq miss latency 1669system.iocache.WriteLineReq_avg_miss_latency::total 118085.039007 # average WriteLineReq miss latency 1670system.iocache.demand_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency 1671system.iocache.demand_avg_miss_latency::total 118124.841046 # average overall miss latency 1672system.iocache.overall_avg_miss_latency::realview.ide 118124.841046 # average overall miss latency 1673system.iocache.overall_avg_miss_latency::total 118124.841046 # average overall miss latency |
| 1677system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1678system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1679system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1680system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1681system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1682system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1683system.iocache.writebacks::writebacks 36190 # number of writebacks 1684system.iocache.writebacks::total 36190 # number of writebacks | 1674system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1675system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1676system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1677system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1678system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1679system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1680system.iocache.writebacks::writebacks 36190 # number of writebacks 1681system.iocache.writebacks::total 36190 # number of writebacks |
| 1685system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses 1686system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses | 1682system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses 1683system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses |
| 1687system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1688system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses | 1684system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1685system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses |
| 1689system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses 1690system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses 1691system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses 1692system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses 1693system.iocache.ReadReq_mshr_miss_latency::realview.ide 17006877 # number of ReadReq MSHR miss cycles 1694system.iocache.ReadReq_mshr_miss_latency::total 17006877 # number of ReadReq MSHR miss cycles 1695system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738747578 # number of WriteLineReq MSHR miss cycles 1696system.iocache.WriteLineReq_mshr_miss_latency::total 2738747578 # number of WriteLineReq MSHR miss cycles 1697system.iocache.demand_mshr_miss_latency::realview.ide 2755754455 # number of demand (read+write) MSHR miss cycles 1698system.iocache.demand_mshr_miss_latency::total 2755754455 # number of demand (read+write) MSHR miss cycles 1699system.iocache.overall_mshr_miss_latency::realview.ide 2755754455 # number of overall MSHR miss cycles 1700system.iocache.overall_mshr_miss_latency::total 2755754455 # number of overall MSHR miss cycles | 1686system.iocache.demand_mshr_misses::realview.ide 36457 # number of demand (read+write) MSHR misses 1687system.iocache.demand_mshr_misses::total 36457 # number of demand (read+write) MSHR misses 1688system.iocache.overall_mshr_misses::realview.ide 36457 # number of overall MSHR misses 1689system.iocache.overall_mshr_misses::total 36457 # number of overall MSHR misses 1690system.iocache.ReadReq_mshr_miss_latency::realview.ide 17314877 # number of ReadReq MSHR miss cycles 1691system.iocache.ReadReq_mshr_miss_latency::total 17314877 # number of ReadReq MSHR miss cycles 1692system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464212681 # number of WriteLineReq MSHR miss cycles 1693system.iocache.WriteLineReq_mshr_miss_latency::total 2464212681 # number of WriteLineReq MSHR miss cycles 1694system.iocache.demand_mshr_miss_latency::realview.ide 2481527558 # number of demand (read+write) MSHR miss cycles 1695system.iocache.demand_mshr_miss_latency::total 2481527558 # number of demand (read+write) MSHR miss cycles 1696system.iocache.overall_mshr_miss_latency::realview.ide 2481527558 # number of overall MSHR miss cycles 1697system.iocache.overall_mshr_miss_latency::total 2481527558 # number of overall MSHR miss cycles |
| 1701system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1702system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1703system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1704system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1705system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1706system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1707system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1708system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1698system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1699system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1700system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1701system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1702system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1703system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1704system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1705system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1709system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76264.022422 # average ReadReq mshr miss latency 1710system.iocache.ReadReq_avg_mshr_miss_latency::total 76264.022422 # average ReadReq mshr miss latency 1711system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75605.884993 # average WriteLineReq mshr miss latency 1712system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75605.884993 # average WriteLineReq mshr miss latency 1713system.iocache.demand_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency 1714system.iocache.demand_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency 1715system.iocache.overall_avg_mshr_miss_latency::realview.ide 75609.911790 # average overall mshr miss latency 1716system.iocache.overall_avg_mshr_miss_latency::total 75609.911790 # average overall mshr miss latency 1717system.membus.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1718system.membus.trans_dist::ReadReq 34132 # Transaction distribution 1719system.membus.trans_dist::ReadResp 67530 # Transaction distribution 1720system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1721system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1722system.membus.trans_dist::WritebackDirty 125486 # Transaction distribution 1723system.membus.trans_dist::CleanEvict 7993 # Transaction distribution 1724system.membus.trans_dist::UpgradeReq 4611 # Transaction distribution 1725system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution | 1706system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74312.776824 # average ReadReq mshr miss latency 1707system.iocache.ReadReq_avg_mshr_miss_latency::total 74312.776824 # average ReadReq mshr miss latency 1708system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68027.072687 # average WriteLineReq mshr miss latency 1709system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68027.072687 # average WriteLineReq mshr miss latency 1710system.iocache.demand_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency 1711system.iocache.demand_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency 1712system.iocache.overall_avg_mshr_miss_latency::realview.ide 68067.245193 # average overall mshr miss latency 1713system.iocache.overall_avg_mshr_miss_latency::total 68067.245193 # average overall mshr miss latency 1714system.membus.snoop_filter.tot_requests 349590 # Total number of requests made to the snoop filter. 1715system.membus.snoop_filter.hit_single_requests 144366 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1716system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1717system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1718system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1719system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1720system.membus.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1721system.membus.trans_dist::ReadReq 34130 # Transaction distribution 1722system.membus.trans_dist::ReadResp 68622 # Transaction distribution 1723system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1724system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1725system.membus.trans_dist::WritebackDirty 131362 # Transaction distribution 1726system.membus.trans_dist::CleanEvict 8484 # Transaction distribution 1727system.membus.trans_dist::UpgradeReq 130 # Transaction distribution 1728system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1726system.membus.trans_dist::UpgradeResp 2 # Transaction distribution | 1729system.membus.trans_dist::UpgradeResp 2 # Transaction distribution |
| 1727system.membus.trans_dist::ReadExReq 133874 # Transaction distribution 1728system.membus.trans_dist::ReadExResp 133874 # Transaction distribution 1729system.membus.trans_dist::ReadSharedReq 33399 # Transaction distribution | 1730system.membus.trans_dist::ReadExReq 138891 # Transaction distribution 1731system.membus.trans_dist::ReadExResp 138891 # Transaction distribution 1732system.membus.trans_dist::ReadSharedReq 34493 # Transaction distribution |
| 1730system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1731system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1732system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) | 1733system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1734system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1735system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) |
| 1733system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1734system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 451368 # Packet count per connected master and slave (bytes) 1735system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558936 # Packet count per connected master and slave (bytes) 1736system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) 1737system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) 1738system.membus.pkt_count::total 631811 # Packet count per connected master and slave (bytes) | 1736system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) 1737system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465445 # Packet count per connected master and slave (bytes) 1738system.membus.pkt_count_system.cpu.l2cache.mem_side::total 573007 # Packet count per connected master and slave (bytes) 1739system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72895 # Packet count per connected master and slave (bytes) 1740system.membus.pkt_count_system.iocache.mem_side::total 72895 # Packet count per connected master and slave (bytes) 1741system.membus.pkt_count::total 645902 # Packet count per connected master and slave (bytes) |
| 1739system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1740system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) | 1742system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1743system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) |
| 1741system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1742system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16456092 # Cumulative packet size per connected master and slave (bytes) 1743system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16619481 # Cumulative packet size per connected master and slave (bytes) | 1744system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) 1745system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17222620 # Cumulative packet size per connected master and slave (bytes) 1746system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17385997 # Cumulative packet size per connected master and slave (bytes) |
| 1744system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1745system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) | 1747system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1748system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) |
| 1746system.membus.pkt_size::total 18936601 # Cumulative packet size per connected master and slave (bytes) 1747system.membus.snoops 487 # Total snoops (count) 1748system.membus.snoopTraffic 31040 # Total snoop traffic (bytes) 1749system.membus.snoop_fanout::samples 403324 # Request fanout histogram 1750system.membus.snoop_fanout::mean 1 # Request fanout histogram 1751system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1749system.membus.pkt_size::total 19703117 # Cumulative packet size per connected master and slave (bytes) 1750system.membus.snoops 497 # Total snoops (count) 1751system.membus.snoopTraffic 31680 # Total snoop traffic (bytes) 1752system.membus.snoop_fanout::samples 271454 # Request fanout histogram 1753system.membus.snoop_fanout::mean 0.017933 # Request fanout histogram 1754system.membus.snoop_fanout::stdev 0.132708 # Request fanout histogram |
| 1752system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1755system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1753system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1754system.membus.snoop_fanout::1 403324 100.00% 100.00% # Request fanout histogram | 1756system.membus.snoop_fanout::0 266586 98.21% 98.21% # Request fanout histogram 1757system.membus.snoop_fanout::1 4868 1.79% 100.00% # Request fanout histogram |
| 1755system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1756system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1758system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1759system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1757system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1760system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1758system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1761system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1759system.membus.snoop_fanout::total 403324 # Request fanout histogram 1760system.membus.reqLayer0.occupancy 83656500 # Layer occupancy (ticks) | 1762system.membus.snoop_fanout::total 271454 # Request fanout histogram 1763system.membus.reqLayer0.occupancy 84464500 # Layer occupancy (ticks) |
| 1761system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1762system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1763system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1764system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1765system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1766system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1764system.membus.reqLayer2.occupancy 1736499 # Layer occupancy (ticks) | 1767system.membus.reqLayer2.occupancy 1723499 # Layer occupancy (ticks) |
| 1765system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1768system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1766system.membus.reqLayer5.occupancy 876921354 # Layer occupancy (ticks) | 1769system.membus.reqLayer5.occupancy 908168519 # Layer occupancy (ticks) |
| 1767system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1770system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1768system.membus.respLayer2.occupancy 979994750 # Layer occupancy (ticks) | 1771system.membus.respLayer2.occupancy 1012308500 # Layer occupancy (ticks) |
| 1769system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 1772system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1770system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) | 1773system.membus.respLayer3.occupancy 1273123 # Layer occupancy (ticks) |
| 1771system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1774system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1772system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1773system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1774system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1775system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1776system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1777system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1778system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 1775system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1776system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1777system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1778system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1779system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1780system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1781system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 1779system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1780system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1781system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1782system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1783system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1784system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1782system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1783system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1784system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1785system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1786system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1787system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1785system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1786system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 1788system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1789system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 1787system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1788system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1789system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1790system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1791system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1792system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1793system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1794system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1810system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1811system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1812system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1813system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1814system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1815system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1816system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1817system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1790system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1791system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1792system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1793system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1794system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1795system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1796system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1797system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1813system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1814system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1815system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1816system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1817system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1818system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1819system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1820system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1818system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1819system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1820system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1821system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1822system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1823system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1824system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 1821system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1822system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1823system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1824system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1825system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1826system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1827system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 1825system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1826system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1827system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1828system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1828system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1829system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1830system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1831system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1829system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1830system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1831system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1832system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1833system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1834system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1835system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1836system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1837system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1838system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1839system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states 1840system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832894126500 # Cumulative time (in ticks) in various power states | 1832system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1833system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1834system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1835system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1836system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1837system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1838system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1839system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1840system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1841system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1842system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states 1843system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2827853096000 # Cumulative time (in ticks) in various power states |
| 1841system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1844system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1842system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed | 1845system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed |
| 1843 1844---------- End Simulation Statistics ---------- | 1846 1847---------- End Simulation Statistics ---------- |