| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 159277 # Simulator instruction rate (inst/s) 8host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3989457396 # Simulator tick rate (ticks/s) 10host_mem_usage 626716 # Number of bytes of host memory used 11host_seconds 710.09 # Real time elapsed on the host | 7host_inst_rate 93807 # Simulator instruction rate (inst/s) 8host_op_rate 113780 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2349621266 # Simulator tick rate (ticks/s) 10host_mem_usage 586720 # Number of bytes of host memory used 11host_seconds 1205.67 # Real time elapsed on the host |
| 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory --- 419 unchanged lines hidden (view full) --- 439system.cpu.dtb.read_hits 25410890 # DTB read hits 440system.cpu.dtb.read_misses 62740 # DTB read misses 441system.cpu.dtb.write_hits 19865163 # DTB write hits 442system.cpu.dtb.write_misses 9628 # DTB write misses 443system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 444system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory --- 419 unchanged lines hidden (view full) --- 439system.cpu.dtb.read_hits 25410890 # DTB read hits 440system.cpu.dtb.read_misses 62740 # DTB read misses 441system.cpu.dtb.write_hits 19865163 # DTB write hits 442system.cpu.dtb.write_misses 9628 # DTB write misses 443system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 444system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 447system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB | 447system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB |
| 448system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 449system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 450system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 451system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 452system.cpu.dtb.read_accesses 25473630 # DTB read accesses 453system.cpu.dtb.write_accesses 19874791 # DTB write accesses 454system.cpu.dtb.inst_accesses 0 # ITB inst accesses 455system.cpu.dtb.hits 45276053 # DTB hits --- 85 unchanged lines hidden (view full) --- 541system.cpu.itb.read_hits 0 # DTB read hits 542system.cpu.itb.read_misses 0 # DTB read misses 543system.cpu.itb.write_hits 0 # DTB write hits 544system.cpu.itb.write_misses 0 # DTB write misses 545system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 546system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 547system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 548system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 448system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 449system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 450system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 451system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 452system.cpu.dtb.read_accesses 25473630 # DTB read accesses 453system.cpu.dtb.write_accesses 19874791 # DTB write accesses 454system.cpu.dtb.inst_accesses 0 # ITB inst accesses 455system.cpu.dtb.hits 45276053 # DTB hits --- 85 unchanged lines hidden (view full) --- 541system.cpu.itb.read_hits 0 # DTB read hits 542system.cpu.itb.read_misses 0 # DTB read misses 543system.cpu.itb.write_hits 0 # DTB write hits 544system.cpu.itb.write_misses 0 # DTB write misses 545system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 546system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 547system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 548system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 549system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB | 549system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB |
| 550system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 554system.cpu.itb.read_accesses 0 # DTB read accesses 555system.cpu.itb.write_accesses 0 # DTB write accesses 556system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 557system.cpu.itb.hits 65995629 # DTB hits --- 1282 unchanged lines hidden --- | 550system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 554system.cpu.itb.read_accesses 0 # DTB read accesses 555system.cpu.itb.write_accesses 0 # DTB write accesses 556system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 557system.cpu.itb.hits 65995629 # DTB hits --- 1282 unchanged lines hidden --- |