| stats.txt (11518:7e0f869f8f7e) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 159961 # Simulator instruction rate (inst/s) 8host_op_rate 194019 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4006592882 # Simulator tick rate (ticks/s) 10host_mem_usage 625056 # Number of bytes of host memory used 11host_seconds 707.05 # Real time elapsed on the host | 7host_inst_rate 159277 # Simulator instruction rate (inst/s) 8host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3989457396 # Simulator tick rate (ticks/s) 10host_mem_usage 626716 # Number of bytes of host memory used 11host_seconds 710.09 # Real time elapsed on the host |
| 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory --- 285 unchanged lines hidden (view full) --- 309system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) 310system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) 311system.physmem_1.averagePower 669.365771 # Core power per rank (mW) 312system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states 313system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states 314system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 315system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states 316system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory --- 285 unchanged lines hidden (view full) --- 310system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) 312system.physmem_1.averagePower 669.365771 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states 314system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 318system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 317system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 318system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 319system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 320system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 321system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 322system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 323system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 328system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) | 319system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 320system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 321system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 322system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 323system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 324system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 325system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 330system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) |
| 331system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 332system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 333system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 329system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 330system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 331system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 332system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 333system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 334system.cf0.dma_write_txs 631 # Number of DMA write transactions. 335system.cpu.branchPred.lookups 46806016 # Number of BP lookups 336system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 341system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage 342system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. 343system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. 344system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. 345system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. 346system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. 347system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. 348system.cpu_clk_domain.clock 500 # Clock period in ticks | 334system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 335system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 336system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 337system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 338system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 339system.cf0.dma_write_txs 631 # Number of DMA write transactions. 340system.cpu.branchPred.lookups 46806016 # Number of BP lookups 341system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 346system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage 347system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. 348system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. 349system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. 350system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. 351system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. 352system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. 353system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 354system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 349system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 370system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 371system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 373system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 374system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 375system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 376system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 377system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 355system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 376system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 384system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 378system.cpu.dtb.walker.walks 72368 # Table walker walks requested 379system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors 380system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate 381system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate 382system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting 383system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency --- 57 unchanged lines hidden (view full) --- 443system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 445system.cpu.dtb.read_accesses 25473630 # DTB read accesses 446system.cpu.dtb.write_accesses 19874791 # DTB write accesses 447system.cpu.dtb.inst_accesses 0 # ITB inst accesses 448system.cpu.dtb.hits 45276053 # DTB hits 449system.cpu.dtb.misses 72368 # DTB misses 450system.cpu.dtb.accesses 45348421 # DTB accesses | 385system.cpu.dtb.walker.walks 72368 # Table walker walks requested 386system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors 387system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate 388system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate 389system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting 390system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency --- 57 unchanged lines hidden (view full) --- 450system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 451system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 452system.cpu.dtb.read_accesses 25473630 # DTB read accesses 453system.cpu.dtb.write_accesses 19874791 # DTB write accesses 454system.cpu.dtb.inst_accesses 0 # ITB inst accesses 455system.cpu.dtb.hits 45276053 # DTB hits 456system.cpu.dtb.misses 72368 # DTB misses 457system.cpu.dtb.accesses 45348421 # DTB accesses |
| 458system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 451system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 472system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 473system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 474system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 475system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 476system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 477system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 478system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 479system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 459system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 480system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 481system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 482system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 483system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 484system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 485system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 486system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 487system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 488system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 480system.cpu.itb.walker.walks 12817 # Table walker walks requested 481system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors 482system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate 483system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate 484system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting 485system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency 486system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency 487system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency --- 55 unchanged lines hidden (view full) --- 543system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 544system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 545system.cpu.itb.read_accesses 0 # DTB read accesses 546system.cpu.itb.write_accesses 0 # DTB write accesses 547system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 548system.cpu.itb.hits 65995629 # DTB hits 549system.cpu.itb.misses 12817 # DTB misses 550system.cpu.itb.accesses 66008446 # DTB accesses | 489system.cpu.itb.walker.walks 12817 # Table walker walks requested 490system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors 491system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate 492system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate 493system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting 494system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency 495system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency --- 55 unchanged lines hidden (view full) --- 552system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 554system.cpu.itb.read_accesses 0 # DTB read accesses 555system.cpu.itb.write_accesses 0 # DTB write accesses 556system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 557system.cpu.itb.hits 65995629 # DTB hits 558system.cpu.itb.misses 12817 # DTB misses 559system.cpu.itb.accesses 66008446 # DTB accesses |
| 560system.cpu.numPwrStateTransitions 6074 # Number of power state transitions 561system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state 572system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states 573system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states |
|
| 551system.cpu.numCycles 278423951 # number of cpu cycles simulated 552system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 553system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 554system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss 555system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 556system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 557system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 558system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 837system.cpu.int_regfile_reads 155524954 # number of integer regfile reads 838system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 839system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 840system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 841system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads 842system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes 843system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads 844system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes | 574system.cpu.numCycles 278423951 # number of cpu cycles simulated 575system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 576system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 577system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss 578system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 579system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 580system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 581system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked --- 278 unchanged lines hidden (view full) --- 860system.cpu.int_regfile_reads 155524954 # number of integer regfile reads 861system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 862system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 863system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 864system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads 865system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes 866system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads 867system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes |
| 868system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 845system.cpu.dcache.tags.replacements 838747 # number of replacements 846system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use 847system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. 848system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. 849system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. 850system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 851system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 852system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 853system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 854system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 856system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 857system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 858system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 859system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses 860system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses | 869system.cpu.dcache.tags.replacements 838747 # number of replacements 870system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use 871system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. 872system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. 873system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. 874system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 875system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 876system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 877system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 878system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 882system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 883system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses 884system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses |
| 885system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 861system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits 862system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits 863system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits 864system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits 865system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 866system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 867system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 868system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits --- 152 unchanged lines hidden (view full) --- 1021system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency 1022system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency 1023system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency 1024system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency 1025system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency 1026system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency 1027system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency 1028system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency | 886system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits 887system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits 888system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits 889system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits 890system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 891system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 892system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 893system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits --- 152 unchanged lines hidden (view full) --- 1046system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency 1047system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency 1048system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency 1049system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency 1050system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency 1051system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency 1052system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency 1053system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency |
| 1054system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1029system.cpu.icache.tags.replacements 1886245 # number of replacements 1030system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use 1031system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. 1032system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. 1033system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. 1034system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. 1035system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor 1036system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1037system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1038system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1039system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1040system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 1041system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1042system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1043system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1044system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses 1045system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses | 1055system.cpu.icache.tags.replacements 1886245 # number of replacements 1056system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use 1057system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. 1058system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. 1059system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. 1060system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. 1061system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor 1062system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1063system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1064system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1065system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1066system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 1067system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1068system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1069system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1070system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses 1071system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses |
| 1072system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1046system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits 1047system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits 1048system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits 1049system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits 1050system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits 1051system.cpu.icache.overall_hits::total 64013417 # number of overall hits 1052system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses 1053system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1124system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1125system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1126system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1127system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1128system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency 1129system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency 1130system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency 1131system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency | 1073system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits 1074system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits 1075system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits 1076system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits 1077system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits 1078system.cpu.icache.overall_hits::total 64013417 # number of overall hits 1079system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses 1080system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses --- 70 unchanged lines hidden (view full) --- 1151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1152system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1154system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1155system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency 1156system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency 1157system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency 1158system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency |
| 1159system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1132system.cpu.l2cache.tags.replacements 96776 # number of replacements 1133system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use 1134system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. 1135system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks. 1136system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks. 1137system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1138system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor 1139system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 1153system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 1154system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1155system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id 1156system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id 1157system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1158system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id 1159system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses 1160system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses | 1160system.cpu.l2cache.tags.replacements 96776 # number of replacements 1161system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use 1162system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. 1163system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks. 1164system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks. 1165system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1166system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor 1167system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 1181system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id 1185system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1186system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id 1187system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses 1188system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses |
| 1189system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1161system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits 1162system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits 1163system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits 1164system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits 1165system.cpu.l2cache.WritebackDirty_hits::total 696773 # number of WritebackDirty hits 1166system.cpu.l2cache.WritebackClean_hits::writebacks 1848340 # number of WritebackClean hits 1167system.cpu.l2cache.WritebackClean_hits::total 1848340 # number of WritebackClean hits 1168system.cpu.l2cache.UpgradeReq_hits::cpu.data 62 # number of UpgradeReq hits --- 266 unchanged lines hidden (view full) --- 1435system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency 1436system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency 1437system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. 1438system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1439system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1440system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. 1441system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1442system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1190system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits 1191system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits 1192system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits 1193system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits 1194system.cpu.l2cache.WritebackDirty_hits::total 696773 # number of WritebackDirty hits 1195system.cpu.l2cache.WritebackClean_hits::writebacks 1848340 # number of WritebackClean hits 1196system.cpu.l2cache.WritebackClean_hits::total 1848340 # number of WritebackClean hits 1197system.cpu.l2cache.UpgradeReq_hits::cpu.data 62 # number of UpgradeReq hits --- 266 unchanged lines hidden (view full) --- 1464system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency 1465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency 1466system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. 1467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1469system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1443system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1444system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution 1445system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1446system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1447system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution 1448system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution 1449system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution 1450system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1484system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) 1485system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1486system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) 1487system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1488system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) 1489system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1490system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) 1491system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1473system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution 1475system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution --- 33 unchanged lines hidden (view full) --- 1514system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) 1515system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1516system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) 1517system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1518system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) 1519system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1520system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) 1521system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1522system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1492system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1493system.iobus.trans_dist::ReadResp 30172 # Transaction distribution 1494system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1495system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1496system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1497system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1498system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1499system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 1578system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) 1579system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1580system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) 1581system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1582system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1583system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1584system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) 1585system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1523system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1524system.iobus.trans_dist::ReadResp 30172 # Transaction distribution 1525system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1526system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1527system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 78 unchanged lines hidden (view full) --- 1609system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) 1610system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1611system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) 1612system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1613system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1614system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1615system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) 1616system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1617system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1586system.iocache.tags.replacements 36413 # number of replacements 1587system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use 1588system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1589system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. 1590system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1591system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. 1592system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor 1593system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy 1594system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy 1595system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1596system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1597system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1598system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1599system.iocache.tags.data_accesses 328023 # Number of data accesses | 1618system.iocache.tags.replacements 36413 # number of replacements 1619system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use 1620system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1621system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. 1622system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1623system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. 1624system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor 1625system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy 1626system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy 1627system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1628system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1629system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1630system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1631system.iocache.tags.data_accesses 328023 # Number of data accesses |
| 1632system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1600system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1601system.iocache.ReadReq_misses::total 223 # number of ReadReq misses 1602system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1603system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1604system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses 1605system.iocache.demand_misses::total 36447 # number of demand (read+write) misses 1606system.iocache.overall_misses::realview.ide 36447 # number of overall misses 1607system.iocache.overall_misses::total 36447 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1672system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency 1673system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency 1674system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency 1675system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency 1676system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1677system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1678system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1679system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency | 1633system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1634system.iocache.ReadReq_misses::total 223 # number of ReadReq misses 1635system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1636system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1637system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses 1638system.iocache.demand_misses::total 36447 # number of demand (read+write) misses 1639system.iocache.overall_misses::realview.ide 36447 # number of overall misses 1640system.iocache.overall_misses::total 36447 # number of overall misses --- 64 unchanged lines hidden (view full) --- 1705system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency 1706system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency 1707system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency 1708system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency 1709system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1710system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1711system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1712system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency |
| 1713system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1680system.membus.trans_dist::ReadReq 34132 # Transaction distribution 1681system.membus.trans_dist::ReadResp 67490 # Transaction distribution 1682system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1683system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1684system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution 1685system.membus.trans_dist::CleanEvict 7777 # Transaction distribution 1686system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution 1687system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1725system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) 1726system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1727system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) 1728system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1729system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) 1730system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1731system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) 1732system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 1714system.membus.trans_dist::ReadReq 34132 # Transaction distribution 1715system.membus.trans_dist::ReadResp 67490 # Transaction distribution 1716system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1717system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1718system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution 1719system.membus.trans_dist::CleanEvict 7777 # Transaction distribution 1720system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution 1721system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution --- 37 unchanged lines hidden (view full) --- 1759system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) 1760system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1761system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) 1762system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1763system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) 1764system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1765system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) 1766system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1767system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1768system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1769system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1770system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1771system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1772system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1773system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1733system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1734system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1735system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1736system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1737system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1738system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1774system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1775system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1776system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1777system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1778system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1779system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1780system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1781system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1739system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1740system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1741system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1742system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1743system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1744system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1745system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1746system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1762system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1763system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1764system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1765system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1766system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1767system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1768system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1769system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1782system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1783system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1784system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1785system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1786system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1787system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1788system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1789system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1805system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1806system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1807system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1808system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1809system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1810system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1811system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1812system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1813system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1814system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1815system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1816system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1817system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1818system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1819system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1770system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1771system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1772system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1773system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1820system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1821system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1822system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1823system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1824system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1825system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1826system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1827system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1828system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1829system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1830system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1831system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1832system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1833system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1834system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1835system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states |
|
| 1774system.cpu.kern.inst.arm 0 # number of arm instructions executed 1775system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1776 1777---------- End Simulation Statistics ---------- | 1836system.cpu.kern.inst.arm 0 # number of arm instructions executed 1837system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1838 1839---------- End Simulation Statistics ---------- |