| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 116306 # Simulator instruction rate (inst/s) 8host_op_rate 141069 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2913147103 # Simulator tick rate (ticks/s) 10host_mem_usage 578076 # Number of bytes of host memory used 11host_seconds 972.44 # Real time elapsed on the host | 7host_inst_rate 70501 # Simulator instruction rate (inst/s) 8host_op_rate 85511 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1765850548 # Simulator tick rate (ticks/s) 10host_mem_usage 578080 # Number of bytes of host memory used 11host_seconds 1604.25 # Real time elapsed on the host |
| 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory --- 404 unchanged lines hidden (view full) --- 424system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst 430system.cpu.dtb.inst_hits 0 # ITB inst hits 431system.cpu.dtb.inst_misses 0 # ITB inst misses | 12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory --- 404 unchanged lines hidden (view full) --- 424system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst 426system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst 430system.cpu.dtb.inst_hits 0 # ITB inst hits 431system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 432system.cpu.dtb.read_hits 25410889 # DTB read hits | 432system.cpu.dtb.read_hits 25410890 # DTB read hits |
| 433system.cpu.dtb.read_misses 62740 # DTB read misses | 433system.cpu.dtb.read_misses 62740 # DTB read misses |
| 434system.cpu.dtb.write_hits 19865162 # DTB write hits | 434system.cpu.dtb.write_hits 19865163 # DTB write hits |
| 435system.cpu.dtb.write_misses 9628 # DTB write misses 436system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 437system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 438system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 439system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 440system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB 441system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 442system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 443system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions | 435system.cpu.dtb.write_misses 9628 # DTB write misses 436system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 437system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 438system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 439system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 440system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB 441system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 442system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 443system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 444system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions |
| 445system.cpu.dtb.read_accesses 25473629 # DTB read accesses 446system.cpu.dtb.write_accesses 19874790 # DTB write accesses | 445system.cpu.dtb.read_accesses 25473630 # DTB read accesses 446system.cpu.dtb.write_accesses 19874791 # DTB write accesses |
| 447system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 447system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 448system.cpu.dtb.hits 45276051 # DTB hits | 448system.cpu.dtb.hits 45276053 # DTB hits |
| 449system.cpu.dtb.misses 72368 # DTB misses | 449system.cpu.dtb.misses 72368 # DTB misses |
| 450system.cpu.dtb.accesses 45348419 # DTB accesses | 450system.cpu.dtb.accesses 45348421 # DTB accesses |
| 451system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 87 unchanged lines hidden (view full) --- 546system.cpu.itb.write_accesses 0 # DTB write accesses 547system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 548system.cpu.itb.hits 65995629 # DTB hits 549system.cpu.itb.misses 12817 # DTB misses 550system.cpu.itb.accesses 66008446 # DTB accesses 551system.cpu.numCycles 278423951 # number of cpu cycles simulated 552system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 553system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 451system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 452system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 453system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 87 unchanged lines hidden (view full) --- 546system.cpu.itb.write_accesses 0 # DTB write accesses 547system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 548system.cpu.itb.hits 65995629 # DTB hits 549system.cpu.itb.misses 12817 # DTB misses 550system.cpu.itb.accesses 66008446 # DTB accesses 551system.cpu.numCycles 278423951 # number of cpu cycles simulated 552system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 553system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 554system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss | 554system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss |
| 555system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 556system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 557system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 558system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked 559system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing 560system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb 561system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 562system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps 563system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions 564system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR 565system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched 566system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed 567system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed | 555system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 556system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 557system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 558system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked 559system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing 560system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb 561system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 562system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps 563system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions 564system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR 565system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched 566system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed 567system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed |
| 568system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total) | 568system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) |
| 569system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 569system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 572system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total) | 572system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) |
| 573system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 573system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 579system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total) | 579system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) |
| 580system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle 581system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle | 580system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle 581system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle |
| 582system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle | 582system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle |
| 583system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked 584system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running 585system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking 586system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing 587system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch 588system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction 589system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode 590system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode 591system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing | 583system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked 584system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running 585system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking 586system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing 587system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch 588system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction 589system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode 590system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode 591system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing |
| 592system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle | 592system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle |
| 593system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking 594system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst 595system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running 596system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking 597system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename 598system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename 599system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full 600system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full --- 14 unchanged lines hidden (view full) --- 615system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. 616system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) 617system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ 618system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued 619system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued 620system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling 621system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph 622system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed | 593system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking 594system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst 595system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running 596system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking 597system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename 598system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename 599system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full 600system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full --- 14 unchanged lines hidden (view full) --- 615system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. 616system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) 617system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ 618system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued 619system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued 620system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling 621system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph 622system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed |
| 623system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle | 623system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle |
| 624system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 624system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 627system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle | 627system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle |
| 631system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 631system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 639system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle | 639system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle |
| 640system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 641system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available 642system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 643system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 704system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued 705system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 708system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued 709system.cpu.iq.rate 0.513744 # Inst issue rate 710system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested 711system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) | 640system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 641system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available 642system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 643system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available --- 56 unchanged lines hidden (view full) --- 704system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued 705system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 708system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued 709system.cpu.iq.rate 0.513744 # Inst issue rate 710system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested 711system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) |
| 712system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads | 712system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads |
| 713system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes 714system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses 715system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads 716system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes 717system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses 718system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses 719system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses 720system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores --- 27 unchanged lines hidden (view full) --- 748system.cpu.iew.exec_swp 0 # number of swp insts executed 749system.cpu.iew.exec_nop 180634 # number of nop insts executed 750system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed 751system.cpu.iew.exec_branches 26490215 # Number of branches executed 752system.cpu.iew.exec_stores 20827406 # Number of stores executed 753system.cpu.iew.exec_rate 0.510511 # Inst execution rate 754system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit 755system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back | 713system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes 714system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses 715system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads 716system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes 717system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses 718system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses 719system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses 720system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores --- 27 unchanged lines hidden (view full) --- 748system.cpu.iew.exec_swp 0 # number of swp insts executed 749system.cpu.iew.exec_nop 180634 # number of nop insts executed 750system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed 751system.cpu.iew.exec_branches 26490215 # Number of branches executed 752system.cpu.iew.exec_stores 20827406 # Number of stores executed 753system.cpu.iew.exec_rate 0.510511 # Inst execution rate 754system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit 755system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back |
| 756system.cpu.iew.wb_producers 63237138 # num instructions producing a value 757system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value | 756system.cpu.iew.wb_producers 63237137 # num instructions producing a value 757system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value |
| 758system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle 759system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back 760system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit 761system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards 762system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted | 758system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle 759system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back 760system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit 761system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards 762system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted |
| 763system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle | 763system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle |
| 764system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 764system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 767system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle | 767system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle |
| 769system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle | 769system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle |
| 773system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle | 773system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle |
| 774system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle | 774system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle |
| 775system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle | 775system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle |
| 776system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 776system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 779system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle | 779system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle |
| 780system.cpu.commit.committedInsts 113255406 # Number of instructions committed 781system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed 782system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 783system.cpu.commit.refs 45494106 # Number of memory references committed 784system.cpu.commit.loads 24903571 # Number of loads committed 785system.cpu.commit.membars 814876 # Number of memory barriers committed 786system.cpu.commit.branches 26023568 # Number of branches committed 787system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 817system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 820system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction 821system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction 822system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 823system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 824system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction | 780system.cpu.commit.committedInsts 113255406 # Number of instructions committed 781system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed 782system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 783system.cpu.commit.refs 45494106 # Number of memory references committed 784system.cpu.commit.loads 24903571 # Number of loads committed 785system.cpu.commit.membars 814876 # Number of memory barriers committed 786system.cpu.commit.branches 26023568 # Number of branches committed 787system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 817system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 820system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction 821system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction 822system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 823system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 824system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction |
| 825system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached 826system.cpu.rob.rob_reads 389119867 # The number of ROB reads | 825system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached 826system.cpu.rob.rob_reads 389119868 # The number of ROB reads |
| 827system.cpu.rob.rob_writes 292294903 # The number of ROB writes 828system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself | 827system.cpu.rob.rob_writes 292294903 # The number of ROB writes 828system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 829system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling | 829system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 830system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 831system.cpu.committedInsts 113100501 # Number of Instructions Simulated 832system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated 833system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction 834system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads 835system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle 836system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads | 830system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 831system.cpu.committedInsts 113100501 # Number of Instructions Simulated 832system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated 833system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction 834system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads 835system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle 836system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads |
| 837system.cpu.int_regfile_reads 155524958 # number of integer regfile reads | 837system.cpu.int_regfile_reads 155524954 # number of integer regfile reads |
| 838system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 839system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 840system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 838system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 839system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 840system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 841system.cpu.cc_regfile_reads 502156058 # number of cc regfile reads | 841system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads |
| 842system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes | 842system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes |
| 843system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads | 843system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads |
| 844system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes 845system.cpu.dcache.tags.replacements 838747 # number of replacements 846system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use | 844system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes 845system.cpu.dcache.tags.replacements 838747 # number of replacements 846system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use |
| 847system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks. | 847system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. |
| 848system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. | 848system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. |
| 849system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks. | 849system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. |
| 850system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 851system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 852system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 853system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 854system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 856system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 857system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 858system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 850system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 851system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 852system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 853system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 854system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 856system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 857system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 858system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 859system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses 860system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses 861system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits 862system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits 863system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits 864system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits | 859system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses 860system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses 861system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits 862system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits 863system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits 864system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits |
| 865system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 866system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 867system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 868system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits 869system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits 870system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits | 865system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 866system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 867system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 868system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits 869system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits 870system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits |
| 871system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits 872system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits 873system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits 874system.cpu.dcache.overall_hits::total 39152130 # number of overall hits | 871system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits 872system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits 873system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits 874system.cpu.dcache.overall_hits::total 39152132 # number of overall hits |
| 875system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses 876system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses 877system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses 878system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses 879system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses 880system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses 881system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses 882system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 893system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles 894system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles 895system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles 896system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles 897system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles 898system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles 899system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles 900system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles | 875system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses 876system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses 877system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses 878system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses 879system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses 880system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses 881system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses 882system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses --- 10 unchanged lines hidden (view full) --- 893system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles 894system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles 895system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles 896system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles 897system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles 898system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles 899system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles 900system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles |
| 901system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses) 902system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses) 903system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses) 904system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses) | 901system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) 902system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) 903system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) 904system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) |
| 905system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) 906system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) 907system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) 908system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) 909system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) 910system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) | 905system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) 906system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) 907system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) 908system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) 909system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) 910system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) |
| 911system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses 912system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses 913system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses 914system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses | 911system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses 912system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses 913system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses 914system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses |
| 915system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses 916system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses 917system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses 918system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses 919system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses 920system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses 921system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses 922system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses --- 855 unchanged lines hidden --- | 915system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses 916system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses 917system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses 918system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses 919system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses 920system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses 921system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses 922system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses --- 855 unchanged lines hidden --- |