| stats.txt (10798:74e3c7359393) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.827616 # Number of seconds simulated 4sim_ticks 2827616186000 # Number of ticks simulated 5final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.827616 # Number of seconds simulated 4sim_ticks 2827616186000 # Number of ticks simulated 5final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 94820 # Simulator instruction rate (inst/s) 8host_op_rate 115016 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2369528287 # Simulator tick rate (ticks/s) 10host_mem_usage 555256 # Number of bytes of host memory used 11host_seconds 1193.32 # Real time elapsed on the host | 7host_inst_rate 97479 # Simulator instruction rate (inst/s) 8host_op_rate 118241 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2435971946 # Simulator tick rate (ticks/s) 10host_mem_usage 621864 # Number of bytes of host memory used 11host_seconds 1160.78 # Real time elapsed on the host |
| 12sim_insts 113151083 # Number of instructions simulated 13sim_ops 137250963 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory | 12sim_insts 113151083 # Number of instructions simulated 13sim_ops 137250963 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory | 21system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory |
| 22system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory | 22system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory | 32system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory |
| 33system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) | 39system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) | 51system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) | 52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 176173 # Number of read requests accepted | 53system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 176174 # Number of read requests accepted |
| 55system.physmem.writeReqs 171661 # Number of write requests accepted | 55system.physmem.writeReqs 171661 # Number of write requests accepted |
| 56system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue | 56system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue |
| 57system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM | 57system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM |
| 59system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue | 59system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue |
| 60system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM | 60system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM |
| 61system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side | 61system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side |
| 62system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side | 62system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side |
| 63system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue | 63system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11334 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10890 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10732 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10393 # Per bank write bursts 70system.physmem.perBankRdBursts::4 14045 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11531 # Per bank write bursts --- 23 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::13 9361 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9018 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9072 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 58 # Number of times write queue was full causing retry 100system.physmem.totGap 2827615975000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) | 64system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11334 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10890 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10732 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10393 # Per bank write bursts 70system.physmem.perBankRdBursts::4 14045 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11531 # Per bank write bursts --- 23 unchanged lines hidden (view full) --- 95system.physmem.perBankWrBursts::13 9361 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9018 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9072 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 58 # Number of times write queue was full causing retry 100system.physmem.totGap 2827615975000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| 103system.physmem.readPktSize::2 541 # Read request sizes (log2) | 103system.physmem.readPktSize::2 542 # Read request sizes (log2) |
| 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 2994 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 172624 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) --- 148 unchanged lines hidden (view full) --- 260system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads | 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 2994 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 172624 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) --- 148 unchanged lines hidden (view full) --- 260system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads |
| 268system.physmem.totQLat 2104910750 # Total ticks spent queuing 269system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM | 268system.physmem.totQLat 2104913750 # Total ticks spent queuing 269system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM |
| 270system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers | 270system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers |
| 271system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst | 271system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst |
| 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 273system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst | 273system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst |
| 274system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.06 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing 284system.physmem.readRowHits 145058 # Number of row buffer hits during reads 285system.physmem.writeRowHits 112529 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes | 274system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.06 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing 284system.physmem.readRowHits 145058 # Number of row buffer hits during reads 285system.physmem.writeRowHits 112529 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes |
| 288system.physmem.avgGap 8129210.99 # Average gap between requests | 288system.physmem.avgGap 8129187.62 # Average gap between requests |
| 289system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) | 289system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) |
| 295system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) | 295system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) |
| 298system.physmem_0.averagePower 669.422846 # Core power per rank (mW) | 298system.physmem_0.averagePower 669.422846 # Core power per rank (mW) |
| 299system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states | 299system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states |
| 300system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 300system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 302system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states | 302system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states |
| 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) | 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) |
| 309system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) | 309system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) |
| 312system.physmem_1.averagePower 669.324331 # Core power per rank (mW) | 312system.physmem_1.averagePower 669.324331 # Core power per rank (mW) |
| 313system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states | 313system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states |
| 314system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 314system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 316system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states | 316system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states |
| 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 324system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) --- 101 unchanged lines hidden (view full) --- 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst 432system.cpu.dtb.inst_hits 0 # ITB inst hits 433system.cpu.dtb.inst_misses 0 # ITB inst misses | 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 324system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) --- 101 unchanged lines hidden (view full) --- 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 427system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst 432system.cpu.dtb.inst_hits 0 # ITB inst hits 433system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 434system.cpu.dtb.read_hits 25461870 # DTB read hits | 434system.cpu.dtb.read_hits 25461869 # DTB read hits |
| 435system.cpu.dtb.read_misses 62291 # DTB read misses 436system.cpu.dtb.write_hits 19915387 # DTB write hits 437system.cpu.dtb.write_misses 10080 # DTB write misses 438system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 439system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 440system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 441system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 442system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB 443system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions 444system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch 445system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions | 435system.cpu.dtb.read_misses 62291 # DTB read misses 436system.cpu.dtb.write_hits 19915387 # DTB write hits 437system.cpu.dtb.write_misses 10080 # DTB write misses 438system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 439system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 440system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 441system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 442system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB 443system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions 444system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch 445system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 446system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions |
| 447system.cpu.dtb.read_accesses 25524161 # DTB read accesses | 447system.cpu.dtb.read_accesses 25524160 # DTB read accesses |
| 448system.cpu.dtb.write_accesses 19925467 # DTB write accesses 449system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 448system.cpu.dtb.write_accesses 19925467 # DTB write accesses 449system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 450system.cpu.dtb.hits 45377257 # DTB hits | 450system.cpu.dtb.hits 45377256 # DTB hits |
| 451system.cpu.dtb.misses 72371 # DTB misses | 451system.cpu.dtb.misses 72371 # DTB misses |
| 452system.cpu.dtb.accesses 45449628 # DTB accesses | 452system.cpu.dtb.accesses 45449627 # DTB accesses |
| 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 125 unchanged lines hidden (view full) --- 586system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing 587system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch 588system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction 589system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode 590system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode 591system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing 592system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle 593system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking | 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 125 unchanged lines hidden (view full) --- 586system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing 587system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch 588system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction 589system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode 590system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode 591system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing 592system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle 593system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking |
| 594system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst | 594system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst |
| 595system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running | 595system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running |
| 596system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking | 596system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking |
| 597system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename 598system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename 599system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full 600system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full 601system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full | 597system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename 598system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename 599system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full 600system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full 601system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full |
| 602system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full | 602system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full |
| 603system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed 604system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made 605system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups 606system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups 607system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed 608system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing 609system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed 610system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed 611system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer 612system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. 613system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. 614system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. 615system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. 616system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) 617system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ | 603system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed 604system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made 605system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups 606system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups 607system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed 608system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing 609system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed 610system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed 611system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer 612system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. 613system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. 614system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. 615system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. 616system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) 617system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ |
| 618system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued | 618system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued |
| 619system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued 620system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling 621system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph 622system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed 623system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 619system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued 620system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling 621system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph 622system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed 623system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 627system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle | 627system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle |
| 629system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle --- 59 unchanged lines hidden (view full) --- 696system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued | 629system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle --- 59 unchanged lines hidden (view full) --- 696system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued |
| 704system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued | 704system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued |
| 705system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 705system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 708system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued | 708system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued |
| 709system.cpu.iq.rate 0.544758 # Inst issue rate 710system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested 711system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) | 709system.cpu.iq.rate 0.544758 # Inst issue rate 710system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested 711system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) |
| 712system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads | 712system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads |
| 713system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes 714system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses 715system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads 716system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes 717system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses | 713system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes 714system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses 715system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads 716system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes 717system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses |
| 718system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses | 718system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses |
| 719system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses 720system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores 721system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 722system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed 723system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed 724system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations 725system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed 726system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 727system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 719system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses 720system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores 721system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 722system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed 723system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed 724system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations 725system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed 726system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 727system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 728system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled | 728system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled |
| 729system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked 730system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 731system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing 732system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking 733system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking 734system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ 735system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 736system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions 737system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions 738system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions 739system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall 740system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall 741system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations 742system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly 743system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly 744system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute | 729system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked 730system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 731system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing 732system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking 733system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking 734system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ 735system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 736system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions 737system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions 738system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions 739system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall 740system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall 741system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations 742system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly 743system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly 744system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute |
| 745system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions 746system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed | 745system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions 746system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed |
| 747system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute 748system.cpu.iew.exec_swp 0 # number of swp insts executed 749system.cpu.iew.exec_nop 201053 # number of nop insts executed | 747system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute 748system.cpu.iew.exec_swp 0 # number of swp insts executed 749system.cpu.iew.exec_nop 201053 # number of nop insts executed |
| 750system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed | 750system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed |
| 751system.cpu.iew.exec_branches 26530134 # Number of branches executed 752system.cpu.iew.exec_stores 20877849 # Number of stores executed 753system.cpu.iew.exec_rate 0.541163 # Inst execution rate | 751system.cpu.iew.exec_branches 26530134 # Number of branches executed 752system.cpu.iew.exec_stores 20877849 # Number of stores executed 753system.cpu.iew.exec_rate 0.541163 # Inst execution rate |
| 754system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit | 754system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit |
| 755system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back 756system.cpu.iew.wb_producers 63271750 # num instructions producing a value 757system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value 758system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 759system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle 760system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back 761system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 762system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit --- 68 unchanged lines hidden (view full) --- 831system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling 832system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 833system.cpu.committedInsts 113151083 # Number of Instructions Simulated 834system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated 835system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction 836system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads 837system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle 838system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads | 755system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back 756system.cpu.iew.wb_producers 63271750 # num instructions producing a value 757system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value 758system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 759system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle 760system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back 761system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 762system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit --- 68 unchanged lines hidden (view full) --- 831system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling 832system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 833system.cpu.committedInsts 113151083 # Number of Instructions Simulated 834system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated 835system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction 836system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads 837system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle 838system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads |
| 839system.cpu.int_regfile_reads 155826637 # number of integer regfile reads | 839system.cpu.int_regfile_reads 155826636 # number of integer regfile reads |
| 840system.cpu.int_regfile_writes 88633021 # number of integer regfile writes 841system.cpu.fp_regfile_reads 9606 # number of floating regfile reads 842system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 840system.cpu.int_regfile_writes 88633021 # number of integer regfile writes 841system.cpu.fp_regfile_reads 9606 # number of floating regfile reads 842system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 843system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads | 843system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads |
| 844system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes | 844system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes |
| 845system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads | 845system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads |
| 846system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes 847system.cpu.dcache.tags.replacements 839617 # number of replacements 848system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use 849system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. 850system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. 851system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. 852system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. 853system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor --- 31 unchanged lines hidden (view full) --- 885system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 886system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 887system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses 888system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses 889system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses 890system.cpu.dcache.overall_misses::total 4478306 # number of overall misses 891system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles 892system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles | 846system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes 847system.cpu.dcache.tags.replacements 839617 # number of replacements 848system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use 849system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. 850system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. 851system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. 852system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. 853system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor --- 31 unchanged lines hidden (view full) --- 885system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 886system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 887system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses 888system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses 889system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses 890system.cpu.dcache.overall_misses::total 4478306 # number of overall misses 891system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles 892system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles |
| 893system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles 894system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles | 893system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles 894system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles |
| 895system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles 896system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles 897system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles 898system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles | 895system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles 896system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles 897system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles 898system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles |
| 899system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles 900system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles 901system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles 902system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles | 899system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles 900system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles 901system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles 902system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles |
| 903system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) 904system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) 905system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) 906system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) 907system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) 908system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) 909system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) 910system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 925system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 926system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 927system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses 928system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses 929system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses 930system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses 931system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency 932system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency | 903system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) 904system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) 905system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) 906system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) 907system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) 908system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) 909system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) 910system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 925system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 926system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 927system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses 928system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses 929system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses 930system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses 931system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency 932system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency |
| 933system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency 934system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency | 933system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency 934system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency |
| 935system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency 936system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency 937system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency 938system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency | 935system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency 936system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency 937system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency 938system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency |
| 939system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency 940system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency 941system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency 942system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency | 939system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency 940system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency 941system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency 942system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency |
| 943system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked 944system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 945system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked 946system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 947system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked 948system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 949system.cpu.dcache.fast_writes 0 # number of fast writes performed 950system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 969system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses 970system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses 971system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 972system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 973system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses 974system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses 975system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses 976system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses | 943system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked 944system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 945system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked 946system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 947system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked 948system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 949system.cpu.dcache.fast_writes 0 # number of fast writes performed 950system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 18 unchanged lines hidden (view full) --- 969system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses 970system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses 971system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 972system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 973system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses 974system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses 975system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses 976system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses |
| 977system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 978system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable 979system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 980system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 981system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 982system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses |
|
| 977system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles 978system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles | 983system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles 984system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles |
| 979system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles 980system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles | 985system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles 986system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles |
| 981system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles 982system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles 983system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles 984system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles 985system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles 986system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles | 987system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles 988system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles 989system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles 990system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles 991system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles 992system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles |
| 987system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles 988system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles 989system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles 990system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles 991system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles 992system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles | 993system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles 994system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles 995system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles 996system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles 997system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles 998system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles |
| 993system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles 994system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles | 999system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles 1000system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles |
| 995system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles 996system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles | 1001system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles 1002system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles |
| 997system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses 998system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses 999system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses 1000system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses 1001system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses 1002system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses 1003system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses 1004system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses 1005system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1006system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1007system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses 1008system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses 1009system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses 1010system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses 1011system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency 1012system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency | 1003system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses 1004system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses 1005system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses 1006system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses 1007system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses 1008system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses 1009system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses 1010system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses 1011system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1012system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1013system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses 1014system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses 1015system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses 1016system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses 1017system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency 1018system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency |
| 1013system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency 1014system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency | 1019system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency 1020system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency |
| 1015system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency 1016system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency 1017system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency 1018system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency 1019system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency 1020system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency | 1021system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency 1022system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency 1023system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency 1024system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency 1025system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency 1026system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency |
| 1021system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency 1022system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency 1023system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency 1024system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency 1025system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1026system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1027system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1028system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1029system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1030system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1027system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency 1028system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency 1029system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency 1030system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency 1031system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency 1032system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency 1033system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency 1034system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency 1035system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency 1036system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency |
| 1031system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1032system.cpu.icache.tags.replacements 1892540 # number of replacements 1033system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use 1034system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. 1035system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. 1036system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. 1037system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. 1038system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor --- 58 unchanged lines hidden (view full) --- 1097system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits 1098system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits 1099system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses 1100system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses 1101system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses 1102system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses 1103system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses 1104system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses | 1037system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1038system.cpu.icache.tags.replacements 1892540 # number of replacements 1039system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use 1040system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. 1041system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. 1042system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. 1043system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. 1044system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor --- 58 unchanged lines hidden (view full) --- 1103system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits 1104system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits 1105system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses 1106system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses 1107system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses 1108system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses 1109system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses 1110system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses |
| 1111system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable 1112system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable 1113system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses 1114system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses |
|
| 1105system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles 1106system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles 1107system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles 1108system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles 1109system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles 1110system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles 1111system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles 1112system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 1119system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses 1120system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses 1121system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency 1122system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency 1123system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1124system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency 1125system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1126system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency | 1115system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles 1116system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles 1117system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles 1118system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles 1119system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles 1120system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles 1121system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles 1122system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles --- 6 unchanged lines hidden (view full) --- 1129system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses 1130system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses 1131system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency 1132system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency 1133system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1134system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency 1135system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1136system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency |
| 1127system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1128system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1129system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1130system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1137system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency 1138system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency 1139system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency 1140system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency |
| 1131system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1132system.cpu.l2cache.tags.replacements 103160 # number of replacements 1133system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use 1134system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. 1135system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. 1136system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. 1137system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1138system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor --- 67 unchanged lines hidden (view full) --- 1206system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles 1207system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles 1208system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles 1209system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles 1210system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles 1211system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles 1212system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles 1213system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles | 1141system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1142system.cpu.l2cache.tags.replacements 103160 # number of replacements 1143system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use 1144system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. 1145system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. 1146system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. 1147system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1148system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor --- 67 unchanged lines hidden (view full) --- 1216system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles 1217system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles 1218system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles 1219system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles 1220system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles 1221system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles 1222system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles 1223system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles |
| 1214system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles 1215system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles | 1224system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles 1225system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles |
| 1216system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles 1217system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles 1218system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles | 1226system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles 1227system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles 1228system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles |
| 1219system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles 1220system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles | 1229system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles 1230system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles |
| 1221system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles 1222system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles 1223system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles | 1231system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles 1232system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles 1233system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles |
| 1224system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles 1225system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles | 1234system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles 1235system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles |
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| 1279system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency 1280system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency | 1289system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency 1290system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency |
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| 1284system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency 1285system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency | 1294system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency 1295system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency |
| 1286system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency 1287system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency 1288system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency | 1296system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency 1297system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency 1298system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency |
| 1289system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency 1290system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency | 1299system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency 1300system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency |
| 1291system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1292system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1293system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1294system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1295system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1296system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1297system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1298system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 24 unchanged lines hidden (view full) --- 1323system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses 1324system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses 1325system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses 1326system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 1327system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1328system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses 1329system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses 1330system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses | 1301system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1302system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1303system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1304system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1305system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1306system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1307system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1308system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 24 unchanged lines hidden (view full) --- 1333system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses 1334system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses 1335system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses 1336system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses 1337system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses 1338system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses 1339system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses 1340system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses |
| 1341system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable 1342system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable 1343system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable 1344system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable 1345system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable 1346system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses 1347system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses 1348system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses |
|
| 1331system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles 1332system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles 1333system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles 1334system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles 1335system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles 1336system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles 1337system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles 1338system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1339system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles | 1349system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles 1350system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles 1351system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles 1352system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles 1353system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles 1354system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles 1355system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles 1356system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1357system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles |
| 1340system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles 1341system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles | 1358system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles 1359system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles |
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| 1345system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles 1346system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles | 1363system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles 1364system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles |
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| 1350system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles 1351system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles | 1368system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles 1369system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles |
| 1352system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles | 1370system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles |
| 1353system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles 1354system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles | 1371system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles 1372system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles |
| 1355system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles 1356system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles 1357system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles | 1373system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles 1374system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles 1375system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles |
| 1358system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles 1359system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles | 1376system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles 1377system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles |
| 1360system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses 1361system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses 1362system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses 1363system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses 1364system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses 1365system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses 1366system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses 1367system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses --- 14 unchanged lines hidden (view full) --- 1382system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency 1383system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency 1384system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency 1385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency 1386system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency 1387system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency 1388system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1389system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency | 1378system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses 1379system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses 1380system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses 1381system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses 1382system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses 1383system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses 1384system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses 1385system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses --- 14 unchanged lines hidden (view full) --- 1400system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency 1401system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency 1402system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency 1403system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency 1404system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency 1405system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency 1406system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1407system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency |
| 1390system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency 1391system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency | 1408system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency 1409system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency |
| 1392system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1393system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1394system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency | 1410system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1411system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1412system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency |
| 1395system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency 1396system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency | 1413system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency 1414system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency |
| 1397system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1398system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1399system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency | 1415system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1416system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1417system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency |
| 1400system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency 1401system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency 1402system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1403system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1404system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1405system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1406system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1407system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1408system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1409system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1418system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency 1419system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency 1420system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency 1421system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency 1422system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency 1423system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency 1424system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency 1425system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency 1426system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency 1427system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency |
| 1410system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1428system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1411system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution 1412system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution | 1429system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution 1430system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution |
| 1413system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1414system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1415system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution 1416system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution 1417system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 1418system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1419system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution 1420system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution 1421system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution 1422system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) | 1431system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1432system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1433system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution 1434system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution 1435system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 1436system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1437system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution 1438system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution 1439system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution 1440system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) |
| 1423system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) | 1441system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) |
| 1424system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) 1425system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) | 1442system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) 1443system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) |
| 1426system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) | 1444system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) |
| 1427system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) | 1445system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) |
| 1428system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) | 1446system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) |
| 1429system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) 1430system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) | 1447system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) 1448system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) |
| 1431system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) | 1449system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) |
| 1432system.cpu.toL2Bus.snoops 62589 # Total snoops (count) | 1450system.cpu.toL2Bus.snoops 62589 # Total snoops (count) |
| 1433system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram 1434system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram 1435system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram | 1451system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram 1452system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram 1453system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram |
| 1436system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1437system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1454system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1455system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1438system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1439system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1440system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram 1441system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram | 1456system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram 1457system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram |
| 1442system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1458system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1443system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1444system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1445system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram 1446system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) | 1459system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1460system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1461system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram 1462system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) |
| 1447system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1448system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) 1449system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1450system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) 1451system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1463system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1464system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) 1465system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1466system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) 1467system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1452system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) | 1468system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) |
| 1453system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1454system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) 1455system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1456system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) 1457system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1458system.iobus.trans_dist::ReadReq 30182 # Transaction distribution 1459system.iobus.trans_dist::ReadResp 30182 # Transaction distribution 1460system.iobus.trans_dist::WriteReq 59014 # Transaction distribution --- 189 unchanged lines hidden (view full) --- 1650system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency 1651system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency 1652system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency 1653system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1654system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency 1655system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1656system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency 1657system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1469system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1470system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) 1471system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1472system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) 1473system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1474system.iobus.trans_dist::ReadReq 30182 # Transaction distribution 1475system.iobus.trans_dist::ReadResp 30182 # Transaction distribution 1476system.iobus.trans_dist::WriteReq 59014 # Transaction distribution --- 189 unchanged lines hidden (view full) --- 1666system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency 1667system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency 1668system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency 1669system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1670system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency 1671system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1672system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency 1673system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1658system.membus.trans_dist::ReadReq 68566 # Transaction distribution 1659system.membus.trans_dist::ReadResp 68565 # Transaction distribution | 1674system.membus.trans_dist::ReadReq 68567 # Transaction distribution 1675system.membus.trans_dist::ReadResp 68566 # Transaction distribution |
| 1660system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1661system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1662system.membus.trans_dist::Writeback 131056 # Transaction distribution 1663system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1664system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1665system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution 1666system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1667system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution 1668system.membus.trans_dist::ReadExReq 138681 # Transaction distribution 1669system.membus.trans_dist::ReadExResp 138681 # Transaction distribution 1670system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1671system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1672system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) | 1676system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1677system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1678system.membus.trans_dist::Writeback 131056 # Transaction distribution 1679system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1680system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1681system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution 1682system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1683system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution 1684system.membus.trans_dist::ReadExReq 138681 # Transaction distribution 1685system.membus.trans_dist::ReadExResp 138681 # Transaction distribution 1686system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1687system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1688system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
| 1673system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) 1674system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) | 1689system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) 1690system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) |
| 1675system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) 1676system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) | 1691system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) 1692system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) |
| 1677system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) | 1693system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) |
| 1678system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1679system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1680system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) | 1694system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1695system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1696system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
| 1681system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) 1682system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) | 1697system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) 1698system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) |
| 1683system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1684system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) | 1699system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1700system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) |
| 1685system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) | 1701system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) |
| 1686system.membus.snoops 497 # Total snoops (count) | 1702system.membus.snoops 497 # Total snoops (count) |
| 1687system.membus.snoop_fanout::samples 345038 # Request fanout histogram | 1703system.membus.snoop_fanout::samples 406751 # Request fanout histogram |
| 1688system.membus.snoop_fanout::mean 1 # Request fanout histogram 1689system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1690system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1691system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1704system.membus.snoop_fanout::mean 1 # Request fanout histogram 1705system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1706system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1707system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1692system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram | 1708system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram |
| 1693system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1694system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1695system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1696system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1709system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1710system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1711system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1712system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1697system.membus.snoop_fanout::total 345038 # Request fanout histogram | 1713system.membus.snoop_fanout::total 406751 # Request fanout histogram |
| 1698system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) 1699system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1700system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1701system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1702system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) 1703system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1714system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) 1715system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1716system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 1717system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1718system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) 1719system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1704system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) | 1720system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) |
| 1705system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 1721system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 1706system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) | 1722system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) |
| 1707system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1708system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) 1709system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1710system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1711system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1712system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1713system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1714system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 30 unchanged lines hidden --- | 1723system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1724system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) 1725system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1726system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1727system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1728system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1729system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1730system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU --- 30 unchanged lines hidden --- |