| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.827025 # Number of seconds simulated 4sim_ticks 2827025397500 # Number of ticks simulated 5final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.827616 # Number of seconds simulated 4sim_ticks 2827616186000 # Number of ticks simulated 5final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 96738 # Simulator instruction rate (inst/s) 8host_op_rate 117339 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2415768223 # Simulator tick rate (ticks/s) 10host_mem_usage 619580 # Number of bytes of host memory used 11host_seconds 1170.24 # Real time elapsed on the host 12sim_insts 113206948 # Number of instructions simulated 13sim_ops 137314363 # Number of ops (including micro ops) simulated | 7host_inst_rate 99248 # Simulator instruction rate (inst/s) 8host_op_rate 120386 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2480177298 # Simulator tick rate (ticks/s) 10host_mem_usage 619560 # Number of bytes of host memory used 11host_seconds 1140.09 # Real time elapsed on the host 12sim_insts 113151083 # Number of instructions simulated 13sim_ops 137250963 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory | 26system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) | 52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 171932 # Number of read requests accepted 55system.physmem.writeReqs 167449 # Number of write requests accepted 56system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue 60system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11320 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10283 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11137 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11363 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13028 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10237 # Per bank write bursts 72system.physmem.perBankRdBursts::6 10954 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11381 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10407 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11232 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10729 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9386 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9853 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10909 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9951 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9636 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10810 # Per bank write bursts 83system.physmem.perBankWrBursts::1 10132 # Per bank write bursts 84system.physmem.perBankWrBursts::2 10502 # Per bank write bursts 85system.physmem.perBankWrBursts::3 10558 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9654 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9978 # Per bank write bursts 88system.physmem.perBankWrBursts::6 10358 # Per bank write bursts 89system.physmem.perBankWrBursts::7 10535 # Per bank write bursts 90system.physmem.perBankWrBursts::8 10309 # Per bank write bursts 91system.physmem.perBankWrBursts::9 10935 # Per bank write bursts 92system.physmem.perBankWrBursts::10 10009 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9154 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9556 # Per bank write bursts 95system.physmem.perBankWrBursts::13 10555 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9521 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9009 # Per bank write bursts | 53system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 176173 # Number of read requests accepted 55system.physmem.writeReqs 171661 # Number of write requests accepted 56system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue 60system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 11334 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10890 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10732 # Per bank write bursts 69system.physmem.perBankRdBursts::3 10393 # Per bank write bursts 70system.physmem.perBankRdBursts::4 14045 # Per bank write bursts 71system.physmem.perBankRdBursts::5 11531 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11498 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11674 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10645 # Per bank write bursts 75system.physmem.perBankRdBursts::9 10993 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10307 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9597 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9956 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10908 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10689 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10844 # Per bank write bursts 82system.physmem.perBankWrBursts::0 9257 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9346 # Per bank write bursts 84system.physmem.perBankWrBursts::2 9336 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8962 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9705 # Per bank write bursts 87system.physmem.perBankWrBursts::5 9746 # Per bank write bursts 88system.physmem.perBankWrBursts::6 9125 # Per bank write bursts 89system.physmem.perBankWrBursts::7 9630 # Per bank write bursts 90system.physmem.perBankWrBursts::8 9307 # Per bank write bursts 91system.physmem.perBankWrBursts::9 9634 # Per bank write bursts 92system.physmem.perBankWrBursts::10 8942 # Per bank write bursts 93system.physmem.perBankWrBursts::11 8449 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8881 # Per bank write bursts 95system.physmem.perBankWrBursts::13 9361 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9018 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9072 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2827025186500 # Total gap between requests | 99system.physmem.numWrRetry 58 # Number of times write queue was full causing retry 100system.physmem.totGap 2827615975000 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 541 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 541 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) |
| 105system.physmem.readPktSize::4 2993 # Read request sizes (log2) | 105system.physmem.readPktSize::4 2994 # Read request sizes (log2) |
| 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 168384 # Read request sizes (log2) | 107system.physmem.readPktSize::6 172624 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 163068 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 167280 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads 282system.physmem.totQLat 2011805750 # Total ticks spent queuing 283system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM 284system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers 285system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst | 162system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads 268system.physmem.totQLat 2104910750 # Total ticks spent queuing 269system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst |
| 286system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 287system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst 288system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s 289system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s 290system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s 291system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s | 273system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s |
| 292system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 293system.physmem.busUtil 0.06 # Data bus utilization in percentage 294system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 295system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 296system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.06 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 297system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing 298system.physmem.readRowHits 141825 # Number of row buffer hits during reads 299system.physmem.writeRowHits 127038 # Number of row buffer hits during writes 300system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads 301system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes 302system.physmem.avgGap 8329945.36 # Average gap between requests 303system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined 304system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) 305system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) 306system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) 307system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) 308system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) 309system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) 310system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) 311system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) 312system.physmem_0.averagePower 669.379373 # Core power per rank (mW) 313system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states 314system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states | 283system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing 284system.physmem.readRowHits 145058 # Number of row buffer hits during reads 285system.physmem.writeRowHits 112529 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes 288system.physmem.avgGap 8129210.99 # Average gap between requests 289system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) 298system.physmem_0.averagePower 669.422846 # Core power per rank (mW) 299system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states 300system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states |
| 315system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 316system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states | 302system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states |
| 317system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 318system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) 319system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) 320system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) 321system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) 322system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) 323system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) 324system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) 325system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) 326system.physmem_1.averagePower 669.289511 # Core power per rank (mW) 327system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states 328system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states | 304system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) 312system.physmem_1.averagePower 669.324331 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states 314system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states |
| 329system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 330system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states | 316system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states |
| 331system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 333system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 334system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 335system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 336system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 337system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 338system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 343system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 344system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 345system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 346system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 347system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 348system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 349system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 319system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 320system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 321system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 322system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 323system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 324system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 329system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 330system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 331system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 332system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 333system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 334system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 335system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 350system.cpu.branchPred.lookups 46965884 # Number of BP lookups 351system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted 352system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect 353system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups 354system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits | 336system.cpu.branchPred.lookups 46937284 # Number of BP lookups 337system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted 338system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect 339system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups 340system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits |
| 355system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 341system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 356system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage 357system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. 358system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. | 342system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage 343system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. 344system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. |
| 359system.cpu_clk_domain.clock 500 # Clock period in ticks 360system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 381system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 382system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 384system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 385system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 386system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 387system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 388system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 345system.cpu_clk_domain.clock 500 # Clock period in ticks 346system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 347system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 367system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 370system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 371system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 372system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 373system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 374system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 389system.cpu.dtb.walker.walks 69937 # Table walker walks requested 390system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors 391system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate 392system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate 393system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting 394system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency | 375system.cpu.dtb.walker.walks 72371 # Table walker walks requested 376system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors 377system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate 378system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate 379system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting 380system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency 381system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency 382system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency 383system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency 384system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency 385system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency 389system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency 390system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency |
| 408system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency | 394system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency |
| 409system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency 410system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution 431system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution 432system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution 433system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated 434system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated 435system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated 436system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst | 395system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency 405system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution 410system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution 411system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution 412system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution 413system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution 414system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution 417system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution 422system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated 423system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated 424system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated 425system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst |
| 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 426system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 438system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst | 427system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst 428system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst |
| 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 429system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 441system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst | 430system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst |
| 443system.cpu.dtb.inst_hits 0 # ITB inst hits 444system.cpu.dtb.inst_misses 0 # ITB inst misses | 432system.cpu.dtb.inst_hits 0 # ITB inst hits 433system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 445system.cpu.dtb.read_hits 25472400 # DTB read hits 446system.cpu.dtb.read_misses 60528 # DTB read misses 447system.cpu.dtb.write_hits 19920178 # DTB write hits 448system.cpu.dtb.write_misses 9409 # DTB write misses | 434system.cpu.dtb.read_hits 25461870 # DTB read hits 435system.cpu.dtb.read_misses 62291 # DTB read misses 436system.cpu.dtb.write_hits 19915387 # DTB write hits 437system.cpu.dtb.write_misses 10080 # DTB write misses |
| 449system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 450system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 451system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 452system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 438system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 439system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 440system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 441system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 453system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB 454system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions 455system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch | 442system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB 443system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions 444system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch |
| 456system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 445system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 457system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions 458system.cpu.dtb.read_accesses 25532928 # DTB read accesses 459system.cpu.dtb.write_accesses 19929587 # DTB write accesses | 446system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions 447system.cpu.dtb.read_accesses 25524161 # DTB read accesses 448system.cpu.dtb.write_accesses 19925467 # DTB write accesses |
| 460system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 449system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 461system.cpu.dtb.hits 45392578 # DTB hits 462system.cpu.dtb.misses 69937 # DTB misses 463system.cpu.dtb.accesses 45462515 # DTB accesses | 450system.cpu.dtb.hits 45377257 # DTB hits 451system.cpu.dtb.misses 72371 # DTB misses 452system.cpu.dtb.accesses 45449628 # DTB accesses |
| 464system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 485system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 486system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 487system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 488system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 489system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 490system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 491system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 492system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 453system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 454system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 455system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 456system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 457system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 474system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 475system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 476system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 477system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 478system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 479system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 480system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 481system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 493system.cpu.itb.walker.walks 11957 # Table walker walks requested 494system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors 495system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate 496system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate 497system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting 498system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency | 482system.cpu.itb.walker.walks 11974 # Table walker walks requested 483system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors 484system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate 485system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate 486system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting 487system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency 488system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency 489system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency 490system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency 491system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency 492system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency 493system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency 494system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency |
| 506system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency | 495system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency |
| 508system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution 522system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution 523system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution 529system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution 530system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated 531system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated 532system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated | 497system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution 512system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution 513system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution 514system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution 515system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution 516system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution 517system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution 518system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution 519system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution 520system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated 521system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated 522system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated |
| 533system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 523system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 534system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst 535system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst | 524system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst 525system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst |
| 536system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 526system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 537system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst 538system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst 539system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst 540system.cpu.itb.inst_hits 66242388 # ITB inst hits 541system.cpu.itb.inst_misses 11957 # ITB inst misses | 527system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst 528system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst 529system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst 530system.cpu.itb.inst_hits 66270436 # ITB inst hits 531system.cpu.itb.inst_misses 11974 # ITB inst misses |
| 542system.cpu.itb.read_hits 0 # DTB read hits 543system.cpu.itb.read_misses 0 # DTB read misses 544system.cpu.itb.write_hits 0 # DTB write hits 545system.cpu.itb.write_misses 0 # DTB write misses 546system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 547system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 548system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 549system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 532system.cpu.itb.read_hits 0 # DTB read hits 533system.cpu.itb.read_misses 0 # DTB read misses 534system.cpu.itb.write_hits 0 # DTB write hits 535system.cpu.itb.write_misses 0 # DTB write misses 536system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 537system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 538system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 539system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 550system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB | 540system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB |
| 551system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 552system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 553system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 541system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 542system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 543system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 554system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions | 544system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions |
| 555system.cpu.itb.read_accesses 0 # DTB read accesses 556system.cpu.itb.write_accesses 0 # DTB write accesses | 545system.cpu.itb.read_accesses 0 # DTB read accesses 546system.cpu.itb.write_accesses 0 # DTB write accesses |
| 557system.cpu.itb.inst_accesses 66254345 # ITB inst accesses 558system.cpu.itb.hits 66242388 # DTB hits 559system.cpu.itb.misses 11957 # DTB misses 560system.cpu.itb.accesses 66254345 # DTB accesses 561system.cpu.numCycles 260505842 # number of cpu cycles simulated | 547system.cpu.itb.inst_accesses 66282410 # ITB inst accesses 548system.cpu.itb.hits 66270436 # DTB hits 549system.cpu.itb.misses 11974 # DTB misses 550system.cpu.itb.accesses 66282410 # DTB accesses 551system.cpu.numCycles 263104506 # number of cpu cycles simulated |
| 562system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 563system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 552system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 553system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 564system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss 565system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed 566system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered 567system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken 568system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked 569system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing 570system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb 571system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 572system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps 573system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions 574system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR 575system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched 576system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed 577system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed 578system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) | 554system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss 555system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed 556system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered 557system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken 558system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked 559system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing 560system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb 561system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 562system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps 563system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions 564system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR 565system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched 566system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed 567system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed 568system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) |
| 581system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 571system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 582system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) 583system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) 584system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) 585system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) | 572system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) |
| 586system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 587system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 588system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 576system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 589system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle 591system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle 592system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle 593system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked 594system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running 595system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking 596system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing 597system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch 598system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction 599system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode 600system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode 601system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing 602system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle 603system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking 604system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst 605system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running 606system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking 607system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename 608system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename 609system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full 610system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full 611system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full 612system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full 613system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed 614system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made 615system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups 616system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups 617system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed 618system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing 619system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed 620system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed 621system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer 622system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. 623system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. 624system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. 625system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. 626system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) 627system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ 628system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued 629system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued 630system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling 631system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph 632system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed 633system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle | 579system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle 581system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle 582system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle 583system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked 584system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running 585system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking 586system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing 587system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch 588system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction 589system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode 590system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode 591system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing 592system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle 593system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking 594system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst 595system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running 596system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking 597system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename 598system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename 599system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full 600system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full 601system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full 602system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full 603system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed 604system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made 605system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups 606system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups 607system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed 608system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing 609system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed 610system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed 611system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer 612system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. 613system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. 614system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. 615system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. 616system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) 617system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ 618system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued 619system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued 620system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling 621system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph 622system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed 623system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle |
| 636system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 626system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 637system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle 641system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle | 627system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle |
| 642system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 643system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 644system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 645system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 632system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 649system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle | 639system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle |
| 650system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 640system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 651system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available 652system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available 653system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 654system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 655system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 656system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 657system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 658system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 659system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available 680system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available 681system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available | 641system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available 642system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available 643system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available 648system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available 670system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available 671system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available |
| 682system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 683system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 684system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued | 672system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 673system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 674system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued |
| 685system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued 686system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued | 675system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued 676system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued |
| 687system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 688system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 689system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 690system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 691system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 692system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 693system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 702system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued | 677system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 678system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 679system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 680system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 681system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 682system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 683system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 692system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued |
| 710system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued | 700system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued |
| 711system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued | 701system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 702system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued |
| 714system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued 715system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued | 704system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued 705system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued |
| 716system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 717system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 706system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 707system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 718system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued 719system.cpu.iq.rate 0.550386 # Inst issue rate 720system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested 721system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) 722system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads 723system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes 724system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses 725system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads 726system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes 727system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses 728system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses 729system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses 730system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores | 708system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued 709system.cpu.iq.rate 0.544758 # Inst issue rate 710system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested 711system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) 712system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads 713system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes 714system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses 715system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads 716system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes 717system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses 718system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses 719system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses 720system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores |
| 731system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 721system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 732system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed 733system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed 734system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations 735system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed | 722system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed 723system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed 724system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations 725system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed |
| 736system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 737system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 726system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 727system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 738system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled 739system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked | 728system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled 729system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked |
| 740system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 730system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 741system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing 742system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking 743system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking 744system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ | 731system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing 732system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking 733system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking 734system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ |
| 745system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 735system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 746system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions 747system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions 748system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions 749system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall 750system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall 751system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations 752system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly 753system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly 754system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute 755system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions 756system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed 757system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute | 736system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions 737system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions 738system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions 739system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall 740system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall 741system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations 742system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly 743system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly 744system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute 745system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions 746system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed 747system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute |
| 758system.cpu.iew.exec_swp 0 # number of swp insts executed | 748system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 759system.cpu.iew.exec_nop 200965 # number of nop insts executed 760system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed 761system.cpu.iew.exec_branches 26544582 # Number of branches executed 762system.cpu.iew.exec_stores 20883032 # Number of stores executed 763system.cpu.iew.exec_rate 0.546767 # Inst execution rate 764system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit 765system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back 766system.cpu.iew.wb_producers 63301991 # num instructions producing a value 767system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value | 749system.cpu.iew.exec_nop 201053 # number of nop insts executed 750system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed 751system.cpu.iew.exec_branches 26530134 # Number of branches executed 752system.cpu.iew.exec_stores 20877849 # Number of stores executed 753system.cpu.iew.exec_rate 0.541163 # Inst execution rate 754system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit 755system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back 756system.cpu.iew.wb_producers 63271750 # num instructions producing a value 757system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value |
| 768system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 758system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 769system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle 770system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back | 759system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle 760system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back |
| 771system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 761system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 772system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit 773system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards 774system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted 775system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle | 762system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit 763system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards 764system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted 765system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle |
| 778system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 768system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 779system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle 783system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle 784system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle 785system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle | 769system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle |
| 788system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 778system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 780system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 791system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle 792system.cpu.commit.committedInsts 113361853 # Number of instructions committed 793system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed | 781system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle 782system.cpu.commit.committedInsts 113305988 # Number of instructions committed 783system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed |
| 794system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 784system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 795system.cpu.commit.refs 45532382 # Number of memory references committed 796system.cpu.commit.loads 24928817 # Number of loads committed 797system.cpu.commit.membars 814713 # Number of memory barriers committed 798system.cpu.commit.branches 26060941 # Number of branches committed | 785system.cpu.commit.refs 45511652 # Number of memory references committed 786system.cpu.commit.loads 24916104 # Number of loads committed 787system.cpu.commit.membars 814017 # Number of memory barriers committed 788system.cpu.commit.branches 26045610 # Number of branches committed |
| 799system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. | 789system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. |
| 800system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. 801system.cpu.commit.function_calls 4896517 # Number of function calls committed. | 790system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. 791system.cpu.commit.function_calls 4892502 # Number of function calls committed. |
| 802system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 792system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 803system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction 804system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction | 793system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction 794system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction |
| 805system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 806system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 807system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 808system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 809system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 810system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 811system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 820system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction | 795system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 796system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 797system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 798system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 799system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 800system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 801system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 7 unchanged lines hidden (view full) --- 810system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 814system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 815system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 816system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction |
| 828system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction | 818system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction |
| 829system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction | 819system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 820system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction |
| 832system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction 833system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction | 822system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction 823system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction |
| 834system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 835system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 824system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 825system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 836system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction 837system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached | 826system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction 827system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached |
| 838system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 828system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 839system.cpu.rob.rob_reads 373323554 # The number of ROB reads 840system.cpu.rob.rob_writes 293054802 # The number of ROB writes 841system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself 842system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling 843system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 844system.cpu.committedInsts 113206948 # Number of Instructions Simulated 845system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated 846system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction 847system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads 848system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle 849system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads 850system.cpu.int_regfile_reads 155872747 # number of integer regfile reads 851system.cpu.int_regfile_writes 88664446 # number of integer regfile writes 852system.cpu.fp_regfile_reads 9607 # number of floating regfile reads | 829system.cpu.rob.rob_reads 375672050 # The number of ROB reads 830system.cpu.rob.rob_writes 292972268 # The number of ROB writes 831system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself 832system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling 833system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 834system.cpu.committedInsts 113151083 # Number of Instructions Simulated 835system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated 836system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction 837system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads 838system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle 839system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads 840system.cpu.int_regfile_reads 155826637 # number of integer regfile reads 841system.cpu.int_regfile_writes 88633021 # number of integer regfile writes 842system.cpu.fp_regfile_reads 9606 # number of floating regfile reads |
| 853system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 843system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 854system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads 855system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes 856system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads 857system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes 858system.cpu.dcache.tags.replacements 837844 # number of replacements 859system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use 860system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. 861system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. 862system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. 863system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. 864system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor 865system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy 866system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy | 844system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads 845system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes 846system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads 847system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes 848system.cpu.dcache.tags.replacements 839617 # number of replacements 849system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use 850system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. 851system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. 852system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. 853system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. 854system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor 855system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy 856system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy |
| 867system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 857system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 868system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 869system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id 870system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id | 858system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 859system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 860system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id |
| 871system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 861system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 872system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses 873system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses 874system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits 875system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits 876system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits 877system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits 878system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits 879system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits 880system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits 881system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits 882system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits 883system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits 884system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits 885system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits 886system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits 887system.cpu.dcache.overall_hits::total 39264228 # number of overall hits 888system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses 889system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses 890system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses 891system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses 892system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses 893system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses 894system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses 895system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses 896system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses 897system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses 898system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses 899system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses 900system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses 901system.cpu.dcache.overall_misses::total 4453577 # number of overall misses 902system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles 903system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles 904system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles 905system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles 906system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles 907system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles 908system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles 909system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles 910system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles 911system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles 912system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles 913system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles 914system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) 915system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) 916system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) 917system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) 918system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) 919system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) 920system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) 921system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) 922system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) 923system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) 924system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses 925system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses 926system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses 927system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses 928system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses 929system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses 930system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses 931system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses 932system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses 933system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses 934system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses 935system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses 936system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 937system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 938system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses 939system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses 940system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses 941system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses 942system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency 943system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency 944system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency 945system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency 946system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency 947system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency 948system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency 949system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency 950system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency 951system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency 952system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency 953system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency 954system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked | 862system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses 863system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses 864system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits 865system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits 866system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits 867system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits 868system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits 869system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits 870system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits 871system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits 872system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits 873system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits 874system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits 875system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits 876system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits 877system.cpu.dcache.overall_hits::total 39222942 # number of overall hits 878system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses 879system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses 880system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses 881system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses 882system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses 883system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses 884system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses 885system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses 886system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 887system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 888system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses 889system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses 890system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses 891system.cpu.dcache.overall_misses::total 4478306 # number of overall misses 892system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles 893system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles 894system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles 895system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles 896system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles 897system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles 898system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles 899system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles 900system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles 901system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles 902system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles 903system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles 904system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) 905system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) 906system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) 907system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) 908system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) 909system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) 910system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) 911system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) 912system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) 913system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) 914system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses 915system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses 916system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses 917system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses 918system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses 919system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses 920system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses 921system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses 922system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses 923system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses 924system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses 925system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses 926system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 927system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 928system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses 929system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses 930system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses 931system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses 932system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency 933system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency 934system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency 935system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency 936system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency 937system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency 938system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency 939system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency 940system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency 941system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency 942system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency 943system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency 944system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked |
| 955system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 945system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 956system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked | 946system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked |
| 957system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 947system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 958system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked | 948system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked |
| 959system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 960system.cpu.dcache.fast_writes 0 # number of fast writes performed 961system.cpu.dcache.cache_copies 0 # number of cache copies performed | 949system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 950system.cpu.dcache.fast_writes 0 # number of fast writes performed 951system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 962system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks 963system.cpu.dcache.writebacks::total 695426 # number of writebacks 964system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits 965system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits 966system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits 967system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits 968system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits 969system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits 970system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits 971system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits 972system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits 973system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits 974system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses 975system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses 976system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses 977system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses 978system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses 979system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses 980system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses 981system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses 982system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses 983system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses 984system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses 985system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses 986system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses 987system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses 988system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles 989system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles 990system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles 991system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles 992system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles 993system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles 994system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles 995system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles 996system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles 997system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles 998system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles 999system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles 1000system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles 1001system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles 1002system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles 1003system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles 1004system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles 1005system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles 1006system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles 1007system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles 1008system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses 1009system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses 1010system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses 1011system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses 1012system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses 1013system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses 1014system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses 1015system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses 1016system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1017system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 1018system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses 1019system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses 1020system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses 1021system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses 1022system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency 1023system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency 1024system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency 1025system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency 1026system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency 1027system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency 1028system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency 1029system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency 1030system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency 1031system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency 1032system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency 1033system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency 1034system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency 1035system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency | 952system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks 953system.cpu.dcache.writebacks::total 696320 # number of writebacks 954system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits 955system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits 956system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits 957system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits 958system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits 959system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits 960system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits 961system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits 962system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits 963system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits 964system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses 965system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses 966system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses 967system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses 968system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses 969system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses 970system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses 971system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses 972system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 973system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 974system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses 975system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses 976system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses 977system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses 978system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles 979system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles 980system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles 981system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles 982system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles 983system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles 984system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles 985system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles 986system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles 987system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles 988system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles 989system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles 990system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles 991system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles 992system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles 993system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles 994system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles 995system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles 996system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles 997system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles 998system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses 999system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses 1000system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses 1001system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses 1002system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses 1003system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses 1004system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses 1005system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses 1006system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1007system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1008system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses 1009system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses 1010system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses 1011system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses 1012system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency 1013system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency 1014system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency 1015system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency 1016system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency 1017system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency 1018system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency 1019system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency 1020system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency 1021system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency 1022system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency 1023system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency 1024system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency 1025system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency |
| 1036system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1037system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1038system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1039system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1040system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1041system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1042system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1026system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1027system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1028system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1029system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1030system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1031system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1032system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1043system.cpu.icache.tags.replacements 1894041 # number of replacements 1044system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use 1045system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. 1046system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. 1047system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. 1048system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. 1049system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor 1050system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy 1051system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy | 1033system.cpu.icache.tags.replacements 1892540 # number of replacements 1034system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use 1035system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. 1036system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. 1037system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. 1038system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. 1039system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor 1040system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy 1041system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy |
| 1052system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1042system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1053system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id 1054system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 1055system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id 1056system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id | 1043system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 1044system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 1045system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id 1046system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
| 1057system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1047system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1058system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses 1059system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses 1060system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits 1061system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits 1062system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits 1063system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits 1064system.cpu.icache.overall_hits::cpu.inst 64258114 # number of overall hits 1065system.cpu.icache.overall_hits::total 64258114 # number of overall hits 1066system.cpu.icache.ReadReq_misses::cpu.inst 1981572 # number of ReadReq misses 1067system.cpu.icache.ReadReq_misses::total 1981572 # number of ReadReq misses 1068system.cpu.icache.demand_misses::cpu.inst 1981572 # number of demand (read+write) misses 1069system.cpu.icache.demand_misses::total 1981572 # number of demand (read+write) misses 1070system.cpu.icache.overall_misses::cpu.inst 1981572 # number of overall misses 1071system.cpu.icache.overall_misses::total 1981572 # number of overall misses 1072system.cpu.icache.ReadReq_miss_latency::cpu.inst 26765848354 # number of ReadReq miss cycles 1073system.cpu.icache.ReadReq_miss_latency::total 26765848354 # number of ReadReq miss cycles 1074system.cpu.icache.demand_miss_latency::cpu.inst 26765848354 # number of demand (read+write) miss cycles 1075system.cpu.icache.demand_miss_latency::total 26765848354 # number of demand (read+write) miss cycles 1076system.cpu.icache.overall_miss_latency::cpu.inst 26765848354 # number of overall miss cycles 1077system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles 1078system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses) 1079system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses) 1080system.cpu.icache.demand_accesses::cpu.inst 66239686 # number of demand (read+write) accesses 1081system.cpu.icache.demand_accesses::total 66239686 # number of demand (read+write) accesses 1082system.cpu.icache.overall_accesses::cpu.inst 66239686 # number of overall (read+write) accesses 1083system.cpu.icache.overall_accesses::total 66239686 # number of overall (read+write) accesses 1084system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029915 # miss rate for ReadReq accesses 1085system.cpu.icache.ReadReq_miss_rate::total 0.029915 # miss rate for ReadReq accesses 1086system.cpu.icache.demand_miss_rate::cpu.inst 0.029915 # miss rate for demand accesses 1087system.cpu.icache.demand_miss_rate::total 0.029915 # miss rate for demand accesses 1088system.cpu.icache.overall_miss_rate::cpu.inst 0.029915 # miss rate for overall accesses 1089system.cpu.icache.overall_miss_rate::total 0.029915 # miss rate for overall accesses 1090system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187 # average ReadReq miss latency 1091system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187 # average ReadReq miss latency 1092system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency 1093system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency 1094system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency 1095system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency 1096system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked | 1048system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses 1049system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses 1050system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits 1051system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits 1052system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits 1053system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits 1054system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits 1055system.cpu.icache.overall_hits::total 64285030 # number of overall hits 1056system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses 1057system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses 1058system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses 1059system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses 1060system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses 1061system.cpu.icache.overall_misses::total 1982600 # number of overall misses 1062system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles 1063system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles 1064system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles 1065system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles 1066system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles 1067system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles 1068system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) 1069system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) 1070system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses 1071system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses 1072system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses 1073system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses 1074system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses 1075system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses 1076system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses 1077system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses 1078system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses 1079system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses 1080system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency 1081system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency 1082system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency 1083system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency 1084system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency 1085system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency 1086system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked |
| 1097system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1087system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1098system.cpu.icache.blocked::no_mshrs 103 # number of cycles access was blocked | 1088system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked |
| 1099system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1089system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1100system.cpu.icache.avg_blocked_cycles::no_mshrs 19.582524 # average number of cycles each access was blocked | 1090system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked |
| 1101system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1102system.cpu.icache.fast_writes 0 # number of fast writes performed 1103system.cpu.icache.cache_copies 0 # number of cache copies performed | 1091system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1092system.cpu.icache.fast_writes 0 # number of fast writes performed 1093system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 1104system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87002 # number of ReadReq MSHR hits 1105system.cpu.icache.ReadReq_mshr_hits::total 87002 # number of ReadReq MSHR hits 1106system.cpu.icache.demand_mshr_hits::cpu.inst 87002 # number of demand (read+write) MSHR hits 1107system.cpu.icache.demand_mshr_hits::total 87002 # number of demand (read+write) MSHR hits 1108system.cpu.icache.overall_mshr_hits::cpu.inst 87002 # number of overall MSHR hits 1109system.cpu.icache.overall_mshr_hits::total 87002 # number of overall MSHR hits 1110system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses 1111system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses 1112system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses 1113system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses 1114system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses 1115system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses 1116system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22163460869 # number of ReadReq MSHR miss cycles 1117system.cpu.icache.ReadReq_mshr_miss_latency::total 22163460869 # number of ReadReq MSHR miss cycles 1118system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles 1119system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles 1120system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles 1121system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles 1122system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles 1123system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles 1124system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles 1125system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles 1126system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses 1127system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses 1128system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses 1129system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses 1130system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses 1131system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses 1132system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235 # average ReadReq mshr miss latency 1133system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235 # average ReadReq mshr miss latency 1134system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency 1135system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency 1136system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency 1137system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency | 1094system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits 1095system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits 1096system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits 1097system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits 1098system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits 1099system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits 1100system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses 1101system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses 1102system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses 1103system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses 1104system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses 1105system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses 1106system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles 1107system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles 1108system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles 1109system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles 1110system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles 1111system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles 1112system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles 1113system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles 1114system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles 1115system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles 1116system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses 1117system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses 1118system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses 1119system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses 1120system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses 1121system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses 1122system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency 1123system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency 1124system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1125system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency 1126system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency 1127system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency |
| 1138system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1139system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1140system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1141system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1142system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1128system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1129system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1130system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1131system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1132system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1143system.cpu.l2cache.tags.replacements 98730 # number of replacements 1144system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use 1145system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks. 1146system.cpu.l2cache.tags.sampled_refs 163872 # Sample count of references to valid blocks. 1147system.cpu.l2cache.tags.avg_refs 18.424606 # Average number of references to valid blocks. | 1133system.cpu.l2cache.tags.replacements 103160 # number of replacements 1134system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use 1135system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. 1136system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. 1137system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. |
| 1148system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1138system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1149system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196 # Average occupied blocks per requestor 1150system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.158546 # Average occupied blocks per requestor 1151system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798547 # Average occupied blocks per requestor 1152system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777 # Average occupied blocks per requestor 1153system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor 1154system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy 1155system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy | 1139system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor 1140system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor 1141system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor 1142system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor 1143system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor 1144system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy 1145system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy |
| 1156system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy | 1146system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy |
| 1157system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155608 # Average percentage of cache occupancy 1158system.cpu.l2cache.tags.occ_percent::cpu.data 0.079798 # Average percentage of cache occupancy 1159system.cpu.l2cache.tags.occ_percent::total 0.992968 # Average percentage of cache occupancy 1160system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1161system.cpu.l2cache.tags.occ_task_id_blocks::1024 65129 # Occupied blocks per task id 1162system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1163system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 1164system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 1165system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2965 # Occupied blocks per task id 1166system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6995 # Occupied blocks per task id 1167system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54988 # Occupied blocks per task id 1168system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1169system.cpu.l2cache.tags.occ_task_id_percent::1024 0.993790 # Percentage of cache occupancy per task id 1170system.cpu.l2cache.tags.tag_accesses 28438035 # Number of tag accesses 1171system.cpu.l2cache.tags.data_accesses 28438035 # Number of data accesses 1172system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53702 # number of ReadReq hits 1173system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11727 # number of ReadReq hits 1174system.cpu.l2cache.ReadReq_hits::cpu.inst 1874573 # number of ReadReq hits 1175system.cpu.l2cache.ReadReq_hits::cpu.data 527970 # number of ReadReq hits 1176system.cpu.l2cache.ReadReq_hits::total 2467972 # number of ReadReq hits 1177system.cpu.l2cache.Writeback_hits::writebacks 695426 # number of Writeback hits 1178system.cpu.l2cache.Writeback_hits::total 695426 # number of Writeback hits 1179system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits 1180system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits 1181system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1182system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1183system.cpu.l2cache.ReadExReq_hits::cpu.data 159827 # number of ReadExReq hits 1184system.cpu.l2cache.ReadExReq_hits::total 159827 # number of ReadExReq hits 1185system.cpu.l2cache.demand_hits::cpu.dtb.walker 53702 # number of demand (read+write) hits 1186system.cpu.l2cache.demand_hits::cpu.itb.walker 11727 # number of demand (read+write) hits 1187system.cpu.l2cache.demand_hits::cpu.inst 1874573 # number of demand (read+write) hits 1188system.cpu.l2cache.demand_hits::cpu.data 687797 # number of demand (read+write) hits 1189system.cpu.l2cache.demand_hits::total 2627799 # number of demand (read+write) hits 1190system.cpu.l2cache.overall_hits::cpu.dtb.walker 53702 # number of overall hits 1191system.cpu.l2cache.overall_hits::cpu.itb.walker 11727 # number of overall hits 1192system.cpu.l2cache.overall_hits::cpu.inst 1874573 # number of overall hits 1193system.cpu.l2cache.overall_hits::cpu.data 687797 # number of overall hits 1194system.cpu.l2cache.overall_hits::total 2627799 # number of overall hits 1195system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 20 # number of ReadReq misses | 1147system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy 1148system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy 1149system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy 1150system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1151system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id 1152system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 1153system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 1154system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id 1155system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id 1156system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id 1157system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id 1158system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id 1159system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id 1160system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses 1161system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses 1162system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits 1163system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits 1164system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits 1165system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits 1166system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits 1167system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits 1168system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits 1169system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits 1170system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits 1171system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1172system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1173system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits 1174system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits 1175system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits 1176system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits 1177system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits 1178system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits 1179system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits 1180system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits 1181system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits 1182system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits 1183system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits 1184system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits 1185system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses |
| 1196system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses | 1186system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses |
| 1197system.cpu.l2cache.ReadReq_misses::cpu.inst 19971 # number of ReadReq misses 1198system.cpu.l2cache.ReadReq_misses::cpu.data 13600 # number of ReadReq misses 1199system.cpu.l2cache.ReadReq_misses::total 33598 # number of ReadReq misses 1200system.cpu.l2cache.UpgradeReq_misses::cpu.data 2743 # number of UpgradeReq misses 1201system.cpu.l2cache.UpgradeReq_misses::total 2743 # number of UpgradeReq misses | 1187system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses 1188system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses 1189system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses 1190system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses 1191system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses |
| 1202system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1203system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 1192system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1193system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 1204system.cpu.l2cache.ReadExReq_misses::cpu.data 136984 # number of ReadExReq misses 1205system.cpu.l2cache.ReadExReq_misses::total 136984 # number of ReadExReq misses 1206system.cpu.l2cache.demand_misses::cpu.dtb.walker 20 # number of demand (read+write) misses | 1194system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses 1195system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses 1196system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses |
| 1207system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses | 1197system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses |
| 1208system.cpu.l2cache.demand_misses::cpu.inst 19971 # number of demand (read+write) misses 1209system.cpu.l2cache.demand_misses::cpu.data 150584 # number of demand (read+write) misses 1210system.cpu.l2cache.demand_misses::total 170582 # number of demand (read+write) misses 1211system.cpu.l2cache.overall_misses::cpu.dtb.walker 20 # number of overall misses | 1198system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses 1199system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses 1200system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses 1201system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses |
| 1212system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses | 1202system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses |
| 1213system.cpu.l2cache.overall_misses::cpu.inst 19971 # number of overall misses 1214system.cpu.l2cache.overall_misses::cpu.data 150584 # number of overall misses 1215system.cpu.l2cache.overall_misses::total 170582 # number of overall misses 1216system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1944750 # number of ReadReq miss cycles 1217system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536750 # number of ReadReq miss cycles 1218system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1503081000 # number of ReadReq miss cycles 1219system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1083875750 # number of ReadReq miss cycles 1220system.cpu.l2cache.ReadReq_miss_latency::total 2589438250 # number of ReadReq miss cycles 1221system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 580975 # number of UpgradeReq miss cycles 1222system.cpu.l2cache.UpgradeReq_miss_latency::total 580975 # number of UpgradeReq miss cycles 1223system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles 1224system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 1225system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9863483701 # number of ReadExReq miss cycles 1226system.cpu.l2cache.ReadExReq_miss_latency::total 9863483701 # number of ReadExReq miss cycles 1227system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1944750 # number of demand (read+write) miss cycles 1228system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536750 # number of demand (read+write) miss cycles 1229system.cpu.l2cache.demand_miss_latency::cpu.inst 1503081000 # number of demand (read+write) miss cycles 1230system.cpu.l2cache.demand_miss_latency::cpu.data 10947359451 # number of demand (read+write) miss cycles 1231system.cpu.l2cache.demand_miss_latency::total 12452921951 # number of demand (read+write) miss cycles 1232system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1944750 # number of overall miss cycles 1233system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536750 # number of overall miss cycles 1234system.cpu.l2cache.overall_miss_latency::cpu.inst 1503081000 # number of overall miss cycles 1235system.cpu.l2cache.overall_miss_latency::cpu.data 10947359451 # number of overall miss cycles 1236system.cpu.l2cache.overall_miss_latency::total 12452921951 # number of overall miss cycles 1237system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53722 # number of ReadReq accesses(hits+misses) 1238system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11734 # number of ReadReq accesses(hits+misses) 1239system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894544 # number of ReadReq accesses(hits+misses) 1240system.cpu.l2cache.ReadReq_accesses::cpu.data 541570 # number of ReadReq accesses(hits+misses) 1241system.cpu.l2cache.ReadReq_accesses::total 2501570 # number of ReadReq accesses(hits+misses) 1242system.cpu.l2cache.Writeback_accesses::writebacks 695426 # number of Writeback accesses(hits+misses) 1243system.cpu.l2cache.Writeback_accesses::total 695426 # number of Writeback accesses(hits+misses) 1244system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2775 # number of UpgradeReq accesses(hits+misses) 1245system.cpu.l2cache.UpgradeReq_accesses::total 2775 # number of UpgradeReq accesses(hits+misses) 1246system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) 1247system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) 1248system.cpu.l2cache.ReadExReq_accesses::cpu.data 296811 # number of ReadExReq accesses(hits+misses) 1249system.cpu.l2cache.ReadExReq_accesses::total 296811 # number of ReadExReq accesses(hits+misses) 1250system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53722 # number of demand (read+write) accesses 1251system.cpu.l2cache.demand_accesses::cpu.itb.walker 11734 # number of demand (read+write) accesses 1252system.cpu.l2cache.demand_accesses::cpu.inst 1894544 # number of demand (read+write) accesses 1253system.cpu.l2cache.demand_accesses::cpu.data 838381 # number of demand (read+write) accesses 1254system.cpu.l2cache.demand_accesses::total 2798381 # number of demand (read+write) accesses 1255system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53722 # number of overall (read+write) accesses 1256system.cpu.l2cache.overall_accesses::cpu.itb.walker 11734 # number of overall (read+write) accesses 1257system.cpu.l2cache.overall_accesses::cpu.inst 1894544 # number of overall (read+write) accesses 1258system.cpu.l2cache.overall_accesses::cpu.data 838381 # number of overall (read+write) accesses 1259system.cpu.l2cache.overall_accesses::total 2798381 # number of overall (read+write) accesses 1260system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000372 # miss rate for ReadReq accesses 1261system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000597 # miss rate for ReadReq accesses 1262system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010541 # miss rate for ReadReq accesses 1263system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025112 # miss rate for ReadReq accesses 1264system.cpu.l2cache.ReadReq_miss_rate::total 0.013431 # miss rate for ReadReq accesses 1265system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988468 # miss rate for UpgradeReq accesses 1266system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988468 # miss rate for UpgradeReq accesses 1267system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses 1268system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses 1269system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461519 # miss rate for ReadExReq accesses 1270system.cpu.l2cache.ReadExReq_miss_rate::total 0.461519 # miss rate for ReadExReq accesses 1271system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000372 # miss rate for demand accesses 1272system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000597 # miss rate for demand accesses 1273system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010541 # miss rate for demand accesses 1274system.cpu.l2cache.demand_miss_rate::cpu.data 0.179613 # miss rate for demand accesses 1275system.cpu.l2cache.demand_miss_rate::total 0.060957 # miss rate for demand accesses 1276system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000372 # miss rate for overall accesses 1277system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000597 # miss rate for overall accesses 1278system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010541 # miss rate for overall accesses 1279system.cpu.l2cache.overall_miss_rate::cpu.data 0.179613 # miss rate for overall accesses 1280system.cpu.l2cache.overall_miss_rate::total 0.060957 # miss rate for overall accesses 1281system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97237.500000 # average ReadReq miss latency 1282system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76678.571429 # average ReadReq miss latency 1283system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75263.181613 # average ReadReq miss latency 1284system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79696.746324 # average ReadReq miss latency 1285system.cpu.l2cache.ReadReq_avg_miss_latency::total 77071.202155 # average ReadReq miss latency 1286system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 211.802771 # average UpgradeReq miss latency 1287system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 211.802771 # average UpgradeReq miss latency 1288system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency 1289system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 1290system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72004.640695 # average ReadExReq miss latency 1291system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72004.640695 # average ReadExReq miss latency 1292system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency 1293system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency 1294system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency 1295system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency 1296system.cpu.l2cache.demand_avg_miss_latency::total 73002.555668 # average overall miss latency 1297system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency 1298system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency 1299system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency 1300system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency 1301system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668 # average overall miss latency | 1203system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses 1204system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses 1205system.cpu.l2cache.overall_misses::total 174879 # number of overall misses 1206system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles 1207system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles 1208system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles 1209system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles 1210system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles 1211system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles 1212system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles 1213system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles 1214system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles 1215system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles 1216system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles 1217system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles 1218system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles 1219system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles 1220system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles 1221system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles 1222system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles 1223system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles 1224system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles 1225system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles 1226system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles 1227system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) 1228system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) 1229system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) 1230system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) 1231system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) 1232system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) 1233system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) 1234system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 1235system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 1236system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1237system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1238system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) 1239system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) 1240system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses 1241system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses 1242system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses 1243system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses 1244system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses 1245system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses 1246system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses 1247system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses 1248system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses 1249system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses 1250system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses 1251system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses 1252system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses 1253system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses 1254system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses 1255system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses 1256system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses 1257system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1258system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses 1259system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses 1260system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses 1261system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses 1262system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses 1263system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses 1264system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses 1265system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses 1266system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses 1267system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses 1268system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses 1269system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses 1270system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses 1271system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency 1272system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency 1273system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency 1274system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency 1275system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency 1276system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency 1277system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency 1278system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency 1279system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency 1280system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency 1281system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency 1282system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency 1283system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency 1284system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency 1285system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency 1286system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency 1287system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency 1288system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency 1289system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency 1290system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency 1291system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency |
| 1302system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1303system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1304system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1305system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1306system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1307system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1308system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1309system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1292system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1293system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1294system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1295system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1296system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1297system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1298system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1299system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1310system.cpu.l2cache.writebacks::writebacks 90654 # number of writebacks 1311system.cpu.l2cache.writebacks::total 90654 # number of writebacks 1312system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits | 1300system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks 1301system.cpu.l2cache.writebacks::total 94866 # number of writebacks 1302system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits |
| 1313system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits | 1303system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits |
| 1314system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits 1315system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits | 1304system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits 1305system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits |
| 1316system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits | 1306system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits |
| 1317system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits 1318system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits | 1307system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits 1308system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits |
| 1319system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits | 1309system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits |
| 1320system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits 1321system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 20 # number of ReadReq MSHR misses | 1310system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits 1311system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses |
| 1322system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses | 1312system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses |
| 1323system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19946 # number of ReadReq MSHR misses 1324system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13488 # number of ReadReq MSHR misses 1325system.cpu.l2cache.ReadReq_mshr_misses::total 33461 # number of ReadReq MSHR misses 1326system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2743 # number of UpgradeReq MSHR misses 1327system.cpu.l2cache.UpgradeReq_mshr_misses::total 2743 # number of UpgradeReq MSHR misses | 1313system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses 1314system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses 1315system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses 1316system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses 1317system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses |
| 1328system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1329system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1318system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1319system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1330system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136984 # number of ReadExReq MSHR misses 1331system.cpu.l2cache.ReadExReq_mshr_misses::total 136984 # number of ReadExReq MSHR misses 1332system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 20 # number of demand (read+write) MSHR misses | 1320system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses 1321system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses 1322system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses |
| 1333system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses | 1323system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses |
| 1334system.cpu.l2cache.demand_mshr_misses::cpu.inst 19946 # number of demand (read+write) MSHR misses 1335system.cpu.l2cache.demand_mshr_misses::cpu.data 150472 # number of demand (read+write) MSHR misses 1336system.cpu.l2cache.demand_mshr_misses::total 170445 # number of demand (read+write) MSHR misses 1337system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 20 # number of overall MSHR misses | 1324system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses 1325system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses 1326system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses 1327system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses |
| 1338system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses | 1328system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses |
| 1339system.cpu.l2cache.overall_mshr_misses::cpu.inst 19946 # number of overall MSHR misses 1340system.cpu.l2cache.overall_mshr_misses::cpu.data 150472 # number of overall MSHR misses 1341system.cpu.l2cache.overall_mshr_misses::total 170445 # number of overall MSHR misses 1342system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1696750 # number of ReadReq MSHR miss cycles 1343system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles 1344system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1250973750 # number of ReadReq MSHR miss cycles 1345system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908888250 # number of ReadReq MSHR miss cycles 1346system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2162010000 # number of ReadReq MSHR miss cycles 1347system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27698243 # number of UpgradeReq MSHR miss cycles 1348system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27698243 # number of UpgradeReq MSHR miss cycles 1349system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles 1350system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 1351system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8149358299 # number of ReadExReq MSHR miss cycles 1352system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8149358299 # number of ReadExReq MSHR miss cycles 1353system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1696750 # number of demand (read+write) MSHR miss cycles 1354system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles 1355system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1250973750 # number of demand (read+write) MSHR miss cycles 1356system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9058246549 # number of demand (read+write) MSHR miss cycles 1357system.cpu.l2cache.demand_mshr_miss_latency::total 10311368299 # number of demand (read+write) MSHR miss cycles 1358system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1696750 # number of overall MSHR miss cycles 1359system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles 1360system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles 1361system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles 1362system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles 1363system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles 1364system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles 1365system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles 1366system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107345000 # number of WriteReq MSHR uncacheable cycles 1367system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107345000 # number of WriteReq MSHR uncacheable cycles 1368system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157876500 # number of overall MSHR uncacheable cycles 1369system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494788500 # number of overall MSHR uncacheable cycles 1370system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652665000 # number of overall MSHR uncacheable cycles 1371system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for ReadReq accesses 1372system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses 1373system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses 1374system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses 1375system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses 1376system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses 1377system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses 1378system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses 1379system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses 1380system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses 1381system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses 1382system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses 1383system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses 1384system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses 1385system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses 1386system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses 1387system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses 1388system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses 1389system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses 1390system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses 1391system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses 1392system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency 1393system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency 1394system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency 1395system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency 1396system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency 1397system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency 1398system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency 1399system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency 1400system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 1401system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency 1402system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency 1403system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency 1404system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency 1405system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency 1406system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency 1407system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency 1408system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency 1409system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency 1410system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency 1411system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency 1412system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency | 1329system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses 1330system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses 1331system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses 1332system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles 1333system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles 1334system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles 1335system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles 1336system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles 1337system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles 1338system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles 1339system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles 1340system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles 1341system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles 1342system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles 1343system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles 1344system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles 1345system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles 1346system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles 1347system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles 1348system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles 1349system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles 1350system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles 1351system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles 1352system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles 1353system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles 1354system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles 1355system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles 1356system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles 1357system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles 1358system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles 1359system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles 1360system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles 1361system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses 1362system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses 1363system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses 1364system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses 1365system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses 1366system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses 1367system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses 1368system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1369system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses 1370system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses 1371system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses 1372system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses 1373system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses 1374system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses 1375system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses 1376system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses 1377system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses 1378system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses 1379system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses 1380system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses 1381system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses 1382system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency 1383system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency 1384system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency 1385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency 1386system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency 1387system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency 1388system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency 1389system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency 1390system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency 1391system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency 1392system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency 1393system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1394system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1395system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency 1396system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency 1397system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency 1398system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency 1399system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency 1400system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency 1401system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency 1402system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency |
| 1413system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1414system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1415system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1416system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1417system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1418system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1419system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1420system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1421system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1403system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1404system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1405system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1406system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1407system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1408system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1409system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1410system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1411system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1422system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution 1423system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution 1424system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution 1425system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution 1426system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution 1427system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1428system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution 1429system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution 1430system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution 1431system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution 1432system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution 1433system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) 1434system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) 1435system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) 1436system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) 1437system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) 1438system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) 1439system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) 1440system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) 1441system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) 1442system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) 1443system.cpu.toL2Bus.snoops 65703 # Total snoops (count) 1444system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram 1445system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram 1446system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram | 1412system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution 1413system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution 1414system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution 1415system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution 1416system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution 1417system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution 1418system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 1419system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1420system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution 1421system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution 1422system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution 1423system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) 1424system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) 1425system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) 1426system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) 1427system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) 1428system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) 1429system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) 1430system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) 1431system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) 1432system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) 1433system.cpu.toL2Bus.snoops 62589 # Total snoops (count) 1434system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram 1435system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram 1436system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram |
| 1447system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1448system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1449system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1450system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1437system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1438system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1439system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1440system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1451system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1452system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1453system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram 1454system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram | 1441system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram 1442system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram |
| 1455system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1443system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1456system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1457system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1458system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram 1459system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) | 1444system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1445system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1446system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram 1447system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) |
| 1460system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1448system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1461system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) | 1449system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) |
| 1462system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1450system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1463system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) | 1451system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) |
| 1464system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1452system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1465system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) | 1453system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) |
| 1466system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1454system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1467system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) | 1455system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) |
| 1468system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1456system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1469system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) | 1457system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) |
| 1470system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1458system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1471system.iobus.trans_dist::ReadReq 30181 # Transaction distribution 1472system.iobus.trans_dist::ReadResp 30181 # Transaction distribution 1473system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1474system.iobus.trans_dist::WriteResp 22814 # Transaction distribution | 1459system.iobus.trans_dist::ReadReq 30182 # Transaction distribution 1460system.iobus.trans_dist::ReadResp 30182 # Transaction distribution 1461system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1462system.iobus.trans_dist::WriteResp 22790 # Transaction distribution |
| 1475system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1463system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1476system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) | 1464system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) |
| 1477system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1478system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1479system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1480system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1481system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1482system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1483system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1484system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1489system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1490system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1491system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1492system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1493system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1494system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1495system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1496system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 1465system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1466system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1467system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1468system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1469system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1470system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1471system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1472system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1477system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1478system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1479system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1480system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1481system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1482system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1483system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1484system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 1497system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1498system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) 1499system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) 1500system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) 1501system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) | 1485system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1486system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) 1487system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) 1488system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) 1489system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) |
| 1502system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1503system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1504system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1505system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1506system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1507system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1508system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1509system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1514system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1515system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1516system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1517system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1518system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1519system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1520system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1521system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 1490system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1491system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1492system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1493system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1494system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1495system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1496system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1497system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1502system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1503system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1504system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1505system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1506system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1507system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1508system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1509system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 1522system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1523system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) 1524system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) 1525system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) 1526system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) | 1510system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1511system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) 1512system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) 1513system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) 1514system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) |
| 1527system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1528system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1529system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1530system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1531system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1532system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1533system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1534system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1558system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1559system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1560system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1561system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1562system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1563system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1564system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1565system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1515system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1516system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1517system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1518system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1519system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1520system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1521system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1522system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) --- 23 unchanged lines hidden (view full) --- 1546system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1547system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1548system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1549system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1550system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1551system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1552system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1553system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1566system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) | 1554system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) |
| 1567system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1568system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1569system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 1555system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1556system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1557system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 1570system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) | 1558system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) |
| 1571system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1559system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1572system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) | 1560system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) |
| 1573system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 1561system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1574system.iocache.tags.replacements 36410 # number of replacements 1575system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use | 1562system.iocache.tags.replacements 36423 # number of replacements 1563system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use |
| 1576system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1564system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1577system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. | 1565system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. |
| 1578system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1566system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1579system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. 1580system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor 1581system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy 1582system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy | 1567system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. 1568system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor 1569system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy 1570system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy |
| 1583system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1584system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1585system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1571system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1572system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1573system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1586system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1587system.iocache.tags.data_accesses 327996 # Number of data accesses 1588system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1589system.iocache.ReadReq_misses::total 220 # number of ReadReq misses | 1574system.iocache.tags.tag_accesses 328113 # Number of tag accesses 1575system.iocache.tags.data_accesses 328113 # Number of data accesses 1576system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses 1577system.iocache.ReadReq_misses::total 233 # number of ReadReq misses |
| 1590system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1591system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses | 1578system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1579system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
| 1592system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses 1593system.iocache.demand_misses::total 220 # number of demand (read+write) misses 1594system.iocache.overall_misses::realview.ide 220 # number of overall misses 1595system.iocache.overall_misses::total 220 # number of overall misses 1596system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles 1597system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles 1598system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles 1599system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles 1600system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles 1601system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles 1602system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles 1603system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles 1604system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1605system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) | 1580system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses 1581system.iocache.demand_misses::total 233 # number of demand (read+write) misses 1582system.iocache.overall_misses::realview.ide 233 # number of overall misses 1583system.iocache.overall_misses::total 233 # number of overall misses 1584system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles 1585system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles 1586system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles 1587system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles 1588system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles 1589system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles 1590system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles 1591system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles 1592system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) 1593system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) |
| 1606system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1607system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) | 1594system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1595system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 1608system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses 1609system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses 1610system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses 1611system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses | 1596system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses 1597system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses 1598system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses 1599system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses |
| 1612system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1613system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1614system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1615system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1616system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1617system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1618system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1619system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1600system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1601system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1602system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1603system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1604system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1605system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1606system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1607system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1620system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency 1621system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency 1622system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency 1623system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency 1624system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency 1625system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency 1626system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency 1627system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency 1628system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked | 1608system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency 1609system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency 1610system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency 1611system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency 1612system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency 1613system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency 1614system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency 1615system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency 1616system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked |
| 1629system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1617system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1630system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked | 1618system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked |
| 1631system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1619system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1632system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked | 1620system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked |
| 1633system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1634system.iocache.fast_writes 0 # number of fast writes performed 1635system.iocache.cache_copies 0 # number of cache copies performed 1636system.iocache.writebacks::writebacks 36190 # number of writebacks 1637system.iocache.writebacks::total 36190 # number of writebacks | 1621system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1622system.iocache.fast_writes 0 # number of fast writes performed 1623system.iocache.cache_copies 0 # number of cache copies performed 1624system.iocache.writebacks::writebacks 36190 # number of writebacks 1625system.iocache.writebacks::total 36190 # number of writebacks |
| 1638system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1639system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses | 1626system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses 1627system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses |
| 1640system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1641system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses | 1628system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1629system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
| 1642system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses 1643system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses 1644system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses 1645system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses 1646system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles 1647system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles 1648system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles 1649system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles 1650system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles 1651system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles 1652system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles 1653system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles | 1630system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses 1631system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses 1632system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses 1633system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses 1634system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles 1635system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles 1636system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles 1637system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles 1638system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles 1639system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles 1640system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles 1641system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles |
| 1654system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1655system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1656system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1657system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1658system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1659system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1660system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1661system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1642system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1643system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1644system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1645system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1646system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1647system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1648system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1649system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1662system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency 1663system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency 1664system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency 1665system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency 1666system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency 1667system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency 1668system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency 1669system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency | 1650system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency 1651system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency 1652system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency 1653system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency 1654system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1655system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency 1656system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency 1657system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency |
| 1670system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1658system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1671system.membus.trans_dist::ReadReq 67820 # Transaction distribution 1672system.membus.trans_dist::ReadResp 67819 # Transaction distribution 1673system.membus.trans_dist::WriteReq 27608 # Transaction distribution 1674system.membus.trans_dist::WriteResp 27608 # Transaction distribution 1675system.membus.trans_dist::Writeback 126844 # Transaction distribution | 1659system.membus.trans_dist::ReadReq 68566 # Transaction distribution 1660system.membus.trans_dist::ReadResp 68565 # Transaction distribution 1661system.membus.trans_dist::WriteReq 27584 # Transaction distribution 1662system.membus.trans_dist::WriteResp 27584 # Transaction distribution 1663system.membus.trans_dist::Writeback 131056 # Transaction distribution |
| 1676system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1677system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1664system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1665system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1678system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution | 1666system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution |
| 1679system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution | 1667system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution |
| 1680system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution 1681system.membus.trans_dist::ReadExReq 135185 # Transaction distribution 1682system.membus.trans_dist::ReadExResp 135185 # Transaction distribution 1683system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) | 1668system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution 1669system.membus.trans_dist::ReadExReq 138681 # Transaction distribution 1670system.membus.trans_dist::ReadExResp 138681 # Transaction distribution 1671system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) |
| 1684system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1685system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) | 1672system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1673system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
| 1686system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) 1687system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) 1688system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) 1689system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) 1690system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) 1691system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) | 1674system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) 1675system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) 1676system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) 1677system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) 1678system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) 1679system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) |
| 1692system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1693system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) | 1680system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1681system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
| 1694system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) 1695system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) | 1682system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) 1683system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) |
| 1696system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1697system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) | 1684system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1685system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) |
| 1698system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) 1699system.membus.snoops 484 # Total snoops (count) 1700system.membus.snoop_fanout::samples 336478 # Request fanout histogram | 1686system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) 1687system.membus.snoops 497 # Total snoops (count) 1688system.membus.snoop_fanout::samples 345038 # Request fanout histogram |
| 1701system.membus.snoop_fanout::mean 1 # Request fanout histogram 1702system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1703system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1704system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1689system.membus.snoop_fanout::mean 1 # Request fanout histogram 1690system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1691system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1692system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1705system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram | 1693system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram |
| 1706system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1707system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1708system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1709system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1694system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1695system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1696system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1697system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1710system.membus.snoop_fanout::total 336478 # Request fanout histogram 1711system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) | 1698system.membus.snoop_fanout::total 345038 # Request fanout histogram 1699system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) |
| 1712system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1700system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1713system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) | 1701system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) |
| 1714system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1702system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1715system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) | 1703system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) |
| 1716system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1704system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1717system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) 1718system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1719system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) 1720system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1721system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) | 1705system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) 1706system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1707system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) 1708system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1709system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) |
| 1722system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1723system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1724system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1725system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1726system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1727system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1728system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1729system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1747system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1748system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1749system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1750system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1751system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1752system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1753system.realview.ethernet.droppedPackets 0 # number of packets dropped 1754system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1710system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1711system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1712system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1713system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1714system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1715system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1716system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1717system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1735system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1736system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1737system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1738system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1739system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1740system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1741system.realview.ethernet.droppedPackets 0 # number of packets dropped 1742system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1755system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed | 1743system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed |
| 1756 1757---------- End Simulation Statistics ---------- | 1744 1745---------- End Simulation Statistics ---------- |