| stats.txt (10535:4ccec5baf82c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.826844 # Number of seconds simulated 4sim_ticks 2826844351500 # Number of ticks simulated 5final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.827042 # Number of seconds simulated 4sim_ticks 2827042159500 # Number of ticks simulated 5final_tick 2827042159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 107954 # Simulator instruction rate (inst/s) 8host_op_rate 130942 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2695726613 # Simulator tick rate (ticks/s) 10host_mem_usage 568304 # Number of bytes of host memory used 11host_seconds 1048.64 # Real time elapsed on the host 12sim_insts 113204796 # Number of instructions simulated 13sim_ops 137311416 # Number of ops (including micro ops) simulated | 7host_inst_rate 100972 # Simulator instruction rate (inst/s) 8host_op_rate 122474 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2522254422 # Simulator tick rate (ticks/s) 10host_mem_usage 564960 # Number of bytes of host memory used 11host_seconds 1120.84 # Real time elapsed on the host 12sim_insts 113173742 # Number of instructions simulated 13sim_ops 137273263 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.data 9496932 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory | 21system.physmem.bytes_read::total 10823604 # Number of bytes read from this memory |
| 22system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory | 22system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory |
| 24system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory | 24system.physmem.bytes_written::writebacks 8116352 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 8133876 # Number of bytes written to this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.data 148909 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 31system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 33system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 171883 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 126818 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 34system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 36system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 37system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory | 35system.physmem.num_writes::total 131199 # Number of write requests responded to by this memory |
| 38system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.inst 468351 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 3359317 # Total read bandwidth from this memory (bytes/s) |
| 42system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) | 40system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) |
| 43system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) | 41system.physmem.bw_read::total 3828597 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 468351 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 468351 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 2870970 # Write bandwidth from this memory (bytes/s) |
| 47system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) | 45system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) |
| 48system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_write::total 2877168 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 2870970 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) |
| 53system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.readReqs 172165 # Number of read requests accepted 58system.physmem.writeReqs 131231 # Number of write requests accepted 59system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue 60system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue 61system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM 62system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue 63system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM 64system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side 65system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side 66system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue 67system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 68system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write 69system.physmem.perBankRdBursts::0 10989 # Per bank write bursts 70system.physmem.perBankRdBursts::1 10130 # Per bank write bursts 71system.physmem.perBankRdBursts::2 11201 # Per bank write bursts 72system.physmem.perBankRdBursts::3 11419 # Per bank write bursts 73system.physmem.perBankRdBursts::4 13122 # Per bank write bursts 74system.physmem.perBankRdBursts::5 10546 # Per bank write bursts 75system.physmem.perBankRdBursts::6 11171 # Per bank write bursts 76system.physmem.perBankRdBursts::7 11539 # Per bank write bursts 77system.physmem.perBankRdBursts::8 10356 # Per bank write bursts 78system.physmem.perBankRdBursts::9 11056 # Per bank write bursts 79system.physmem.perBankRdBursts::10 10496 # Per bank write bursts 80system.physmem.perBankRdBursts::11 9259 # Per bank write bursts 81system.physmem.perBankRdBursts::12 10183 # Per bank write bursts 82system.physmem.perBankRdBursts::13 10761 # Per bank write bursts 83system.physmem.perBankRdBursts::14 10049 # Per bank write bursts 84system.physmem.perBankRdBursts::15 9745 # Per bank write bursts 85system.physmem.perBankWrBursts::0 8312 # Per bank write bursts 86system.physmem.perBankWrBursts::1 7765 # Per bank write bursts 87system.physmem.perBankWrBursts::2 8704 # Per bank write bursts 88system.physmem.perBankWrBursts::3 8604 # Per bank write bursts 89system.physmem.perBankWrBursts::4 7611 # Per bank write bursts 90system.physmem.perBankWrBursts::5 7949 # Per bank write bursts 91system.physmem.perBankWrBursts::6 8258 # Per bank write bursts 92system.physmem.perBankWrBursts::7 8579 # Per bank write bursts 93system.physmem.perBankWrBursts::8 7843 # Per bank write bursts 94system.physmem.perBankWrBursts::9 8531 # Per bank write bursts 95system.physmem.perBankWrBursts::10 7842 # Per bank write bursts 96system.physmem.perBankWrBursts::11 6872 # Per bank write bursts 97system.physmem.perBankWrBursts::12 7611 # Per bank write bursts 98system.physmem.perBankWrBursts::13 8198 # Per bank write bursts 99system.physmem.perBankWrBursts::14 7543 # Per bank write bursts 100system.physmem.perBankWrBursts::15 7118 # Per bank write bursts | 50system.physmem.bw_total::cpu.inst 468351 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3365516 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 6705765 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 171884 # Number of read requests accepted 55system.physmem.writeReqs 167423 # Number of write requests accepted 56system.physmem.readBursts 171884 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 167423 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 10992576 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue 60system.physmem.bytesWritten 10315392 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 10823668 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 10452212 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 6228 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4543 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10965 # Per bank write bursts 67system.physmem.perBankRdBursts::1 10116 # Per bank write bursts 68system.physmem.perBankRdBursts::2 11197 # Per bank write bursts 69system.physmem.perBankRdBursts::3 11389 # Per bank write bursts 70system.physmem.perBankRdBursts::4 13120 # Per bank write bursts 71system.physmem.perBankRdBursts::5 10535 # Per bank write bursts 72system.physmem.perBankRdBursts::6 11120 # Per bank write bursts 73system.physmem.perBankRdBursts::7 11540 # Per bank write bursts 74system.physmem.perBankRdBursts::8 10348 # Per bank write bursts 75system.physmem.perBankRdBursts::9 11053 # Per bank write bursts 76system.physmem.perBankRdBursts::10 10478 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9244 # Per bank write bursts 78system.physmem.perBankRdBursts::12 10124 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10758 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10029 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9743 # Per bank write bursts 82system.physmem.perBankWrBursts::0 10407 # Per bank write bursts 83system.physmem.perBankWrBursts::1 9909 # Per bank write bursts 84system.physmem.perBankWrBursts::2 10642 # Per bank write bursts 85system.physmem.perBankWrBursts::3 10446 # Per bank write bursts 86system.physmem.perBankWrBursts::4 9703 # Per bank write bursts 87system.physmem.perBankWrBursts::5 10218 # Per bank write bursts 88system.physmem.perBankWrBursts::6 10399 # Per bank write bursts 89system.physmem.perBankWrBursts::7 10626 # Per bank write bursts 90system.physmem.perBankWrBursts::8 10202 # Per bank write bursts 91system.physmem.perBankWrBursts::9 10761 # Per bank write bursts 92system.physmem.perBankWrBursts::10 9802 # Per bank write bursts 93system.physmem.perBankWrBursts::11 9030 # Per bank write bursts 94system.physmem.perBankWrBursts::12 9755 # Per bank write bursts 95system.physmem.perBankWrBursts::13 10443 # Per bank write bursts 96system.physmem.perBankWrBursts::14 9720 # Per bank write bursts 97system.physmem.perBankWrBursts::15 9115 # Per bank write bursts |
| 101system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 102system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 103system.physmem.totGap 2826844140500 # Total gap between requests | 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2827041948500 # Total gap between requests |
| 104system.physmem.readPktSize::0 0 # Read request sizes (log2) 105system.physmem.readPktSize::1 0 # Read request sizes (log2) 106system.physmem.readPktSize::2 541 # Read request sizes (log2) 107system.physmem.readPktSize::3 14 # Read request sizes (log2) 108system.physmem.readPktSize::4 2993 # Read request sizes (log2) 109system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 541 # Read request sizes (log2) 104system.physmem.readPktSize::3 14 # Read request sizes (log2) 105system.physmem.readPktSize::4 2993 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 110system.physmem.readPktSize::6 168617 # Read request sizes (log2) | 107system.physmem.readPktSize::6 168336 # Read request sizes (log2) |
| 111system.physmem.writePktSize::0 0 # Write request sizes (log2) 112system.physmem.writePktSize::1 0 # Write request sizes (log2) 113system.physmem.writePktSize::2 4381 # Write request sizes (log2) 114system.physmem.writePktSize::3 0 # Write request sizes (log2) 115system.physmem.writePktSize::4 0 # Write request sizes (log2) 116system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 4381 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 117system.physmem.writePktSize::6 126850 # Write request sizes (log2) 118system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 163042 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151765 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 15965 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 3221 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 790 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see |
| 123system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 157system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 120system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::15 2193 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3936 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 7495 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 8655 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 9236 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 10115 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 10433 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 11221 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 11062 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 11566 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 10773 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 10372 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 9486 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 9237 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 7920 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 7681 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 7574 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 7391 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 595 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 474 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 411 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 347 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 335 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 305 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 250 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 229 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 224 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 203 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 164 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 97 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see |
| 202system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see | 199system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see |
| 203system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 214system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation 228system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads 270system.physmem.totQLat 2072280000 # Total ticks spent queuing 271system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst | 200system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 64399 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 330.873212 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 190.977516 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 347.816153 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 23539 36.55% 36.55% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 14785 22.96% 59.51% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 6319 9.81% 69.32% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3687 5.73% 75.05% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2636 4.09% 79.14% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1562 2.43% 81.57% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1140 1.77% 83.34% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1107 1.72% 85.06% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 9624 14.94% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 64399 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6814 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 25.206340 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 540.339482 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 6812 99.97% 99.97% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6814 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6814 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 23.653948 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 19.805353 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 22.459775 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5702 83.68% 83.68% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 39 0.57% 84.25% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 26 0.38% 84.63% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 231 3.39% 88.02% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 131 1.92% 89.95% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 61 0.90% 90.84% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 35 0.51% 91.36% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 27 0.40% 91.75% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 123 1.81% 93.56% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 13 0.19% 93.75% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 19 0.28% 94.03% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 11 0.16% 94.19% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 31 0.45% 94.64% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 13 0.19% 94.83% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 13 0.19% 95.02% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 26 0.38% 95.41% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 61 0.90% 96.30% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 10 0.15% 96.45% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 9 0.13% 96.58% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 11 0.16% 96.74% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 89 1.31% 98.05% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 4 0.06% 98.11% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 7 0.10% 98.21% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::112-115 18 0.26% 98.47% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::116-119 4 0.06% 98.53% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::120-123 5 0.07% 98.61% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::124-127 4 0.06% 98.66% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::128-131 26 0.38% 99.05% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::132-135 4 0.06% 99.10% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::136-139 4 0.06% 99.16% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::140-143 5 0.07% 99.24% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::144-147 11 0.16% 99.40% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::148-151 11 0.16% 99.56% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::152-155 3 0.04% 99.60% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::160-163 3 0.04% 99.68% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::164-167 2 0.03% 99.71% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::172-175 3 0.04% 99.75% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::176-179 3 0.04% 99.79% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::180-183 1 0.01% 99.81% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::188-191 2 0.03% 99.84% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::200-203 3 0.04% 99.88% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::212-215 1 0.01% 99.90% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::216-219 1 0.01% 99.91% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::220-223 1 0.01% 99.93% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::224-227 3 0.04% 99.97% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::228-231 1 0.01% 99.99% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::total 6814 # Writes before turning the bus around for reads 285system.physmem.totQLat 2084525750 # Total ticks spent queuing 286system.physmem.totMemAccLat 5305007000 # Total ticks spent from burst creation until serviced by the DRAM 287system.physmem.totBusLat 858795000 # Total ticks spent in databus transfers 288system.physmem.avgQLat 12136.34 # Average queueing delay per DRAM burst |
| 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 289system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 275system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst | 290system.physmem.avgMemAccLat 30886.34 # Average memory access latency per DRAM burst |
| 276system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s | 291system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s |
| 277system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s | 292system.physmem.avgWrBW 3.65 # Average achieved write bandwidth in MiByte/s 293system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s 294system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s |
| 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 295system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 281system.physmem.busUtil 0.05 # Data bus utilization in percentage | 296system.physmem.busUtil 0.06 # Data bus utilization in percentage |
| 282system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads | 297system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads |
| 283system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 298system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes |
| 284system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 299system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 285system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing 286system.physmem.readRowHits 142002 # Number of row buffer hits during reads 287system.physmem.writeRowHits 95212 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes 290system.physmem.avgGap 9317341.50 # Average gap between requests 291system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined 292system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states 293system.physmem.memoryStateTime::REF 94394300000 # Time in different power states | 300system.physmem.avgWrQLen 25.50 # Average write queue length when enqueuing 301system.physmem.readRowHits 141721 # Number of row buffer hits during reads 302system.physmem.writeRowHits 126816 # Number of row buffer hits during writes 303system.physmem.readRowHitRate 82.51 # Row buffer hit rate for reads 304system.physmem.writeRowHitRate 78.67 # Row buffer hit rate for writes 305system.physmem.avgGap 8331811.45 # Average gap between requests 306system.physmem.pageHitRate 80.65 # Row buffer hit rate, read and write combined 307system.physmem.memoryStateTime::IDLE 2694668588500 # Time in different power states 308system.physmem.memoryStateTime::REF 94401060000 # Time in different power states |
| 294system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 309system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 295system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states | 310system.physmem.memoryStateTime::ACT 37972497000 # Time in different power states |
| 296system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 311system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 297system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ) 298system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ) 299system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ) 300system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ) 301system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) 302system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ) 303system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) 304system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) 305system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) 306system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) 307system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ) 308system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ) 309system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ) 310system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ) 311system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ) 312system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ) 313system.physmem.averagePower::0 669.336036 # Core power per rank (mW) 314system.physmem.averagePower::1 669.240113 # Core power per rank (mW) | 312system.physmem.actEnergy::0 254499840 # Energy for activate commands per rank (pJ) 313system.physmem.actEnergy::1 232356600 # Energy for activate commands per rank (pJ) 314system.physmem.preEnergy::0 138864000 # Energy for precharge commands per rank (pJ) 315system.physmem.preEnergy::1 126781875 # Energy for precharge commands per rank (pJ) 316system.physmem.readEnergy::0 701859600 # Energy for read commands per rank (pJ) 317system.physmem.readEnergy::1 637852800 # Energy for read commands per rank (pJ) 318system.physmem.writeEnergy::0 533628000 # Energy for write commands per rank (pJ) 319system.physmem.writeEnergy::1 510805440 # Energy for write commands per rank (pJ) 320system.physmem.refreshEnergy::0 184648473360 # Energy for refresh commands per rank (pJ) 321system.physmem.refreshEnergy::1 184648473360 # Energy for refresh commands per rank (pJ) 322system.physmem.actBackEnergy::0 80377758270 # Energy for active background per rank (pJ) 323system.physmem.actBackEnergy::1 79142156730 # Energy for active background per rank (pJ) 324system.physmem.preBackEnergy::0 1625717004000 # Energy for precharge background per rank (pJ) 325system.physmem.preBackEnergy::1 1626800865000 # Energy for precharge background per rank (pJ) 326system.physmem.totalEnergy::0 1892372087070 # Total energy per rank (pJ) 327system.physmem.totalEnergy::1 1892099291805 # Total energy per rank (pJ) 328system.physmem.averagePower::0 669.382923 # Core power per rank (mW) 329system.physmem.averagePower::1 669.286428 # Core power per rank (mW) |
| 315system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 316system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 317system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 318system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 319system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 320system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 321system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 322system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 326system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 327system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 328system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 329system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 330system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 331system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 332system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 330system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 331system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 332system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 333system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 334system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 335system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 336system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 341system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 342system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 343system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 344system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 345system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 346system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 347system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 333system.cpu.branchPred.lookups 46964274 # Number of BP lookups 334system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted 335system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect 336system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups 337system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits | 348system.cpu.branchPred.lookups 46933448 # Number of BP lookups 349system.cpu.branchPred.condPredicted 24039449 # Number of conditional branches predicted 350system.cpu.branchPred.condIncorrect 1232882 # Number of conditional branches incorrect 351system.cpu.branchPred.BTBLookups 29542848 # Number of BTB lookups 352system.cpu.branchPred.BTBHits 21360620 # Number of BTB hits |
| 338system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 353system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 339system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage 340system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target. 341system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. | 354system.cpu.branchPred.BTBHitPct 72.303862 # BTB Hit Percentage 355system.cpu.branchPred.usedRAS 11754095 # Number of times the RAS was used to get a target. 356system.cpu.branchPred.RASInCorrect 33720 # Number of incorrect RAS predictions. |
| 342system.cpu_clk_domain.clock 500 # Clock period in ticks 343system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 344system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 345system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 346system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 347system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 348system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 349system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 358system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 359system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 360system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 361system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 362system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 363system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 364system.cpu.dtb.inst_hits 0 # ITB inst hits 365system.cpu.dtb.inst_misses 0 # ITB inst misses | 357system.cpu_clk_domain.clock 500 # Clock period in ticks 358system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 359system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 360system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 361system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 362system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 363system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 364system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 8 unchanged lines hidden (view full) --- 373system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 374system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 375system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 376system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 377system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 378system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 379system.cpu.dtb.inst_hits 0 # ITB inst hits 380system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 366system.cpu.dtb.read_hits 25471879 # DTB read hits 367system.cpu.dtb.read_misses 60408 # DTB read misses 368system.cpu.dtb.write_hits 19919747 # DTB write hits 369system.cpu.dtb.write_misses 9388 # DTB write misses | 381system.cpu.dtb.read_hits 25465003 # DTB read hits 382system.cpu.dtb.read_misses 60438 # DTB read misses 383system.cpu.dtb.write_hits 19916425 # DTB write hits 384system.cpu.dtb.write_misses 9382 # DTB write misses |
| 370system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 371system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 372system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 373system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 374system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB | 385system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 386system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 387system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 388system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 389system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB |
| 375system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions 376system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch | 390system.cpu.dtb.align_faults 344 # Number of TLB faults due to alignment restrictions 391system.cpu.dtb.prefetch_faults 2309 # Number of TLB faults due to prefetch |
| 377system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 392system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 378system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions 379system.cpu.dtb.read_accesses 25532287 # DTB read accesses 380system.cpu.dtb.write_accesses 19929135 # DTB write accesses | 393system.cpu.dtb.perms_faults 1303 # Number of TLB faults due to permissions restrictions 394system.cpu.dtb.read_accesses 25525441 # DTB read accesses 395system.cpu.dtb.write_accesses 19925807 # DTB write accesses |
| 381system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 396system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 382system.cpu.dtb.hits 45391626 # DTB hits 383system.cpu.dtb.misses 69796 # DTB misses 384system.cpu.dtb.accesses 45461422 # DTB accesses | 397system.cpu.dtb.hits 45381428 # DTB hits 398system.cpu.dtb.misses 69820 # DTB misses 399system.cpu.dtb.accesses 45451248 # DTB accesses |
| 385system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 386system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 387system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 388system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 389system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 390system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 398system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 401system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 402system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 403system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 404system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 405system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 400system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 401system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 402system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 403system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 404system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 405system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 406system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 413system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 416system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 417system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 418system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 419system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 420system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 406system.cpu.itb.inst_hits 66240582 # ITB inst hits 407system.cpu.itb.inst_misses 11936 # ITB inst misses | 421system.cpu.itb.inst_hits 66294026 # ITB inst hits 422system.cpu.itb.inst_misses 11939 # ITB inst misses |
| 408system.cpu.itb.read_hits 0 # DTB read hits 409system.cpu.itb.read_misses 0 # DTB read misses 410system.cpu.itb.write_hits 0 # DTB write hits 411system.cpu.itb.write_misses 0 # DTB write misses 412system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 413system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 414system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 415system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 423system.cpu.itb.read_hits 0 # DTB read hits 424system.cpu.itb.read_misses 0 # DTB read misses 425system.cpu.itb.write_hits 0 # DTB write hits 426system.cpu.itb.write_misses 0 # DTB write misses 427system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 428system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 429system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 430system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 416system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB | 431system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB |
| 417system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 418system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 419system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 432system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 433system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 434system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 420system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions | 435system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions |
| 421system.cpu.itb.read_accesses 0 # DTB read accesses 422system.cpu.itb.write_accesses 0 # DTB write accesses | 436system.cpu.itb.read_accesses 0 # DTB read accesses 437system.cpu.itb.write_accesses 0 # DTB write accesses |
| 423system.cpu.itb.inst_accesses 66252518 # ITB inst accesses 424system.cpu.itb.hits 66240582 # DTB hits 425system.cpu.itb.misses 11936 # DTB misses 426system.cpu.itb.accesses 66252518 # DTB accesses 427system.cpu.numCycles 260548868 # number of cpu cycles simulated | 438system.cpu.itb.inst_accesses 66305965 # ITB inst accesses 439system.cpu.itb.hits 66294026 # DTB hits 440system.cpu.itb.misses 11939 # DTB misses 441system.cpu.itb.accesses 66305965 # DTB accesses 442system.cpu.numCycles 260580731 # number of cpu cycles simulated |
| 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 443system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 444system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 430system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss 431system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed 432system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered 433system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken 434system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked 435system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing 436system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb 437system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 438system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps 439system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions 440system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR 441system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched 442system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed 443system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed 444system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) | 445system.cpu.fetch.icacheStallCycles 104873538 # Number of cycles fetch is stalled on an Icache miss 446system.cpu.fetch.Insts 184739295 # Number of instructions fetch has processed 447system.cpu.fetch.Branches 46933448 # Number of branches that fetch encountered 448system.cpu.fetch.predictedBranches 33114715 # Number of branches that fetch has predicted taken 449system.cpu.fetch.Cycles 145635789 # Number of cycles fetch has run and was not squashing or blocked 450system.cpu.fetch.SquashCycles 6158762 # Number of cycles fetch has spent squashing 451system.cpu.fetch.TlbCycles 168952 # Number of cycles fetch has spent waiting for tlb 452system.cpu.fetch.MiscStallCycles 8750 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 453system.cpu.fetch.PendingTrapStallCycles 338958 # Number of stall cycles due to pending traps 454system.cpu.fetch.PendingQuiesceStallCycles 503648 # Number of stall cycles due to pending quiesce instructions 455system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR 456system.cpu.fetch.CacheLines 66294321 # Number of cache lines fetched 457system.cpu.fetch.IcacheSquashes 1128854 # Number of outstanding Icache misses that were squashed 458system.cpu.fetch.ItlbSquashes 4994 # Number of outstanding ITLB misses that were squashed 459system.cpu.fetch.rateDist::samples 254609122 # Number of instructions fetched each cycle (Total) 460system.cpu.fetch.rateDist::mean 0.884999 # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::stdev 1.237560 # Number of instructions fetched each cycle (Total) |
| 447system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 462system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 448system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total) | 463system.cpu.fetch.rateDist::0 155317216 61.00% 61.00% # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.rateDist::1 29235163 11.48% 72.48% # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::2 14076452 5.53% 78.01% # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::3 55980291 21.99% 100.00% # Number of instructions fetched each cycle (Total) |
| 452system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 467system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 455system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle 457system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle 458system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle 459system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked 460system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running 461system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking 462system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing 463system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch 464system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction 465system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode 466system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode 467system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing 468system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle 469system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking 470system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst 471system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running 472system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking 473system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename 474system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename 475system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full 476system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full 477system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full 478system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full 479system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed 480system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made 481system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups 482system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups 483system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed 484system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing 485system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed 486system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed 487system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer 488system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit. 489system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit. 490system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads. 491system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores. 492system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec) 493system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ 494system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued 495system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued 496system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling 497system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph 498system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed 499system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle | 470system.cpu.fetch.rateDist::total 254609122 # Number of instructions fetched each cycle (Total) 471system.cpu.fetch.branchRate 0.180111 # Number of branch fetches per cycle 472system.cpu.fetch.rate 0.708952 # Number of inst fetches per cycle 473system.cpu.decode.IdleCycles 78085586 # Number of cycles decode is idle 474system.cpu.decode.BlockedCycles 105431733 # Number of cycles decode is blocked 475system.cpu.decode.RunCycles 64660886 # Number of cycles decode is running 476system.cpu.decode.UnblockCycles 3829260 # Number of cycles decode is unblocking 477system.cpu.decode.SquashCycles 2601657 # Number of cycles decode is squashing 478system.cpu.decode.BranchResolved 3422216 # Number of times decode resolved a branch 479system.cpu.decode.BranchMispred 485978 # Number of times decode detected a branch misprediction 480system.cpu.decode.DecodedInsts 157447803 # Number of instructions handled by decode 481system.cpu.decode.SquashedInsts 3691485 # Number of squashed instructions handled by decode 482system.cpu.rename.SquashCycles 2601657 # Number of cycles rename is squashing 483system.cpu.rename.IdleCycles 83925210 # Number of cycles rename is idle 484system.cpu.rename.BlockCycles 10033565 # Number of cycles rename is blocking 485system.cpu.rename.serializeStallCycles 74541150 # count of cycles rename stalled for serializing inst 486system.cpu.rename.RunCycles 62655394 # Number of cycles rename is running 487system.cpu.rename.UnblockCycles 20852146 # Number of cycles rename is unblocking 488system.cpu.rename.RenamedInsts 146807646 # Number of instructions processed by rename 489system.cpu.rename.SquashedInsts 950357 # Number of squashed instructions processed by rename 490system.cpu.rename.ROBFullEvents 437123 # Number of times rename has blocked due to ROB full 491system.cpu.rename.IQFullEvents 62766 # Number of times rename has blocked due to IQ full 492system.cpu.rename.LQFullEvents 16447 # Number of times rename has blocked due to LQ full 493system.cpu.rename.SQFullEvents 18089237 # Number of times rename has blocked due to SQ full 494system.cpu.rename.RenamedOperands 150492315 # Number of destination operands rename has renamed 495system.cpu.rename.RenameLookups 678770164 # Number of register rename lookups that rename has made 496system.cpu.rename.int_rename_lookups 164434086 # Number of integer rename lookups 497system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups 498system.cpu.rename.CommittedMaps 141835122 # Number of HB maps that are committed 499system.cpu.rename.UndoneMaps 8657190 # Number of HB maps that are undone due to squashing 500system.cpu.rename.serializingInsts 2845976 # count of serializing insts renamed 501system.cpu.rename.tempSerializingInsts 2649716 # count of temporary serializing insts renamed 502system.cpu.rename.skidInsts 13845319 # count of insts added to the skid buffer 503system.cpu.memDep0.insertedLoads 26411369 # Number of loads inserted to the mem dependence unit. 504system.cpu.memDep0.insertedStores 21300781 # Number of stores inserted to the mem dependence unit. 505system.cpu.memDep0.conflictingLoads 1686386 # Number of conflicting loads. 506system.cpu.memDep0.conflictingStores 2189128 # Number of conflicting stores. 507system.cpu.iq.iqInstsAdded 143541895 # Number of instructions added to the IQ (excludes non-spec) 508system.cpu.iq.iqNonSpecInstsAdded 2120957 # Number of non-speculative instructions added to the IQ 509system.cpu.iq.iqInstsIssued 143337283 # Number of instructions issued 510system.cpu.iq.iqSquashedInstsIssued 269192 # Number of squashed instructions issued 511system.cpu.iq.iqSquashedInstsExamined 6251828 # Number of squashed instructions iterated over during squash; mainly for profiling 512system.cpu.iq.iqSquashedOperandsExamined 14653372 # Number of squashed operands that are examined and possibly removed from graph 513system.cpu.iq.iqSquashedNonSpecRemoved 125306 # Number of squashed non-spec instructions that were removed 514system.cpu.iq.issued_per_cycle::samples 254609122 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::mean 0.562970 # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::stdev 0.882443 # Number of insts issued each cycle |
| 502system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 517system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 503system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle | 518system.cpu.iq.issued_per_cycle::0 166344309 65.33% 65.33% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::1 45117660 17.72% 83.05% # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::2 32035421 12.58% 95.64% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::3 10298180 4.04% 99.68% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::4 813519 0.32% 100.00% # Number of insts issued each cycle |
| 508system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 523system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 515system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle | 530system.cpu.iq.issued_per_cycle::total 254609122 # Number of insts issued each cycle |
| 516system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 531system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 517system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available | 532system.cpu.iq.fu_full::IntAlu 7370311 32.63% 32.63% # attempts to use FU when none available |
| 518system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available 519system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 520system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 538system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available | 533system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available 534system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 535system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 536system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 537system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 538system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 539system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 553system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 558system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 559system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 560system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available |
| 546system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available 547system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available | 561system.cpu.iq.fu_full::MemRead 5632420 24.93% 57.56% # attempts to use FU when none available 562system.cpu.iq.fu_full::MemWrite 9586874 42.44% 100.00% # attempts to use FU when none available |
| 548system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued | 563system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 564system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 565system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued |
| 551system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued 552system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued | 566system.cpu.iq.FU_type_0::IntAlu 96009315 66.98% 66.98% # Type of FU issued 567system.cpu.iq.FU_type_0::IntMult 113982 0.08% 67.06% # Type of FU issued |
| 553system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 554system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 568system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued | 568system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 569system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 570system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 571system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 572system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 573system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 574system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 583system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.06% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.06% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.06% # Type of FU issued 586system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.06% # Type of FU issued 587system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 588system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 589system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 590system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued |
| 576system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued | 591system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued |
| 577system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued | 592system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued |
| 580system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued 581system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued | 595system.cpu.iq.FU_type_0::MemRead 26194290 18.27% 85.34% # Type of FU issued 596system.cpu.iq.FU_type_0::MemWrite 21008765 14.66% 100.00% # Type of FU issued |
| 582system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 597system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 598system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 584system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued 585system.cpu.iq.rate 0.550285 # Inst issue rate 586system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested 587system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst) 588system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads 589system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes 590system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses 591system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads 592system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes | 599system.cpu.iq.FU_type_0::total 143337283 # Type of FU issued 600system.cpu.iq.rate 0.550069 # Inst issue rate 601system.cpu.iq.fu_busy_cnt 22589637 # FU busy when requested 602system.cpu.iq.fu_busy_rate 0.157598 # FU busy rate (busy events/executed inst) 603system.cpu.iq.int_inst_queue_reads 564106761 # Number of integer instruction queue reads 604system.cpu.iq.int_inst_queue_writes 151919680 # Number of integer instruction queue writes 605system.cpu.iq.int_inst_queue_wakeup_accesses 140223084 # Number of integer instruction queue wakeup accesses 606system.cpu.iq.fp_inst_queue_reads 35756 # Number of floating instruction queue reads 607system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes |
| 593system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses | 608system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses |
| 594system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses 595system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses 596system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores | 609system.cpu.iq.int_alu_accesses 165901147 # Number of integer alu accesses 610system.cpu.iq.fp_alu_accesses 23436 # Number of floating point alu accesses 611system.cpu.iew.lsq.thread0.forwLoads 324147 # Number of loads that had data forwarded from stores |
| 597system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 612system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 598system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed | 613system.cpu.iew.lsq.thread0.squashedLoads 1490308 # Number of loads squashed |
| 599system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed | 614system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed |
| 600system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations 601system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed | 615system.cpu.iew.lsq.thread0.memOrderViolation 18251 # Number of memory ordering violations 616system.cpu.iew.lsq.thread0.squashedStores 701176 # Number of stores squashed |
| 602system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 603system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 617system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 618system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 604system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled 605system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked | 619system.cpu.iew.lsq.thread0.rescheduledLoads 88081 # Number of loads that were rescheduled 620system.cpu.iew.lsq.thread0.cacheBlocked 6304 # Number of times an access to memory failed due to the cache being blocked |
| 606system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 621system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 607system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing 608system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking 609system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking 610system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ | 622system.cpu.iew.iewSquashCycles 2601657 # Number of cycles IEW is squashing 623system.cpu.iew.iewBlockCycles 950737 # Number of cycles IEW is blocking 624system.cpu.iew.iewUnblockCycles 291154 # Number of cycles IEW is unblocking 625system.cpu.iew.iewDispatchedInsts 145863821 # Number of instructions dispatched to IQ |
| 611system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 626system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 612system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions 613system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions 614system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions 615system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall 616system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall 617system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations 618system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly 619system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly 620system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute 621system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions 622system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed 623system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute | 627system.cpu.iew.iewDispLoadInsts 26411369 # Number of dispatched load instructions 628system.cpu.iew.iewDispStoreInsts 21300781 # Number of dispatched store instructions 629system.cpu.iew.iewDispNonSpecInsts 1096076 # Number of dispatched non-speculative instructions 630system.cpu.iew.iewIQFullEvents 17895 # Number of times the IQ has become full, causing a stall 631system.cpu.iew.iewLSQFullEvents 256263 # Number of times the LSQ has become full, causing a stall 632system.cpu.iew.memOrderViolationEvents 18251 # Number of memory order violations 633system.cpu.iew.predictedTakenIncorrect 317548 # Number of branches that were predicted taken incorrectly 634system.cpu.iew.predictedNotTakenIncorrect 471732 # Number of branches that were predicted not taken incorrectly 635system.cpu.iew.branchMispredicts 789280 # Number of branch mispredicts detected at execute 636system.cpu.iew.iewExecutedInsts 142394540 # Number of executed instructions 637system.cpu.iew.iewExecLoadInsts 25793108 # Number of load instructions executed 638system.cpu.iew.iewExecSquashedInsts 873030 # Number of squashed instructions skipped in execute |
| 624system.cpu.iew.exec_swp 0 # number of swp insts executed | 639system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 625system.cpu.iew.exec_nop 200927 # number of nop insts executed 626system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed 627system.cpu.iew.exec_branches 26544085 # Number of branches executed 628system.cpu.iew.exec_stores 20882571 # Number of stores executed 629system.cpu.iew.exec_rate 0.546668 # Inst execution rate 630system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit 631system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back 632system.cpu.iew.wb_producers 63301578 # num instructions producing a value 633system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value | 640system.cpu.iew.exec_nop 200969 # number of nop insts executed 641system.cpu.iew.exec_refs 46672402 # number of memory reference insts executed 642system.cpu.iew.exec_branches 26533167 # Number of branches executed 643system.cpu.iew.exec_stores 20879294 # Number of stores executed 644system.cpu.iew.exec_rate 0.546451 # Inst execution rate 645system.cpu.iew.wb_sent 142007306 # cumulative count of insts sent to commit 646system.cpu.iew.wb_count 140234515 # cumulative count of insts written-back 647system.cpu.iew.wb_producers 63283849 # num instructions producing a value 648system.cpu.iew.wb_consumers 95860591 # num instructions consuming a value |
| 634system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 649system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 635system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle 636system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back | 650system.cpu.iew.wb_rate 0.538161 # insts written-back per cycle 651system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back |
| 637system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 652system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 638system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit 639system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards 640system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted 641system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle | 653system.cpu.commit.commitSquashedInsts 7591533 # The number of squashed insts skipped by commit 654system.cpu.commit.commitNonSpecStalls 1995651 # The number of times commit has been forced to stall to communicate backwards 655system.cpu.commit.branchMispredicts 755158 # The number of times a branch was mispredicted 656system.cpu.commit.committed_per_cycle::samples 251674404 # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::mean 0.546055 # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::stdev 1.146686 # Number of insts commited each cycle |
| 644system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 659system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 645system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle | 660system.cpu.commit.committed_per_cycle::0 178222235 70.81% 70.81% # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::1 43294364 17.20% 88.02% # Number of insts commited each cycle 662system.cpu.commit.committed_per_cycle::2 15476639 6.15% 94.17% # Number of insts commited each cycle 663system.cpu.commit.committed_per_cycle::3 4357303 1.73% 95.90% # Number of insts commited each cycle 664system.cpu.commit.committed_per_cycle::4 6369018 2.53% 98.43% # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::5 1679088 0.67% 99.10% # Number of insts commited each cycle 666system.cpu.commit.committed_per_cycle::6 777340 0.31% 99.40% # Number of insts commited each cycle 667system.cpu.commit.committed_per_cycle::7 414271 0.16% 99.57% # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::8 1084146 0.43% 100.00% # Number of insts commited each cycle |
| 654system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 669system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 670system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 671system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 657system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle 658system.cpu.commit.committedInsts 113359701 # Number of instructions committed 659system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed | 672system.cpu.commit.committed_per_cycle::total 251674404 # Number of insts commited each cycle 673system.cpu.commit.committedInsts 113328647 # Number of instructions committed 674system.cpu.commit.committedOps 137428168 # Number of ops (including micro ops) committed |
| 660system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 675system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 661system.cpu.commit.refs 45531319 # Number of memory references committed 662system.cpu.commit.loads 24928258 # Number of loads committed 663system.cpu.commit.membars 814674 # Number of memory barriers committed 664system.cpu.commit.branches 26060472 # Number of branches committed | 676system.cpu.commit.refs 45520666 # Number of memory references committed 677system.cpu.commit.loads 24921061 # Number of loads committed 678system.cpu.commit.membars 814701 # Number of memory barriers committed 679system.cpu.commit.branches 26049415 # Number of branches committed |
| 665system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. | 680system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. |
| 666system.cpu.commit.int_insts 120282111 # Number of committed integer instructions. 667system.cpu.commit.function_calls 4896381 # Number of function calls committed. | 681system.cpu.commit.int_insts 120247607 # Number of committed integer instructions. 682system.cpu.commit.function_calls 4892692 # Number of function calls committed. |
| 668system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 683system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 669system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction | 684system.cpu.commit.op_class_0::IntAlu 91785919 66.79% 66.79% # Class of committed instruction |
| 670system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction 671system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction --- 8 unchanged lines hidden (view full) --- 686system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction | 685system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction 686system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 687system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 688system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 689system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 690system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 691system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 692system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction --- 8 unchanged lines hidden (view full) --- 701system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 702system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 703system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 704system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 705system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 706system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 707system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 708system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction |
| 694system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction | 709system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction |
| 695system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction | 710system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 711system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 712system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction |
| 698system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction 699system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction | 713system.cpu.commit.op_class_0::MemRead 24921061 18.13% 85.01% # Class of committed instruction 714system.cpu.commit.op_class_0::MemWrite 20599605 14.99% 100.00% # Class of committed instruction |
| 700system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 701system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 715system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 716system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 702system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction 703system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached | 717system.cpu.commit.op_class_0::total 137428168 # Class of committed instruction 718system.cpu.commit.bw_lim_events 1084146 # number cycles where commit BW limit reached |
| 704system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 719system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 705system.cpu.rob.rob_reads 373370450 # The number of ROB reads 706system.cpu.rob.rob_writes 293050441 # The number of ROB writes 707system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself 708system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling 709system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 710system.cpu.committedInsts 113204796 # Number of Instructions Simulated 711system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated 712system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction 713system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads 714system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle 715system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads 716system.cpu.int_regfile_reads 155870535 # number of integer regfile reads 717system.cpu.int_regfile_writes 88662743 # number of integer regfile writes 718system.cpu.fp_regfile_reads 9591 # number of floating regfile reads | 720system.cpu.rob.rob_reads 373381031 # The number of ROB reads 721system.cpu.rob.rob_writes 292971684 # The number of ROB writes 722system.cpu.timesIdled 892930 # Number of times that the entire CPU went into an idle state and unscheduled itself 723system.cpu.idleCycles 5971609 # Total number of cycles that the CPU has spent unscheduled due to idling 724system.cpu.quiesceCycles 5393503589 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 725system.cpu.committedInsts 113173742 # Number of Instructions Simulated 726system.cpu.committedOps 137273263 # Number of Ops (including micro ops) Simulated 727system.cpu.cpi 2.302484 # CPI: Cycles Per Instruction 728system.cpu.cpi_total 2.302484 # CPI: Total CPI of All Threads 729system.cpu.ipc 0.434314 # IPC: Instructions Per Cycle 730system.cpu.ipc_total 0.434314 # IPC: Total IPC of All Threads 731system.cpu.int_regfile_reads 155831391 # number of integer regfile reads 732system.cpu.int_regfile_writes 88636024 # number of integer regfile writes 733system.cpu.fp_regfile_reads 9607 # number of floating regfile reads |
| 719system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 734system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 720system.cpu.cc_regfile_reads 503158959 # number of cc regfile reads 721system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes 722system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads 723system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes 724system.cpu.dcache.tags.replacements 837744 # number of replacements 725system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use 726system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks. 727system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks. 728system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks. | 735system.cpu.cc_regfile_reads 503020695 # number of cc regfile reads 736system.cpu.cc_regfile_writes 53185327 # number of cc regfile writes 737system.cpu.misc_regfile_reads 444130548 # number of misc regfile reads 738system.cpu.misc_regfile_writes 1521619 # number of misc regfile writes 739system.cpu.dcache.tags.replacements 837995 # number of replacements 740system.cpu.dcache.tags.tagsinuse 511.958491 # Cycle average of tags in use 741system.cpu.dcache.tags.total_refs 40159583 # Total number of references to valid blocks. 742system.cpu.dcache.tags.sampled_refs 838507 # Sample count of references to valid blocks. 743system.cpu.dcache.tags.avg_refs 47.894154 # Average number of references to valid blocks. |
| 729system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. | 744system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. |
| 730system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor | 745system.cpu.dcache.tags.occ_blocks::cpu.data 511.958491 # Average occupied blocks per requestor |
| 731system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy 732system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy 733system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 734system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 736system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 737system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 746system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy 747system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy 748system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 749system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 750system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 751system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 752system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 738system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses 739system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses 740system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits 741system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits 742system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits 743system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits 744system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits 745system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits 746system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits 747system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits 748system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits 749system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits 750system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits 751system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits 752system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits 753system.cpu.dcache.overall_hits::total 39265000 # number of overall hits 754system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses 755system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses 756system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses 757system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses 758system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses 759system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses 760system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses 761system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses | 753system.cpu.dcache.tags.tag_accesses 179379502 # Number of tag accesses 754system.cpu.dcache.tags.data_accesses 179379502 # Number of data accesses 755system.cpu.dcache.ReadReq_hits::cpu.data 23322864 # number of ReadReq hits 756system.cpu.dcache.ReadReq_hits::total 23322864 # number of ReadReq hits 757system.cpu.dcache.WriteReq_hits::cpu.data 15584894 # number of WriteReq hits 758system.cpu.dcache.WriteReq_hits::total 15584894 # number of WriteReq hits 759system.cpu.dcache.SoftPFReq_hits::cpu.data 346636 # number of SoftPFReq hits 760system.cpu.dcache.SoftPFReq_hits::total 346636 # number of SoftPFReq hits 761system.cpu.dcache.LoadLockedReq_hits::cpu.data 442009 # number of LoadLockedReq hits 762system.cpu.dcache.LoadLockedReq_hits::total 442009 # number of LoadLockedReq hits 763system.cpu.dcache.StoreCondReq_hits::cpu.data 460310 # number of StoreCondReq hits 764system.cpu.dcache.StoreCondReq_hits::total 460310 # number of StoreCondReq hits 765system.cpu.dcache.demand_hits::cpu.data 38907758 # number of demand (read+write) hits 766system.cpu.dcache.demand_hits::total 38907758 # number of demand (read+write) hits 767system.cpu.dcache.overall_hits::cpu.data 39254394 # number of overall hits 768system.cpu.dcache.overall_hits::total 39254394 # number of overall hits 769system.cpu.dcache.ReadReq_misses::cpu.data 700618 # number of ReadReq misses 770system.cpu.dcache.ReadReq_misses::total 700618 # number of ReadReq misses 771system.cpu.dcache.WriteReq_misses::cpu.data 3574058 # number of WriteReq misses 772system.cpu.dcache.WriteReq_misses::total 3574058 # number of WriteReq misses 773system.cpu.dcache.SoftPFReq_misses::cpu.data 177109 # number of SoftPFReq misses 774system.cpu.dcache.SoftPFReq_misses::total 177109 # number of SoftPFReq misses 775system.cpu.dcache.LoadLockedReq_misses::cpu.data 26740 # number of LoadLockedReq misses 776system.cpu.dcache.LoadLockedReq_misses::total 26740 # number of LoadLockedReq misses |
| 762system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 763system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses | 777system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 778system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses |
| 764system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses 765system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses 766system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses 767system.cpu.dcache.overall_misses::total 4451395 # number of overall misses 768system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles 769system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles 770system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles 772system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles 774system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles 775system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles 776system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles 777system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles 778system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles 779system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles 780system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses) 781system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses) 784system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) 785system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) 786system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) 787system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) 788system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) 789system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) 790system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses 791system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses 792system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses 793system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses 794system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses 795system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses 796system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses 797system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses 798system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses 799system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses 800system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses 801system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses | 779system.cpu.dcache.demand_misses::cpu.data 4274676 # number of demand (read+write) misses 780system.cpu.dcache.demand_misses::total 4274676 # number of demand (read+write) misses 781system.cpu.dcache.overall_misses::cpu.data 4451785 # number of overall misses 782system.cpu.dcache.overall_misses::total 4451785 # number of overall misses 783system.cpu.dcache.ReadReq_miss_latency::cpu.data 9939142148 # number of ReadReq miss cycles 784system.cpu.dcache.ReadReq_miss_latency::total 9939142148 # number of ReadReq miss cycles 785system.cpu.dcache.WriteReq_miss_latency::cpu.data 135148977049 # number of WriteReq miss cycles 786system.cpu.dcache.WriteReq_miss_latency::total 135148977049 # number of WriteReq miss cycles 787system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356483749 # number of LoadLockedReq miss cycles 788system.cpu.dcache.LoadLockedReq_miss_latency::total 356483749 # number of LoadLockedReq miss cycles 789system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 189500 # number of StoreCondReq miss cycles 790system.cpu.dcache.StoreCondReq_miss_latency::total 189500 # number of StoreCondReq miss cycles 791system.cpu.dcache.demand_miss_latency::cpu.data 145088119197 # number of demand (read+write) miss cycles 792system.cpu.dcache.demand_miss_latency::total 145088119197 # number of demand (read+write) miss cycles 793system.cpu.dcache.overall_miss_latency::cpu.data 145088119197 # number of overall miss cycles 794system.cpu.dcache.overall_miss_latency::total 145088119197 # number of overall miss cycles 795system.cpu.dcache.ReadReq_accesses::cpu.data 24023482 # number of ReadReq accesses(hits+misses) 796system.cpu.dcache.ReadReq_accesses::total 24023482 # number of ReadReq accesses(hits+misses) 797system.cpu.dcache.WriteReq_accesses::cpu.data 19158952 # number of WriteReq accesses(hits+misses) 798system.cpu.dcache.WriteReq_accesses::total 19158952 # number of WriteReq accesses(hits+misses) 799system.cpu.dcache.SoftPFReq_accesses::cpu.data 523745 # number of SoftPFReq accesses(hits+misses) 800system.cpu.dcache.SoftPFReq_accesses::total 523745 # number of SoftPFReq accesses(hits+misses) 801system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468749 # number of LoadLockedReq accesses(hits+misses) 802system.cpu.dcache.LoadLockedReq_accesses::total 468749 # number of LoadLockedReq accesses(hits+misses) 803system.cpu.dcache.StoreCondReq_accesses::cpu.data 460315 # number of StoreCondReq accesses(hits+misses) 804system.cpu.dcache.StoreCondReq_accesses::total 460315 # number of StoreCondReq accesses(hits+misses) 805system.cpu.dcache.demand_accesses::cpu.data 43182434 # number of demand (read+write) accesses 806system.cpu.dcache.demand_accesses::total 43182434 # number of demand (read+write) accesses 807system.cpu.dcache.overall_accesses::cpu.data 43706179 # number of overall (read+write) accesses 808system.cpu.dcache.overall_accesses::total 43706179 # number of overall (read+write) accesses 809system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029164 # miss rate for ReadReq accesses 810system.cpu.dcache.ReadReq_miss_rate::total 0.029164 # miss rate for ReadReq accesses 811system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186548 # miss rate for WriteReq accesses 812system.cpu.dcache.WriteReq_miss_rate::total 0.186548 # miss rate for WriteReq accesses 813system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338159 # miss rate for SoftPFReq accesses 814system.cpu.dcache.SoftPFReq_miss_rate::total 0.338159 # miss rate for SoftPFReq accesses 815system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057045 # miss rate for LoadLockedReq accesses 816system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057045 # miss rate for LoadLockedReq accesses |
| 802system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 803system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses | 817system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 818system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses |
| 804system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency 814system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency 815system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency 816system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency 817system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency 818system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency 819system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency 820system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked | 819system.cpu.dcache.demand_miss_rate::cpu.data 0.098991 # miss rate for demand accesses 820system.cpu.dcache.demand_miss_rate::total 0.098991 # miss rate for demand accesses 821system.cpu.dcache.overall_miss_rate::cpu.data 0.101857 # miss rate for overall accesses 822system.cpu.dcache.overall_miss_rate::total 0.101857 # miss rate for overall accesses 823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14186.250065 # average ReadReq miss latency 824system.cpu.dcache.ReadReq_avg_miss_latency::total 14186.250065 # average ReadReq miss latency 825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37813.873488 # average WriteReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::total 37813.873488 # average WriteReq miss latency 827system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13331.479020 # average LoadLockedReq miss latency 828system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13331.479020 # average LoadLockedReq miss latency 829system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 37900 # average StoreCondReq miss latency 830system.cpu.dcache.StoreCondReq_avg_miss_latency::total 37900 # average StoreCondReq miss latency 831system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.313727 # average overall miss latency 832system.cpu.dcache.demand_avg_miss_latency::total 33941.313727 # average overall miss latency 833system.cpu.dcache.overall_avg_miss_latency::cpu.data 32590.998711 # average overall miss latency 834system.cpu.dcache.overall_avg_miss_latency::total 32590.998711 # average overall miss latency 835system.cpu.dcache.blocked_cycles::no_mshrs 505021 # number of cycles access was blocked |
| 821system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 836system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 822system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked | 837system.cpu.dcache.blocked::no_mshrs 6926 # number of cycles access was blocked |
| 823system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 838system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 824system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked | 839system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.916691 # average number of cycles each access was blocked |
| 825system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 826system.cpu.dcache.fast_writes 0 # number of fast writes performed 827system.cpu.dcache.cache_copies 0 # number of cache copies performed | 840system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu.dcache.fast_writes 0 # number of fast writes performed 842system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 828system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks 829system.cpu.dcache.writebacks::total 695413 # number of writebacks 830system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits 831system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits 832system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits 833system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits 834system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits 835system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits 836system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits 837system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits 838system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits 839system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits 840system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses 841system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses 842system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses 843system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses 844system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses 845system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses 846system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses 847system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses | 843system.cpu.dcache.writebacks::writebacks 695574 # number of writebacks 844system.cpu.dcache.writebacks::total 695574 # number of writebacks 845system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286297 # number of ReadReq MSHR hits 846system.cpu.dcache.ReadReq_mshr_hits::total 286297 # number of ReadReq MSHR hits 847system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274736 # number of WriteReq MSHR hits 848system.cpu.dcache.WriteReq_mshr_hits::total 3274736 # number of WriteReq MSHR hits 849system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18417 # number of LoadLockedReq MSHR hits 850system.cpu.dcache.LoadLockedReq_mshr_hits::total 18417 # number of LoadLockedReq MSHR hits 851system.cpu.dcache.demand_mshr_hits::cpu.data 3561033 # number of demand (read+write) MSHR hits 852system.cpu.dcache.demand_mshr_hits::total 3561033 # number of demand (read+write) MSHR hits 853system.cpu.dcache.overall_mshr_hits::cpu.data 3561033 # number of overall MSHR hits 854system.cpu.dcache.overall_mshr_hits::total 3561033 # number of overall MSHR hits 855system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414321 # number of ReadReq MSHR misses 856system.cpu.dcache.ReadReq_mshr_misses::total 414321 # number of ReadReq MSHR misses 857system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299322 # number of WriteReq MSHR misses 858system.cpu.dcache.WriteReq_mshr_misses::total 299322 # number of WriteReq MSHR misses 859system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119334 # number of SoftPFReq MSHR misses 860system.cpu.dcache.SoftPFReq_mshr_misses::total 119334 # number of SoftPFReq MSHR misses 861system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8323 # number of LoadLockedReq MSHR misses 862system.cpu.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses |
| 848system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 849system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses | 863system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 864system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses |
| 850system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses 851system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses 852system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses 853system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses 854system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles 855system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles 856system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles 857system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles 858system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles 859system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles 860system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles 861system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles 862system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles 863system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles 864system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles 865system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles 866system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles 867system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles 868system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles 869system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles 870system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles 871system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles 872system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles 873system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles 874system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses 875system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses 876system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses 877system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses 878system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses 879system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses 880system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses 881system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses | 865system.cpu.dcache.demand_mshr_misses::cpu.data 713643 # number of demand (read+write) MSHR misses 866system.cpu.dcache.demand_mshr_misses::total 713643 # number of demand (read+write) MSHR misses 867system.cpu.dcache.overall_mshr_misses::cpu.data 832977 # number of overall MSHR misses 868system.cpu.dcache.overall_mshr_misses::total 832977 # number of overall MSHR misses 869system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5358688665 # number of ReadReq MSHR miss cycles 870system.cpu.dcache.ReadReq_mshr_miss_latency::total 5358688665 # number of ReadReq MSHR miss cycles 871system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11888843709 # number of WriteReq MSHR miss cycles 872system.cpu.dcache.WriteReq_mshr_miss_latency::total 11888843709 # number of WriteReq MSHR miss cycles 873system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1476460251 # number of SoftPFReq MSHR miss cycles 874system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1476460251 # number of SoftPFReq MSHR miss cycles 875system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110246000 # number of LoadLockedReq MSHR miss cycles 876system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110246000 # number of LoadLockedReq MSHR miss cycles 877system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 179500 # number of StoreCondReq MSHR miss cycles 878system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 179500 # number of StoreCondReq MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17247532374 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.demand_mshr_miss_latency::total 17247532374 # number of demand (read+write) MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18723992625 # number of overall MSHR miss cycles 882system.cpu.dcache.overall_mshr_miss_latency::total 18723992625 # number of overall MSHR miss cycles 883system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792718250 # number of ReadReq MSHR uncacheable cycles 884system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792718250 # number of ReadReq MSHR uncacheable cycles 885system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457453 # number of WriteReq MSHR uncacheable cycles 886system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457453 # number of WriteReq MSHR uncacheable cycles 887system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233175703 # number of overall MSHR uncacheable cycles 888system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233175703 # number of overall MSHR uncacheable cycles 889system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017247 # mshr miss rate for ReadReq accesses 890system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017247 # mshr miss rate for ReadReq accesses 891system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015623 # mshr miss rate for WriteReq accesses 892system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015623 # mshr miss rate for WriteReq accesses 893system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227848 # mshr miss rate for SoftPFReq accesses 894system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227848 # mshr miss rate for SoftPFReq accesses 895system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017756 # mshr miss rate for LoadLockedReq accesses 896system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017756 # mshr miss rate for LoadLockedReq accesses |
| 882system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 883system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses | 897system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 898system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses |
| 884system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses 885system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses 886system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses 887system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses 888system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency 889system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency 890system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency 891system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency 892system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency 893system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency 894system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency 895system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency 896system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency 897system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency 898system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency 899system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency 900system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency 901system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency | 899system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016526 # mshr miss rate for demand accesses 900system.cpu.dcache.demand_mshr_miss_rate::total 0.016526 # mshr miss rate for demand accesses 901system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019059 # mshr miss rate for overall accesses 902system.cpu.dcache.overall_mshr_miss_rate::total 0.019059 # mshr miss rate for overall accesses 903system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12933.664152 # average ReadReq mshr miss latency 904system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12933.664152 # average ReadReq mshr miss latency 905system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39719.244523 # average WriteReq mshr miss latency 906system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39719.244523 # average WriteReq mshr miss latency 907system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12372.502816 # average SoftPFReq mshr miss latency 908system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12372.502816 # average SoftPFReq mshr miss latency 909system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.944972 # average LoadLockedReq mshr miss latency 910system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.944972 # average LoadLockedReq mshr miss latency 911system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 35900 # average StoreCondReq mshr miss latency 912system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 35900 # average StoreCondReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24168.291953 # average overall mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::total 24168.291953 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22478.402915 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::total 22478.402915 # average overall mshr miss latency |
| 902system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 903system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 904system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 905system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 906system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 907system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 908system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 917system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 918system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 919system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 920system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 921system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 922system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 923system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 909system.cpu.icache.tags.replacements 1894031 # number of replacements 910system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use 911system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks. 912system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks. 913system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks. | 924system.cpu.icache.tags.replacements 1894210 # number of replacements 925system.cpu.icache.tags.tagsinuse 511.373832 # Cycle average of tags in use 926system.cpu.icache.tags.total_refs 64309690 # Total number of references to valid blocks. 927system.cpu.icache.tags.sampled_refs 1894722 # Sample count of references to valid blocks. 928system.cpu.icache.tags.avg_refs 33.941491 # Average number of references to valid blocks. |
| 914system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. | 929system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. |
| 915system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor | 930system.cpu.icache.tags.occ_blocks::cpu.inst 511.373832 # Average occupied blocks per requestor |
| 916system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy 917system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy 918system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 919system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 920system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 921system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id 922system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 923system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 931system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy 932system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy 933system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 934system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 935system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 936system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id 937system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 938system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 924system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses 925system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses 926system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits 927system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits 928system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits 929system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits 930system.cpu.icache.overall_hits::cpu.inst 64256441 # number of overall hits 931system.cpu.icache.overall_hits::total 64256441 # number of overall hits 932system.cpu.icache.ReadReq_misses::cpu.inst 1981452 # number of ReadReq misses 933system.cpu.icache.ReadReq_misses::total 1981452 # number of ReadReq misses 934system.cpu.icache.demand_misses::cpu.inst 1981452 # number of demand (read+write) misses 935system.cpu.icache.demand_misses::total 1981452 # number of demand (read+write) misses 936system.cpu.icache.overall_misses::cpu.inst 1981452 # number of overall misses 937system.cpu.icache.overall_misses::total 1981452 # number of overall misses 938system.cpu.icache.ReadReq_miss_latency::cpu.inst 26762198879 # number of ReadReq miss cycles 939system.cpu.icache.ReadReq_miss_latency::total 26762198879 # number of ReadReq miss cycles 940system.cpu.icache.demand_miss_latency::cpu.inst 26762198879 # number of demand (read+write) miss cycles 941system.cpu.icache.demand_miss_latency::total 26762198879 # number of demand (read+write) miss cycles 942system.cpu.icache.overall_miss_latency::cpu.inst 26762198879 # number of overall miss cycles 943system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles 944system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses) 945system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses) 946system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses 947system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses 948system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses 949system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses 950system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses 951system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses 952system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses 953system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses 954system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses 955system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses 956system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency 957system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency 958system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency 959system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency 960system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency 961system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency 962system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked | 939system.cpu.icache.tags.tag_accesses 68186062 # Number of tag accesses 940system.cpu.icache.tags.data_accesses 68186062 # Number of data accesses 941system.cpu.icache.ReadReq_hits::cpu.inst 64309690 # number of ReadReq hits 942system.cpu.icache.ReadReq_hits::total 64309690 # number of ReadReq hits 943system.cpu.icache.demand_hits::cpu.inst 64309690 # number of demand (read+write) hits 944system.cpu.icache.demand_hits::total 64309690 # number of demand (read+write) hits 945system.cpu.icache.overall_hits::cpu.inst 64309690 # number of overall hits 946system.cpu.icache.overall_hits::total 64309690 # number of overall hits 947system.cpu.icache.ReadReq_misses::cpu.inst 1981630 # number of ReadReq misses 948system.cpu.icache.ReadReq_misses::total 1981630 # number of ReadReq misses 949system.cpu.icache.demand_misses::cpu.inst 1981630 # number of demand (read+write) misses 950system.cpu.icache.demand_misses::total 1981630 # number of demand (read+write) misses 951system.cpu.icache.overall_misses::cpu.inst 1981630 # number of overall misses 952system.cpu.icache.overall_misses::total 1981630 # number of overall misses 953system.cpu.icache.ReadReq_miss_latency::cpu.inst 26770075875 # number of ReadReq miss cycles 954system.cpu.icache.ReadReq_miss_latency::total 26770075875 # number of ReadReq miss cycles 955system.cpu.icache.demand_miss_latency::cpu.inst 26770075875 # number of demand (read+write) miss cycles 956system.cpu.icache.demand_miss_latency::total 26770075875 # number of demand (read+write) miss cycles 957system.cpu.icache.overall_miss_latency::cpu.inst 26770075875 # number of overall miss cycles 958system.cpu.icache.overall_miss_latency::total 26770075875 # number of overall miss cycles 959system.cpu.icache.ReadReq_accesses::cpu.inst 66291320 # number of ReadReq accesses(hits+misses) 960system.cpu.icache.ReadReq_accesses::total 66291320 # number of ReadReq accesses(hits+misses) 961system.cpu.icache.demand_accesses::cpu.inst 66291320 # number of demand (read+write) accesses 962system.cpu.icache.demand_accesses::total 66291320 # number of demand (read+write) accesses 963system.cpu.icache.overall_accesses::cpu.inst 66291320 # number of overall (read+write) accesses 964system.cpu.icache.overall_accesses::total 66291320 # number of overall (read+write) accesses 965system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029893 # miss rate for ReadReq accesses 966system.cpu.icache.ReadReq_miss_rate::total 0.029893 # miss rate for ReadReq accesses 967system.cpu.icache.demand_miss_rate::cpu.inst 0.029893 # miss rate for demand accesses 968system.cpu.icache.demand_miss_rate::total 0.029893 # miss rate for demand accesses 969system.cpu.icache.overall_miss_rate::cpu.inst 0.029893 # miss rate for overall accesses 970system.cpu.icache.overall_miss_rate::total 0.029893 # miss rate for overall accesses 971system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13509.119197 # average ReadReq miss latency 972system.cpu.icache.ReadReq_avg_miss_latency::total 13509.119197 # average ReadReq miss latency 973system.cpu.icache.demand_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency 974system.cpu.icache.demand_avg_miss_latency::total 13509.119197 # average overall miss latency 975system.cpu.icache.overall_avg_miss_latency::cpu.inst 13509.119197 # average overall miss latency 976system.cpu.icache.overall_avg_miss_latency::total 13509.119197 # average overall miss latency 977system.cpu.icache.blocked_cycles::no_mshrs 1592 # number of cycles access was blocked |
| 963system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 978system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 964system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked | 979system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked |
| 965system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 980system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 966system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked | 981system.cpu.icache.avg_blocked_cycles::no_mshrs 15.307692 # average number of cycles each access was blocked |
| 967system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 968system.cpu.icache.fast_writes 0 # number of fast writes performed 969system.cpu.icache.cache_copies 0 # number of cache copies performed | 982system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 983system.cpu.icache.fast_writes 0 # number of fast writes performed 984system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 970system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits 971system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits 972system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits 973system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits 974system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits 975system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits 976system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses 977system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses 978system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses 979system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses 980system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses 981system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses 982system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles 983system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles 984system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles 985system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles 986system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles 987system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles | 985system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86886 # number of ReadReq MSHR hits 986system.cpu.icache.ReadReq_mshr_hits::total 86886 # number of ReadReq MSHR hits 987system.cpu.icache.demand_mshr_hits::cpu.inst 86886 # number of demand (read+write) MSHR hits 988system.cpu.icache.demand_mshr_hits::total 86886 # number of demand (read+write) MSHR hits 989system.cpu.icache.overall_mshr_hits::cpu.inst 86886 # number of overall MSHR hits 990system.cpu.icache.overall_mshr_hits::total 86886 # number of overall MSHR hits 991system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894744 # number of ReadReq MSHR misses 992system.cpu.icache.ReadReq_mshr_misses::total 1894744 # number of ReadReq MSHR misses 993system.cpu.icache.demand_mshr_misses::cpu.inst 1894744 # number of demand (read+write) MSHR misses 994system.cpu.icache.demand_mshr_misses::total 1894744 # number of demand (read+write) MSHR misses 995system.cpu.icache.overall_mshr_misses::cpu.inst 1894744 # number of overall MSHR misses 996system.cpu.icache.overall_mshr_misses::total 1894744 # number of overall MSHR misses 997system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22166113097 # number of ReadReq MSHR miss cycles 998system.cpu.icache.ReadReq_mshr_miss_latency::total 22166113097 # number of ReadReq MSHR miss cycles 999system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22166113097 # number of demand (read+write) MSHR miss cycles 1000system.cpu.icache.demand_mshr_miss_latency::total 22166113097 # number of demand (read+write) MSHR miss cycles 1001system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22166113097 # number of overall MSHR miss cycles 1002system.cpu.icache.overall_mshr_miss_latency::total 22166113097 # number of overall MSHR miss cycles |
| 988system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles 989system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles 990system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles 991system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles | 1003system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles 1004system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles 1005system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles 1006system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles |
| 992system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses 993system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses 994system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses 995system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses 996system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses 997system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses 998system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency 999system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency 1000system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency 1001system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency 1002system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency 1003system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency | 1007system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028582 # mshr miss rate for ReadReq accesses 1008system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028582 # mshr miss rate for ReadReq accesses 1009system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028582 # mshr miss rate for demand accesses 1010system.cpu.icache.demand_mshr_miss_rate::total 0.028582 # mshr miss rate for demand accesses 1011system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028582 # mshr miss rate for overall accesses 1012system.cpu.icache.overall_mshr_miss_rate::total 0.028582 # mshr miss rate for overall accesses 1013system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.737717 # average ReadReq mshr miss latency 1014system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.737717 # average ReadReq mshr miss latency 1015system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.737717 # average overall mshr miss latency 1016system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.737717 # average overall mshr miss latency 1017system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.737717 # average overall mshr miss latency 1018system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.737717 # average overall mshr miss latency |
| 1004system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1005system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1006system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1007system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1008system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1019system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1020system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1021system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1022system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1023system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1009system.cpu.l2cache.tags.replacements 98619 # number of replacements 1010system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use 1011system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks. 1012system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. 1013system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks. | 1024system.cpu.l2cache.tags.replacements 98615 # number of replacements 1025system.cpu.l2cache.tags.tagsinuse 65077.693225 # Cycle average of tags in use 1026system.cpu.l2cache.tags.total_refs 3021592 # Total number of references to valid blocks. 1027system.cpu.l2cache.tags.sampled_refs 163828 # Sample count of references to valid blocks. 1028system.cpu.l2cache.tags.avg_refs 18.443685 # Average number of references to valid blocks. |
| 1014system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1029system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1015system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor 1016system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor 1017system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor 1018system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor 1019system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor 1020system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy | 1030system.cpu.l2cache.tags.occ_blocks::writebacks 49562.273815 # Average occupied blocks per requestor 1031system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218373 # Average occupied blocks per requestor 1032system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798544 # Average occupied blocks per requestor 1033system.cpu.l2cache.tags.occ_blocks::cpu.inst 10309.775657 # Average occupied blocks per requestor 1034system.cpu.l2cache.tags.occ_blocks::cpu.data 5192.626837 # Average occupied blocks per requestor 1035system.cpu.l2cache.tags.occ_percent::writebacks 0.756260 # Average percentage of cache occupancy |
| 1021system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy 1022system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy | 1036system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy 1037system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy |
| 1023system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy 1024system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy 1025system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy | 1038system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157315 # Average percentage of cache occupancy 1039system.cpu.l2cache.tags.occ_percent::cpu.data 0.079233 # Average percentage of cache occupancy 1040system.cpu.l2cache.tags.occ_percent::total 0.993007 # Average percentage of cache occupancy |
| 1026system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1027system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id 1028system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1029system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 1030system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id | 1041system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1042system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id 1043system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1044system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 1045system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id |
| 1031system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id 1032system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id 1033system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id | 1046system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2969 # Occupied blocks per task id 1047system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7003 # Occupied blocks per task id 1048system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55048 # Occupied blocks per task id |
| 1034system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1035system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id | 1049system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1050system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id |
| 1036system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses 1037system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses 1038system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits 1039system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits 1040system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits 1041system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits 1042system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits 1043system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits 1044system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits 1045system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits 1046system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits | 1051system.cpu.l2cache.tags.tag_accesses 28442992 # Number of tag accesses 1052system.cpu.l2cache.tags.data_accesses 28442992 # Number of data accesses 1053system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53902 # number of ReadReq hits 1054system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11707 # number of ReadReq hits 1055system.cpu.l2cache.ReadReq_hits::cpu.inst 1874744 # number of ReadReq hits 1056system.cpu.l2cache.ReadReq_hits::cpu.data 528230 # number of ReadReq hits 1057system.cpu.l2cache.ReadReq_hits::total 2468583 # number of ReadReq hits 1058system.cpu.l2cache.Writeback_hits::writebacks 695574 # number of Writeback hits 1059system.cpu.l2cache.Writeback_hits::total 695574 # number of Writeback hits 1060system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits 1061system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits |
| 1047system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1048system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits | 1062system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1063system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits |
| 1049system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits 1050system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits 1051system.cpu.l2cache.demand_hits::cpu.dtb.walker 53838 # number of demand (read+write) hits 1052system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits 1053system.cpu.l2cache.demand_hits::cpu.inst 1874564 # number of demand (read+write) hits 1054system.cpu.l2cache.demand_hits::cpu.data 687722 # number of demand (read+write) hits 1055system.cpu.l2cache.demand_hits::total 2627784 # number of demand (read+write) hits 1056system.cpu.l2cache.overall_hits::cpu.dtb.walker 53838 # number of overall hits 1057system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits 1058system.cpu.l2cache.overall_hits::cpu.inst 1874564 # number of overall hits 1059system.cpu.l2cache.overall_hits::cpu.data 687722 # number of overall hits 1060system.cpu.l2cache.overall_hits::total 2627784 # number of overall hits | 1064system.cpu.l2cache.ReadExReq_hits::cpu.data 159750 # number of ReadExReq hits 1065system.cpu.l2cache.ReadExReq_hits::total 159750 # number of ReadExReq hits 1066system.cpu.l2cache.demand_hits::cpu.dtb.walker 53902 # number of demand (read+write) hits 1067system.cpu.l2cache.demand_hits::cpu.itb.walker 11707 # number of demand (read+write) hits 1068system.cpu.l2cache.demand_hits::cpu.inst 1874744 # number of demand (read+write) hits 1069system.cpu.l2cache.demand_hits::cpu.data 687980 # number of demand (read+write) hits 1070system.cpu.l2cache.demand_hits::total 2628333 # number of demand (read+write) hits 1071system.cpu.l2cache.overall_hits::cpu.dtb.walker 53902 # number of overall hits 1072system.cpu.l2cache.overall_hits::cpu.itb.walker 11707 # number of overall hits 1073system.cpu.l2cache.overall_hits::cpu.inst 1874744 # number of overall hits 1074system.cpu.l2cache.overall_hits::cpu.data 687980 # number of overall hits 1075system.cpu.l2cache.overall_hits::total 2628333 # number of overall hits |
| 1061system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1062system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses | 1076system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1077system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses |
| 1063system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses 1064system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses 1065system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses 1066system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses 1067system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses | 1078system.cpu.l2cache.ReadReq_misses::cpu.inst 19968 # number of ReadReq misses 1079system.cpu.l2cache.ReadReq_misses::cpu.data 13616 # number of ReadReq misses 1080system.cpu.l2cache.ReadReq_misses::total 33610 # number of ReadReq misses 1081system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses 1082system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses |
| 1068system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1069system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses | 1083system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1084system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses |
| 1070system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses 1071system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses | 1085system.cpu.l2cache.ReadExReq_misses::cpu.data 136934 # number of ReadExReq misses 1086system.cpu.l2cache.ReadExReq_misses::total 136934 # number of ReadExReq misses |
| 1072system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1073system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses | 1087system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1088system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses |
| 1074system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses 1075system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses 1076system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses | 1089system.cpu.l2cache.demand_misses::cpu.inst 19968 # number of demand (read+write) misses 1090system.cpu.l2cache.demand_misses::cpu.data 150550 # number of demand (read+write) misses 1091system.cpu.l2cache.demand_misses::total 170544 # number of demand (read+write) misses |
| 1077system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1078system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses | 1092system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1093system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses |
| 1079system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses 1080system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses 1081system.cpu.l2cache.overall_misses::total 170549 # number of overall misses 1082system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles | 1094system.cpu.l2cache.overall_misses::cpu.inst 19968 # number of overall misses 1095system.cpu.l2cache.overall_misses::cpu.data 150550 # number of overall misses 1096system.cpu.l2cache.overall_misses::total 170544 # number of overall misses 1097system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1472750 # number of ReadReq miss cycles |
| 1083system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles | 1098system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles |
| 1084system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1499718000 # number of ReadReq miss cycles 1085system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078687250 # number of ReadReq miss cycles 1086system.cpu.l2cache.ReadReq_miss_latency::total 2580400000 # number of ReadReq miss cycles 1087system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles 1088system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles 1089system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles 1090system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles 1091system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9923495690 # number of ReadExReq miss cycles 1092system.cpu.l2cache.ReadExReq_miss_latency::total 9923495690 # number of ReadExReq miss cycles 1093system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles | 1099system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1503894000 # number of ReadReq miss cycles 1100system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1090000000 # number of ReadReq miss cycles 1101system.cpu.l2cache.ReadReq_miss_latency::total 2595903000 # number of ReadReq miss cycles 1102system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581975 # number of UpgradeReq miss cycles 1103system.cpu.l2cache.UpgradeReq_miss_latency::total 581975 # number of UpgradeReq miss cycles 1104system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles 1105system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles 1106system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9927756441 # number of ReadExReq miss cycles 1107system.cpu.l2cache.ReadExReq_miss_latency::total 9927756441 # number of ReadExReq miss cycles 1108system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1472750 # number of demand (read+write) miss cycles |
| 1094system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles | 1109system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles |
| 1095system.cpu.l2cache.demand_miss_latency::cpu.inst 1499718000 # number of demand (read+write) miss cycles 1096system.cpu.l2cache.demand_miss_latency::cpu.data 11002182940 # number of demand (read+write) miss cycles 1097system.cpu.l2cache.demand_miss_latency::total 12503895690 # number of demand (read+write) miss cycles 1098system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles | 1110system.cpu.l2cache.demand_miss_latency::cpu.inst 1503894000 # number of demand (read+write) miss cycles 1111system.cpu.l2cache.demand_miss_latency::cpu.data 11017756441 # number of demand (read+write) miss cycles 1112system.cpu.l2cache.demand_miss_latency::total 12523659441 # number of demand (read+write) miss cycles 1113system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1472750 # number of overall miss cycles |
| 1099system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles | 1114system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles |
| 1100system.cpu.l2cache.overall_miss_latency::cpu.inst 1499718000 # number of overall miss cycles 1101system.cpu.l2cache.overall_miss_latency::cpu.data 11002182940 # number of overall miss cycles 1102system.cpu.l2cache.overall_miss_latency::total 12503895690 # number of overall miss cycles 1103system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53857 # number of ReadReq accesses(hits+misses) 1104system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses) 1105system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894530 # number of ReadReq accesses(hits+misses) 1106system.cpu.l2cache.ReadReq_accesses::cpu.data 541654 # number of ReadReq accesses(hits+misses) 1107system.cpu.l2cache.ReadReq_accesses::total 2501708 # number of ReadReq accesses(hits+misses) 1108system.cpu.l2cache.Writeback_accesses::writebacks 695413 # number of Writeback accesses(hits+misses) 1109system.cpu.l2cache.Writeback_accesses::total 695413 # number of Writeback accesses(hits+misses) 1110system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses) 1111system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses) | 1115system.cpu.l2cache.overall_miss_latency::cpu.inst 1503894000 # number of overall miss cycles 1116system.cpu.l2cache.overall_miss_latency::cpu.data 11017756441 # number of overall miss cycles 1117system.cpu.l2cache.overall_miss_latency::total 12523659441 # number of overall miss cycles 1118system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53921 # number of ReadReq accesses(hits+misses) 1119system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11714 # number of ReadReq accesses(hits+misses) 1120system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894712 # number of ReadReq accesses(hits+misses) 1121system.cpu.l2cache.ReadReq_accesses::cpu.data 541846 # number of ReadReq accesses(hits+misses) 1122system.cpu.l2cache.ReadReq_accesses::total 2502193 # number of ReadReq accesses(hits+misses) 1123system.cpu.l2cache.Writeback_accesses::writebacks 695574 # number of Writeback accesses(hits+misses) 1124system.cpu.l2cache.Writeback_accesses::total 695574 # number of Writeback accesses(hits+misses) 1125system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2770 # number of UpgradeReq accesses(hits+misses) 1126system.cpu.l2cache.UpgradeReq_accesses::total 2770 # number of UpgradeReq accesses(hits+misses) |
| 1112system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1113system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) | 1127system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1128system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) |
| 1114system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses) 1115system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses) 1116system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53857 # number of demand (read+write) accesses 1117system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses 1118system.cpu.l2cache.demand_accesses::cpu.inst 1894530 # number of demand (read+write) accesses 1119system.cpu.l2cache.demand_accesses::cpu.data 838279 # number of demand (read+write) accesses 1120system.cpu.l2cache.demand_accesses::total 2798333 # number of demand (read+write) accesses 1121system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53857 # number of overall (read+write) accesses 1122system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses 1123system.cpu.l2cache.overall_accesses::cpu.inst 1894530 # number of overall (read+write) accesses 1124system.cpu.l2cache.overall_accesses::cpu.data 838279 # number of overall (read+write) accesses 1125system.cpu.l2cache.overall_accesses::total 2798333 # number of overall (read+write) accesses 1126system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses 1127system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses | 1129system.cpu.l2cache.ReadExReq_accesses::cpu.data 296684 # number of ReadExReq accesses(hits+misses) 1130system.cpu.l2cache.ReadExReq_accesses::total 296684 # number of ReadExReq accesses(hits+misses) 1131system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53921 # number of demand (read+write) accesses 1132system.cpu.l2cache.demand_accesses::cpu.itb.walker 11714 # number of demand (read+write) accesses 1133system.cpu.l2cache.demand_accesses::cpu.inst 1894712 # number of demand (read+write) accesses 1134system.cpu.l2cache.demand_accesses::cpu.data 838530 # number of demand (read+write) accesses 1135system.cpu.l2cache.demand_accesses::total 2798877 # number of demand (read+write) accesses 1136system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53921 # number of overall (read+write) accesses 1137system.cpu.l2cache.overall_accesses::cpu.itb.walker 11714 # number of overall (read+write) accesses 1138system.cpu.l2cache.overall_accesses::cpu.inst 1894712 # number of overall (read+write) accesses 1139system.cpu.l2cache.overall_accesses::cpu.data 838530 # number of overall (read+write) accesses 1140system.cpu.l2cache.overall_accesses::total 2798877 # number of overall (read+write) accesses 1141system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000352 # miss rate for ReadReq accesses 1142system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000598 # miss rate for ReadReq accesses |
| 1128system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses | 1143system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses |
| 1129system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses 1130system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses 1131system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses 1132system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses | 1144system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025129 # miss rate for ReadReq accesses 1145system.cpu.l2cache.ReadReq_miss_rate::total 0.013432 # miss rate for ReadReq accesses 1146system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987004 # miss rate for UpgradeReq accesses 1147system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987004 # miss rate for UpgradeReq accesses |
| 1133system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1134system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses | 1148system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1149system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses |
| 1135system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses 1136system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses 1137system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses 1138system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses | 1150system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461548 # miss rate for ReadExReq accesses 1151system.cpu.l2cache.ReadExReq_miss_rate::total 0.461548 # miss rate for ReadExReq accesses 1152system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000352 # miss rate for demand accesses 1153system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000598 # miss rate for demand accesses |
| 1139system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses | 1154system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses |
| 1140system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses 1141system.cpu.l2cache.demand_miss_rate::total 0.060947 # miss rate for demand accesses 1142system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses 1143system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses | 1155system.cpu.l2cache.demand_miss_rate::cpu.data 0.179540 # miss rate for demand accesses 1156system.cpu.l2cache.demand_miss_rate::total 0.060933 # miss rate for demand accesses 1157system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000352 # miss rate for overall accesses 1158system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000598 # miss rate for overall accesses |
| 1144system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses | 1159system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses |
| 1145system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses 1146system.cpu.l2cache.overall_miss_rate::total 0.060947 # miss rate for overall accesses 1147system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency | 1160system.cpu.l2cache.overall_miss_rate::cpu.data 0.179540 # miss rate for overall accesses 1161system.cpu.l2cache.overall_miss_rate::total 0.060933 # miss rate for overall accesses 1162system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 77513.157895 # average ReadReq miss latency |
| 1148system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency | 1163system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency |
| 1149system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75113.593108 # average ReadReq miss latency 1150system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79198.770191 # average ReadReq miss latency 1151system.cpu.l2cache.ReadReq_avg_miss_latency::total 76770.201119 # average ReadReq miss latency 1152system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency 1153system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency 1154system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency 1155system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency 1156system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72467.599626 # average ReadExReq miss latency 1157system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72467.599626 # average ReadExReq miss latency 1158system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency | 1164system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75315.204327 # average ReadReq miss latency 1165system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80052.878966 # average ReadReq miss latency 1166system.cpu.l2cache.ReadReq_avg_miss_latency::total 77236.030943 # average ReadReq miss latency 1167system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 212.865764 # average UpgradeReq miss latency 1168system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 212.865764 # average UpgradeReq miss latency 1169system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency 1170system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency 1171system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72500.302635 # average ReadExReq miss latency 1172system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72500.302635 # average ReadExReq miss latency 1173system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 77513.157895 # average overall miss latency |
| 1159system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency | 1174system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency |
| 1160system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency 1161system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency 1162system.cpu.l2cache.demand_avg_miss_latency::total 73315.561452 # average overall miss latency 1163system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency | 1175system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75315.204327 # average overall miss latency 1176system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73183.370581 # average overall miss latency 1177system.cpu.l2cache.demand_avg_miss_latency::total 73433.597435 # average overall miss latency 1178system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 77513.157895 # average overall miss latency |
| 1164system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency | 1179system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency |
| 1165system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency 1166system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency 1167system.cpu.l2cache.overall_avg_miss_latency::total 73315.561452 # average overall miss latency | 1180system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75315.204327 # average overall miss latency 1181system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73183.370581 # average overall miss latency 1182system.cpu.l2cache.overall_avg_miss_latency::total 73433.597435 # average overall miss latency |
| 1168system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1169system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1170system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1171system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1172system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1173system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1174system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1175system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1183system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1190system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1176system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks 1177system.cpu.l2cache.writebacks::total 90626 # number of writebacks | 1191system.cpu.l2cache.writebacks::writebacks 90628 # number of writebacks 1192system.cpu.l2cache.writebacks::total 90628 # number of writebacks |
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| 1194system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1195system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses | 1209system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1210system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses |
| 1196system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses 1197system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses | 1211system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136934 # number of ReadExReq MSHR misses 1212system.cpu.l2cache.ReadExReq_mshr_misses::total 136934 # number of ReadExReq MSHR misses |
| 1198system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1199system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses | 1213system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1214system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses |
| 1200system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses 1201system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses 1202system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses | 1215system.cpu.l2cache.demand_mshr_misses::cpu.inst 19943 # number of demand (read+write) MSHR misses 1216system.cpu.l2cache.demand_mshr_misses::cpu.data 150438 # number of demand (read+write) MSHR misses 1217system.cpu.l2cache.demand_mshr_misses::total 170407 # number of demand (read+write) MSHR misses |
| 1203system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1204system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses | 1218system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1219system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses |
| 1205system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses 1206system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses 1207system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses 1208system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles | 1220system.cpu.l2cache.overall_mshr_misses::cpu.inst 19943 # number of overall MSHR misses 1221system.cpu.l2cache.overall_mshr_misses::cpu.data 150438 # number of overall MSHR misses 1222system.cpu.l2cache.overall_mshr_misses::total 170407 # number of overall MSHR misses 1223system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1237250 # number of ReadReq MSHR miss cycles |
| 1209system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles | 1224system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles |
| 1210system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1247817250 # number of ReadReq MSHR miss cycles 1211system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902981250 # number of ReadReq MSHR miss cycles 1212system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152473250 # number of ReadReq MSHR miss cycles 1213system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles 1214system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles 1215system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 1216system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles 1217system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8210001310 # number of ReadExReq MSHR miss cycles 1218system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8210001310 # number of ReadExReq MSHR miss cycles 1219system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles | 1225system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1251787750 # number of ReadReq MSHR miss cycles 1226system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 914145000 # number of ReadReq MSHR miss cycles 1227system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167621250 # number of ReadReq MSHR miss cycles 1228system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27559234 # number of UpgradeReq MSHR miss cycles 1229system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27559234 # number of UpgradeReq MSHR miss cycles 1230system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles 1231system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles 1232system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8214311559 # number of ReadExReq MSHR miss cycles 1233system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8214311559 # number of ReadExReq MSHR miss cycles 1234system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1237250 # number of demand (read+write) MSHR miss cycles |
| 1220system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles | 1235system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles |
| 1221system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1247817250 # number of demand (read+write) MSHR miss cycles 1222system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112982560 # number of demand (read+write) MSHR miss cycles 1223system.cpu.l2cache.demand_mshr_miss_latency::total 10362474560 # number of demand (read+write) MSHR miss cycles 1224system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles | 1236system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1251787750 # number of demand (read+write) MSHR miss cycles 1237system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9128456559 # number of demand (read+write) MSHR miss cycles 1238system.cpu.l2cache.demand_mshr_miss_latency::total 10381932809 # number of demand (read+write) MSHR miss cycles 1239system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1237250 # number of overall MSHR miss cycles |
| 1225system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles | 1240system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles |
| 1226system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1247817250 # number of overall MSHR miss cycles 1227system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112982560 # number of overall MSHR miss cycles 1228system.cpu.l2cache.overall_mshr_miss_latency::total 10362474560 # number of overall MSHR miss cycles | 1241system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1251787750 # number of overall MSHR miss cycles 1242system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9128456559 # number of overall MSHR miss cycles 1243system.cpu.l2cache.overall_mshr_miss_latency::total 10381932809 # number of overall MSHR miss cycles |
| 1229system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles | 1244system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles |
| 1230system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387482250 # number of ReadReq MSHR uncacheable cycles 1231system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545359250 # number of ReadReq MSHR uncacheable cycles 1232system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles 1233system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles | 1245system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387474750 # number of ReadReq MSHR uncacheable cycles 1246system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545351750 # number of ReadReq MSHR uncacheable cycles 1247system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107339500 # number of WriteReq MSHR uncacheable cycles 1248system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107339500 # number of WriteReq MSHR uncacheable cycles |
| 1234system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles | 1249system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles |
| 1235system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494823250 # number of overall MSHR uncacheable cycles 1236system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652700250 # number of overall MSHR uncacheable cycles 1237system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses 1238system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses | 1250system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494814250 # number of overall MSHR uncacheable cycles 1251system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652691250 # number of overall MSHR uncacheable cycles 1252system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for ReadReq accesses 1253system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for ReadReq accesses |
| 1239system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses | 1254system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses |
| 1240system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses 1241system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses 1242system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses 1243system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses | 1255system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024922 # mshr miss rate for ReadReq accesses 1256system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013377 # mshr miss rate for ReadReq accesses 1257system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987004 # mshr miss rate for UpgradeReq accesses 1258system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987004 # mshr miss rate for UpgradeReq accesses |
| 1244system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1245system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses | 1259system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1260system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses |
| 1246system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses 1247system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses 1248system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses 1249system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses | 1261system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461548 # mshr miss rate for ReadExReq accesses 1262system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461548 # mshr miss rate for ReadExReq accesses 1263system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for demand accesses 1264system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for demand accesses |
| 1250system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses | 1265system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses |
| 1251system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for demand accesses 1252system.cpu.l2cache.demand_mshr_miss_rate::total 0.060898 # mshr miss rate for demand accesses 1253system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses 1254system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses | 1266system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for demand accesses 1267system.cpu.l2cache.demand_mshr_miss_rate::total 0.060884 # mshr miss rate for demand accesses 1268system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000352 # mshr miss rate for overall accesses 1269system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000598 # mshr miss rate for overall accesses |
| 1255system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses | 1270system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses |
| 1256system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for overall accesses 1257system.cpu.l2cache.overall_mshr_miss_rate::total 0.060898 # mshr miss rate for overall accesses 1258system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency | 1271system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179407 # mshr miss rate for overall accesses 1272system.cpu.l2cache.overall_mshr_miss_rate::total 0.060884 # mshr miss rate for overall accesses 1273system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average ReadReq mshr miss latency |
| 1259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency | 1274system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency |
| 1260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107 # average ReadReq mshr miss latency 1261system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438 # average ReadReq mshr miss latency 1262system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596 # average ReadReq mshr miss latency 1263system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency 1264system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency 1265system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1266system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1267system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency 1268system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency 1269system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency | 1275system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62768.277090 # average ReadReq mshr miss latency 1276system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67694.386848 # average ReadReq mshr miss latency 1277system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64757.304395 # average ReadReq mshr miss latency 1278system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10080.188003 # average UpgradeReq mshr miss latency 1279system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10080.188003 # average UpgradeReq mshr miss latency 1280system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency 1281system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency 1282system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59987.377561 # average ReadExReq mshr miss latency 1283system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59987.377561 # average ReadExReq mshr miss latency 1284system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency |
| 1270system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency | 1285system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency |
| 1271system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency 1272system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency 1273system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency 1274system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency | 1286system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency 1287system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency 1288system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency 1289system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65118.421053 # average overall mshr miss latency |
| 1275system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency | 1290system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency |
| 1276system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency 1277system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency 1278system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency | 1291system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62768.277090 # average overall mshr miss latency 1292system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60679.193814 # average overall mshr miss latency 1293system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60924.332973 # average overall mshr miss latency |
| 1279system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1280system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1281system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1282system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1283system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1284system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1285system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1286system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1287system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1294system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1295system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1296system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1297system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1298system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1299system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1300system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1301system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1302system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1288system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution 1289system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution | 1303system.cpu.toL2Bus.trans_dist::ReadReq 2565344 # Transaction distribution 1304system.cpu.toL2Bus.trans_dist::ReadResp 2565278 # Transaction distribution |
| 1290system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution 1291system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution | 1305system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution 1306system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution |
| 1292system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution 1293system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution 1294system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution | 1307system.cpu.toL2Bus.trans_dist::Writeback 695574 # Transaction distribution 1308system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1309system.cpu.toL2Bus.trans_dist::UpgradeReq 2770 # Transaction distribution |
| 1295system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution | 1310system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution |
| 1296system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution 1297system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution 1298system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution 1299system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes) 1300system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes) 1301system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) 1302system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes) 1303system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes) 1304system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes) 1305system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes) 1306system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) 1307system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes) 1308system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes) 1309system.cpu.toL2Bus.snoops 65488 # Total snoops (count) 1310system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram 1311system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram 1312system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram | 1311system.cpu.toL2Bus.trans_dist::UpgradeResp 2775 # Transaction distribution 1312system.cpu.toL2Bus.trans_dist::ReadExReq 296684 # Transaction distribution 1313system.cpu.toL2Bus.trans_dist::ReadExResp 296684 # Transaction distribution 1314system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795456 # Packet count per connected master and slave (bytes) 1315system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495832 # Packet count per connected master and slave (bytes) 1316system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31236 # Packet count per connected master and slave (bytes) 1317system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128794 # Packet count per connected master and slave (bytes) 1318system.cpu.toL2Bus.pkt_count::total 6451318 # Packet count per connected master and slave (bytes) 1319system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121309456 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98375777 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46856 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215684 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu.toL2Bus.pkt_size::total 219947773 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu.toL2Bus.snoops 65392 # Total snoops (count) 1325system.cpu.toL2Bus.snoop_fanout::samples 3562462 # Request fanout histogram 1326system.cpu.toL2Bus.snoop_fanout::mean 5.010230 # Request fanout histogram 1327system.cpu.toL2Bus.snoop_fanout::stdev 0.100625 # Request fanout histogram |
| 1313system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1314system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1315system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1316system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1317system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1318system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1328system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1329system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1330system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1331system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1332system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1333system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1319system.cpu.toL2Bus.snoop_fanout::5 3525400 98.98% 98.98% # Request fanout histogram 1320system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram | 1334system.cpu.toL2Bus.snoop_fanout::5 3526018 98.98% 98.98% # Request fanout histogram 1335system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram |
| 1321system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1322system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1323system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1336system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1337system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1338system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1324system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram 1325system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks) | 1339system.cpu.toL2Bus.snoop_fanout::total 3562462 # Request fanout histogram 1340system.cpu.toL2Bus.reqLayer0.occupancy 2503396529 # Layer occupancy (ticks) |
| 1326system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1341system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1327system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) | 1342system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) |
| 1328system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1343system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1329system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks) | 1344system.cpu.toL2Bus.respLayer0.occupancy 2849706150 # Layer occupancy (ticks) |
| 1330system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 1345system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 1331system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks) | 1346system.cpu.toL2Bus.respLayer1.occupancy 1334755109 # Layer occupancy (ticks) |
| 1332system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1347system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1333system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) | 1348system.cpu.toL2Bus.respLayer2.occupancy 19527240 # Layer occupancy (ticks) |
| 1334system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1349system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1335system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks) | 1350system.cpu.toL2Bus.respLayer3.occupancy 74897454 # Layer occupancy (ticks) |
| 1336system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1337system.iobus.trans_dist::ReadReq 30181 # Transaction distribution 1338system.iobus.trans_dist::ReadResp 30181 # Transaction distribution 1339system.iobus.trans_dist::WriteReq 59038 # Transaction distribution | 1351system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1352system.iobus.trans_dist::ReadReq 30181 # Transaction distribution 1353system.iobus.trans_dist::ReadResp 30181 # Transaction distribution 1354system.iobus.trans_dist::WriteReq 59038 # Transaction distribution |
| 1340system.iobus.trans_dist::WriteResp 59038 # Transaction distribution | 1355system.iobus.trans_dist::WriteResp 22814 # Transaction distribution 1356system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1341system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1345system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1346system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1348system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 1423system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1424system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1425system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1426system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1427system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1428system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1429system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1430system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 1357system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1358system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1359system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1360system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1361system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1362system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1363system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1364system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 1439system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1440system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1441system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1442system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1443system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1444system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1445system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1446system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 1431system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) | 1447system.iobus.reqLayer27.occupancy 347066130 # Layer occupancy (ticks) |
| 1432system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1433system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1434system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1435system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1436system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1448system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1449system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1450system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1451system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1452system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1437system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) | 1453system.iobus.respLayer3.occupancy 36776516 # Layer occupancy (ticks) |
| 1438system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1439system.iocache.tags.replacements 36410 # number of replacements | 1454system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1455system.iocache.tags.replacements 36410 # number of replacements |
| 1440system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use | 1456system.iocache.tags.tagsinuse 1.000725 # Cycle average of tags in use |
| 1441system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1442system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. 1443system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1457system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1458system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. 1459system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1444system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. 1445system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor 1446system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy 1447system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy | 1460system.iocache.tags.warmup_cycle 251942535000 # Cycle when the warmup percentage was hit. 1461system.iocache.tags.occ_blocks::realview.ide 1.000725 # Average occupied blocks per requestor 1462system.iocache.tags.occ_percent::realview.ide 0.062545 # Average percentage of cache occupancy 1463system.iocache.tags.occ_percent::total 0.062545 # Average percentage of cache occupancy |
| 1448system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1449system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1450system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1451system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1452system.iocache.tags.data_accesses 327996 # Number of data accesses | 1464system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1465system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1466system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1467system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1468system.iocache.tags.data_accesses 327996 # Number of data accesses |
| 1453system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1454system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | |
| 1455system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1456system.iocache.ReadReq_misses::total 220 # number of ReadReq misses | 1469system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1470system.iocache.ReadReq_misses::total 220 # number of ReadReq misses |
| 1471system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1472system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
|
| 1457system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses 1458system.iocache.demand_misses::total 220 # number of demand (read+write) misses 1459system.iocache.overall_misses::realview.ide 220 # number of overall misses 1460system.iocache.overall_misses::total 220 # number of overall misses | 1473system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses 1474system.iocache.demand_misses::total 220 # number of demand (read+write) misses 1475system.iocache.overall_misses::realview.ide 220 # number of overall misses 1476system.iocache.overall_misses::total 220 # number of overall misses |
| 1461system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles 1462system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles 1463system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles 1464system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles 1465system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles 1466system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles | 1477system.iocache.ReadReq_miss_latency::realview.ide 26411377 # number of ReadReq miss cycles 1478system.iocache.ReadReq_miss_latency::total 26411377 # number of ReadReq miss cycles 1479system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9622478237 # number of WriteInvalidateReq miss cycles 1480system.iocache.WriteInvalidateReq_miss_latency::total 9622478237 # number of WriteInvalidateReq miss cycles 1481system.iocache.demand_miss_latency::realview.ide 26411377 # number of demand (read+write) miss cycles 1482system.iocache.demand_miss_latency::total 26411377 # number of demand (read+write) miss cycles 1483system.iocache.overall_miss_latency::realview.ide 26411377 # number of overall miss cycles 1484system.iocache.overall_miss_latency::total 26411377 # number of overall miss cycles |
| 1467system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1468system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) 1469system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1470system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1471system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses 1472system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses 1473system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses 1474system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses 1475system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1476system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 1485system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1486system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) 1487system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1488system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1489system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses 1490system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses 1491system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses 1492system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses 1493system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1494system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 1495system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1496system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
|
| 1477system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1478system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1479system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1480system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1497system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1498system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1499system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1500system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1481system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency 1482system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency 1483system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency 1484system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency 1485system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency 1486system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency 1487system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1501system.iocache.ReadReq_avg_miss_latency::realview.ide 120051.713636 # average ReadReq miss latency 1502system.iocache.ReadReq_avg_miss_latency::total 120051.713636 # average ReadReq miss latency 1503system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265638.202214 # average WriteInvalidateReq miss latency 1504system.iocache.WriteInvalidateReq_avg_miss_latency::total 265638.202214 # average WriteInvalidateReq miss latency 1505system.iocache.demand_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency 1506system.iocache.demand_avg_miss_latency::total 120051.713636 # average overall miss latency 1507system.iocache.overall_avg_miss_latency::realview.ide 120051.713636 # average overall miss latency 1508system.iocache.overall_avg_miss_latency::total 120051.713636 # average overall miss latency 1509system.iocache.blocked_cycles::no_mshrs 56749 # number of cycles access was blocked |
| 1488system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1510system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1489system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked | 1511system.iocache.blocked::no_mshrs 7275 # number of cycles access was blocked |
| 1490system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1512system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1491system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1513system.iocache.avg_blocked_cycles::no_mshrs 7.800550 # average number of cycles each access was blocked |
| 1492system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1514system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1493system.iocache.fast_writes 36224 # number of fast writes performed | 1515system.iocache.fast_writes 0 # number of fast writes performed |
| 1494system.iocache.cache_copies 0 # number of cache copies performed | 1516system.iocache.cache_copies 0 # number of cache copies performed |
| 1517system.iocache.writebacks::writebacks 36190 # number of writebacks 1518system.iocache.writebacks::total 36190 # number of writebacks |
|
| 1495system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1496system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses | 1519system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1520system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses |
| 1521system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses 1522system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses |
|
| 1497system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses 1498system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses 1499system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses 1500system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses | 1523system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses 1524system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses 1525system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses 1526system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses |
| 1501system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles 1502system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles 1503system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles 1504system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles 1505system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles 1506system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles 1507system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles 1508system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles | 1527system.iocache.ReadReq_mshr_miss_latency::realview.ide 14970377 # number of ReadReq MSHR miss cycles 1528system.iocache.ReadReq_mshr_miss_latency::total 14970377 # number of ReadReq MSHR miss cycles 1529system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7738798269 # number of WriteInvalidateReq MSHR miss cycles 1530system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7738798269 # number of WriteInvalidateReq MSHR miss cycles 1531system.iocache.demand_mshr_miss_latency::realview.ide 14970377 # number of demand (read+write) MSHR miss cycles 1532system.iocache.demand_mshr_miss_latency::total 14970377 # number of demand (read+write) MSHR miss cycles 1533system.iocache.overall_mshr_miss_latency::realview.ide 14970377 # number of overall MSHR miss cycles 1534system.iocache.overall_mshr_miss_latency::total 14970377 # number of overall MSHR miss cycles |
| 1509system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1510system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 1535system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1536system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 1537system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1538system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 1511system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1512system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1513system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1514system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1539system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1540system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1541system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1542system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1515system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency 1516system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency 1517system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1518system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1519system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency 1520system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency 1521system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency 1522system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency | 1543system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68047.168182 # average ReadReq mshr miss latency 1544system.iocache.ReadReq_avg_mshr_miss_latency::total 68047.168182 # average ReadReq mshr miss latency 1545system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213637.319705 # average WriteInvalidateReq mshr miss latency 1546system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213637.319705 # average WriteInvalidateReq mshr miss latency 1547system.iocache.demand_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency 1548system.iocache.demand_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency 1549system.iocache.overall_avg_mshr_miss_latency::realview.ide 68047.168182 # average overall mshr miss latency 1550system.iocache.overall_avg_mshr_miss_latency::total 68047.168182 # average overall mshr miss latency |
| 1523system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1551system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1524system.membus.trans_dist::ReadReq 67834 # Transaction distribution 1525system.membus.trans_dist::ReadResp 67833 # Transaction distribution | 1552system.membus.trans_dist::ReadReq 67832 # Transaction distribution 1553system.membus.trans_dist::ReadResp 67831 # Transaction distribution |
| 1526system.membus.trans_dist::WriteReq 27608 # Transaction distribution 1527system.membus.trans_dist::WriteResp 27608 # Transaction distribution | 1554system.membus.trans_dist::WriteReq 27608 # Transaction distribution 1555system.membus.trans_dist::WriteResp 27608 # Transaction distribution |
| 1528system.membus.trans_dist::Writeback 90626 # Transaction distribution | 1556system.membus.trans_dist::Writeback 126818 # Transaction distribution |
| 1529system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1530system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1531system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution 1532system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1533system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution | 1557system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1558system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1559system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution 1560system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1561system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution |
| 1534system.membus.trans_dist::ReadExReq 135127 # Transaction distribution 1535system.membus.trans_dist::ReadExResp 135127 # Transaction distribution | 1562system.membus.trans_dist::ReadExReq 135125 # Transaction distribution 1563system.membus.trans_dist::ReadExResp 135125 # Transaction distribution |
| 1536system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1537system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1538system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) | 1564system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 1566system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
| 1539system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) 1540system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) 1541system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) 1542system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) 1543system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) | 1567system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452492 # Packet count per connected master and slave (bytes) 1568system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560128 # Packet count per connected master and slave (bytes) 1569system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) 1570system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) 1571system.membus.pkt_count::total 669001 # Packet count per connected master and slave (bytes) |
| 1544system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1545system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1546system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) | 1572system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
| 1547system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) 1548system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) 1549system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 1550system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 1551system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) 1552system.membus.snoops 205 # Total snoops (count) 1553system.membus.snoop_fanout::samples 300222 # Request fanout histogram | 1575system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16640360 # Cumulative packet size per connected master and slave (bytes) 1576system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16803825 # Cumulative packet size per connected master and slave (bytes) 1577system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) 1578system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) 1579system.membus.pkt_size::total 21439281 # Cumulative packet size per connected master and slave (bytes) 1580system.membus.snoops 484 # Total snoops (count) 1581system.membus.snoop_fanout::samples 336405 # Request fanout histogram |
| 1554system.membus.snoop_fanout::mean 1 # Request fanout histogram 1555system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1556system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1557system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1582system.membus.snoop_fanout::mean 1 # Request fanout histogram 1583system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1584system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1585system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1558system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram | 1586system.membus.snoop_fanout::1 336405 100.00% 100.00% # Request fanout histogram |
| 1559system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1560system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1561system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1562system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1587system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1588system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1589system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1590system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1563system.membus.snoop_fanout::total 300222 # Request fanout histogram 1564system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks) | 1591system.membus.snoop_fanout::total 336405 # Request fanout histogram 1592system.membus.reqLayer0.occupancy 94190000 # Layer occupancy (ticks) |
| 1565system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1566system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1567system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1593system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1594system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1595system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1568system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks) | 1596system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) |
| 1569system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1597system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1570system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks) 1571system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1572system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks) | 1598system.membus.reqLayer5.occupancy 1683660499 # Layer occupancy (ticks) 1599system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) 1600system.membus.respLayer2.occupancy 1677935457 # Layer occupancy (ticks) |
| 1573system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 1601system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 1574system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) | 1602system.membus.respLayer3.occupancy 38220484 # Layer occupancy (ticks) |
| 1575system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1576system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1577system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1578system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1579system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1580system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1581system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1582system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1600system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1601system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1602system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1603system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1604system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1605system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1606system.realview.ethernet.droppedPackets 0 # number of packets dropped 1607system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1603system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1604system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1605system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1606system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1607system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1608system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1609system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1610system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 17 unchanged lines hidden (view full) --- 1628system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1629system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1630system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1631system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1632system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1633system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1634system.realview.ethernet.droppedPackets 0 # number of packets dropped 1635system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1608system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed | 1636system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed |
| 1609 1610---------- End Simulation Statistics ---------- | 1637 1638---------- End Simulation Statistics ---------- |