| stats.txt (10513:ca4438b6e39a) | stats.txt (10517:ba51f8572571) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.826846 # Number of seconds simulated 4sim_ticks 2826845674500 # Number of ticks simulated 5final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.826844 # Number of seconds simulated 4sim_ticks 2826844351500 # Number of ticks simulated 5final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 98010 # Simulator instruction rate (inst/s) 8host_op_rate 118881 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2448127815 # Simulator tick rate (ticks/s) 10host_mem_usage 558668 # Number of bytes of host memory used 11host_seconds 1154.70 # Real time elapsed on the host 12sim_insts 113172343 # Number of instructions simulated 13sim_ops 137271263 # Number of ops (including micro ops) simulated | 7host_inst_rate 97337 # Simulator instruction rate (inst/s) 8host_op_rate 118064 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2430592330 # Simulator tick rate (ticks/s) 10host_mem_usage 558776 # Number of bytes of host memory used 11host_seconds 1163.03 # Real time elapsed on the host 12sim_insts 113205077 # Number of instructions simulated 13sim_ops 137311743 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory 22system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) 23system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) 27system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 29system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 30system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory |
| 31system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory 32system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory 33system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory 34system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory 35system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory 36system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory | 31system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory 32system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory 33system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory 34system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory 35system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory 36system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory |
| 37system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 38system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory | 37system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 38system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory |
| 39system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory | 39system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory |
| 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory | 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory |
| 43system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory | 43system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory 45system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory 46system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory |
| 47system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory | 47system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory | 49system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory |
| 50system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) |
| 53system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) |
| 59system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) |
| 61system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) |
| 63system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 172183 # Number of read requests accepted 70system.physmem.writeReqs 131246 # Number of write requests accepted 71system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue 72system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue 75system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM 76system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side 77system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue | 66system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 172165 # Number of read requests accepted 70system.physmem.writeReqs 131231 # Number of write requests accepted 71system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue 72system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue 73system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM 74system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue 75system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM 76system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side 77system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side 78system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue |
| 79system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write | 79system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 80system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write |
| 81system.physmem.perBankRdBursts::0 10992 # Per bank write bursts | 81system.physmem.perBankRdBursts::0 10989 # Per bank write bursts |
| 82system.physmem.perBankRdBursts::1 10130 # Per bank write bursts | 82system.physmem.perBankRdBursts::1 10130 # Per bank write bursts |
| 83system.physmem.perBankRdBursts::2 11200 # Per bank write bursts 84system.physmem.perBankRdBursts::3 11425 # Per bank write bursts | 83system.physmem.perBankRdBursts::2 11201 # Per bank write bursts 84system.physmem.perBankRdBursts::3 11419 # Per bank write bursts |
| 85system.physmem.perBankRdBursts::4 13122 # Per bank write bursts | 85system.physmem.perBankRdBursts::4 13122 # Per bank write bursts |
| 86system.physmem.perBankRdBursts::5 10553 # Per bank write bursts 87system.physmem.perBankRdBursts::6 11175 # Per bank write bursts 88system.physmem.perBankRdBursts::7 11538 # Per bank write bursts 89system.physmem.perBankRdBursts::8 10354 # Per bank write bursts 90system.physmem.perBankRdBursts::9 11059 # Per bank write bursts 91system.physmem.perBankRdBursts::10 10499 # Per bank write bursts | 86system.physmem.perBankRdBursts::5 10546 # Per bank write bursts 87system.physmem.perBankRdBursts::6 11171 # Per bank write bursts 88system.physmem.perBankRdBursts::7 11539 # Per bank write bursts 89system.physmem.perBankRdBursts::8 10356 # Per bank write bursts 90system.physmem.perBankRdBursts::9 11055 # Per bank write bursts 91system.physmem.perBankRdBursts::10 10496 # Per bank write bursts |
| 92system.physmem.perBankRdBursts::11 9259 # Per bank write bursts 93system.physmem.perBankRdBursts::12 10183 # Per bank write bursts 94system.physmem.perBankRdBursts::13 10761 # Per bank write bursts 95system.physmem.perBankRdBursts::14 10049 # Per bank write bursts | 92system.physmem.perBankRdBursts::11 9259 # Per bank write bursts 93system.physmem.perBankRdBursts::12 10183 # Per bank write bursts 94system.physmem.perBankRdBursts::13 10761 # Per bank write bursts 95system.physmem.perBankRdBursts::14 10049 # Per bank write bursts |
| 96system.physmem.perBankRdBursts::15 9748 # Per bank write bursts | 96system.physmem.perBankRdBursts::15 9745 # Per bank write bursts |
| 97system.physmem.perBankWrBursts::0 8312 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7765 # Per bank write bursts 99system.physmem.perBankWrBursts::2 8704 # Per bank write bursts | 97system.physmem.perBankWrBursts::0 8312 # Per bank write bursts 98system.physmem.perBankWrBursts::1 7765 # Per bank write bursts 99system.physmem.perBankWrBursts::2 8704 # Per bank write bursts |
| 100system.physmem.perBankWrBursts::3 8608 # Per bank write bursts | 100system.physmem.perBankWrBursts::3 8604 # Per bank write bursts |
| 101system.physmem.perBankWrBursts::4 7611 # Per bank write bursts | 101system.physmem.perBankWrBursts::4 7611 # Per bank write bursts |
| 102system.physmem.perBankWrBursts::5 7956 # Per bank write bursts 103system.physmem.perBankWrBursts::6 8259 # Per bank write bursts | 102system.physmem.perBankWrBursts::5 7949 # Per bank write bursts 103system.physmem.perBankWrBursts::6 8258 # Per bank write bursts |
| 104system.physmem.perBankWrBursts::7 8579 # Per bank write bursts | 104system.physmem.perBankWrBursts::7 8579 # Per bank write bursts |
| 105system.physmem.perBankWrBursts::8 7842 # Per bank write bursts 106system.physmem.perBankWrBursts::9 8532 # Per bank write bursts 107system.physmem.perBankWrBursts::10 7844 # Per bank write bursts | 105system.physmem.perBankWrBursts::8 7843 # Per bank write bursts 106system.physmem.perBankWrBursts::9 8531 # Per bank write bursts 107system.physmem.perBankWrBursts::10 7842 # Per bank write bursts |
| 108system.physmem.perBankWrBursts::11 6872 # Per bank write bursts 109system.physmem.perBankWrBursts::12 7611 # Per bank write bursts 110system.physmem.perBankWrBursts::13 8198 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7543 # Per bank write bursts | 108system.physmem.perBankWrBursts::11 6872 # Per bank write bursts 109system.physmem.perBankWrBursts::12 7611 # Per bank write bursts 110system.physmem.perBankWrBursts::13 8198 # Per bank write bursts 111system.physmem.perBankWrBursts::14 7543 # Per bank write bursts |
| 112system.physmem.perBankWrBursts::15 7119 # Per bank write bursts | 112system.physmem.perBankWrBursts::15 7118 # Per bank write bursts |
| 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 113system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 114system.physmem.numWrRetry 6 # Number of times write queue was full causing retry 115system.physmem.totGap 2826845408500 # Total gap between requests | 114system.physmem.numWrRetry 5 # Number of times write queue was full causing retry 115system.physmem.totGap 2826844140500 # Total gap between requests |
| 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 541 # Read request sizes (log2) 119system.physmem.readPktSize::3 14 # Read request sizes (log2) 120system.physmem.readPktSize::4 2993 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) | 116system.physmem.readPktSize::0 0 # Read request sizes (log2) 117system.physmem.readPktSize::1 0 # Read request sizes (log2) 118system.physmem.readPktSize::2 541 # Read request sizes (log2) 119system.physmem.readPktSize::3 14 # Read request sizes (log2) 120system.physmem.readPktSize::4 2993 # Read request sizes (log2) 121system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 122system.physmem.readPktSize::6 168635 # Read request sizes (log2) | 122system.physmem.readPktSize::6 168617 # Read request sizes (log2) |
| 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 4381 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) | 123system.physmem.writePktSize::0 0 # Write request sizes (log2) 124system.physmem.writePktSize::1 0 # Write request sizes (log2) 125system.physmem.writePktSize::2 4381 # Write request sizes (log2) 126system.physmem.writePktSize::3 0 # Write request sizes (log2) 127system.physmem.writePktSize::4 0 # Write request sizes (log2) 128system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 129system.physmem.writePktSize::6 126865 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 129system.physmem.writePktSize::6 126850 # Write request sizes (log2) 130system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 135system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 169system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 135system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 169system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 177system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see | 177system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see |
| 221system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see | 221system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see |
| 222system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see | 222system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see |
| 224system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see | 224system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see |
| 225system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see 226system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation 227system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation 228system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation 240system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes 241system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes 242system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes | 225system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see 226system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation 227system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation 228system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation 229system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation 230system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation 240system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes 241system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes 242system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes 243system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes |
| 244system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes | 244system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 245system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 246system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes 247system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads 280system.physmem.totQLat 2068507750 # Total ticks spent queuing 281system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM 282system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers 283system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst | 246system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes 247system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads 282system.physmem.totQLat 2071957750 # Total ticks spent queuing 283system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM 284system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers 285system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst |
| 284system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 286system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 285system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst 286system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s | 287system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst 288system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s |
| 287system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s 288system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s 289system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s 290system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 291system.physmem.busUtil 0.05 # Data bus utilization in percentage 292system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 293system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 294system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 289system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s 290system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s 291system.physmem.avgWrBWSys 2.88 # Average system write bandwidth in MiByte/s 292system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 293system.physmem.busUtil 0.05 # Data bus utilization in percentage 294system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 295system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 296system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 295system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing 296system.physmem.readRowHits 142034 # Number of row buffer hits during reads 297system.physmem.writeRowHits 95196 # Number of row buffer hits during writes 298system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads 299system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes 300system.physmem.avgGap 9316332.35 # Average gap between requests 301system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined 302system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states 303system.physmem.memoryStateTime::REF 94394560000 # Time in different power states | 297system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing 298system.physmem.readRowHits 141999 # Number of row buffer hits during reads 299system.physmem.writeRowHits 95218 # Number of row buffer hits during writes 300system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads 301system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes 302system.physmem.avgGap 9317341.50 # Average gap between requests 303system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined 304system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states 305system.physmem.memoryStateTime::REF 94394300000 # Time in different power states |
| 304system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 306system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 305system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states | 307system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states |
| 306system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 308system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 307system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ) 308system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ) 309system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ) 310system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ) 311system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ) 312system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ) 313system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ) 314system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ) 315system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ) 316system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ) 317system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ) 318system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ) 319system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ) 320system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ) 321system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ) 322system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ) 323system.physmem.averagePower::0 669.338580 # Core power per rank (mW) 324system.physmem.averagePower::1 669.240432 # Core power per rank (mW) 325system.membus.trans_dist::ReadReq 67851 # Transaction distribution 326system.membus.trans_dist::ReadResp 67850 # Transaction distribution | 309system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ) 310system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) 311system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ) 312system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) 313system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) 314system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ) 315system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) 316system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) 317system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) 318system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) 319system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ) 320system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ) 321system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ) 322system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ) 323system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ) 324system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ) 325system.physmem.averagePower::0 669.335912 # Core power per rank (mW) 326system.physmem.averagePower::1 669.239814 # Core power per rank (mW) 327system.membus.trans_dist::ReadReq 67834 # Transaction distribution 328system.membus.trans_dist::ReadResp 67833 # Transaction distribution |
| 327system.membus.trans_dist::WriteReq 27608 # Transaction distribution 328system.membus.trans_dist::WriteResp 27608 # Transaction distribution | 329system.membus.trans_dist::WriteReq 27608 # Transaction distribution 330system.membus.trans_dist::WriteResp 27608 # Transaction distribution |
| 329system.membus.trans_dist::Writeback 90641 # Transaction distribution | 331system.membus.trans_dist::Writeback 90626 # Transaction distribution |
| 330system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 331system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 332system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution 333system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 334system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution | 332system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 333system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 334system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution 335system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 336system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution |
| 335system.membus.trans_dist::ReadExReq 135128 # Transaction distribution 336system.membus.trans_dist::ReadExResp 135128 # Transaction distribution | 337system.membus.trans_dist::ReadExReq 135127 # Transaction distribution 338system.membus.trans_dist::ReadExResp 135127 # Transaction distribution |
| 337system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) | 339system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) |
| 340system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes) 341system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes) | 342system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) |
| 342system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) | 344system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) 345system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) |
| 344system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes) | 346system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) |
| 345system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) | 347system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) |
| 348system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes) 349system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes) | 350system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) |
| 350system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 351system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) | 352system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 353system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) |
| 352system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes) | 354system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) |
| 353system.membus.snoops 205 # Total snoops (count) | 355system.membus.snoops 205 # Total snoops (count) |
| 354system.membus.snoop_fanout::samples 300256 # Request fanout histogram | 356system.membus.snoop_fanout::samples 300222 # Request fanout histogram |
| 355system.membus.snoop_fanout::mean 1 # Request fanout histogram 356system.membus.snoop_fanout::stdev 0 # Request fanout histogram 357system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 358system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 357system.membus.snoop_fanout::mean 1 # Request fanout histogram 358system.membus.snoop_fanout::stdev 0 # Request fanout histogram 359system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 360system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 359system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram | 361system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram |
| 360system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 361system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 362system.membus.snoop_fanout::min_value 1 # Request fanout histogram 363system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 362system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 363system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 364system.membus.snoop_fanout::min_value 1 # Request fanout histogram 365system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 364system.membus.snoop_fanout::total 300256 # Request fanout histogram 365system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks) | 366system.membus.snoop_fanout::total 300222 # Request fanout histogram 367system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks) |
| 366system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 367system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 368system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 368system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 369system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 370system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 369system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) | 371system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks) |
| 370system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 372system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 371system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks) | 373system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks) |
| 372system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 374system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 373system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks) | 375system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks) |
| 374system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 376system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 375system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks) | 377system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) |
| 376system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 377system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 378system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 379system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 380system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 381system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 382system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 383system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 24 unchanged lines hidden (view full) --- 408system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 409system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 410system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 411system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 412system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 413system.cf0.dma_write_txs 631 # Number of DMA write transactions. 414system.iobus.trans_dist::ReadReq 30181 # Transaction distribution 415system.iobus.trans_dist::ReadResp 30181 # Transaction distribution | 378system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 379system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 380system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 381system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 382system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 383system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 384system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 385system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 24 unchanged lines hidden (view full) --- 410system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 411system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 412system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 413system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 414system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 415system.cf0.dma_write_txs 631 # Number of DMA write transactions. 416system.iobus.trans_dist::ReadReq 30181 # Transaction distribution 417system.iobus.trans_dist::ReadResp 30181 # Transaction distribution |
| 416system.iobus.trans_dist::WriteReq 59035 # Transaction distribution | 418system.iobus.trans_dist::WriteReq 59038 # Transaction distribution |
| 417system.iobus.trans_dist::WriteResp 59038 # Transaction distribution | 419system.iobus.trans_dist::WriteResp 59038 # Transaction distribution |
| 418system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution | |
| 419system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 420system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 421system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 501system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 502system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 503system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 504system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 505system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 506system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 507system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 508system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 420system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 421system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 422system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 423system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 424system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 425system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 426system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 427system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) --- 74 unchanged lines hidden (view full) --- 502system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 503system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 504system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 505system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 506system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 507system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 508system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 509system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 509system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks) | 510system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) |
| 510system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 511system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 512system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 513system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 514system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 511system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 512system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 513system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 514system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 515system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 515system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks) | 516system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) |
| 516system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 517system.cpu_clk_domain.clock 500 # Clock period in ticks | 517system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 518system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 518system.cpu.branchPred.lookups 46931803 # Number of BP lookups 519system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted 520system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect 521system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups 522system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits | 519system.cpu.branchPred.lookups 46964481 # Number of BP lookups 520system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted 521system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect 522system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups 523system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits |
| 523system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 524system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 524system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage 525system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target. 526system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions. | 525system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage 526system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target. 527system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. |
| 527system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 528system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 529system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 530system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 531system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 532system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 533system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 534system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 542system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 543system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 544system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 545system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 546system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 547system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 548system.cpu.dtb.inst_hits 0 # ITB inst hits 549system.cpu.dtb.inst_misses 0 # ITB inst misses | 528system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 529system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 530system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 531system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 532system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 533system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 534system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 535system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 543system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 544system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 545system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 546system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 547system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 548system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 549system.cpu.dtb.inst_hits 0 # ITB inst hits 550system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 550system.cpu.dtb.read_hits 25464394 # DTB read hits 551system.cpu.dtb.read_misses 60419 # DTB read misses 552system.cpu.dtb.write_hits 19915991 # DTB write hits 553system.cpu.dtb.write_misses 9380 # DTB write misses | 551system.cpu.dtb.read_hits 25471928 # DTB read hits 552system.cpu.dtb.read_misses 60410 # DTB read misses 553system.cpu.dtb.write_hits 19919780 # DTB write hits 554system.cpu.dtb.write_misses 9388 # DTB write misses |
| 554system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 555system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 556system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 557system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 558system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB 559system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions 560system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch 561system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 555system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 556system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 557system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 558system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 559system.cpu.dtb.flush_entries 4324 # Number of entries that have been flushed from TLB 560system.cpu.dtb.align_faults 351 # Number of TLB faults due to alignment restrictions 561system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch 562system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 562system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions 563system.cpu.dtb.read_accesses 25524813 # DTB read accesses 564system.cpu.dtb.write_accesses 19925371 # DTB write accesses | 563system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions 564system.cpu.dtb.read_accesses 25532338 # DTB read accesses 565system.cpu.dtb.write_accesses 19929168 # DTB write accesses |
| 565system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 566system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 566system.cpu.dtb.hits 45380385 # DTB hits 567system.cpu.dtb.misses 69799 # DTB misses 568system.cpu.dtb.accesses 45450184 # DTB accesses | 567system.cpu.dtb.hits 45391708 # DTB hits 568system.cpu.dtb.misses 69798 # DTB misses 569system.cpu.dtb.accesses 45461506 # DTB accesses |
| 569system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 570system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 571system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 572system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 573system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 574system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 575system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 576system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 582system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 583system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 584system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 585system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 586system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 587system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 588system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 589system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 570system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 571system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 572system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 573system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 574system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 575system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 576system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 577system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 583system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 584system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 585system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 586system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 587system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 588system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 589system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 590system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 590system.cpu.itb.inst_hits 66292387 # ITB inst hits 591system.cpu.itb.inst_misses 11931 # ITB inst misses | 591system.cpu.itb.inst_hits 66240861 # ITB inst hits 592system.cpu.itb.inst_misses 11936 # ITB inst misses |
| 592system.cpu.itb.read_hits 0 # DTB read hits 593system.cpu.itb.read_misses 0 # DTB read misses 594system.cpu.itb.write_hits 0 # DTB write hits 595system.cpu.itb.write_misses 0 # DTB write misses 596system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 597system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 598system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 599system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 600system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB 601system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 602system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 603system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 593system.cpu.itb.read_hits 0 # DTB read hits 594system.cpu.itb.read_misses 0 # DTB read misses 595system.cpu.itb.write_hits 0 # DTB write hits 596system.cpu.itb.write_misses 0 # DTB write misses 597system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 598system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 599system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 600system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 601system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB 602system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 603system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 604system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 604system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions | 605system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions |
| 605system.cpu.itb.read_accesses 0 # DTB read accesses 606system.cpu.itb.write_accesses 0 # DTB write accesses | 606system.cpu.itb.read_accesses 0 # DTB read accesses 607system.cpu.itb.write_accesses 0 # DTB write accesses |
| 607system.cpu.itb.inst_accesses 66304318 # ITB inst accesses 608system.cpu.itb.hits 66292387 # DTB hits 609system.cpu.itb.misses 11931 # DTB misses 610system.cpu.itb.accesses 66304318 # DTB accesses 611system.cpu.numCycles 260551438 # number of cpu cycles simulated | 608system.cpu.itb.inst_accesses 66252797 # ITB inst accesses 609system.cpu.itb.hits 66240861 # DTB hits 610system.cpu.itb.misses 11936 # DTB misses 611system.cpu.itb.accesses 66252797 # DTB accesses 612system.cpu.numCycles 260549216 # number of cpu cycles simulated |
| 612system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 613system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 614system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 614system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss 615system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed 616system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered 617system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken 618system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked 619system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing 620system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb 621system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 622system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps 623system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions | 615system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss 616system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed 617system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered 618system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken 619system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked 620system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing 621system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb 622system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 623system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps 624system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions |
| 624system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR | 625system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR |
| 625system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched 626system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed 627system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed 628system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total) 629system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total) 630system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total) | 626system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched 627system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed 628system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed 629system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total) 630system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total) 631system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) |
| 631system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 632system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 632system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total) 633system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total) 634system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total) 635system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total) | 633system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total) 634system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total) 635system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total) 636system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total) |
| 636system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 637system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 638system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 637system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 638system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 639system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 639system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total) 640system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle 641system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle 642system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle 643system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked 644system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running 645system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking 646system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing 647system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch 648system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction 649system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode 650system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode 651system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing 652system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle 653system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking 654system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst 655system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running 656system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking 657system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename 658system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename 659system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full 660system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full 661system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full 662system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full 663system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed 664system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made 665system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups | 640system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total) 641system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle 642system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle 643system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle 644system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked 645system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running 646system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking 647system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing 648system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch 649system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction 650system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode 651system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode 652system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing 653system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle 654system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking 655system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst 656system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running 657system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking 658system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename 659system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename 660system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full 661system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full 662system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full 663system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full 664system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed 665system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made 666system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups |
| 666system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups | 667system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups |
| 667system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed 668system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing 669system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed 670system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed 671system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer 672system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit. 673system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit. 674system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads. 675system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores. 676system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec) 677system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ 678system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued 679system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued 680system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling 681system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph 682system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed 683system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle 684system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle 685system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle | 668system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed 669system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing 670system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed 671system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed 672system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer 673system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit. 674system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit. 675system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads. 676system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores. 677system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec) 678system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ 679system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued 680system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued 681system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling 682system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph 683system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed 684system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle 685system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle 686system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle |
| 686system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 687system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 687system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle 688system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle 689system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle 690system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle 691system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle | 688system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle 689system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle 690system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle 691system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle 692system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle |
| 692system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 693system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 698system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 693system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 694system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 698system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 699system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 699system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle | 700system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle |
| 700system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 701system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 701system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available | 702system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available |
| 702system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available 703system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 704system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 705system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 706system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 707system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 708system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 709system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 722system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 723system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 724system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 725system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 726system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 727system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 728system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 729system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available | 703system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available 704system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available 705system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available 706system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available 707system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available 708system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available 709system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available 710system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available --- 12 unchanged lines hidden (view full) --- 723system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available 724system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available 725system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available 726system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available 727system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available 728system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available 729system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available 730system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available |
| 730system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available 731system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available | 731system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available 732system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available |
| 732system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 733system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued | 733system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 735system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued |
| 735system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued 736system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued | 736system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued 737system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued |
| 737system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 738system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 739system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 740system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 741system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 742system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 743system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 744system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 756system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 757system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 758system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 759system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 760system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued 761system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 762system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 763system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued | 738system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued 739system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued 740system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued 741system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.06% # Type of FU issued 742system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.06% # Type of FU issued 743system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.06% # Type of FU issued 744system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.06% # Type of FU issued 745system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.06% # Type of FU issued --- 11 unchanged lines hidden (view full) --- 757system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Type of FU issued 758system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued 759system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued 760system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued 761system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Type of FU issued 762system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued 763system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued 764system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued |
| 764system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued 765system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued | 765system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued 766system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued |
| 766system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 767system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 767system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 768system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 768system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued 769system.cpu.iq.rate 0.550119 # Inst issue rate 770system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested 771system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst) 772system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads 773system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes 774system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses 775system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads | 769system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued 770system.cpu.iq.rate 0.550285 # Inst issue rate 771system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested 772system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst) 773system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads 774system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes 775system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses 776system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads |
| 776system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes 777system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses | 777system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes 778system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses |
| 778system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses 779system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses 780system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores | 779system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses 780system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses 781system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores |
| 781system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 782system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 782system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed 783system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed 784system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations 785system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed | 783system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed 784system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed 785system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations 786system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed |
| 786system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 787system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 787system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 788system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 788system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled 789system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked | 789system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled 790system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked |
| 790system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 791system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 791system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing 792system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking 793system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking 794system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ | 792system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing 793system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking 794system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking 795system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ |
| 795system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 796system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 796system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions 797system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions 798system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions | 797system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions 798system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions 799system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions |
| 799system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall | 800system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall |
| 800system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall 801system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations 802system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly 803system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly 804system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute 805system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions 806system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed 807system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute | 801system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall 802system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations 803system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly 804system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly 805system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute 806system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions 807system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed 808system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute |
| 808system.cpu.iew.exec_swp 0 # number of swp insts executed | 809system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 809system.cpu.iew.exec_nop 200946 # number of nop insts executed 810system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed 811system.cpu.iew.exec_branches 26532601 # Number of branches executed 812system.cpu.iew.exec_stores 20878795 # Number of stores executed 813system.cpu.iew.exec_rate 0.546502 # Inst execution rate 814system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit 815system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back 816system.cpu.iew.wb_producers 63282838 # num instructions producing a value 817system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value | 810system.cpu.iew.exec_nop 200927 # number of nop insts executed 811system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed 812system.cpu.iew.exec_branches 26544157 # Number of branches executed 813system.cpu.iew.exec_stores 20882594 # Number of stores executed 814system.cpu.iew.exec_rate 0.546668 # Inst execution rate 815system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit 816system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back 817system.cpu.iew.wb_producers 63301722 # num instructions producing a value 818system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value |
| 818system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 819system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 819system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle 820system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back | 820system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle 821system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back |
| 821system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 822system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 822system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit 823system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards 824system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted 825system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle 826system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle 827system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle | 823system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit 824system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards 825system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted 826system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle 827system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle 828system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle |
| 828system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 829system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 829system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle 830system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle 831system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle 832system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle 833system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle 834system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle 835system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle 836system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle 837system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle | 830system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle 831system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle 832system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle 833system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle 834system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle 835system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle 836system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle 837system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle 838system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle |
| 838system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 839system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 840system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 839system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 840system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 841system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 841system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle 842system.cpu.commit.committedInsts 113327248 # Number of instructions committed 843system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed | 842system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle 843system.cpu.commit.committedInsts 113359982 # Number of instructions committed 844system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed |
| 844system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 845system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 845system.cpu.commit.refs 45519928 # Number of memory references committed 846system.cpu.commit.loads 24920655 # Number of loads committed 847system.cpu.commit.membars 814679 # Number of memory barriers committed 848system.cpu.commit.branches 26048896 # Number of branches committed | 846system.cpu.commit.refs 45531388 # Number of memory references committed 847system.cpu.commit.loads 24928306 # Number of loads committed 848system.cpu.commit.membars 814674 # Number of memory barriers committed 849system.cpu.commit.branches 26060542 # Number of branches committed |
| 849system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. | 850system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. |
| 850system.cpu.commit.int_insts 120245785 # Number of committed integer instructions. 851system.cpu.commit.function_calls 4892513 # Number of function calls committed. | 851system.cpu.commit.int_insts 120282409 # Number of committed integer instructions. 852system.cpu.commit.function_calls 4896404 # Number of function calls committed. |
| 852system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 853system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 853system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction 854system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction | 854system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction 855system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction |
| 855system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 856system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 857system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 858system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 859system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 860system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 861system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 862system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 874system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 875system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 876system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 877system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 878system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction 879system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 880system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 881system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction | 856system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 857system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 858system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 859system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 860system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 861system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 862system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 863system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 875system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 876system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 877system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 878system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 879system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # Class of committed instruction 880system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction 881system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 882system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction |
| 882system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction 883system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction | 883system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction 884system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction |
| 884system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 885system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 885system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 886system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 886system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction 887system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached | 887system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction 888system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached |
| 888system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 889system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 889system.cpu.rob.rob_reads 373356629 # The number of ROB reads 890system.cpu.rob.rob_writes 292965429 # The number of ROB writes 891system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself 892system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling 893system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 894system.cpu.committedInsts 113172343 # Number of Instructions Simulated 895system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated 896system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction 897system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads 898system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle 899system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads 900system.cpu.int_regfile_reads 155828809 # number of integer regfile reads 901system.cpu.int_regfile_writes 88634133 # number of integer regfile writes | 890system.cpu.rob.rob_reads 373371044 # The number of ROB reads 891system.cpu.rob.rob_writes 293051212 # The number of ROB writes 892system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself 893system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling 894system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 895system.cpu.committedInsts 113205077 # Number of Instructions Simulated 896system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated 897system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction 898system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads 899system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle 900system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads 901system.cpu.int_regfile_reads 155870959 # number of integer regfile reads 902system.cpu.int_regfile_writes 88663005 # number of integer regfile writes |
| 902system.cpu.fp_regfile_reads 9591 # number of floating regfile reads 903system.cpu.fp_regfile_writes 2716 # number of floating regfile writes | 903system.cpu.fp_regfile_reads 9591 # number of floating regfile reads 904system.cpu.fp_regfile_writes 2716 # number of floating regfile writes |
| 904system.cpu.cc_regfile_reads 503010933 # number of cc regfile reads 905system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes 906system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads 907system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes 908system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution | 905system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads 906system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes 907system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads 908system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes 909system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution |
| 910system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution 911system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution | 911system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution 912system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution |
| 912system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution 913system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution | 913system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution 914system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution 915system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution |
| 915system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution | 916system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution |
| 916system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution 917system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution 919system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes) 920system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes) 921system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes) 922system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes) 923system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes) 929system.cpu.toL2Bus.snoops 65503 # Total snoops (count) 930system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram | 917system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution 918system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution 919system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution 920system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes) 921system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes) 922system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) 923system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes) 924system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes) 925system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes) 927system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) 928system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes) 929system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes) 930system.cpu.toL2Bus.snoops 65488 # Total snoops (count) 931system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram |
| 931system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram 932system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 934system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 932system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram 933system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram 934system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 935system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 936system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 937system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 938system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 939system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 939system.cpu.toL2Bus.snoop_fanout::5 3525536 98.98% 98.98% # Request fanout histogram 940system.cpu.toL2Bus.snoop_fanout::6 36450 1.02% 100.00% # Request fanout histogram | 940system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram |
| 941system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 943system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 942system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 943system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 944system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 944system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram 945system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks) | 945system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram 946system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks) |
| 946system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 947system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 948system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 947system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 948system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 949system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 949system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks) | 950system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks) |
| 950system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 951system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 951system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks) | 952system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks) |
| 952system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 953system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 953system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks) | 954system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) |
| 954system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 955system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 955system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks) | 956system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks) |
| 956system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 957system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 957system.cpu.icache.tags.replacements 1894110 # number of replacements 958system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use 959system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks. 960system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks. 961system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks. | 958system.cpu.icache.tags.replacements 1894038 # number of replacements 959system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use 960system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks. 961system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks. 962system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks. |
| 962system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. | 963system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. |
| 963system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor | 964system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor |
| 964system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy 965system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy 966system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 967system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 968system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 969system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id 970system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 971system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 965system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy 966system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy 967system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 968system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 969system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 970system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id 971system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 972system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 972system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses 973system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses 974system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits 975system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits 976system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits 977system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits 978system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits 979system.cpu.icache.overall_hits::total 64308148 # number of overall hits 980system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses 981system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses 982system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses 983system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses 984system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses 985system.cpu.icache.overall_misses::total 1981542 # number of overall misses 986system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles 987system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles 988system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles 989system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles 990system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles 991system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles 992system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses) 993system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses) 994system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses 995system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses 996system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses 997system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses 998system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses 999system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses 1000system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses 1001system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses 1002system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses 1003system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses 1004system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency 1005system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency 1006system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency 1007system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency 1008system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency 1009system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency 1010system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked | 973system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses 974system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses 975system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits 976system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits 977system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits 978system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits 979system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits 980system.cpu.icache.overall_hits::total 64256715 # number of overall hits 981system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses 982system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses 983system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses 984system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses 985system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses 986system.cpu.icache.overall_misses::total 1981457 # number of overall misses 987system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles 988system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles 989system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles 990system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles 991system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles 992system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles 993system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses) 994system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses) 995system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses 996system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses 997system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses 998system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses 999system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses 1000system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses 1001system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses 1002system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses 1003system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses 1004system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses 1005system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency 1006system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency 1007system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency 1008system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency 1009system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency 1010system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency 1011system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked |
| 1011system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1012system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1012system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked | 1013system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked |
| 1013system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 1014system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 1014system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked | 1015system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked |
| 1015system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1016system.cpu.icache.fast_writes 0 # number of fast writes performed 1017system.cpu.icache.cache_copies 0 # number of cache copies performed | 1016system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1017system.cpu.icache.fast_writes 0 # number of fast writes performed 1018system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 1018system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits 1019system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits 1020system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits 1021system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits 1022system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits 1023system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits 1024system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses 1025system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses 1026system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses 1027system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses 1028system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses 1029system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses 1030system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles 1031system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles 1032system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles 1033system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles 1034system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles 1035system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles 1036system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles 1037system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles 1038system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles 1039system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles 1040system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses 1041system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses 1042system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses 1043system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses 1044system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses 1045system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses 1046system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency 1047system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency 1048system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency 1049system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency 1050system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency 1051system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency | 1019system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits 1020system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits 1021system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits 1022system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits 1023system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits 1024system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits 1025system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses 1026system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses 1027system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses 1028system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses 1029system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses 1030system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses 1031system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles 1032system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles 1033system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles 1034system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles 1035system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles 1036system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles 1037system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles 1038system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles 1039system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles 1040system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles 1041system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses 1042system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses 1043system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses 1044system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses 1045system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses 1046system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses 1047system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency 1048system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency 1049system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency 1050system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency 1051system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency 1052system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency |
| 1052system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1053system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1054system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1055system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1056system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1053system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1054system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1055system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1056system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1057system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1057system.cpu.l2cache.tags.replacements 98637 # number of replacements 1058system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use 1059system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks. 1060system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks. 1061system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks. | 1058system.cpu.l2cache.tags.replacements 98619 # number of replacements 1059system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use 1060system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks. 1061system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. 1062system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks. |
| 1062system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1063system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1063system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor 1064system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor | 1064system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor 1065system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor |
| 1065system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor | 1066system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor |
| 1066system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor 1067system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor 1068system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy | 1067system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor 1068system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor 1069system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy |
| 1069system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy 1070system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy | 1070system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy 1071system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy |
| 1071system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy 1072system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy | 1072system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy 1073system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy |
| 1073system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy 1074system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1075system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id 1076system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1077system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 1078system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id | 1074system.cpu.l2cache.tags.occ_percent::total 0.993008 # Average percentage of cache occupancy 1075system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1076system.cpu.l2cache.tags.occ_task_id_blocks::1024 65200 # Occupied blocks per task id 1077system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1078system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 1079system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id |
| 1079system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id 1080system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id 1081system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id | 1080system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id 1081system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id 1082system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id |
| 1082system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1083system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id | 1083system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1084system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id |
| 1084system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses 1085system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses 1086system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits 1087system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits 1088system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits 1089system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits 1090system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits 1091system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits 1092system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits | 1085system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses 1086system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses 1087system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits 1088system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits 1089system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits 1090system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits 1091system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits 1092system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits 1093system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits |
| 1093system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits 1094system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits 1095system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1096system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits | 1094system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits 1095system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits 1096system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits 1097system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits |
| 1097system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits 1098system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits 1099system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits 1100system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits 1101system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits 1102system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits 1103system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits 1104system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits 1105system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits 1106system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits 1107system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits 1108system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits | 1098system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits 1099system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits 1100system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits 1101system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits 1102system.cpu.l2cache.demand_hits::cpu.inst 1874571 # number of demand (read+write) hits 1103system.cpu.l2cache.demand_hits::cpu.data 687724 # number of demand (read+write) hits 1104system.cpu.l2cache.demand_hits::total 2627795 # number of demand (read+write) hits 1105system.cpu.l2cache.overall_hits::cpu.dtb.walker 53840 # number of overall hits 1106system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits 1107system.cpu.l2cache.overall_hits::cpu.inst 1874571 # number of overall hits 1108system.cpu.l2cache.overall_hits::cpu.data 687724 # number of overall hits 1109system.cpu.l2cache.overall_hits::total 2627795 # number of overall hits |
| 1109system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1110system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses | 1110system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1111system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses |
| 1111system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses 1112system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses 1113system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses 1114system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses 1115system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses | 1112system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses 1113system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses 1114system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses 1115system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses 1116system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses |
| 1116system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1117system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1118system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses 1119system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses 1120system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1121system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses | 1117system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1118system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1119system.cpu.l2cache.ReadExReq_misses::cpu.data 136937 # number of ReadExReq misses 1120system.cpu.l2cache.ReadExReq_misses::total 136937 # number of ReadExReq misses 1121system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1122system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses |
| 1122system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses 1123system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses 1124system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses | 1123system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses 1124system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses 1125system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses |
| 1125system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1126system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses | 1126system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1127system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses |
| 1127system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses 1128system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses 1129system.cpu.l2cache.overall_misses::total 170566 # number of overall misses 1130system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles | 1128system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses 1129system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses 1130system.cpu.l2cache.overall_misses::total 170549 # number of overall misses 1131system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles |
| 1131system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles | 1132system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536250 # number of ReadReq miss cycles |
| 1132system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles 1133system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles 1134system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles | 1133system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1500107250 # number of ReadReq miss cycles 1134system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078643000 # number of ReadReq miss cycles 1135system.cpu.l2cache.ReadReq_miss_latency::total 2580745000 # number of ReadReq miss cycles |
| 1135system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles 1136system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles 1137system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles 1138system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles | 1136system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 582975 # number of UpgradeReq miss cycles 1137system.cpu.l2cache.UpgradeReq_miss_latency::total 582975 # number of UpgradeReq miss cycles 1138system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 46498 # number of SCUpgradeReq miss cycles 1139system.cpu.l2cache.SCUpgradeReq_miss_latency::total 46498 # number of SCUpgradeReq miss cycles |
| 1139system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles 1140system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles 1141system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles | 1140system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9922806190 # number of ReadExReq miss cycles 1141system.cpu.l2cache.ReadExReq_miss_latency::total 9922806190 # number of ReadExReq miss cycles 1142system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles |
| 1142system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles | 1143system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536250 # number of demand (read+write) miss cycles |
| 1143system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles 1144system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles 1145system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles 1146system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles | 1144system.cpu.l2cache.demand_miss_latency::cpu.inst 1500107250 # number of demand (read+write) miss cycles 1145system.cpu.l2cache.demand_miss_latency::cpu.data 11001449190 # number of demand (read+write) miss cycles 1146system.cpu.l2cache.demand_miss_latency::total 12503551190 # number of demand (read+write) miss cycles 1147system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles |
| 1147system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles | 1148system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536250 # number of overall miss cycles |
| 1148system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles 1149system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles 1150system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles 1151system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses) 1152system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses) 1153system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses) 1154system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses) 1155system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses) 1156system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses) 1157system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses) 1158system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses) 1159system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses) | 1149system.cpu.l2cache.overall_miss_latency::cpu.inst 1500107250 # number of overall miss cycles 1150system.cpu.l2cache.overall_miss_latency::cpu.data 11001449190 # number of overall miss cycles 1151system.cpu.l2cache.overall_miss_latency::total 12503551190 # number of overall miss cycles 1152system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53859 # number of ReadReq accesses(hits+misses) 1153system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses) 1154system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894537 # number of ReadReq accesses(hits+misses) 1155system.cpu.l2cache.ReadReq_accesses::cpu.data 541656 # number of ReadReq accesses(hits+misses) 1156system.cpu.l2cache.ReadReq_accesses::total 2501719 # number of ReadReq accesses(hits+misses) 1157system.cpu.l2cache.Writeback_accesses::writebacks 695414 # number of Writeback accesses(hits+misses) 1158system.cpu.l2cache.Writeback_accesses::total 695414 # number of Writeback accesses(hits+misses) 1159system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses) 1160system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses) |
| 1160system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1161system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) | 1161system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1162system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) |
| 1162system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses) 1163system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses) 1164system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses 1165system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses 1166system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses 1167system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses 1168system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses 1169system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses 1170system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses 1171system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses 1172system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses 1173system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses | 1163system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses) 1164system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses) 1165system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53859 # number of demand (read+write) accesses 1166system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses 1167system.cpu.l2cache.demand_accesses::cpu.inst 1894537 # number of demand (read+write) accesses 1168system.cpu.l2cache.demand_accesses::cpu.data 838281 # number of demand (read+write) accesses 1169system.cpu.l2cache.demand_accesses::total 2798344 # number of demand (read+write) accesses 1170system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53859 # number of overall (read+write) accesses 1171system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses 1172system.cpu.l2cache.overall_accesses::cpu.inst 1894537 # number of overall (read+write) accesses 1173system.cpu.l2cache.overall_accesses::cpu.data 838281 # number of overall (read+write) accesses 1174system.cpu.l2cache.overall_accesses::total 2798344 # number of overall (read+write) accesses |
| 1174system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses 1175system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses | 1175system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000353 # miss rate for ReadReq accesses 1176system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000600 # miss rate for ReadReq accesses |
| 1176system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses 1177system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses 1178system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses 1179system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses 1180system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses | 1177system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses 1178system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses 1179system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses 1180system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses 1181system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses |
| 1181system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1182system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses | 1182system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses 1183system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses |
| 1183system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses 1184system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses | 1184system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses 1185system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses |
| 1185system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses 1186system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses | 1186system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000353 # miss rate for demand accesses 1187system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000600 # miss rate for demand accesses |
| 1187system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses 1188system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses 1189system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses | 1188system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses 1189system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses 1190system.cpu.l2cache.demand_miss_rate::total 0.060946 # miss rate for demand accesses |
| 1190system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses 1191system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses | 1191system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000353 # miss rate for overall accesses 1192system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000600 # miss rate for overall accesses |
| 1192system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses 1193system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses 1194system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses 1195system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency | 1193system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses 1194system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses 1195system.cpu.l2cache.overall_miss_rate::total 0.060946 # miss rate for overall accesses 1196system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency |
| 1196system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency | 1197system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76607.142857 # average ReadReq miss latency |
| 1197system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency 1198system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency 1199system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency 1200system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency 1201system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency | 1198system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75133.088751 # average ReadReq miss latency 1199system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79195.521292 # average ReadReq miss latency 1200system.cpu.l2cache.ReadReq_avg_miss_latency::total 76780.465310 # average ReadReq miss latency 1201system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency 1202system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency |
| 1202system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency 1203system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency | 1203system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23249 # average SCUpgradeReq miss latency 1204system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23249 # average SCUpgradeReq miss latency |
| 1204system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency 1205system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency 1206system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency | 1205system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72462.564464 # average ReadExReq miss latency 1206system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72462.564464 # average ReadExReq miss latency 1207system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency |
| 1207system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency | 1208system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency |
| 1208system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency 1209system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency 1210system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency 1211system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency | 1209system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency 1210system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency 1211system.cpu.l2cache.demand_avg_miss_latency::total 73313.541504 # average overall miss latency 1212system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency |
| 1212system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency | 1213system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76607.142857 # average overall miss latency |
| 1213system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency 1214system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency 1215system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency | 1214system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency 1215system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency 1216system.cpu.l2cache.overall_avg_miss_latency::total 73313.541504 # average overall miss latency |
| 1216system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1217system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1218system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1219system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1220system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1221system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1222system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1223system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1217system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1218system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1219system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1220system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1221system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1222system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1223system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1224system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1224system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks 1225system.cpu.l2cache.writebacks::total 90641 # number of writebacks | 1225system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks 1226system.cpu.l2cache.writebacks::total 90626 # number of writebacks |
| 1226system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits 1227system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits 1228system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits 1229system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1230system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits 1231system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits 1232system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits 1233system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits 1234system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits 1235system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses 1236system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses | 1227system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits 1228system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits 1229system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits 1230system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits 1231system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits 1232system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits 1233system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits 1234system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits 1235system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits 1236system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses 1237system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses |
| 1237system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses 1238system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses 1239system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses 1240system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses 1241system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses | 1238system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19941 # number of ReadReq MSHR misses 1239system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13508 # number of ReadReq MSHR misses 1240system.cpu.l2cache.ReadReq_mshr_misses::total 33475 # number of ReadReq MSHR misses 1241system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2733 # number of UpgradeReq MSHR misses 1242system.cpu.l2cache.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses |
| 1242system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1243system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1244system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses 1245system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses 1246system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1247system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses | 1243system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1244system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1245system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136937 # number of ReadExReq MSHR misses 1246system.cpu.l2cache.ReadExReq_mshr_misses::total 136937 # number of ReadExReq MSHR misses 1247system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1248system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses |
| 1248system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses 1249system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses 1250system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses | 1249system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses 1250system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses 1251system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses |
| 1251system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1252system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses | 1252system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1253system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses |
| 1253system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses 1254system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses 1255system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses 1256system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles | 1254system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses 1255system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses 1256system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses 1257system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles |
| 1257system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles | 1258system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles |
| 1258system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles 1259system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles 1260system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles 1261system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles 1262system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles | 1259system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1248209500 # number of ReadReq MSHR miss cycles 1260system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902938000 # number of ReadReq MSHR miss cycles 1261system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152822250 # number of ReadReq MSHR miss cycles 1262system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles 1263system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles |
| 1263system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 1264system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles | 1264system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 1265system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles |
| 1265system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles 1266system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles 1267system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles | 1266system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8209305810 # number of ReadExReq MSHR miss cycles 1267system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8209305810 # number of ReadExReq MSHR miss cycles 1268system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles |
| 1268system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles | 1269system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles |
| 1269system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles 1270system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles 1271system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles 1272system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles | 1270system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1248209500 # number of demand (read+write) MSHR miss cycles 1271system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112243810 # number of demand (read+write) MSHR miss cycles 1272system.cpu.l2cache.demand_mshr_miss_latency::total 10362128060 # number of demand (read+write) MSHR miss cycles 1273system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles |
| 1273system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles | 1274system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles |
| 1274system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles 1275system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles 1276system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles 1277system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles 1278system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles 1279system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles 1280system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles 1281system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles 1282system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles 1283system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles 1284system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles | 1275system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1248209500 # number of overall MSHR miss cycles 1276system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112243810 # number of overall MSHR miss cycles 1277system.cpu.l2cache.overall_mshr_miss_latency::total 10362128060 # number of overall MSHR miss cycles 1278system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles 1279system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387481250 # number of ReadReq MSHR uncacheable cycles 1280system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545358250 # number of ReadReq MSHR uncacheable cycles 1281system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles 1282system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles 1283system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles 1284system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494822250 # number of overall MSHR uncacheable cycles 1285system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652699250 # number of overall MSHR uncacheable cycles |
| 1285system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses 1286system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses | 1286system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for ReadReq accesses 1287system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for ReadReq accesses |
| 1287system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses 1288system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses 1289system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses 1290system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses 1291system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses | 1288system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses 1289system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses 1290system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses 1291system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses 1292system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses |
| 1292system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1293system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses | 1293system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses 1294system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses |
| 1294system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses 1295system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses | 1295system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses 1296system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses |
| 1296system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses 1297system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses | 1297system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for demand accesses 1298system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for demand accesses |
| 1298system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses 1299system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses 1300system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses | 1299system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses 1300system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for demand accesses 1301system.cpu.l2cache.demand_mshr_miss_rate::total 0.060897 # mshr miss rate for demand accesses |
| 1301system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses 1302system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses | 1302system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000353 # mshr miss rate for overall accesses 1303system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000600 # mshr miss rate for overall accesses |
| 1303system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses 1304system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses 1305system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses 1306system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency | 1304system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses 1305system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for overall accesses 1306system.cpu.l2cache.overall_mshr_miss_rate::total 0.060897 # mshr miss rate for overall accesses 1307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency |
| 1307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency | 1308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency |
| 1308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency 1309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency 1310system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency 1311system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency 1312system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency | 1309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62595.130635 # average ReadReq mshr miss latency 1310system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66844.684631 # average ReadReq mshr miss latency 1311system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64311.344287 # average ReadReq mshr miss latency 1312system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency 1313system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency |
| 1313system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1314system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency | 1314system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1315system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency |
| 1315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency 1316system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency 1317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency | 1316system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency 1317system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency 1318system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency |
| 1318system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency | 1319system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency |
| 1319system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency 1320system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency 1321system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency 1322system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency | 1320system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency 1321system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency 1322system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency 1323system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency |
| 1323system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency | 1324system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency |
| 1324system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency 1325system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency 1326system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency | 1325system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency 1326system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency 1327system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency |
| 1327system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1328system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1329system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1330system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1331system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1332system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1333system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1334system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1335system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1328system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1329system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1330system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1331system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1332system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1333system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1334system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1335system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1336system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1336system.cpu.dcache.tags.replacements 837784 # number of replacements 1337system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use 1338system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks. 1339system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks. 1340system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks. 1341system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit. 1342system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor | 1337system.cpu.dcache.tags.replacements 837746 # number of replacements 1338system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use 1339system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks. 1340system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks. 1341system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks. 1342system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. 1343system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor |
| 1343system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy 1344system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy 1345system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1346system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1347system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 1348system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 1349system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1344system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy 1345system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy 1346system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1347system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 1348system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id 1349system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 1350system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1350system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses 1351system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses 1352system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits 1353system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits 1354system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits 1355system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits 1356system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits 1357system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits 1358system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits 1359system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits 1360system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits 1361system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits 1362system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits 1363system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits 1364system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits 1365system.cpu.dcache.overall_hits::total 39254192 # number of overall hits 1366system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses 1367system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses 1368system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses 1369system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses 1370system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses 1371system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses 1372system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses 1373system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses | 1351system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses 1352system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses 1353system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits 1354system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits 1355system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits 1356system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits 1357system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits 1358system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits 1359system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits 1360system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits 1361system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits 1362system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits 1363system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits 1364system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits 1365system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits 1366system.cpu.dcache.overall_hits::total 39265074 # number of overall hits 1367system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses 1368system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses 1369system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses 1370system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses 1371system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses 1372system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses 1373system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses 1374system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses |
| 1374system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 1375system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses | 1375system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 1376system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses |
| 1376system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses 1377system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses 1378system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses 1379system.cpu.dcache.overall_misses::total 4450997 # number of overall misses 1380system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles 1381system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles 1382system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles 1383system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles 1384system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles 1385system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles | 1377system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses 1378system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses 1379system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses 1380system.cpu.dcache.overall_misses::total 4451402 # number of overall misses 1381system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles 1382system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles 1383system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles 1384system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles 1385system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles 1386system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles |
| 1386system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles 1387system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles | 1387system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles 1388system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles |
| 1388system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles 1389system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles 1390system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles 1391system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles 1392system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses) 1393system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses) 1394system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses) 1395system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses) 1396system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses) 1397system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses) 1398system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses) 1399system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses) 1400system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses) 1401system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses) 1402system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses 1403system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses 1404system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses 1405system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses 1406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses 1407system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses 1408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses 1409system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses | 1389system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles 1390system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles 1391system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles 1392system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles 1393system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses) 1394system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses) 1395system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses) 1396system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses) 1397system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) 1398system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) 1399system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) 1400system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) 1401system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) 1402system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) 1403system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses 1404system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses 1405system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses 1406system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses 1407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses 1408system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses 1409system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses 1410system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses |
| 1410system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses 1411system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses | 1411system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses 1412system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses |
| 1412system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses 1413system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses | 1413system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses 1414system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses |
| 1414system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 1415system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses | 1415system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 1416system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses |
| 1416system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses 1417system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses 1418system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses 1419system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses 1420system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency 1421system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency 1422system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency 1423system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency 1424system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency 1425system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency | 1417system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses 1418system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses 1419system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses 1420system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses 1421system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency 1422system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency 1423system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency 1424system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency 1425system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency 1426system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency |
| 1426system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency 1427system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency | 1427system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency 1428system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency |
| 1428system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency 1429system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency 1430system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency 1431system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency 1432system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked | 1429system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency 1430system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency 1431system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency 1432system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency 1433system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked |
| 1433system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1434system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1434system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked | 1435system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked |
| 1435system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 1436system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 1436system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked | 1437system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked |
| 1437system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1438system.cpu.dcache.fast_writes 0 # number of fast writes performed 1439system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1438system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1439system.cpu.dcache.fast_writes 0 # number of fast writes performed 1440system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1440system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks 1441system.cpu.dcache.writebacks::total 695424 # number of writebacks 1442system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits 1443system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits 1444system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits 1445system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits | 1441system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks 1442system.cpu.dcache.writebacks::total 695414 # number of writebacks 1443system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits 1444system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits 1445system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits 1446system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits |
| 1446system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits 1447system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits | 1447system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits 1448system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits |
| 1448system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits 1449system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits 1450system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits 1451system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits 1452system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses 1453system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses 1454system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses 1455system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses | 1449system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits 1450system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits 1451system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits 1452system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits 1453system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses 1454system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses 1455system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses 1456system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses |
| 1456system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses 1457system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses | 1457system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses 1458system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses |
| 1458system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses 1459system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses | 1459system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses 1460system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses |
| 1460system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 1461system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses | 1461system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 1462system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses |
| 1462system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses 1463system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses 1464system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses 1465system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses 1466system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles 1467system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles 1468system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles 1469system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles 1470system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles 1471system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles 1472system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles 1473system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles | 1463system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses 1464system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses 1465system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses 1466system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses 1467system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles 1468system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles 1469system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles 1470system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles 1471system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles 1472system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles 1473system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles 1474system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles |
| 1474system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles 1475system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles | 1475system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles 1476system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles |
| 1476system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles 1477system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles 1478system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles 1479system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles 1480system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles 1481system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles 1482system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles 1483system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles 1484system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles 1485system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles 1486system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses 1487system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses 1488system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses 1489system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses 1490system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses 1491system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses 1492system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses 1493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses | 1477system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles 1478system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles 1479system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles 1480system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles 1481system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles 1482system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles 1483system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles 1484system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles 1485system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles 1486system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles 1487system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses 1488system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses 1489system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses 1490system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses 1491system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses 1492system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses 1493system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses 1494system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses |
| 1494system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1495system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses | 1495system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1496system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses |
| 1496system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses 1497system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses 1498system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses 1499system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses 1500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency 1501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency 1502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency 1503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency 1504system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency 1505system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency 1506system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency 1507system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency | 1497system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses 1498system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses 1499system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses 1500system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses 1501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency 1502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency 1503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency 1504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency 1505system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency 1506system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency 1507system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency 1508system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency |
| 1508system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency 1509system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency | 1509system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency 1510system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency |
| 1510system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency 1511system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency 1512system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency 1513system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency | 1511system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency 1512system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency 1513system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency 1514system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency |
| 1514system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1515system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1516system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1517system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1518system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1519system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1520system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1521system.iocache.tags.replacements 36410 # number of replacements | 1515system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1516system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1517system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1518system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1519system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1520system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1521system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1522system.iocache.tags.replacements 36410 # number of replacements |
| 1522system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use | 1523system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use |
| 1523system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1524system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. 1525system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1526system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. | 1524system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1525system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. 1526system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1527system.iocache.tags.warmup_cycle 251942463000 # Cycle when the warmup percentage was hit. |
| 1527system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor | 1528system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor |
| 1528system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy 1529system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy 1530system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1531system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1532system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1529system.iocache.tags.occ_percent::realview.ide 0.062480 # Average percentage of cache occupancy 1530system.iocache.tags.occ_percent::total 0.062480 # Average percentage of cache occupancy 1531system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1532system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1533system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1533system.iocache.tags.tag_accesses 328020 # Number of tag accesses 1534system.iocache.tags.data_accesses 328020 # Number of data accesses | 1534system.iocache.tags.tag_accesses 327996 # Number of tag accesses 1535system.iocache.tags.data_accesses 327996 # Number of data accesses |
| 1535system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1536system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1537system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1538system.iocache.ReadReq_misses::total 220 # number of ReadReq misses | 1536system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1537system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1538system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses 1539system.iocache.ReadReq_misses::total 220 # number of ReadReq misses |
| 1539system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses 1540system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses | |
| 1541system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses 1542system.iocache.demand_misses::total 220 # number of demand (read+write) misses 1543system.iocache.overall_misses::realview.ide 220 # number of overall misses 1544system.iocache.overall_misses::total 220 # number of overall misses | 1540system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses 1541system.iocache.demand_misses::total 220 # number of demand (read+write) misses 1542system.iocache.overall_misses::realview.ide 220 # number of overall misses 1543system.iocache.overall_misses::total 220 # number of overall misses |
| 1545system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles 1546system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles 1547system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles 1548system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles 1549system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles 1550system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles | 1544system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles 1545system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles 1546system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles 1547system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles 1548system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles 1549system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles |
| 1551system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1552system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) | 1550system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) 1551system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) |
| 1553system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses) 1554system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses) | 1552system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1553system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) |
| 1555system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses 1556system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses 1557system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses 1558system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses 1559system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1560system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 1554system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses 1555system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses 1556system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses 1557system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses 1558system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1559system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 1561system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses 1562system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses | |
| 1563system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1564system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1565system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1566system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1560system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1561system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1562system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1563system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1567system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency 1568system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency 1569system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency 1570system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency 1571system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency 1572system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency | 1564system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency 1565system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency 1566system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency 1567system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency 1568system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency 1569system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency |
| 1573system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1574system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1575system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1576system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1577system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1578system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1579system.iocache.fast_writes 36224 # number of fast writes performed 1580system.iocache.cache_copies 0 # number of cache copies performed 1581system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1582system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses 1583system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses 1584system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses 1585system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses 1586system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses | 1570system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1571system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1572system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1573system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1574system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1575system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1576system.iocache.fast_writes 36224 # number of fast writes performed 1577system.iocache.cache_copies 0 # number of cache copies performed 1578system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses 1579system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses 1580system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses 1581system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses 1582system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses 1583system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses |
| 1587system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles 1588system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles 1589system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles 1590system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles 1591system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles 1592system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles 1593system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles 1594system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles | 1584system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles 1585system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles 1586system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles 1587system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles 1588system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles 1589system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles 1590system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles 1591system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles |
| 1595system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1596system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1597system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1598system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1599system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1600system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1592system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1593system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1594system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1595system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1596system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1597system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1601system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency 1602system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency | 1598system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency 1599system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency |
| 1603system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1604system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency | 1600system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1601system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 1605system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency 1606system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency 1607system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency 1608system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency | 1602system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency 1603system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency 1604system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency 1605system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency |
| 1609system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1610system.cpu.kern.inst.arm 0 # number of arm instructions executed 1611system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed 1612 1613---------- End Simulation Statistics ---------- | 1606system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1607system.cpu.kern.inst.arm 0 # number of arm instructions executed 1608system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed 1609 1610---------- End Simulation Statistics ---------- |