| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.542203 # Number of seconds simulated 4sim_ticks 2542202956000 # Number of ticks simulated 5final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.542157 # Number of seconds simulated 4sim_ticks 2542156879500 # Number of ticks simulated 5final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 47189 # Simulator instruction rate (inst/s) 8host_op_rate 56852 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1989066585 # Simulator tick rate (ticks/s) 10host_mem_usage 412724 # Number of bytes of host memory used 11host_seconds 1278.09 # Real time elapsed on the host 12sim_insts 60311945 # Number of instructions simulated 13sim_ops 72661478 # Number of ops (including micro ops) simulated | 7host_inst_rate 53622 # Simulator instruction rate (inst/s) 8host_op_rate 64601 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2260157205 # Simulator tick rate (ticks/s) 10host_mem_usage 463148 # Number of bytes of host memory used 11host_seconds 1124.77 # Real time elapsed on the host 12sim_insts 60311972 # Number of instructions simulated 13sim_ops 72661518 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory 21system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory | 19system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory 21system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory |
| 24system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory | 24system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory |
| 33system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory | 33system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15295607 # Number of read requests accepted | 51system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15295608 # Number of read requests accepted |
| 55system.physmem.writeReqs 812506 # Number of write requests accepted | 55system.physmem.writeReqs 812506 # Number of write requests accepted |
| 56system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue | 56system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue |
| 57system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue | 57system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue |
| 58system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side | 58system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side |
| 62system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side | 62system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side |
| 63system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one | 63system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write | 65system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write |
| 66system.physmem.perBankRdBursts::0 955786 # Per bank write bursts | 66system.physmem.perBankRdBursts::0 955787 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::1 955478 # Per bank write bursts | 67system.physmem.perBankRdBursts::1 955478 # Per bank write bursts |
| 68system.physmem.perBankRdBursts::2 953003 # Per bank write bursts 69system.physmem.perBankRdBursts::3 951059 # Per bank write bursts 70system.physmem.perBankRdBursts::4 958601 # Per bank write bursts 71system.physmem.perBankRdBursts::5 955602 # Per bank write bursts 72system.physmem.perBankRdBursts::6 952653 # Per bank write bursts 73system.physmem.perBankRdBursts::7 950407 # Per bank write bursts 74system.physmem.perBankRdBursts::8 956154 # Per bank write bursts | 68system.physmem.perBankRdBursts::2 953511 # Per bank write bursts 69system.physmem.perBankRdBursts::3 951566 # Per bank write bursts 70system.physmem.perBankRdBursts::4 958612 # Per bank write bursts 71system.physmem.perBankRdBursts::5 955530 # Per bank write bursts 72system.physmem.perBankRdBursts::6 953056 # Per bank write bursts 73system.physmem.perBankRdBursts::7 951020 # Per bank write bursts 74system.physmem.perBankRdBursts::8 956158 # Per bank write bursts |
| 75system.physmem.perBankRdBursts::9 955874 # Per bank write bursts | 75system.physmem.perBankRdBursts::9 955874 # Per bank write bursts |
| 76system.physmem.perBankRdBursts::10 952889 # Per bank write bursts 77system.physmem.perBankRdBursts::11 950148 # Per bank write bursts | 76system.physmem.perBankRdBursts::10 952686 # Per bank write bursts 77system.physmem.perBankRdBursts::11 950200 # Per bank write bursts |
| 78system.physmem.perBankRdBursts::12 956166 # Per bank write bursts 79system.physmem.perBankRdBursts::13 955918 # Per bank write bursts | 78system.physmem.perBankRdBursts::12 956166 # Per bank write bursts 79system.physmem.perBankRdBursts::13 955918 # Per bank write bursts |
| 80system.physmem.perBankRdBursts::14 953918 # Per bank write bursts 81system.physmem.perBankRdBursts::15 950940 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6546 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6352 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6488 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6518 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6421 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6701 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6665 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6611 # Per bank write bursts 90system.physmem.perBankWrBursts::8 6966 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6759 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6421 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6055 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7037 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6645 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6920 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6806 # Per bank write bursts | 80system.physmem.perBankRdBursts::14 953812 # Per bank write bursts 81system.physmem.perBankRdBursts::15 951254 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6556 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6344 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6481 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6512 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6422 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6709 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6691 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6631 # Per bank write bursts 90system.physmem.perBankWrBursts::8 6968 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6764 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6424 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6068 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7033 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6638 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6915 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6799 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 100system.physmem.totGap 2542201638000 # Total gap between requests | 100system.physmem.totGap 2542155562500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 18 # Read request sizes (log2) 104system.physmem.readPktSize::3 15138826 # Read request sizes (log2) 105system.physmem.readPktSize::4 3351 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 18 # Read request sizes (log2) 104system.physmem.readPktSize::3 15138826 # Read request sizes (log2) 105system.physmem.readPktSize::4 3351 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 153412 # Read request sizes (log2) | 107system.physmem.readPktSize::6 153413 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 58488 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 58488 # Write request sizes (log2) |
| 115system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see | 115system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see |
| 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see |
| 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 211system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes | 211system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 232system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads 248system.physmem.totQLat 395449280750 # Total ticks spent queuing 249system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst | 232system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads 251system.physmem.totQLat 395458190750 # Total ticks spent queuing 252system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst |
| 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 253system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s | 256system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s |
| 255system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 256system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s 257system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 3.02 # Data bus utilization in percentage 260system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 258system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 3.02 # Data bus utilization in percentage 263system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 262system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing 264system.physmem.readRowHits 14269193 # Number of row buffer hits during reads 265system.physmem.writeRowHits 90708 # Number of row buffer hits during writes | 265system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing 266system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing 267system.physmem.readRowHits 14271218 # Number of row buffer hits during reads 268system.physmem.writeRowHits 90719 # Number of row buffer hits during writes |
| 266system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads | 269system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads |
| 267system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes 268system.physmem.avgGap 157821.19 # Average gap between requests 269system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined 270system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states 271system.physmem.memoryStateTime::REF 84889480000 # Time in different power states | 270system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes 271system.physmem.avgGap 157818.32 # Average gap between requests 272system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined 273system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states 274system.physmem.memoryStateTime::REF 84888180000 # Time in different power states |
| 272system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 275system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 273system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states | 276system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states |
| 274system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory 276system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory 277system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory 278system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory 279system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory 280system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory 281system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) 282system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) 283system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) 284system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) 285system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) 286system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) | 277system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 278system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory 279system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory 280system.realview.nvmem.bytes_inst_read::cpu.inst 48 # Number of instructions bytes read from this memory 281system.realview.nvmem.bytes_inst_read::total 48 # Number of instructions bytes read from this memory 282system.realview.nvmem.num_reads::cpu.inst 3 # Number of read requests responded to by this memory 283system.realview.nvmem.num_reads::total 3 # Number of read requests responded to by this memory 284system.realview.nvmem.bw_read::cpu.inst 19 # Total read bandwidth from this memory (bytes/s) 285system.realview.nvmem.bw_read::total 19 # Total read bandwidth from this memory (bytes/s) 286system.realview.nvmem.bw_inst_read::cpu.inst 19 # Instruction read bandwidth from this memory (bytes/s) 287system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) 288system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) 289system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) |
| 287system.membus.throughput 55125441 # Throughput (bytes/s) 288system.membus.trans_dist::ReadReq 16348039 # Transaction distribution 289system.membus.trans_dist::ReadResp 16348039 # Transaction distribution | 290system.membus.trans_dist::ReadReq 16348037 # Transaction distribution 291system.membus.trans_dist::ReadResp 16348037 # Transaction distribution |
| 290system.membus.trans_dist::WriteReq 763357 # Transaction distribution 291system.membus.trans_dist::WriteResp 763357 # Transaction distribution 292system.membus.trans_dist::Writeback 58488 # Transaction distribution 293system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution 294system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution | 292system.membus.trans_dist::WriteReq 763357 # Transaction distribution 293system.membus.trans_dist::WriteResp 763357 # Transaction distribution 294system.membus.trans_dist::Writeback 58488 # Transaction distribution 295system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution 296system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution |
| 295system.membus.trans_dist::ReadExReq 131651 # Transaction distribution 296system.membus.trans_dist::ReadExResp 131651 # Transaction distribution | 297system.membus.trans_dist::ReadExReq 131654 # Transaction distribution 298system.membus.trans_dist::ReadExResp 131654 # Transaction distribution |
| 297system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) 298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) | 303system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) |
| 303system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) | 305system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) |
| 305system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) 306system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) 307system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) 309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) 315system.membus.data_through_bus 140140058 # Total data (bytes) 316system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 317system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) | 307system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) 308system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) 309system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) 310system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) 311system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 312system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) 313system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) 314system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) 315system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) 316system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) 317system.membus.snoops 0 # Total snoops (count) 318system.membus.snoop_fanout::samples 216513 # Request fanout histogram 319system.membus.snoop_fanout::mean 1 # Request fanout histogram 320system.membus.snoop_fanout::stdev 0 # Request fanout histogram 321system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 322system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 323system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram 324system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 325system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 326system.membus.snoop_fanout::min_value 1 # Request fanout histogram 327system.membus.snoop_fanout::max_value 1 # Request fanout histogram 328system.membus.snoop_fanout::total 216513 # Request fanout histogram 329system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) |
| 318system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 319system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) 320system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 330system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 331system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) 332system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 321system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) | 333system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) |
| 322system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 323system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 324system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) | 334system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 335system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 336system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 325system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) | 337system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) |
| 326system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) | 338system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) |
| 327system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) | 339system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) |
| 328system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 340system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 329system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) | 341system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) |
| 330system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 336system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 342system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 343system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 344system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 345system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 346system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 347system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 348system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 337system.iobus.throughput 48580309 # Throughput (bytes/s) | |
| 338system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution 339system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution 340system.iobus.trans_dist::WriteReq 8176 # Transaction distribution 341system.iobus.trans_dist::WriteResp 8176 # Transaction distribution 342system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 343system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 361system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) | 349system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution 350system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution 351system.iobus.trans_dist::WriteReq 8176 # Transaction distribution 352system.iobus.trans_dist::WriteResp 8176 # Transaction distribution 353system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 372system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 373system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 374system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 375system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 376system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) 377system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) 378system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) 379system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) |
| 369system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.data_through_bus 123501006 # Total data (bytes) | 380system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 398system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 399system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 400system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 401system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 402system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 403system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) 404system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) 405system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) 406system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) |
| 397system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 398system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 399system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) 400system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 401system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) 402system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 403system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) 404system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 30 unchanged lines hidden (view full) --- 435system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 436system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 437system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 438system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 439system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 440system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 441system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 442system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 407system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 408system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 409system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) 410system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 411system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) 412system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 413system.iobus.reqLayer3.occupancy 520000 # Layer occupancy (ticks) 414system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 30 unchanged lines hidden (view full) --- 445system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 446system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 447system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 448system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 449system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 450system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 451system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 452system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 443system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) 444system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) | 453system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) 454system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) |
| 445system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) 446system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 455system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) 456system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 447system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) | 457system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) |
| 448system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 449system.cpu_clk_domain.clock 500 # Clock period in ticks | 458system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 459system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 450system.cpu.branchPred.lookups 13201290 # Number of BP lookups 451system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted 452system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect 453system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups 454system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits | 460system.cpu.branchPred.lookups 13200672 # Number of BP lookups 461system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted 462system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect 463system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups 464system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits |
| 455system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 465system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 456system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage 457system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. 458system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. | 466system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage 467system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. 468system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. |
| 459system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 460system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 461system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 462system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 463system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 464system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 465system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 466system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 474system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 475system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 476system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 477system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 478system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 479system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 480system.cpu.dtb.inst_hits 0 # ITB inst hits 481system.cpu.dtb.inst_misses 0 # ITB inst misses | 469system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 470system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 471system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 472system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 473system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 474system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 475system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 476system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 484system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 485system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 486system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 487system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 488system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 489system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 490system.cpu.dtb.inst_hits 0 # ITB inst hits 491system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 482system.cpu.dtb.read_hits 31642294 # DTB read hits 483system.cpu.dtb.read_misses 39524 # DTB read misses 484system.cpu.dtb.write_hits 11381361 # DTB write hits 485system.cpu.dtb.write_misses 10135 # DTB write misses | 492system.cpu.dtb.read_hits 31644036 # DTB read hits 493system.cpu.dtb.read_misses 39518 # DTB read misses 494system.cpu.dtb.write_hits 11381434 # DTB write hits 495system.cpu.dtb.write_misses 10146 # DTB write misses |
| 486system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 487system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 488system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 489system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 496system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 497system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 498system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 499system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 490system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB 491system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions | 500system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB 501system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions |
| 492system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch 493system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 494system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions | 502system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch 503system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 504system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions |
| 495system.cpu.dtb.read_accesses 31681818 # DTB read accesses 496system.cpu.dtb.write_accesses 11391496 # DTB write accesses | 505system.cpu.dtb.read_accesses 31683554 # DTB read accesses 506system.cpu.dtb.write_accesses 11391580 # DTB write accesses |
| 497system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 507system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 498system.cpu.dtb.hits 43023655 # DTB hits 499system.cpu.dtb.misses 49659 # DTB misses 500system.cpu.dtb.accesses 43073314 # DTB accesses | 508system.cpu.dtb.hits 43025470 # DTB hits 509system.cpu.dtb.misses 49664 # DTB misses 510system.cpu.dtb.accesses 43075134 # DTB accesses |
| 501system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 502system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 503system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 504system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 505system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 506system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 507system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 508system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 514system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 516system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 517system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 518system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 519system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 520system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 521system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 511system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 512system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 513system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 514system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 515system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 516system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 517system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 518system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 524system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 525system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 526system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 527system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 528system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 529system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 530system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 531system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 522system.cpu.itb.inst_hits 24159481 # ITB inst hits 523system.cpu.itb.inst_misses 10516 # ITB inst misses | 532system.cpu.itb.inst_hits 24158829 # ITB inst hits 533system.cpu.itb.inst_misses 10513 # ITB inst misses |
| 524system.cpu.itb.read_hits 0 # DTB read hits 525system.cpu.itb.read_misses 0 # DTB read misses 526system.cpu.itb.write_hits 0 # DTB write hits 527system.cpu.itb.write_misses 0 # DTB write misses 528system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 529system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 530system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 531system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID | 534system.cpu.itb.read_hits 0 # DTB read hits 535system.cpu.itb.read_misses 0 # DTB read misses 536system.cpu.itb.write_hits 0 # DTB write hits 537system.cpu.itb.write_misses 0 # DTB write misses 538system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 539system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 540system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 541system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID |
| 532system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB | 542system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB |
| 533system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 534system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 535system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 543system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 544system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 545system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 536system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions | 546system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions |
| 537system.cpu.itb.read_accesses 0 # DTB read accesses 538system.cpu.itb.write_accesses 0 # DTB write accesses | 547system.cpu.itb.read_accesses 0 # DTB read accesses 548system.cpu.itb.write_accesses 0 # DTB write accesses |
| 539system.cpu.itb.inst_accesses 24169997 # ITB inst accesses 540system.cpu.itb.hits 24159481 # DTB hits 541system.cpu.itb.misses 10516 # DTB misses 542system.cpu.itb.accesses 24169997 # DTB accesses 543system.cpu.numCycles 499350041 # number of cpu cycles simulated | 549system.cpu.itb.inst_accesses 24169342 # ITB inst accesses 550system.cpu.itb.hits 24158829 # DTB hits 551system.cpu.itb.misses 10513 # DTB misses 552system.cpu.itb.accesses 24169342 # DTB accesses 553system.cpu.numCycles 499362415 # number of cpu cycles simulated |
| 544system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 545system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 554system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 555system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 546system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss 547system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed 548system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered 549system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken 550system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked 551system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing 552system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb 553system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 554system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps 555system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions 556system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR 557system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched 558system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed 559system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed 560system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) 561system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) 562system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) | 556system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss 557system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed 558system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered 559system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken 560system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked 561system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing 562system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb 563system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 564system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps 565system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions 566system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR 567system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched 568system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed 569system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed 570system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) |
| 563system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 573system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 564system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) 565system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) 566system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) 567system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) | 574system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) |
| 568system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 578system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 580system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 571system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle 573system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle 574system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle 575system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked 576system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running 577system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking 578system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing 579system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch 580system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction 581system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode 582system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode 583system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing 584system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle 585system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking 586system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst 587system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running 588system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking 589system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename 590system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename 591system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full 592system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full 593system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full 594system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full 595system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed 596system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made 597system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups | 581system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) 582system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle 583system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle 584system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle 585system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked 586system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running 587system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking 588system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing 589system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch 590system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction 591system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode 592system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode 593system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing 594system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle 595system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking 596system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst 597system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running 598system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking 599system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename 600system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename 601system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full 602system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full 603system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full 604system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full 605system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed 606system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made 607system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups |
| 598system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups | 608system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups |
| 599system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed 600system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing 601system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed 602system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed 603system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer 604system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. 605system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. 606system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. 607system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. 608system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) 609system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ 610system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued 611system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued 612system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling 613system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph 614system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed 615system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle | 609system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed 610system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing 611system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed 612system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed 613system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer 614system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. 615system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. 616system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. 617system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. 618system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) 619system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ 620system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued 621system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued 622system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling 623system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph 624system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed 625system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle |
| 616system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle | 626system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle |
| 617system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle | 627system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle |
| 618system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 628system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 619system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle 620system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle 621system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle 622system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle | 629system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle |
| 624system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 634system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 638system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 639system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 640system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 631system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle | 641system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle |
| 632system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 642system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 633system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available 634system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available 635system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available 636system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available 637system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available 638system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available 639system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available 640system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available 641system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available 642system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available 643system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available 644system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available 645system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available 646system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available 647system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available 648system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available 662system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available 663system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available | 643system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available 644system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available 645system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available 648system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available 649system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available 650system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available 651system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available 668system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available 669system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available 670system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available 671system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available 672system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available 673system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available |
| 664system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 665system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 666system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued | 674system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 675system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 676system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued |
| 667system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued 668system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued | 677system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued 678system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued |
| 669system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued 670system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued 671system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued 672system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued 673system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued 674system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued 675system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued 676system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 684system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued | 679system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued 680system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued 681system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued 682system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.88% # Type of FU issued 683system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.88% # Type of FU issued 684system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.88% # Type of FU issued 685system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.88% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.88% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 694system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.88% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.88% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.88% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.88% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued |
| 692system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued 696system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued 697system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued | 702system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued 703system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued 704system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued 705system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued 706system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued 707system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued |
| 698system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 699system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 708system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 709system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 700system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued 701system.cpu.iq.rate 0.188050 # Inst issue rate 702system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested 703system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) 704system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads 705system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes 706system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses | 710system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued 711system.cpu.iq.rate 0.188049 # Inst issue rate 712system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested 713system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) 714system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads 715system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes 716system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses |
| 707system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads 708system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes 709system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses | 717system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads 718system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes 719system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses |
| 710system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses | 720system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses |
| 711system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses | 721system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses |
| 712system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores | 722system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores |
| 713system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 723system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 714system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed 715system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed 716system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations 717system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed | 724system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed 725system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed 726system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations 727system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed |
| 718system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 719system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 728system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 729system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 720system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled 721system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked | 730system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled 731system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked |
| 722system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 732system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 723system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing 724system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking 725system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking 726system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ | 733system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing 734system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking 735system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking 736system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ |
| 727system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 737system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 728system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions 729system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions 730system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions 731system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall 732system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall 733system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations 734system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly 735system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly 736system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute 737system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions 738system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed 739system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute | 738system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions 739system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions 740system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions 741system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall 742system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall 743system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations 744system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly 745system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly 746system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute 747system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions 748system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed 749system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute |
| 740system.cpu.iew.exec_swp 0 # number of swp insts executed | 750system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 741system.cpu.iew.exec_nop 176010 # number of nop insts executed 742system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed 743system.cpu.iew.exec_branches 10791342 # Number of branches executed 744system.cpu.iew.exec_stores 11888889 # Number of stores executed 745system.cpu.iew.exec_rate 0.186738 # Inst execution rate 746system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit 747system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back 748system.cpu.iew.wb_producers 35465784 # num instructions producing a value 749system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value | 751system.cpu.iew.exec_nop 176011 # number of nop insts executed 752system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed 753system.cpu.iew.exec_branches 10791373 # Number of branches executed 754system.cpu.iew.exec_stores 11888962 # Number of stores executed 755system.cpu.iew.exec_rate 0.186737 # Inst execution rate 756system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit 757system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back 758system.cpu.iew.wb_producers 35461894 # num instructions producing a value 759system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value |
| 750system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 760system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 751system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle 752system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back | 761system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle 762system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back |
| 753system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 763system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 754system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit | 764system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit |
| 755system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards | 765system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards |
| 756system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted 757system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle 758system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle 759system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle | 766system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted 767system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle |
| 760system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 770system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 761system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle 762system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle 763system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle | 771system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle |
| 770system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 780system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 781system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 782system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 773system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle 774system.cpu.commit.committedInsts 60462326 # Number of instructions committed 775system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed | 783system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle 784system.cpu.commit.committedInsts 60462353 # Number of instructions committed 785system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed |
| 776system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 786system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 777system.cpu.commit.refs 25244569 # Number of memory references committed 778system.cpu.commit.loads 13512926 # Number of loads committed | 787system.cpu.commit.refs 25244590 # Number of memory references committed 788system.cpu.commit.loads 13512938 # Number of loads committed |
| 779system.cpu.commit.membars 403660 # Number of memory barriers committed | 789system.cpu.commit.membars 403660 # Number of memory barriers committed |
| 780system.cpu.commit.branches 10308073 # Number of branches committed | 790system.cpu.commit.branches 10308077 # Number of branches committed |
| 781system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. | 791system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. |
| 782system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. | 792system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. |
| 783system.cpu.commit.function_calls 991634 # Number of function calls committed. 784system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 793system.cpu.commit.function_calls 991634 # Number of function calls committed. 794system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 785system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction 786system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction | 795system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction 796system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction |
| 787system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction 788system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction 789system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction 790system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction 791system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction 792system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction 793system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction 794system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 806system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction 809system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction 810system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction | 797system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction 798system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction 799system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction 800system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.33% # Class of committed instruction 801system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.33% # Class of committed instruction 802system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.33% # Class of committed instruction 803system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.33% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.33% # Class of committed instruction --- 11 unchanged lines hidden (view full) --- 816system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.33% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.33% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.33% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.33% # Class of committed instruction 820system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction |
| 814system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction 815system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction | 824system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction 825system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction |
| 816system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 817system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 826system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 827system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 818system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction 819system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached | 828system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction 829system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached |
| 820system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 830system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 821system.cpu.rob.rob_reads 568287463 # The number of ROB reads 822system.cpu.rob.rob_writes 154414560 # The number of ROB writes 823system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself 824system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling 825system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 826system.cpu.committedInsts 60311945 # Number of Instructions Simulated 827system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated 828system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction 829system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads 830system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle 831system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads 832system.cpu.int_regfile_reads 109116898 # number of integer regfile reads 833system.cpu.int_regfile_writes 47012340 # number of integer regfile writes | 831system.cpu.rob.rob_reads 568215140 # The number of ROB reads 832system.cpu.rob.rob_writes 154414029 # The number of ROB writes 833system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself 834system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling 835system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 836system.cpu.committedInsts 60311972 # Number of Instructions Simulated 837system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated 838system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction 839system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads 840system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle 841system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads 842system.cpu.int_regfile_reads 109116744 # number of integer regfile reads 843system.cpu.int_regfile_writes 47012206 # number of integer regfile writes |
| 834system.cpu.fp_regfile_reads 8305 # number of floating regfile reads 835system.cpu.fp_regfile_writes 2780 # number of floating regfile writes | 844system.cpu.fp_regfile_reads 8305 # number of floating regfile reads 845system.cpu.fp_regfile_writes 2780 # number of floating regfile writes |
| 836system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads 837system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes 838system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads 839system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes 840system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) 841system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution | 846system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads 847system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes 848system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads 849system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes 850system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution |
| 843system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution | 852system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution |
| 845system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution | 854system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution |
| 846system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 848system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution | 855system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution 856system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 857system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution |
| 849system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution 851system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) 852system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) 853system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) 854system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) 855system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) 856system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) 857system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) 858system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) 859system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) 860system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) 861system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) 862system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) 863system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) | 858system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution 860system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) 861system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) 862system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) 863system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) 864system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) 865system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) 866system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) 867system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) 868system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) 869system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) 870system.cpu.toL2Bus.snoops 26770 # Total snoops (count) 871system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram 872system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 873system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 874system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 876system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 878system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram 886system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) |
| 864system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 887system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 865system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) | 888system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) |
| 866system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 889system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 867system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) | 890system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) |
| 868system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 891system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 869system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) | 892system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) |
| 870system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 893system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 871system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) | 894system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) |
| 872system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 895system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 873system.cpu.icache.tags.replacements 959881 # number of replacements 874system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use 875system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. 876system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. 877system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. 878system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. 879system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor | 896system.cpu.icache.tags.replacements 959838 # number of replacements 897system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use 898system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. 899system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. 900system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. 901system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. 902system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor |
| 880system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy 881system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy 882system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 887system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 903system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy 904system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy 905system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 906system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id 907system.cpu.icache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id 908system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id 909system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 910system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 888system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses 889system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses 890system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits 891system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits 892system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits 893system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits 894system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits 895system.cpu.icache.overall_hits::total 23149457 # number of overall hits 896system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses 897system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses 898system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses 899system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses 900system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses 901system.cpu.icache.overall_misses::total 1005369 # number of overall misses 902system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles 903system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles 904system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles 905system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles 906system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles 907system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles 908system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) 909system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) 910system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses 911system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses 912system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses 913system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses | 911system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses 912system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses 913system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits 914system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits 915system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits 916system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits 917system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits 918system.cpu.icache.overall_hits::total 23148830 # number of overall hits 919system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses 920system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses 921system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses 922system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses 923system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses 924system.cpu.icache.overall_misses::total 1005344 # number of overall misses 925system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles 926system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles 927system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles 928system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles 929system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles 930system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles 931system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses) 932system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses) 933system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses 934system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses 935system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses 936system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses |
| 914system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses 915system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses 916system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses 917system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses 918system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses 919system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses | 937system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses 938system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses 939system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses 940system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses 941system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses 942system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses |
| 920system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency 921system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency 922system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency 923system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency 924system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency 925system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency 926system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked | 943system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency 944system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency 945system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency 946system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency 947system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency 948system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency 949system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked |
| 927system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 950system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 928system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked | 951system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked |
| 929system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 952system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 930system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked | 953system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked |
| 931system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 932system.cpu.icache.fast_writes 0 # number of fast writes performed 933system.cpu.icache.cache_copies 0 # number of cache copies performed | 954system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 955system.cpu.icache.fast_writes 0 # number of fast writes performed 956system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 934system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits 935system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits 936system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits 937system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits 938system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits 939system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits 940system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses 941system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses 942system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses 943system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses 944system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses 945system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses 946system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles 947system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles 948system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles 949system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles 950system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles 951system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles 952system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles 953system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles 954system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles 955system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles 956system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses 957system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses 958system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses 959system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses 960system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses 961system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses 962system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency 963system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency 964system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency 965system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency 966system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency 967system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency | 957system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits 958system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits 959system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits 960system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits 961system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits 962system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits 963system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses 964system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses 965system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses 966system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses 967system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses 968system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses 969system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles 970system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles 971system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles 972system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles 973system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles 974system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles 975system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles 976system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles 977system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles 978system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles 979system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses 980system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses 981system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses 982system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses 983system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses 984system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses 985system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency 986system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency 987system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency 988system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency 989system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency 990system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency |
| 968system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 969system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 970system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 971system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 972system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 991system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 992system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 993system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 994system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 995system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 973system.cpu.l2cache.tags.replacements 63302 # number of replacements 974system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. 978system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. 979system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor | 996system.cpu.l2cache.tags.replacements 63303 # number of replacements 997system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use 998system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. 999system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. 1000system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. 1001system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. 1002system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor 1003system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor |
| 981system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor | 1004system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000703 # Average occupied blocks per requestor |
| 982system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor 983system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor 984system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy | 1005system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor 1006system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor 1007system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy |
| 985system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy 986system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 1008system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000104 # Average percentage of cache occupancy 1009system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 987system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy | 1010system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy |
| 988system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy | 1011system.cpu.l2cache.tags.occ_percent::cpu.data 0.093020 # Average percentage of cache occupancy |
| 989system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy | 1012system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy |
| 990system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 991system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id | 1013system.cpu.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 1014system.cpu.l2cache.tags.occ_task_id_blocks::1024 65381 # Occupied blocks per task id 1015system.cpu.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 1016system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id |
| 994system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id | 1017system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id 1018system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id 1019system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id 1020system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id |
| 998system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 999system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id | 1021system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 1022system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997635 # Percentage of cache occupancy per task id |
| 1000system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses 1001system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses 1002system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits 1003system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits 1004system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits 1005system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits 1006system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits 1007system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits 1008system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits | 1023system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses 1024system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses 1025system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits 1026system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits 1027system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits 1028system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits 1029system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits 1030system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits 1031system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits |
| 1009system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits 1010system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits 1011system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1012system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits | 1032system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits 1033system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits 1034system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1035system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits |
| 1013system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits 1014system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits 1015system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits 1016system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits 1017system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits 1018system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits 1019system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits 1020system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits 1021system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits 1022system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits 1023system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits 1024system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits | 1036system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits 1037system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits 1038system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits 1039system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits 1040system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits 1041system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits 1042system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits 1043system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits 1044system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits 1045system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits 1046system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits 1047system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits |
| 1025system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses 1026system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses | 1048system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 11 # number of ReadReq misses 1049system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses |
| 1027system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses | 1050system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses |
| 1028system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses | 1051system.cpu.l2cache.ReadReq_misses::cpu.data 10148 # number of ReadReq misses |
| 1029system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses | 1052system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses |
| 1030system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses 1031system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses | 1053system.cpu.l2cache.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses 1054system.cpu.l2cache.UpgradeReq_misses::total 2909 # number of UpgradeReq misses |
| 1032system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses 1033system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses | 1055system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses 1056system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses |
| 1034system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses 1035system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses | 1057system.cpu.l2cache.demand_misses::cpu.dtb.walker 11 # number of demand (read+write) misses 1058system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses |
| 1036system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses 1037system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses 1038system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses | 1059system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses 1060system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses 1061system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses |
| 1039system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses 1040system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses | 1062system.cpu.l2cache.overall_misses::cpu.dtb.walker 11 # number of overall misses 1063system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses |
| 1041system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses 1042system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses 1043system.cpu.l2cache.overall_misses::total 155170 # number of overall misses 1044system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles 1045system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles 1046system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles 1047system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles 1048system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles 1049system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles 1050system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles 1051system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles 1052system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles 1053system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles 1054system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles 1055system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles 1056system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles 1057system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles 1058system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles 1059system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles 1060system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles 1061system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles 1062system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles 1063system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses) 1064system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses) 1065system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses) 1066system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses) 1067system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses) 1068system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses) 1069system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses) | 1064system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses 1065system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses 1066system.cpu.l2cache.overall_misses::total 155171 # number of overall misses 1067system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles 1068system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles 1069system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles 1070system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles 1071system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles 1072system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles 1073system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles 1074system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles 1075system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles 1076system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles 1077system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles 1078system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles 1079system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles 1080system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles 1081system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles 1082system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles 1083system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles 1084system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles 1085system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles 1086system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses) 1087system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses) 1088system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses) 1089system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses) 1090system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses) 1091system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses) 1092system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses) |
| 1070system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) 1071system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) 1072system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) | 1093system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2950 # number of UpgradeReq accesses(hits+misses) 1094system.cpu.l2cache.UpgradeReq_accesses::total 2950 # number of UpgradeReq accesses(hits+misses) 1095system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1096system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) |
| 1074system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses) 1075system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses) 1076system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses 1077system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses 1078system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses 1079system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses 1080system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses 1081system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses 1082system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses 1083system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses 1084system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses 1085system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses 1086system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses 1087system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses 1088system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses 1089system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses | 1097system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses) 1098system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses) 1099system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses 1100system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses 1101system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses 1102system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses 1103system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses 1104system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses 1105system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses 1106system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses 1107system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses 1108system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses 1109system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses 1110system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses 1111system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses 1112system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses |
| 1090system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses 1091system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses 1092system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses | 1113system.cpu.l2cache.ReadReq_miss_rate::total 0.015694 # miss rate for ReadReq accesses 1114system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986102 # miss rate for UpgradeReq accesses 1115system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986102 # miss rate for UpgradeReq accesses |
| 1093system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses 1094system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses 1095system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses 1096system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses 1097system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses 1098system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses 1099system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses 1100system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses 1101system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses 1102system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses 1103system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses 1104system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses 1105system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency 1106system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency 1107system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency 1108system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency 1109system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency 1110system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency 1111system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency 1112system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency 1113system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency 1114system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency 1115system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency 1116system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency 1117system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency 1118system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency 1119system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency 1120system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency 1121system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency 1122system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency 1123system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency | 1116system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses 1117system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses 1118system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses 1119system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses 1120system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses 1121system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses 1122system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses 1123system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses 1124system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses 1125system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses 1126system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses 1127system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses 1128system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency 1129system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency 1130system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency 1131system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency 1132system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency 1133system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency 1134system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency 1135system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency 1136system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency 1137system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency 1138system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency 1139system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency 1140system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency 1141system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency 1142system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency 1143system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency 1144system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency 1145system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency 1146system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency |
| 1124system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1125system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1126system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1127system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1128system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1129system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1130system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1131system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 1140system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits 1141system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 1142system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits 1143system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1144system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits 1145system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits 1146system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses 1147system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses | 1147system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1148system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1149system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1150system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1151system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1152system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1153system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1154system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 1163system.cpu.l2cache.demand_mshr_hits::cpu.data 40 # number of demand (read+write) MSHR hits 1164system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits 1165system.cpu.l2cache.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits 1166system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1167system.cpu.l2cache.overall_mshr_hits::cpu.data 40 # number of overall MSHR hits 1168system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits 1169system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 10 # number of ReadReq MSHR misses 1170system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses |
| 1148system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses | 1171system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses |
| 1149system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses | 1172system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10108 # number of ReadReq MSHR misses |
| 1150system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses | 1173system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses |
| 1151system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses 1152system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses | 1174system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses 1175system.cpu.l2cache.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses |
| 1153system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses 1154system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses | 1176system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses 1177system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses |
| 1155system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses 1156system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses | 1178system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 10 # number of demand (read+write) MSHR misses 1179system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses |
| 1157system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses 1158system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses 1159system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses | 1180system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses 1181system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses 1182system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses |
| 1160system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses 1161system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses | 1183system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 10 # number of overall MSHR misses 1184system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses |
| 1162system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses 1163system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses 1164system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses | 1185system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses 1186system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses 1187system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses |
| 1165system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles 1166system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles | 1188system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 596250 # number of ReadReq MSHR miss cycles 1189system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 201250 # number of ReadReq MSHR miss cycles |
| 1167system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles 1168system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles 1169system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles 1170system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles 1171system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles 1172system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles 1173system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles | 1190system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles 1191system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles 1192system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles 1193system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles 1194system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles 1195system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles 1196system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles |
| 1174system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles 1175system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles | 1197system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 596250 # number of demand (read+write) MSHR miss cycles 1198system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 201250 # number of demand (read+write) MSHR miss cycles |
| 1176system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles 1177system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles 1178system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles | 1199system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles 1200system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles 1201system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles |
| 1179system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles 1180system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles | 1202system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 596250 # number of overall MSHR miss cycles 1203system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 201250 # number of overall MSHR miss cycles |
| 1181system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles 1182system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles 1183system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles 1184system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles 1185system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles 1186system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles 1187system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles 1188system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles 1189system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles 1190system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles 1191system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles | 1204system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles 1205system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles 1206system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles 1207system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles 1208system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles 1209system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles 1210system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles 1211system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles 1212system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles 1213system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles 1214system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles |
| 1192system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses | 1215system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses |
| 1193system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses 1194system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses 1195system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses 1196system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses | 1216system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses 1217system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses 1218system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses 1219system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses |
| 1197system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses 1198system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses | 1220system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses 1221system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses |
| 1199system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses 1200system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses | 1222system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses 1223system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses |
| 1201system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses | 1224system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for demand accesses |
| 1202system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses 1203system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses 1204system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses 1205system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses | 1225system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses 1226system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses 1227system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses 1228system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses |
| 1206system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses | 1229system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses |
| 1207system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses 1208system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses 1209system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses 1210system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses | 1230system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses 1231system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses 1232system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses 1233system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses |
| 1211system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency 1212system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency | 1234system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency 1235system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency |
| 1213system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency 1214system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency 1215system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency 1216system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency 1217system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency 1218system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency 1219system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency | 1236system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency 1237system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency 1238system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency 1239system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency 1240system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency 1241system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency 1242system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency |
| 1220system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency 1221system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency | 1243system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency 1244system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency |
| 1222system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency 1223system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency 1224system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency | 1245system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency 1246system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency 1247system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency |
| 1225system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency 1226system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency | 1248system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency 1249system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency |
| 1227system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency 1228system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency 1229system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency | 1250system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency 1251system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency 1252system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency |
| 1230system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1231system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1232system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1233system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1234system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1235system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1236system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1237system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1238system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1253system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1254system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1255system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1256system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1257system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1258system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1259system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1260system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1261system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1239system.cpu.dcache.tags.replacements 633309 # number of replacements 1240system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use 1241system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks. 1242system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks. 1243system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks. | 1262system.cpu.dcache.tags.replacements 633278 # number of replacements 1263system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use 1264system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks. 1265system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. 1266system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. |
| 1244system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. | 1267system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. |
| 1245system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor | 1268system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor |
| 1246system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy 1247system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy 1248system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1269system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy 1270system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy 1271system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1249system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 1250system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id | 1272system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 1273system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id |
| 1251system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 1252system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1274system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id 1275system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1253system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses 1254system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses 1255system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits 1256system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits 1257system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits 1258system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits 1259system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits 1260system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits 1261system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits 1262system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits | 1276system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses 1277system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses 1278system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits 1279system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits 1280system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits 1281system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits 1282system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits 1283system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits 1284system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits 1285system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits |
| 1263system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits 1264system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits | 1286system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits 1287system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits |
| 1265system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits 1266system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits 1267system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits 1268system.cpu.dcache.overall_hits::total 18581521 # number of overall hits 1269system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses 1270system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses 1271system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses 1272system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses 1273system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses 1274system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses 1275system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses 1276system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses | 1288system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits 1289system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits 1290system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits 1291system.cpu.dcache.overall_hits::total 18581554 # number of overall hits 1292system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses 1293system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses 1294system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses 1295system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses 1296system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses 1297system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses 1298system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses 1299system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses |
| 1277system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1278system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses | 1300system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1301system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses |
| 1279system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses 1280system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses 1281system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses 1282system.cpu.dcache.overall_misses::total 3712246 # number of overall misses 1283system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles 1284system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles 1285system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles 1286system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles 1287system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles 1288system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles | 1302system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses 1303system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses 1304system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses 1305system.cpu.dcache.overall_misses::total 3712231 # number of overall misses 1306system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles 1307system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles 1308system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles 1309system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles 1310system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles 1311system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles |
| 1289system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 1290system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles | 1312system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 1313system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles |
| 1291system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles 1292system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles 1293system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles 1294system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles 1295system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) 1296system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) 1297system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) 1298system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) 1299system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses) 1300system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses) 1301system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses) 1302system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses) | 1314system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles 1315system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles 1316system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles 1317system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles 1318system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses) 1319system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses) 1320system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses) 1321system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses) 1322system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses) 1323system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses) 1324system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses) 1325system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses) |
| 1303system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) 1304system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) | 1326system.cpu.dcache.StoreCondReq_accesses::cpu.data 247596 # number of StoreCondReq accesses(hits+misses) 1327system.cpu.dcache.StoreCondReq_accesses::total 247596 # number of StoreCondReq accesses(hits+misses) |
| 1305system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses 1306system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses 1307system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses 1308system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses 1309system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses 1310system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses | 1328system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses 1329system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses 1330system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses 1331system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses 1332system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses 1333system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses |
| 1311system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses 1312system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses | 1334system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses 1335system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses |
| 1313system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses 1314system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses 1315system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses 1316system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses | 1336system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses 1337system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses 1338system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses 1339system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses |
| 1317system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses 1318system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses | 1340system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses 1341system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses |
| 1319system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses 1320system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses 1321system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses 1322system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses 1323system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency 1324system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency 1325system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency 1326system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency 1327system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency 1328system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency | 1342system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses 1343system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses 1344system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses 1345system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses 1346system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency 1347system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency 1348system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency 1349system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency 1350system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency 1351system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency |
| 1329system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1330system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency | 1352system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1353system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency |
| 1331system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency 1332system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency 1333system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency 1334system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency 1335system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked 1336system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1337system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked 1338system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1339system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked 1340system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1354system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency 1355system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency 1356system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency 1357system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency 1358system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked 1359system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked 1360system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked 1361system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 1362system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked 1363system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked |
| 1341system.cpu.dcache.fast_writes 0 # number of fast writes performed 1342system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1364system.cpu.dcache.fast_writes 0 # number of fast writes performed 1365system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1343system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks 1344system.cpu.dcache.writebacks::total 599976 # number of writebacks 1345system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits 1346system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits 1347system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits 1348system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits | 1366system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks 1367system.cpu.dcache.writebacks::total 599947 # number of writebacks 1368system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits 1369system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits 1370system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits 1371system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits |
| 1349system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits 1350system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits | 1372system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits 1373system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits |
| 1351system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits 1352system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits 1353system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits 1354system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits 1355system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses 1356system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses 1357system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses 1358system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses 1359system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses 1360system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses 1361system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses 1362system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses | 1374system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits 1375system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits 1376system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits 1377system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits 1378system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses 1379system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses 1380system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses 1381system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses 1382system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses 1383system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses 1384system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses 1385system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses |
| 1363system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1364system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses | 1386system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1387system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses |
| 1365system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses 1366system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses 1367system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses 1368system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses 1369system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles 1370system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles 1371system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles 1372system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles 1373system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles 1374system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles 1375system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles 1376system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles | 1388system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses 1389system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses 1390system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses 1391system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses 1392system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles 1393system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles 1394system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles 1395system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles 1396system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles 1397system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles 1398system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles 1399system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles |
| 1377system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 1378system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles | 1400system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 1401system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles |
| 1379system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles 1380system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles 1381system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles 1382system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles 1383system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles 1384system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles 1385system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles 1386system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles 1387system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles 1388system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles 1389system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses 1390system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses | 1402system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles 1403system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles 1404system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles 1405system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles 1406system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles 1407system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles 1408system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles 1409system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles 1410system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles 1411system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles 1412system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses 1413system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses |
| 1391system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses 1392system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses | 1414system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses 1415system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses |
| 1393system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses 1394system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses 1395system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses 1396system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses | 1416system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses 1417system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses 1418system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses 1419system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses |
| 1397system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses 1398system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses | 1420system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses 1421system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses |
| 1399system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses 1400system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses 1401system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses 1402system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses 1403system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency 1404system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency 1405system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency 1406system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency 1407system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency 1408system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency 1409system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency 1410system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency | 1422system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses 1423system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses 1424system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses 1425system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses 1426system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency 1427system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency 1428system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency 1429system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency 1430system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency 1431system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency 1432system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency 1433system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency |
| 1411system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1412system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency | 1434system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1435system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency |
| 1413system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency 1414system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency 1415system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency 1416system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency | 1436system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency 1437system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency 1438system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency 1439system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency |
| 1417system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1418system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1419system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1420system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1421system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1422system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1423system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1424system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1432system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1433system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1434system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1435system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1436system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1437system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1438system.iocache.fast_writes 0 # number of fast writes performed 1439system.iocache.cache_copies 0 # number of cache copies performed | 1440system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1441system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1442system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1443system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1444system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1445system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1446system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1447system.iocache.tags.replacements 0 # number of replacements --- 7 unchanged lines hidden (view full) --- 1455system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1456system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1457system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1458system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1459system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1460system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1461system.iocache.fast_writes 0 # number of fast writes performed 1462system.iocache.cache_copies 0 # number of cache copies performed |
| 1440system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles 1441system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles 1442system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles 1443system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles | 1463system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles 1464system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles 1465system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles 1466system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles |
| 1444system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1445system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1446system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1447system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1448system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1449system.cpu.kern.inst.arm 0 # number of arm instructions executed | 1467system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1468system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1469system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1470system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1471system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1472system.cpu.kern.inst.arm 0 # number of arm instructions executed |
| 1450system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed | 1473system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed |
| 1451 1452---------- End Simulation Statistics ---------- | 1474 1475---------- End Simulation Statistics ---------- |