1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.827616 # Number of seconds simulated 4sim_ticks 2827616186000 # Number of ticks simulated 5final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 99248 # Simulator instruction rate (inst/s) 8host_op_rate 120386 # Simulator op (including micro ops) rate (op/s) --- 811 unchanged lines hidden (view full) --- 820system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction 821system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction 822system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction 823system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction 824system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 825system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 826system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction 827system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached |
828system.cpu.rob.rob_reads 375672050 # The number of ROB reads 829system.cpu.rob.rob_writes 292972268 # The number of ROB writes 830system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself 831system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling 832system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 833system.cpu.committedInsts 113151083 # Number of Instructions Simulated 834system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated 835system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction --- 909 unchanged lines hidden --- |