3,5c3,5
< sim_seconds 2.524310 # Number of seconds simulated
< sim_ticks 2524309551500 # Number of ticks simulated
< final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.525141 # Number of seconds simulated
> sim_ticks 2525141046500 # Number of ticks simulated
> final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 65403 # Simulator instruction rate (inst/s)
< host_op_rate 84155 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2737677908 # Simulator tick rate (ticks/s)
< host_mem_usage 401408 # Number of bytes of host memory used
< host_seconds 922.06 # Real time elapsed on the host
< sim_insts 60305560 # Number of instructions simulated
< sim_ops 77596391 # Number of ops (including micro ops) simulated
---
> host_inst_rate 61643 # Simulator instruction rate (inst/s)
> host_op_rate 79318 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2581152882 # Simulator tick rate (ticks/s)
> host_mem_usage 426780 # Number of bytes of host memory used
> host_seconds 978.30 # Real time elapsed on the host
> sim_insts 60305756 # Number of instructions simulated
> sim_ops 77596741 # Number of ops (including micro ops) simulated
15,22c15,22
< system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
< system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory
> system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory
24c24
< system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory
26,31c26,31
< system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory
33,129c33,131
< system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 966197440 # Total number of bytes read from memory
< system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 2524308440000 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 36 # Categorize read packet sizes
< system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 154591 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 754018 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 59118 # Categorize write packet sizes
< system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
---
> system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15096843 # Number of read requests accepted
> system.physmem.writeReqs 813143 # Number of write requests accepted
> system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 943582 # Per bank write bursts
> system.physmem.perBankRdBursts::1 943145 # Per bank write bursts
> system.physmem.perBankRdBursts::2 939291 # Per bank write bursts
> system.physmem.perBankRdBursts::3 939307 # Per bank write bursts
> system.physmem.perBankRdBursts::4 943115 # Per bank write bursts
> system.physmem.perBankRdBursts::5 943141 # Per bank write bursts
> system.physmem.perBankRdBursts::6 939138 # Per bank write bursts
> system.physmem.perBankRdBursts::7 938546 # Per bank write bursts
> system.physmem.perBankRdBursts::8 943996 # Per bank write bursts
> system.physmem.perBankRdBursts::9 943390 # Per bank write bursts
> system.physmem.perBankRdBursts::10 938426 # Per bank write bursts
> system.physmem.perBankRdBursts::11 937974 # Per bank write bursts
> system.physmem.perBankRdBursts::12 943928 # Per bank write bursts
> system.physmem.perBankRdBursts::13 943533 # Per bank write bursts
> system.physmem.perBankRdBursts::14 939234 # Per bank write bursts
> system.physmem.perBankRdBursts::15 938672 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6704 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6457 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6598 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6635 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6561 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6794 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6789 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6723 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7136 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6877 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6538 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6183 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7149 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6765 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7038 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6899 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 2525139929000 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 36 # Read request sizes (log2)
> system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 154599 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 754018 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 59125 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
143,168c145,170
< system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
175,430c177,742
< system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
< system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
< system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
< system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
< system.physmem.avgQLat 19314.15 # Average queueing delay per request
< system.physmem.avgBankLat 1014.34 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 25328.49 # Average memory access latency
< system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
< system.physmem.busUtil 3.15 # Data bus utilization in percentage
< system.physmem.avgRdQLen 0.15 # Average read queue length over time
< system.physmem.avgWrQLen 14.41 # Average write queue length over time
< system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
< system.physmem.avgGap 158662.04 # Average gap between requests
---
> system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2055 327 0.38% 60.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2119 6 0.01% 60.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2183 31 0.04% 60.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2247 13 0.02% 60.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2311 124 0.14% 61.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2375 3 0.00% 61.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2439 17 0.02% 61.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2503 9 0.01% 61.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2567 99 0.11% 61.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2631 7 0.01% 61.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2695 25 0.03% 61.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2759 11 0.01% 61.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2823 90 0.10% 61.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2887 6 0.01% 61.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2951 23 0.03% 61.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3015 2 0.00% 61.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3079 292 0.34% 61.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3143 7 0.01% 61.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3207 16 0.02% 61.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3271 8 0.01% 61.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3335 98 0.11% 61.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4039 10 0.01% 62.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4103 373 0.43% 62.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4167 4 0.00% 62.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4231 16 0.02% 62.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4295 8 0.01% 62.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4359 116 0.13% 62.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4423 14 0.02% 62.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4487 12 0.01% 62.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4551 8 0.01% 62.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4615 99 0.11% 63.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4672-4679 3 0.00% 63.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4736-4743 8 0.01% 63.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4807 2 0.00% 63.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4871 19 0.02% 63.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4935 2 0.00% 63.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4999 13 0.02% 63.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5063 5 0.01% 63.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5760-5767 10 0.01% 63.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5824-5831 2 0.00% 63.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5895 131 0.15% 63.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5959 1 0.00% 63.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6023 15 0.02% 63.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6087 11 0.01% 64.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6151 413 0.48% 64.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6215 1 0.00% 64.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6279 8 0.01% 64.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6343 2 0.00% 64.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6407 87 0.10% 64.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6471 4 0.00% 64.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6528-6535 12 0.01% 64.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6599 5 0.01% 64.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6663 145 0.17% 64.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6727 1 0.00% 64.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6791 14 0.02% 64.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6855 7 0.01% 64.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6919 24 0.03% 64.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6976-6983 2 0.00% 64.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7047 8 0.01% 64.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7744-7751 3 0.00% 65.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7808-7815 9 0.01% 65.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7872-7879 5 0.01% 65.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7943 82 0.10% 65.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8007 1 0.00% 65.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8071 13 0.02% 65.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8128-8135 1 0.00% 65.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8199 508 0.59% 66.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8256-8263 1 0.00% 66.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8320-8327 1 0.00% 66.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8448-8455 76 0.09% 66.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8640-8647 1 0.00% 66.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8704-8711 89 0.10% 66.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8832-8839 1 0.00% 66.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8896-8903 1 0.00% 66.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8960-8967 74 0.09% 66.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9216-9223 350 0.41% 66.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9344-9351 1 0.00% 66.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9472-9479 17 0.02% 66.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9536-9543 1 0.00% 66.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9600-9607 3 0.00% 66.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10752-10759 76 0.09% 67.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::10944-10951 3 0.00% 67.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11008-11015 15 0.02% 67.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11136-11143 1 0.00% 67.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11264-11271 416 0.48% 68.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11392-11399 1 0.00% 68.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11520-11527 13 0.02% 68.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11584-11591 2 0.00% 68.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11712-11719 2 0.00% 68.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11776-11783 84 0.10% 68.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::11968-11975 1 0.00% 68.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12032-12039 98 0.11% 68.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12160-12167 5 0.01% 68.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12288-12295 335 0.39% 69.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12416-12423 3 0.00% 69.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12480-12487 1 0.00% 69.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12544-12551 141 0.16% 69.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12800-12807 79 0.09% 69.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12864-12871 1 0.00% 69.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::12992-12999 1 0.00% 69.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13056-13063 86 0.10% 69.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13120-13127 1 0.00% 69.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13184-13191 4 0.00% 69.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13312-13319 286 0.33% 69.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13568-13575 76 0.09% 69.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13824-13831 74 0.09% 69.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::13888-13895 1 0.00% 69.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14080-14087 91 0.11% 70.01% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14208-14215 3 0.00% 70.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14336-14343 284 0.33% 70.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14464-14471 2 0.00% 70.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14592-14599 139 0.16% 70.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14720-14727 4 0.00% 70.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14848-14855 146 0.17% 70.68% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14912-14919 2 0.00% 70.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::14976-14983 1 0.00% 70.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15104-15111 13 0.02% 70.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15168-15175 1 0.00% 70.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15232-15239 2 0.00% 70.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15296-15303 2 0.00% 70.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15360-15367 405 0.47% 71.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15424-15431 1 0.00% 71.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15552-15559 1 0.00% 71.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15616-15623 17 0.02% 71.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15680-15687 1 0.00% 71.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::15872-15879 80 0.09% 71.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16064-16071 1 0.00% 71.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16128-16135 74 0.09% 71.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16256-16263 11 0.01% 71.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16384-16391 645 0.75% 72.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16640-16647 72 0.08% 72.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16704-16711 2 0.00% 72.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16832-16839 1 0.00% 72.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::16896-16903 78 0.09% 72.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17088-17095 1 0.00% 72.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17152-17159 28 0.03% 72.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17280-17287 5 0.01% 72.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17408-17415 407 0.47% 72.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17472-17479 1 0.00% 72.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17536-17543 2 0.00% 72.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17664-17671 18 0.02% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17728-17735 2 0.00% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17792-17799 3 0.00% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17856-17863 1 0.00% 72.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17920-17927 147 0.17% 73.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::17984-17991 1 0.00% 73.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18048-18055 2 0.00% 73.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18112-18119 2 0.00% 73.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18176-18183 144 0.17% 73.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18304-18311 4 0.00% 73.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18432-18439 279 0.32% 73.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18496-18503 1 0.00% 73.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18688-18695 89 0.10% 73.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18880-18887 2 0.00% 73.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::18944-18951 73 0.08% 73.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19072-19079 1 0.00% 73.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19136-19143 1 0.00% 73.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19200-19207 77 0.09% 73.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19328-19335 5 0.01% 73.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19456-19463 263 0.31% 74.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19520-19527 1 0.00% 74.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19712-19719 82 0.10% 74.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::19968-19975 79 0.09% 74.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20096-20103 1 0.00% 74.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20224-20231 140 0.16% 74.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20288-20295 1 0.00% 74.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20352-20359 3 0.00% 74.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20480-20487 343 0.40% 74.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20672-20679 1 0.00% 74.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20736-20743 96 0.11% 75.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20864-20871 2 0.00% 75.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::20992-20999 82 0.10% 75.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21120-21127 1 0.00% 75.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21184-21191 1 0.00% 75.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21248-21255 14 0.02% 75.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21312-21319 1 0.00% 75.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21376-21383 4 0.00% 75.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21504-21511 401 0.47% 75.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21568-21575 1 0.00% 75.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21632-21639 1 0.00% 75.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21760-21767 17 0.02% 75.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::21888-21895 2 0.00% 75.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22016-22023 77 0.09% 75.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22144-22151 1 0.00% 75.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22272-22279 84 0.10% 75.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22400-22407 3 0.00% 75.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22464-22471 1 0.00% 75.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22528-22535 400 0.46% 76.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22656-22663 1 0.00% 76.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22720-22727 2 0.00% 76.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22784-22791 80 0.09% 76.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22848-22855 1 0.00% 76.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22912-22919 1 0.00% 76.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::22976-22983 2 0.00% 76.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23040-23047 136 0.16% 76.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23104-23111 1 0.00% 76.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23296-23303 21 0.02% 76.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23360-23367 3 0.00% 76.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23424-23431 2 0.00% 76.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23552-23559 351 0.41% 76.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23680-23687 2 0.00% 76.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23808-23815 73 0.08% 77.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::23936-23943 1 0.00% 77.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24000-24007 2 0.00% 77.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24064-24071 83 0.10% 77.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24256-24263 1 0.00% 77.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24320-24327 83 0.10% 77.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24448-24455 4 0.00% 77.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24576-24583 387 0.45% 77.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24832-24839 78 0.09% 77.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::24960-24967 1 0.00% 77.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25024-25031 1 0.00% 77.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25088-25095 89 0.10% 77.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25280-25287 1 0.00% 77.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25344-25351 72 0.08% 77.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25472-25479 4 0.00% 77.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25600-25607 349 0.41% 78.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25728-25735 1 0.00% 78.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25856-25863 19 0.02% 78.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::25984-25991 3 0.00% 78.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26112-26119 133 0.15% 78.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26176-26183 1 0.00% 78.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26240-26247 1 0.00% 78.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26304-26311 2 0.00% 78.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26368-26375 78 0.09% 78.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26432-26439 1 0.00% 78.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26496-26503 1 0.00% 78.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26560-26567 1 0.00% 78.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26624-26631 401 0.47% 79.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26688-26695 1 0.00% 79.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26752-26759 2 0.00% 79.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26816-26823 1 0.00% 79.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::26880-26887 82 0.10% 79.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27008-27015 2 0.00% 79.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27136-27143 77 0.09% 79.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27200-27207 1 0.00% 79.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27392-27399 15 0.02% 79.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27520-27527 3 0.00% 79.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27584-27591 1 0.00% 79.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27648-27655 403 0.47% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27840-27847 1 0.00% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27904-27911 11 0.01% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::27968-27975 2 0.00% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28032-28039 1 0.00% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28096-28103 1 0.00% 79.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28160-28167 83 0.10% 79.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28288-28295 2 0.00% 79.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28352-28359 1 0.00% 79.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28416-28423 97 0.11% 80.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28480-28487 2 0.00% 80.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28544-28551 2 0.00% 80.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28608-28615 1 0.00% 80.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28672-28679 341 0.40% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28736-28743 1 0.00% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28800-28807 1 0.00% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28864-28871 2 0.00% 80.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28928-28935 143 0.17% 80.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::28992-28999 1 0.00% 80.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29056-29063 1 0.00% 80.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29184-29191 77 0.09% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29248-29255 2 0.00% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29312-29319 1 0.00% 80.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29440-29447 85 0.10% 80.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29504-29511 3 0.00% 80.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29568-29575 2 0.00% 80.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29632-29639 1 0.00% 80.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29696-29703 268 0.31% 81.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29824-29831 1 0.00% 81.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29888-29895 2 0.00% 81.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::29952-29959 76 0.09% 81.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30208-30215 74 0.09% 81.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30336-30343 2 0.00% 81.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30464-30471 92 0.11% 81.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30592-30599 4 0.00% 81.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30656-30663 1 0.00% 81.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30720-30727 271 0.31% 81.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30784-30791 1 0.00% 81.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30848-30855 2 0.00% 81.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30912-30919 1 0.00% 81.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::30976-30983 145 0.17% 81.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31104-31111 2 0.00% 81.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31232-31239 148 0.17% 82.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31296-31303 1 0.00% 82.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31360-31367 1 0.00% 82.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31488-31495 19 0.02% 82.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31552-31559 2 0.00% 82.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31616-31623 5 0.01% 82.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31680-31687 4 0.00% 82.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31744-31751 398 0.46% 82.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31872-31879 1 0.00% 82.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::31936-31943 1 0.00% 82.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32000-32007 18 0.02% 82.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32128-32135 1 0.00% 82.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32256-32263 78 0.09% 82.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32320-32327 1 0.00% 82.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32448-32455 1 0.00% 82.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32512-32519 83 0.10% 82.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32576-32583 1 0.00% 82.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32768-32775 642 0.75% 83.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::32832-32839 2 0.00% 83.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33024-33031 73 0.08% 83.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33152-33159 1 0.00% 83.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33216-33223 2 0.00% 83.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33280-33287 78 0.09% 83.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33408-33415 4 0.00% 83.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33536-33543 27 0.03% 83.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33600-33607 2 0.00% 83.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33728-33735 1 0.00% 83.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33792-33799 406 0.47% 84.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33856-33863 1 0.00% 84.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33920-33927 1 0.00% 84.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::33984-33991 1 0.00% 84.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34048-34055 16 0.02% 84.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34304-34311 144 0.17% 84.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34432-34439 2 0.00% 84.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34560-34567 147 0.17% 84.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34816-34823 269 0.31% 84.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::34944-34951 1 0.00% 84.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35072-35079 87 0.10% 85.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35136-35143 1 0.00% 85.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35328-35335 72 0.08% 85.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35456-35463 2 0.00% 85.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35584-35591 77 0.09% 85.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35712-35719 1 0.00% 85.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35840-35847 268 0.31% 85.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::35968-35975 1 0.00% 85.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36096-36103 81 0.09% 85.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36224-36231 2 0.00% 85.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36352-36359 77 0.09% 85.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36480-36487 1 0.00% 85.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36608-36615 144 0.17% 85.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36736-36743 2 0.00% 85.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36864-36871 338 0.39% 86.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::36992-36999 1 0.00% 86.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37120-37127 91 0.11% 86.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37248-37255 1 0.00% 86.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37376-37383 83 0.10% 86.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37504-37511 2 0.00% 86.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37568-37575 1 0.00% 86.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37632-37639 11 0.01% 86.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37888-37895 404 0.47% 86.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::37952-37959 1 0.00% 86.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38016-38023 2 0.00% 86.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38144-38151 15 0.02% 86.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38272-38279 1 0.00% 86.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38336-38343 1 0.00% 86.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38400-38407 77 0.09% 87.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38528-38535 1 0.00% 87.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38592-38599 1 0.00% 87.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38656-38663 84 0.10% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38720-38727 1 0.00% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38912-38919 401 0.47% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::38976-38983 1 0.00% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39040-39047 2 0.00% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39104-39111 1 0.00% 87.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39168-39175 77 0.09% 87.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39232-39239 1 0.00% 87.73% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39424-39431 130 0.15% 87.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39552-39559 1 0.00% 87.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39680-39687 15 0.02% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39808-39815 1 0.00% 87.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::39936-39943 348 0.40% 88.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40064-40071 3 0.00% 88.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40192-40199 71 0.08% 88.39% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40448-40455 86 0.10% 88.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40576-40583 3 0.00% 88.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40640-40647 1 0.00% 88.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40704-40711 78 0.09% 88.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::40960-40967 387 0.45% 89.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41152-41159 2 0.00% 89.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41216-41223 78 0.09% 89.12% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41344-41351 2 0.00% 89.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41408-41415 1 0.00% 89.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41472-41479 83 0.10% 89.22% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41728-41735 72 0.08% 89.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41856-41863 3 0.00% 89.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::41984-41991 347 0.40% 89.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42112-42119 2 0.00% 89.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42240-42247 18 0.02% 89.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42368-42375 1 0.00% 89.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42496-42503 133 0.15% 89.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42624-42631 3 0.00% 89.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42688-42695 1 0.00% 89.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42752-42759 79 0.09% 89.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::42816-42823 1 0.00% 89.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43008-43015 399 0.46% 90.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43264-43271 82 0.10% 90.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43520-43527 76 0.09% 90.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43648-43655 2 0.00% 90.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43776-43783 20 0.02% 90.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44032-44039 403 0.47% 91.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44288-44295 10 0.01% 91.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49664-49671 1 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49728-49735 1 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49856-49863 1 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::49920-49927 1 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50240-50247 1 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50368-50375 2 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50496-50503 1 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50560-50567 2 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50624-50631 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50688-50695 2 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50752-50759 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::50944-50951 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51072-51079 1 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51136-51143 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51200-51207 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51264-51271 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51392-51399 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation
> system.physmem.totQLat 365610387500 # Total ticks spent queuing
> system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks
> system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
> system.physmem.busUtil 3.00 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing
> system.physmem.readRowHits 14986740 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93410 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes
> system.physmem.avgGap 158714.15 # Average gap between requests
> system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state
443c755
< system.membus.throughput 54917647 # Throughput (bytes/s)
---
> system.membus.throughput 54899945 # Throughput (bytes/s)
448,454c760,766
< system.membus.trans_dist::Writeback 59118 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
< system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
< system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::Writeback 59125 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution
> system.membus.trans_dist::ReadExReq 131442 # Transaction distribution
> system.membus.trans_dist::ReadExResp 131442 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes)
458,459c770,771
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes)
462,463c774,775
< system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes)
467,468c779,780
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes)
471,472c783,784
< system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 138629141 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 138630105 # Total data (bytes)
474c786
< system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks)
478c790
< system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks)
482c794
< system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks)
484c796
< system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks)
486c798
< system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks)
494,496c806,808
< system.iobus.throughput 48301509 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
< system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
---
> system.iobus.throughput 48285606 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution
> system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution
500c812
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
522c834
< system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 2382942 # Packet count per connected master and slave (bytes)
525c837
< system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 32267358 # Packet count per connected master and slave (bytes)
527c839
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
549c861
< system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.tot_pkt_size_system.bridge.master::total 2390301 # Cumulative packet size per connected master and slave (bytes)
552,553c864,865
< system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 121927961 # Total data (bytes)
---
> system.iobus.tot_pkt_size::total 121927965 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 121927965 # Total data (bytes)
556c868
< system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
602c914
< system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks)
604c916
< system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks)
606,610c918,922
< system.cpu.branchPred.lookups 14390442 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14384905 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits
612,614c924,926
< system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions.
617,620c929,932
< system.cpu.dtb.read_hits 51188083 # DTB read hits
< system.cpu.dtb.read_misses 64353 # DTB read misses
< system.cpu.dtb.write_hits 11697459 # DTB write hits
< system.cpu.dtb.write_misses 15788 # DTB write misses
---
> system.cpu.dtb.read_hits 51179212 # DTB read hits
> system.cpu.dtb.read_misses 64531 # DTB read misses
> system.cpu.dtb.write_hits 11698539 # DTB write hits
> system.cpu.dtb.write_misses 15837 # DTB write misses
625,627c937,939
< system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
629,631c941,943
< system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 51252436 # DTB read accesses
< system.cpu.dtb.write_accesses 11713247 # DTB write accesses
---
> system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 51243743 # DTB read accesses
> system.cpu.dtb.write_accesses 11714376 # DTB write accesses
633,637c945,949
< system.cpu.dtb.hits 62885542 # DTB hits
< system.cpu.dtb.misses 80141 # DTB misses
< system.cpu.dtb.accesses 62965683 # DTB accesses
< system.cpu.itb.inst_hits 11520428 # ITB inst hits
< system.cpu.itb.inst_misses 11439 # ITB inst misses
---
> system.cpu.dtb.hits 62877751 # DTB hits
> system.cpu.dtb.misses 80368 # DTB misses
> system.cpu.dtb.accesses 62958119 # DTB accesses
> system.cpu.itb.inst_hits 11513998 # ITB inst hits
> system.cpu.itb.inst_misses 11344 # ITB inst misses
646c958
< system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB
650c962
< system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions
653,657c965,969
< system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
< system.cpu.itb.hits 11520428 # DTB hits
< system.cpu.itb.misses 11439 # DTB misses
< system.cpu.itb.accesses 11531867 # DTB accesses
< system.cpu.numCycles 473080437 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 11525342 # ITB inst accesses
> system.cpu.itb.hits 11513998 # DTB hits
> system.cpu.itb.misses 11344 # DTB misses
> system.cpu.itb.accesses 11525342 # DTB accesses
> system.cpu.numCycles 474882944 # number of cpu cycles simulated
660,677c972,989
< system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total)
679,687c991,999
< system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total)
691,736c1003,1048
< system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle
738,746c1050,1058
< system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle
750c1062
< system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle
752,753c1064,1065
< system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available
781,782c1093,1094
< system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available
786,787c1098,1099
< system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued
800c1112
< system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued
804c1116
< system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued
811c1123
< system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued
813c1125
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued
815,816c1127,1128
< system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued
819,831c1131,1143
< system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
< system.cpu.iq.rate 0.259812 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued
> system.cpu.iq.rate 0.258795 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores
833,836c1145,1148
< system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed
839,840c1151,1152
< system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked
842,858c1154,1170
< system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute
860,868c1172,1180
< system.cpu.iew.exec_nop 221034 # number of nop insts executed
< system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
< system.cpu.iew.exec_branches 11474602 # Number of branches executed
< system.cpu.iew.exec_stores 12209197 # Number of stores executed
< system.cpu.iew.exec_rate 0.255417 # Inst execution rate
< system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 47030253 # num instructions producing a value
< system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 221869 # number of nop insts executed
> system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed
> system.cpu.iew.exec_branches 11475076 # Number of branches executed
> system.cpu.iew.exec_stores 12210518 # Number of stores executed
> system.cpu.iew.exec_rate 0.254424 # Inst execution rate
> system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 47026181 # num instructions producing a value
> system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value
870,871c1182,1183
< system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back
873,878c1185,1190
< system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle
880,888c1192,1200
< system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle
892,894c1204,1206
< system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 60455941 # Number of instructions committed
< system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 60456137 # Number of instructions committed
> system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed
896,899c1208,1211
< system.cpu.commit.refs 27385481 # Number of memory references committed
< system.cpu.commit.loads 15653838 # Number of loads committed
< system.cpu.commit.membars 403568 # Number of memory barriers committed
< system.cpu.commit.branches 9961054 # Number of branches committed
---
> system.cpu.commit.refs 27385736 # Number of memory references committed
> system.cpu.commit.loads 15654008 # Number of loads committed
> system.cpu.commit.membars 403573 # Number of memory barriers committed
> system.cpu.commit.branches 9961077 # Number of branches committed
901,903c1213,1215
< system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
< system.cpu.commit.function_calls 991205 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 68852562 # Number of committed integer instructions.
> system.cpu.commit.function_calls 991208 # Number of function calls committed.
> system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached
905,925c1217,1237
< system.cpu.rob.rob_reads 239241509 # The number of ROB reads
< system.cpu.rob.rob_writes 195965670 # The number of ROB writes
< system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 60305560 # Number of Instructions Simulated
< system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated
< system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 547265501 # number of integer regfile reads
< system.cpu.int_regfile_writes 87536109 # number of integer regfile writes
< system.cpu.fp_regfile_reads 8349 # number of floating regfile reads
< system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
< system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads
< system.cpu.misc_regfile_writes 831835 # number of misc regfile writes
< system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution
---
> system.cpu.rob.rob_reads 240636318 # The number of ROB reads
> system.cpu.rob.rob_writes 195934369 # The number of ROB writes
> system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 60305756 # Number of Instructions Simulated
> system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated
> system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 547208469 # number of integer regfile reads
> system.cpu.int_regfile_writes 87526188 # number of integer regfile writes
> system.cpu.fp_regfile_reads 8624 # number of floating regfile reads
> system.cpu.fp_regfile_writes 3008 # number of floating regfile writes
> system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads
> system.cpu.misc_regfile_writes 831837 # number of misc regfile writes
> system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution
928c1240
< system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution
930,946c1242,1258
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks)
948c1260
< system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1474440753 # Layer occupancy (ticks)
950c1262
< system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2550199081 # Layer occupancy (ticks)
952c1264
< system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 20321978 # Layer occupancy (ticks)
954c1266
< system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 74655295 # Layer occupancy (ticks)
956,1001c1268,1313
< system.cpu.icache.tags.replacements 979660 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits
< system.cpu.icache.overall_hits::total 10456897 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses
< system.cpu.icache.overall_misses::total 1059959 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked
---
> system.cpu.icache.tags.replacements 980741 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.579116 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 10449649 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 981253 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 10.649291 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 6918450250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.579116 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 10449649 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 10449649 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 10449649 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 10449649 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 10449649 # number of overall hits
> system.cpu.icache.overall_hits::total 10449649 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1060761 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1060761 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1060761 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses
> system.cpu.icache.overall_misses::total 1060761 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked
1003c1315
< system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked
1005c1317
< system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked
1009,1042c1321,1354
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 79476 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 79476 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 79476 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981285 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 981285 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 981285 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 981285 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 981285 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 981285 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587356987 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11587356987 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8658250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8658250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8658250 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 8658250 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085252 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.085252 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency
1048,1060c1360,1372
< system.cpu.l2cache.tags.replacements 64363 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 64371 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2490009951000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36925.668640 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.934134 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.003945 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.587712 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6237.500172 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.563441 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy
1062,1073c1374,1385
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits
1076,1134c1388,1446
< system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses
< system.cpu.l2cache.overall_misses::total 156307 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9919140742 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 112944 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 112944 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 53605 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 10777 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 967799 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 499975 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1532156 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 53605 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 10777 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 967799 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 499975 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1532156 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 10721 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 23115 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2915 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2915 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133198 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133198 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143919 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 12350 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143919 # number of overall misses
> system.cpu.l2cache.overall_misses::total 156313 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3352500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 233000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 906466500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 812441248 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1722493248 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465980 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 465980 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10117185994 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 10117185994 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3352500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 233000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 906466500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10929627242 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11839679242 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3352500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 233000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 906466500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10929627242 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11839679242 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53646 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10780 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 980149 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 397752 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1442327 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 607699 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 607699 # number of Writeback accesses(hits+misses)
1137,1190c1449,1502
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 644126 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1686096 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency
---
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 246142 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 246142 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53646 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 10780 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 980149 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 643894 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1688469 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53646 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 10780 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 980149 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 643894 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1688469 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000764 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000278 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012600 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026954 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016026 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986464 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986464 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541143 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.541143 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000764 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000278 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012600 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.223513 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.092577 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000764 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000278 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012600 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.223513 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.092577 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81768.292683 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77666.666667 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73398.097166 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75780.360787 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74518.418689 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.855918 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.855918 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75955.990285 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75955.990285 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75743.407407 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81768.292683 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77666.666667 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73398.097166 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75942.907066 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75743.407407 # average overall miss latency
1199,1201c1511,1513
< system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks
< system.cpu.l2cache.writebacks::total 59118 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 59125 # number of writebacks
> system.cpu.l2cache.writebacks::total 59125 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
1203,1204c1515,1516
< system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
1206,1207c1518,1519
< system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
1209,1287c1521,1599
< system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12339 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 23039 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2915 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2915 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133198 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133198 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12339 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143854 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 156237 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12339 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143854 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 156237 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2846500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 196000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 750549750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 675500748 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1429092998 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29153914 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29153914 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8456317006 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8456317006 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2846500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 196000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 750549750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9131817754 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9885410004 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2846500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 196000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 750549750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9131817754 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9885410004 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6187249 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166934965500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166941152749 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17442637817 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17442637817 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6187249 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377603317 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383790566 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026791 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015973 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986464 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986464 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541143 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541143 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.092532 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000764 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000278 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012589 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223413 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.092532 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342710 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342710 # average UpgradeReq mshr miss latency
1290,1301c1602,1613
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63486.816664 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63486.816664 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69426.829268 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60827.437394 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63479.762495 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63271.888247 # average overall mshr miss latency
1311,1317c1623,1629
< system.cpu.dcache.tags.replacements 643614 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 643382 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor
1320,1361c1632,1673
< system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits
< system.cpu.dcache.overall_hits::total 21018772 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses
< system.cpu.dcache.overall_misses::total 3700946 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits
> system.cpu.dcache.overall_hits::total 21010251 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses
> system.cpu.dcache.overall_misses::total 3701471 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses)
1364,1397c1676,1709
< system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked
1400,1465c1712,1777
< system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks
< system.cpu.dcache.writebacks::total 607864 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks
> system.cpu.dcache.writebacks::total 607699 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4970319128 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4970319128 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11601864538 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11601864538 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011000 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572183666 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16572183666 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572183666 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 16572183666 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328180000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328180000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841518267 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841518267 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169698267 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169698267 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026613 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026613 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024361 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024361 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047628 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047628 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency
1487,1490c1799,1802
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles