64,330c64,330
< system.l2c.replacements 64349 # number of replacements
< system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
< system.l2c.total_refs 1931844 # Total number of references to valid blocks.
< system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
< system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
< system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
< system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
< system.l2c.Writeback_hits::total 609524 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits
< system.l2c.overall_hits::cpu.inst 977692 # number of overall hits
< system.l2c.overall_hits::cpu.data 502174 # number of overall hits
< system.l2c.overall_hits::total 1576793 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses
< system.l2c.demand_misses::total 156282 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses
< system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
< system.l2c.overall_misses::cpu.inst 12366 # number of overall misses
< system.l2c.overall_misses::cpu.data 143849 # number of overall misses
< system.l2c.overall_misses::total 156282 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked::no_targets 0 # number of cycles access was blocked
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
< system.l2c.writebacks::writebacks 59057 # number of writebacks
< system.l2c.writebacks::total 59057 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.replacements 64349 # number of replacements
> system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143849 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses
> system.cpu.l2cache.overall_misses::total 156282 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks
> system.cpu.l2cache.writebacks::total 59057 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.l2c.replacements 64349 # number of replacements
< system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
< system.l2c.total_refs 1931844 # Total number of references to valid blocks.
< system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
< system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
< system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
< system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
< system.l2c.Writeback_hits::total 609524 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits
< system.l2c.overall_hits::cpu.inst 977692 # number of overall hits
< system.l2c.overall_hits::cpu.data 502174 # number of overall hits
< system.l2c.overall_hits::total 1576793 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses
< system.l2c.demand_misses::total 156282 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses
< system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
< system.l2c.overall_misses::cpu.inst 12366 # number of overall misses
< system.l2c.overall_misses::cpu.data 143849 # number of overall misses
< system.l2c.overall_misses::total 156282 # number of overall misses
< system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
< system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
< system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles
< system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses
< system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
< system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
< system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
< system.l2c.blocked::no_targets 0 # number of cycles access was blocked
< system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
< system.l2c.writebacks::writebacks 59057 # number of writebacks
< system.l2c.writebacks::total 59057 # number of writebacks
< system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
< system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
< system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits
< system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
< system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
< system.l2c.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
< system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
< system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
< system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
< system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.replacements 64349 # number of replacements
> system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 502174 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1576793 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 84751 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 12176 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143849 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 156282 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses
> system.cpu.l2cache.overall_misses::total 156282 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.l2cache.fast_writes 0 # number of fast writes performed
> system.cpu.l2cache.cache_copies 0 # number of cache copies performed
> system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks
> system.cpu.l2cache.writebacks::total 59057 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate