7,11c7,11
< host_inst_rate 62639 # Simulator instruction rate (inst/s)
< host_op_rate 80877 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2630163340 # Simulator tick rate (ticks/s)
< host_mem_usage 384244 # Number of bytes of host memory used
< host_seconds 951.15 # Real time elapsed on the host
---
> host_inst_rate 57858 # Simulator instruction rate (inst/s)
> host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
> host_mem_usage 387132 # Number of bytes of host memory used
> host_seconds 1029.75 # Real time elapsed on the host
14,32c14,63
< system.physmem.bytes_read 129658608 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 9585736 # Number of bytes written to this memory
< system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
< system.physmem.num_writes 856669 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
< system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
< system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
< system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
< system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
---
> system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
> system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
141a173
> system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
142a175
> system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
143a177
> system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
144a179
> system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
148a184
> system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
152a189
> system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
156a194
> system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
157a196
> system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
158a198
> system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
159a200
> system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
163a205
> system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
167a210
> system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
243a287
> system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
244a289
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
245a291
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
246a293
> system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
250a298
> system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
254a303
> system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
258a308
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
259a310
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
260a312
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
261a314
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
265a319
> system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
269a324
> system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
271a327
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
272a329
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
274a332
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
633a692
> system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
634a694
> system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
635a696
> system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
636a698
> system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
637a700
> system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
638a702
> system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
671a736
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
672a738
> system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
673a740
> system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
674a742
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
675a744
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
676a746
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
677a748
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
678a750
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
737a810
> system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
738a812
> system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
739a814
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
740a816
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
741a818
> system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
742a820
> system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
743a822
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
744a824
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
745a826
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
746a828
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
747a830
> system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
748a832
> system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
799a884
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
800a886
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
801a888
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
802a890
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
803a892
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
804a894
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
805a896
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
806a898
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
807a900
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
808a902
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
809a904
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
810a906
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
811a908
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
812a910
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
813a912
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
833a933
> system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
834a935
> system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< host_inst_rate 62639 # Simulator instruction rate (inst/s)
< host_op_rate 80877 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2630163340 # Simulator tick rate (ticks/s)
< host_mem_usage 384244 # Number of bytes of host memory used
< host_seconds 951.15 # Real time elapsed on the host
---
> host_inst_rate 57858 # Simulator instruction rate (inst/s)
> host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
> host_mem_usage 387132 # Number of bytes of host memory used
> host_seconds 1029.75 # Real time elapsed on the host
14,32c14,63
< system.physmem.bytes_read 129658608 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 9585736 # Number of bytes written to this memory
< system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
< system.physmem.num_writes 856669 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
< system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
< system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
< system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
< system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
---
> system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
> system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
> system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
> system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
> system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
141a173
> system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
142a175
> system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
143a177
> system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
144a179
> system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
148a184
> system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
152a189
> system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
156a194
> system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
157a196
> system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
158a198
> system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
159a200
> system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
163a205
> system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
167a210
> system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
243a287
> system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
244a289
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
245a291
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
246a293
> system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
250a298
> system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
254a303
> system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
258a308
> system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
259a310
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
260a312
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
261a314
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
265a319
> system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
269a324
> system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
271a327
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
272a329
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
274a332
> system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
633a692
> system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
634a694
> system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
635a696
> system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
636a698
> system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
637a700
> system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
638a702
> system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
671a736
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
672a738
> system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
673a740
> system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
674a742
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
675a744
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
676a746
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
677a748
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
678a750
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
737a810
> system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
738a812
> system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
739a814
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
740a816
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
741a818
> system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
742a820
> system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
743a822
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
744a824
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
745a826
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
746a828
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
747a830
> system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
748a832
> system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
799a884
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
800a886
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
801a888
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
802a890
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
803a892
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
804a894
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
805a896
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
806a898
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
807a900
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
808a902
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
809a904
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
810a906
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
811a908
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
812a910
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
813a912
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
833a933
> system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
834a935
> system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency