7,11c7,11
< host_inst_rate 116306 # Simulator instruction rate (inst/s)
< host_op_rate 141069 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2913147103 # Simulator tick rate (ticks/s)
< host_mem_usage 578076 # Number of bytes of host memory used
< host_seconds 972.44 # Real time elapsed on the host
---
> host_inst_rate 70501 # Simulator instruction rate (inst/s)
> host_op_rate 85511 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1765850548 # Simulator tick rate (ticks/s)
> host_mem_usage 578080 # Number of bytes of host memory used
> host_seconds 1604.25 # Real time elapsed on the host
432c432
< system.cpu.dtb.read_hits 25410889 # DTB read hits
---
> system.cpu.dtb.read_hits 25410890 # DTB read hits
434c434
< system.cpu.dtb.write_hits 19865162 # DTB write hits
---
> system.cpu.dtb.write_hits 19865163 # DTB write hits
445,446c445,446
< system.cpu.dtb.read_accesses 25473629 # DTB read accesses
< system.cpu.dtb.write_accesses 19874790 # DTB write accesses
---
> system.cpu.dtb.read_accesses 25473630 # DTB read accesses
> system.cpu.dtb.write_accesses 19874791 # DTB write accesses
448c448
< system.cpu.dtb.hits 45276051 # DTB hits
---
> system.cpu.dtb.hits 45276053 # DTB hits
450c450
< system.cpu.dtb.accesses 45348419 # DTB accesses
---
> system.cpu.dtb.accesses 45348421 # DTB accesses
554c554
< system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss
568c568
< system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total)
572c572
< system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total)
579c579
< system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total)
582c582
< system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle
592c592
< system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle
623c623
< system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle
627,630c627,630
< system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle
639c639
< system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle
712c712
< system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads
756,757c756,757
< system.cpu.iew.wb_producers 63237138 # num instructions producing a value
< system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 63237137 # num instructions producing a value
> system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value
763c763
< system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle
767,768c767,768
< system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle
773c773
< system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle
775c775
< system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle
779c779
< system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle
825,826c825,826
< system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 389119867 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 389119868 # The number of ROB reads
829c829
< system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling
837c837
< system.cpu.int_regfile_reads 155524958 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 155524954 # number of integer regfile reads
841c841
< system.cpu.cc_regfile_reads 502156058 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads
843c843
< system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads
847c847
< system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
849c849
< system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks.
859,864c859,864
< system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits
871,874c871,874
< system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits
< system.cpu.dcache.overall_hits::total 39152130 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits
> system.cpu.dcache.overall_hits::total 39152132 # number of overall hits
901,904c901,904
< system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses)
911,914c911,914
< system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses
< host_inst_rate 116306 # Simulator instruction rate (inst/s)
< host_op_rate 141069 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2913147103 # Simulator tick rate (ticks/s)
< host_mem_usage 578076 # Number of bytes of host memory used
< host_seconds 972.44 # Real time elapsed on the host
---
> host_inst_rate 70501 # Simulator instruction rate (inst/s)
> host_op_rate 85511 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1765850548 # Simulator tick rate (ticks/s)
> host_mem_usage 578080 # Number of bytes of host memory used
> host_seconds 1604.25 # Real time elapsed on the host
432c432
< system.cpu.dtb.read_hits 25410889 # DTB read hits
---
> system.cpu.dtb.read_hits 25410890 # DTB read hits
434c434
< system.cpu.dtb.write_hits 19865162 # DTB write hits
---
> system.cpu.dtb.write_hits 19865163 # DTB write hits
445,446c445,446
< system.cpu.dtb.read_accesses 25473629 # DTB read accesses
< system.cpu.dtb.write_accesses 19874790 # DTB write accesses
---
> system.cpu.dtb.read_accesses 25473630 # DTB read accesses
> system.cpu.dtb.write_accesses 19874791 # DTB write accesses
448c448
< system.cpu.dtb.hits 45276051 # DTB hits
---
> system.cpu.dtb.hits 45276053 # DTB hits
450c450
< system.cpu.dtb.accesses 45348419 # DTB accesses
---
> system.cpu.dtb.accesses 45348421 # DTB accesses
554c554
< system.cpu.fetch.icacheStallCycles 104963925 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss
568c568
< system.cpu.fetch.rateDist::samples 270560619 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total)
572c572
< system.cpu.fetch.rateDist::0 171637462 63.44% 63.44% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total)
579c579
< system.cpu.fetch.rateDist::total 270560619 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total)
582c582
< system.cpu.decode.IdleCycles 77946486 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle
592c592
< system.cpu.rename.IdleCycles 83703987 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle
623c623
< system.cpu.iq.issued_per_cycle::samples 270560619 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle
627,630c627,630
< system.cpu.iq.issued_per_cycle::0 182379690 67.41% 67.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45219626 16.71% 84.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 31881926 11.78% 95.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10262341 3.79% 99.70% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle
639c639
< system.cpu.iq.issued_per_cycle::total 270560619 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle
712c712
< system.cpu.iq.int_inst_queue_reads 579270173 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads
756,757c756,757
< system.cpu.iew.wb_producers 63237138 # num instructions producing a value
< system.cpu.iew.wb_consumers 95708451 # num instructions consuming a value
---
> system.cpu.iew.wb_producers 63237137 # num instructions producing a value
> system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value
763c763
< system.cpu.commit.committed_per_cycle::samples 267668720 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle
767,768c767,768
< system.cpu.commit.committed_per_cycle::0 194241015 72.57% 72.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43280699 16.17% 88.74% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle
773c773
< system.cpu.commit.committed_per_cycle::6 798347 0.30% 99.45% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle
775c775
< system.cpu.commit.committed_per_cycle::8 1072344 0.40% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle
779c779
< system.cpu.commit.committed_per_cycle::total 267668720 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle
825,826c825,826
< system.cpu.commit.bw_lim_events 1072344 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 389119867 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 389119868 # The number of ROB reads
829c829
< system.cpu.idleCycles 7863332 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling
837c837
< system.cpu.int_regfile_reads 155524958 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 155524954 # number of integer regfile reads
841c841
< system.cpu.cc_regfile_reads 502156058 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads
843c843
< system.cpu.misc_regfile_reads 347863698 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads
847c847
< system.cpu.dcache.tags.total_refs 40056709 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks.
849c849
< system.cpu.dcache.tags.avg_refs 47.728662 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks.
859,864c859,864
< system.cpu.dcache.tags.tag_accesses 179125101 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179125101 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23264147 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23264147 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15542285 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15542285 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits
871,874c871,874
< system.cpu.dcache.demand_hits::cpu.data 38806432 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38806432 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39152130 # number of overall hits
< system.cpu.dcache.overall_hits::total 39152130 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits
> system.cpu.dcache.overall_hits::total 39152132 # number of overall hits
901,904c901,904
< system.cpu.dcache.ReadReq_accesses::cpu.data 23969281 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 23969281 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19149712 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19149712 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses)
911,914c911,914
< system.cpu.dcache.demand_accesses::cpu.data 43118993 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43118993 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43642403 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43642403 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses