3,5c3,5
< sim_seconds 2.832913 # Number of seconds simulated
< sim_ticks 2832912592000 # Number of ticks simulated
< final_tick 2832912592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.832892 # Number of seconds simulated
> sim_ticks 2832892490000 # Number of ticks simulated
> final_tick 2832892490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 98871 # Simulator instruction rate (inst/s)
< host_op_rate 119922 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2476970660 # Simulator tick rate (ticks/s)
< host_mem_usage 585504 # Number of bytes of host memory used
< host_seconds 1143.70 # Real time elapsed on the host
< sim_insts 113079343 # Number of instructions simulated
< sim_ops 137154534 # Number of ops (including micro ops) simulated
---
> host_inst_rate 124603 # Simulator instruction rate (inst/s)
> host_op_rate 151132 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3121592879 # Simulator tick rate (ticks/s)
> host_mem_usage 587312 # Number of bytes of host memory used
> host_seconds 907.52 # Real time elapsed on the host
> sim_insts 113079496 # Number of instructions simulated
> sim_ops 137154742 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1316096 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1315968 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9383464 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10702120 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1316096 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1316096 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 7997312 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10702248 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1315968 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1315968 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 7997504 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 8014836 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8015028 # Number of bytes written to this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 22811 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 22809 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 147137 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 169988 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 124958 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 169990 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 124961 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 129339 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 129342 # Number of write requests responded to by this memory
38,39c38,39
< system.physmem.bw_read::cpu.inst 464573 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3312212 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 464532 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3312326 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 3777780 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 464573 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 464573 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2823000 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3777852 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 464532 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 464532 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2823088 # Write bandwidth from this memory (bytes/s)
46,47c46,47
< system.physmem.bw_write::total 2829186 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2823000 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2829274 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2823088 # Total bandwidth to/from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_total::cpu.inst 464573 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3318398 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 464532 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3318512 # Total bandwidth to/from this memory (bytes/s)
53,63c53,63
< system.physmem.bw_total::total 6606966 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 169989 # Number of read requests accepted
< system.physmem.writeReqs 129339 # Number of write requests accepted
< system.physmem.readBursts 169989 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 129339 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10867584 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8027584 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10702184 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8014836 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::total 6607125 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 169991 # Number of read requests accepted
> system.physmem.writeReqs 129342 # Number of write requests accepted
> system.physmem.readBursts 169991 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 129342 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10867968 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10702312 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8015028 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue
65c65
< system.physmem.neitherReadNorWriteReqs 48490 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
67c67
< system.physmem.perBankRdBursts::1 10615 # Per bank write bursts
---
> system.physmem.perBankRdBursts::1 10614 # Per bank write bursts
72,76c72,76
< system.physmem.perBankRdBursts::6 10904 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11084 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10554 # Per bank write bursts
< system.physmem.perBankRdBursts::9 10523 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10030 # Per bank write bursts
---
> system.physmem.perBankRdBursts::6 10908 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11081 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10555 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10526 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10031 # Per bank write bursts
78,80c78,80
< system.physmem.perBankRdBursts::12 9967 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10661 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9878 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 9969 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10658 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9880 # Per bank write bursts
88,92c88,92
< system.physmem.perBankWrBursts::6 8077 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8182 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8055 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7911 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7496 # Per bank write bursts
---
> system.physmem.perBankWrBursts::6 8076 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8179 # Per bank write bursts
> system.physmem.perBankWrBursts::8 8056 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7908 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7497 # Per bank write bursts
95,96c95,96
< system.physmem.perBankWrBursts::13 8042 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7357 # Per bank write bursts
---
> system.physmem.perBankWrBursts::13 8041 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7359 # Per bank write bursts
100c100
< system.physmem.totGap 2832912360000 # Total gap between requests
---
> system.physmem.totGap 2832892258000 # Total gap between requests
107c107
< system.physmem.readPktSize::6 166437 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 166439 # Read request sizes (log2)
114,115c114,115
< system.physmem.writePktSize::6 124958 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 150468 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 124961 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see
117,118c117,118
< system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 725 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::2 2151 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 723 # What read queue length does an incoming req see
162,222c162,222
< system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6051 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6673 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6911 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7819 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 7306 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 8270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8353 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 9948 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7795 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7406 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6937 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6695 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 104 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 62097 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 304.283685 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 179.850271 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 324.574400 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 23280 37.49% 37.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14997 24.15% 61.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6479 10.43% 72.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3584 5.77% 77.85% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2530 4.07% 81.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1603 2.58% 84.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1574 2.53% 87.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1048 1.69% 88.72% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::15 1893 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2898 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6078 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 7072 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6757 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 7213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6984 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7664 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8718 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7565 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7876 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 8848 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 324 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 62068 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 304.427918 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 179.985587 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.629395 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 23230 37.43% 37.43% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 15016 24.19% 61.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6492 10.46% 72.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3585 5.78% 77.85% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2536 4.09% 81.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1572 2.53% 84.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1564 2.52% 86.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1071 1.73% 88.72% # Bytes accessed per row activation
224,228c224,228
< system.physmem.bytesPerActivate::total 62097 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6262 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 27.116097 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 564.155612 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6261 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::total 62068 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6143 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.640729 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 569.576579 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6142 99.98% 99.98% # Reads before turning the bus around for writes
230,266c230,268
< system.physmem.rdPerTurnAround::total 6262 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6262 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 20.030501 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.464444 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 12.039261 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5446 86.97% 86.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 116 1.85% 88.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 36 0.57% 89.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 167 2.67% 92.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 22 0.35% 92.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 138 2.20% 94.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 54 0.86% 95.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 12 0.19% 95.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 19 0.30% 95.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 16 0.26% 96.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 6 0.10% 96.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.05% 96.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 160 2.56% 98.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 6 0.10% 99.03% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 9 0.14% 99.17% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 25 0.40% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 2 0.03% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 1 0.02% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.05% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.02% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.02% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 13 0.21% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6262 # Writes before turning the bus around for reads
< system.physmem.totQLat 2134847750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5318710250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 849030000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12572.28 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6143 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6143 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.417874 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.493305 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.002502 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5451 88.74% 88.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 111 1.81% 90.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 34 0.55% 91.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 44 0.72% 91.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 33 0.54% 92.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 15 0.24% 92.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 54 0.88% 93.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 11 0.18% 93.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 132 2.15% 95.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 17 0.28% 96.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 5 0.08% 96.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 11 0.18% 96.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 78 1.27% 97.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 3 0.05% 97.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 5 0.08% 97.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 21 0.34% 98.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 92 1.50% 99.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.02% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 4 0.07% 99.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 9 0.15% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6143 # Writes before turning the bus around for reads
> system.physmem.totQLat 2131723500 # Total ticks spent queuing
> system.physmem.totMemAccLat 5315698500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 849060000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12553.43 # Average queueing delay per DRAM burst
268c270
< system.physmem.avgMemAccLat 31322.28 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31303.43 # Average memory access latency per DRAM burst
279,286c281,288
< system.physmem.readRowHits 139313 # Number of row buffer hits during reads
< system.physmem.writeRowHits 93826 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.79 # Row buffer hit rate for writes
< system.physmem.avgGap 9464241.10 # Average gap between requests
< system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 247680720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 135143250 # Energy for precharge commands per rank (pJ)
---
> system.physmem.readRowHits 139329 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93841 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes
> system.physmem.avgGap 9464015.86 # Average gap between requests
> system.physmem.pageHitRate 78.97 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 247484160 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 135036000 # Energy for precharge commands per rank (pJ)
288,295c290,297
< system.physmem_0.writeEnergy 421193520 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 83693103705 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1626331305750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1896556621545 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.472831 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2705407276500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states
---
> system.physmem_0.writeEnergy 421167600 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 83639897910 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1626363962250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1896534216840 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.470442 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2705464523500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states
297c299
< system.physmem_0.memoryStateTime::ACT 32908202000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32831633000 # Time in different power states
299,301c301,303
< system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 628212000 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 221749920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 120994500 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 628258800 # Energy for read commands per rank (pJ)
303,309c305,311
< system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 81799663455 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1627992218250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1896186400140 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.342145 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2708183660500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states
---
> system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 81914804595 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1627877202000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1896185011095 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.347174 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2707992537250 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states
311c313
< system.physmem_1.memoryStateTime::ACT 30129768250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30298312750 # Time in different power states
331,335c333,337
< system.cpu.branchPred.lookups 46857763 # Number of BP lookups
< system.cpu.branchPred.condPredicted 24018162 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1233841 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 29502900 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 21322687 # Number of BTB hits
---
> system.cpu.branchPred.lookups 46858247 # Number of BP lookups
> system.cpu.branchPred.condPredicted 24018458 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1233894 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 29504756 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 21322919 # Number of BTB hits
337,339c339,341
< system.cpu.branchPred.BTBHitPct 72.273190 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 11723693 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 33902 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.269430 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 11723897 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 33908 # Number of incorrect RAS predictions.
370,378c372,380
< system.cpu.dtb.walker.walks 71876 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 71876 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29748 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22357 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 19771 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 52105 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 423.395068 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 2574.283993 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-4095 50327 96.59% 96.59% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walks 71892 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 71892 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29751 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22366 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 19775 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 52117 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 422.184700 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 2564.754173 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-4095 50340 96.59% 96.59% # Table walker wait (enqueue to first request) latency
380c382
< system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.01% 98.72% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walkWaitTime::8192-12287 526 1.01% 98.72% # Table walker wait (enqueue to first request) latency
383c385
< system.cpu.dtb.walker.walkWaitTime::20480-24575 221 0.42% 99.89% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency
386,387c388,389
< system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
389c391
< system.cpu.dtb.walker.walkWaitTime::45056-49151 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
394,399c396,401
< system.cpu.dtb.walker.walkWaitTime::total 52105 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 17499 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 9158.153521 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 8139.378931 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-32767 17316 98.95% 98.95% # Table walker service (enqueue to completion) latency
---
> system.cpu.dtb.walker.walkWaitTime::total 52117 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 17509 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 11528.471072 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 9159.485910 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 8140.517404 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-32767 17326 98.95% 98.95% # Table walker service (enqueue to completion) latency
403,410c405,412
< system.cpu.dtb.walker.walkCompletionTime::total 17499 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 131377054816 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.616890 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.493493 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 131322424316 99.96% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 37436500 0.03% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 7011000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 6169000 0.00% 100.00% # Table walker pending requests distribution
---
> system.cpu.dtb.walker.walkCompletionTime::total 17509 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 131356952816 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.616906 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.493482 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 131302352316 99.96% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 37456000 0.03% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 6990000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 6140500 0.00% 100.00% # Table walker pending requests distribution
416,420c418,422
< system.cpu.dtb.walker.walksPending::total 131377054816 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6345 82.32% 82.32% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1363 17.68% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7708 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71876 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walksPending::total 131356952816 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6353 82.36% 82.36% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1361 17.64% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7714 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71892 # Table walker requests started/completed, data/inst
422,423c424,425
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71876 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7708 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71892 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7714 # Table walker requests started/completed, data/inst
425,426c427,428
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7708 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 79584 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7714 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 79606 # Table walker requests started/completed, data/inst
429,432c431,434
< system.cpu.dtb.read_hits 25445789 # DTB read hits
< system.cpu.dtb.read_misses 61974 # DTB read misses
< system.cpu.dtb.write_hits 19906281 # DTB write hits
< system.cpu.dtb.write_misses 9902 # DTB write misses
---
> system.cpu.dtb.read_hits 25445841 # DTB read hits
> system.cpu.dtb.read_misses 61989 # DTB read misses
> system.cpu.dtb.write_hits 19906354 # DTB write hits
> system.cpu.dtb.write_misses 9903 # DTB write misses
442,443c444,445
< system.cpu.dtb.read_accesses 25507763 # DTB read accesses
< system.cpu.dtb.write_accesses 19916183 # DTB write accesses
---
> system.cpu.dtb.read_accesses 25507830 # DTB read accesses
> system.cpu.dtb.write_accesses 19916257 # DTB write accesses
445,447c447,449
< system.cpu.dtb.hits 45352070 # DTB hits
< system.cpu.dtb.misses 71876 # DTB misses
< system.cpu.dtb.accesses 45423946 # DTB accesses
---
> system.cpu.dtb.hits 45352195 # DTB hits
> system.cpu.dtb.misses 71892 # DTB misses
> system.cpu.dtb.accesses 45424087 # DTB accesses
477,480c479,482
< system.cpu.itb.walker.walks 11893 # Table walker walks requested
< system.cpu.itb.walker.walksShort 11893 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate
---
> system.cpu.itb.walker.walks 11896 # Table walker walks requested
> system.cpu.itb.walker.walksShort 11896 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 3936 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 7739 # Level at which table walker walks with short descriptors terminate
482,488c484,490
< system.cpu.itb.walker.walkWaitTime::samples 11672 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 618.017478 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 2885.502200 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-4095 11116 95.24% 95.24% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 98.24% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.77% # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walkWaitTime::samples 11675 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 618.158458 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 2886.319815 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-4095 11119 95.24% 95.24% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::4096-8191 158 1.35% 96.59% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.24% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency
496,502c498,504
< system.cpu.itb.walker.walkWaitTime::total 11672 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3547 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 12874.259938 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 8701.526273 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-16383 2599 73.27% 73.27% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.09% 98.36% # Table walker service (enqueue to completion) latency
---
> system.cpu.itb.walker.walkWaitTime::total 11675 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3548 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 12874.295378 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 10192.055773 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 8701.296219 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.28% 73.28% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.08% 98.37% # Table walker service (enqueue to completion) latency
505,510c507,512
< system.cpu.itb.walker.walkCompletionTime::total 3547 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 24002810416 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.962951 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.189029 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 889895500 3.71% 3.71% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 23112364416 96.29% 100.00% # Table walker pending requests distribution
---
> system.cpu.itb.walker.walkCompletionTime::total 3548 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 23982708416 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.963466 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.187762 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 876788500 3.66% 3.66% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 23105369416 96.34% 100.00% # Table walker pending requests distribution
513,516c515,518
< system.cpu.itb.walker.walksPending::total 24002810416 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 3008 90.44% 90.44% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 318 9.56% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated
---
> system.cpu.itb.walker.walksPending::total 23982708416 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 3008 90.41% 90.41% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 319 9.59% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3327 # Table walker page sizes translated
518,519c520,521
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11893 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 11893 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11896 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 11896 # Table walker requests started/completed, data/inst
521,525c523,527
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 15219 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 66221269 # ITB inst hits
< system.cpu.itb.inst_misses 11893 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3327 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3327 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 15223 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 66221900 # ITB inst hits
> system.cpu.itb.inst_misses 11896 # ITB inst misses
534c536
< system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
538c540
< system.cpu.itb.perms_faults 2209 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions
541,545c543,547
< system.cpu.itb.inst_accesses 66233162 # ITB inst accesses
< system.cpu.itb.hits 66221269 # DTB hits
< system.cpu.itb.misses 11893 # DTB misses
< system.cpu.itb.accesses 66233162 # DTB accesses
< system.cpu.numCycles 278796094 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 66233796 # ITB inst accesses
> system.cpu.itb.hits 66221900 # DTB hits
> system.cpu.itb.misses 11896 # DTB misses
> system.cpu.itb.accesses 66233796 # DTB accesses
> system.cpu.numCycles 278773245 # number of cpu cycles simulated
548,557c550,559
< system.cpu.fetch.icacheStallCycles 104750737 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 184597310 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 46857763 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 33046380 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 161828011 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 6150220 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 189816 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 10180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 357136 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 560173 # Number of stall cycles due to pending quiesce instructions
---
> system.cpu.fetch.icacheStallCycles 104752235 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 184598573 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 46858247 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 33046816 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 161804794 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 6150362 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 189820 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 10294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 357135 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 560172 # Number of stall cycles due to pending quiesce instructions
559,564c561,566
< system.cpu.fetch.CacheLines 66221459 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1133676 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5180 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 270771349 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.831471 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.217911 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 66222091 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1133757 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5184 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 270749817 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.831543 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.217938 # Number of instructions fetched each cycle (Total)
566,569c568,571
< system.cpu.fetch.rateDist::0 171553381 63.36% 63.36% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 29224188 10.79% 74.15% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 14067085 5.20% 79.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55926695 20.65% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 171531140 63.35% 63.35% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 29224382 10.79% 74.15% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 14067275 5.20% 79.34% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 55927020 20.66% 100.00% # Number of instructions fetched each cycle (Total)
573,599c575,601
< system.cpu.fetch.rateDist::total 270771349 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.168072 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.662123 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 77850364 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 121893157 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 64586539 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3844068 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 2597221 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3423151 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 486287 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 157328219 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3698916 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 2597221 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 83695488 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 11783440 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 76673328 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62587040 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 33434832 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 146701505 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 957116 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 452960 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 63776 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 16375 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 30685156 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 150380164 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 678249075 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 164321181 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 270749817 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.168087 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.662182 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 77852001 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 121869294 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 64587229 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3844010 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 2597283 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3423147 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 486289 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 157329382 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3698909 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 2597283 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 83697131 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 11783559 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 76650059 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 62587653 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 33434132 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 146702491 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 957120 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 451934 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 63799 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 16325 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 30684565 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 150381225 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 678253528 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 164322158 # Number of integer rename lookups
601,619c603,621
< system.cpu.rename.CommittedMaps 141709271 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 8670890 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2840534 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2644382 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13862021 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26394587 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21292605 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1688978 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2214312 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 143440731 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2121629 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 143228275 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 270765 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 8407822 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14697300 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 125774 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 270771349 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.528964 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.865543 # Number of insts issued each cycle
---
> system.cpu.rename.CommittedMaps 141709530 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 8671692 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2840546 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2644403 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13862058 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26394800 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21292698 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1688864 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2213691 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 143441668 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2121624 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 143228772 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 270823 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 8408546 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14699465 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 125775 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 270749817 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.529008 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.865566 # Number of insts issued each cycle
621,625c623,627
< system.cpu.iq.issued_per_cycle::0 182535287 67.41% 67.41% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45134238 16.67% 84.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 32022031 11.83% 95.91% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10269230 3.79% 99.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 810530 0.30% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 182513589 67.41% 67.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45134220 16.67% 84.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 32022113 11.83% 95.91% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10269287 3.79% 99.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 810575 0.30% 100.00% # Number of insts issued each cycle
633c635
< system.cpu.iq.issued_per_cycle::total 270771349 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 270749817 # Number of insts issued each cycle
635,665c637,667
< system.cpu.iq.fu_full::IntAlu 7336420 32.74% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 5631672 25.13% 57.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9443165 42.14% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 7336339 32.73% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 32 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 5631595 25.13% 57.86% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 9443725 42.14% 100.00% # attempts to use FU when none available
669c671
< system.cpu.iq.FU_type_0::IntAlu 95929589 66.98% 66.98% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 95929894 66.98% 66.98% # Type of FU issued
698,699c700,701
< system.cpu.iq.FU_type_0::MemRead 26176168 18.28% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 20997807 14.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26176243 18.28% 85.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 20997924 14.66% 100.00% # Type of FU issued
702,708c704,710
< system.cpu.iq.FU_type_0::total 143228275 # Type of FU issued
< system.cpu.iq.rate 0.513738 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 22411289 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.156473 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 579874368 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 153975557 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 140119306 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 143228772 # Type of FU issued
> system.cpu.iq.rate 0.513782 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 22411691 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.156475 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 579854290 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 153977213 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 140119725 # Number of integer instruction queue wakeup accesses
712c714
< system.cpu.iq.int_alu_accesses 165613882 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 165614781 # Number of integer alu accesses
714c716
< system.cpu.iew.lsq.thread0.forwLoads 322775 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 322762 # Number of loads that had data forwarded from stores
716,719c718,721
< system.cpu.iew.lsq.thread0.squashedLoads 1495918 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18543 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 704297 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1496089 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 504 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18542 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 704390 # Number of stores squashed
722,723c724,725
< system.cpu.iew.lsq.thread0.rescheduledLoads 87804 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 6457 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 87859 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 6368 # Number of times an access to memory failed due to the cache being blocked
725,728c727,730
< system.cpu.iew.iewSquashCycles 2597221 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 1240950 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 535645 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 145763292 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 2597283 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1242021 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 536402 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 145764225 # Number of instructions dispatched to IQ
730,741c732,743
< system.cpu.iew.iewDispLoadInsts 26394587 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21292605 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 17982 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 501480 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18543 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 317940 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 471176 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 789116 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 142285522 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25773547 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 870984 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 26394800 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21292698 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1096198 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 17994 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 502218 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18542 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 317968 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 471203 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 789171 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 142285969 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25773594 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 871017 # Number of squashed instructions skipped in execute
743,752c745,754
< system.cpu.iew.exec_nop 200932 # number of nop insts executed
< system.cpu.iew.exec_refs 46642466 # number of memory reference insts executed
< system.cpu.iew.exec_branches 26501161 # Number of branches executed
< system.cpu.iew.exec_stores 20868919 # Number of stores executed
< system.cpu.iew.exec_rate 0.510357 # Inst execution rate
< system.cpu.iew.wb_sent 141899022 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 140130673 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 63222272 # num instructions producing a value
< system.cpu.iew.wb_consumers 95712658 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.502628 # insts written-back per cycle
---
> system.cpu.iew.exec_nop 200933 # number of nop insts executed
> system.cpu.iew.exec_refs 46642596 # number of memory reference insts executed
> system.cpu.iew.exec_branches 26501312 # Number of branches executed
> system.cpu.iew.exec_stores 20869002 # Number of stores executed
> system.cpu.iew.exec_rate 0.510400 # Inst execution rate
> system.cpu.iew.wb_sent 141899463 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 140131092 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 63222174 # num instructions producing a value
> system.cpu.iew.wb_consumers 95712525 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.502671 # insts written-back per cycle
754,759c756,761
< system.cpu.commit.commitSquashedInsts 7606616 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1995855 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 755952 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 267837215 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.512660 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.117818 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7607261 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1995849 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 755996 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 267815570 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.512702 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.117847 # Number of insts commited each cycle
761,769c763,771
< system.cpu.commit.committed_per_cycle::0 194442706 72.60% 72.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43232016 16.14% 88.74% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 15468771 5.78% 94.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4394333 1.64% 96.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 6341721 2.37% 98.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1685699 0.63% 99.15% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 801066 0.30% 99.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 412117 0.15% 99.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1058786 0.40% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 194420599 72.59% 72.59% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43232205 16.14% 88.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 15469123 5.78% 94.51% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4394347 1.64% 96.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 6341720 2.37% 98.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1685703 0.63% 99.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 801057 0.30% 99.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 412110 0.15% 99.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1058706 0.40% 100.00% # Number of insts commited each cycle
773,775c775,777
< system.cpu.commit.committed_per_cycle::total 267837215 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 113234248 # Number of instructions committed
< system.cpu.commit.committedOps 137309439 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 267815570 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 113234401 # Number of instructions committed
> system.cpu.commit.committedOps 137309647 # Number of ops (including micro ops) committed
777,780c779,782
< system.cpu.commit.refs 45486977 # Number of memory references committed
< system.cpu.commit.loads 24898669 # Number of loads committed
< system.cpu.commit.membars 814916 # Number of memory barriers committed
< system.cpu.commit.branches 26015904 # Number of branches committed
---
> system.cpu.commit.refs 45487019 # Number of memory references committed
> system.cpu.commit.loads 24898711 # Number of loads committed
> system.cpu.commit.membars 814912 # Number of memory barriers committed
> system.cpu.commit.branches 26016004 # Number of branches committed
782,783c784,785
< system.cpu.commit.int_insts 120139692 # Number of committed integer instructions.
< system.cpu.commit.function_calls 4881505 # Number of function calls committed.
---
> system.cpu.commit.int_insts 120139877 # Number of committed integer instructions.
> system.cpu.commit.function_calls 4881537 # Number of function calls committed.
785c787
< system.cpu.commit.op_class_0::IntAlu 91701155 66.78% 66.78% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 91701321 66.78% 66.78% # Class of committed instruction
814c816
< system.cpu.commit.op_class_0::MemRead 24898669 18.13% 85.01% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 24898711 18.13% 85.01% # Class of committed instruction
818,832c820,834
< system.cpu.commit.op_class_0::total 137309439 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1058786 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 389537878 # The number of ROB reads
< system.cpu.rob.rob_writes 292763814 # The number of ROB writes
< system.cpu.timesIdled 892824 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 8024745 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 5387029091 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 113079343 # Number of Instructions Simulated
< system.cpu.committedOps 137154534 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.465491 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.465491 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.405599 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.405599 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 155725297 # number of integer regfile reads
< system.cpu.int_regfile_writes 88564293 # number of integer regfile writes
---
> system.cpu.commit.op_class_0::total 137309647 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1058706 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 389516895 # The number of ROB reads
> system.cpu.rob.rob_writes 292765635 # The number of ROB writes
> system.cpu.timesIdled 892830 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 8023428 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 5387011736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 113079496 # Number of Instructions Simulated
> system.cpu.committedOps 137154742 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.465286 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.465286 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.405633 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.405633 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 155725818 # number of integer regfile reads
> system.cpu.int_regfile_writes 88564532 # number of integer regfile writes
835,838c837,840
< system.cpu.cc_regfile_reads 502644821 # number of cc regfile reads
< system.cpu.cc_regfile_writes 53156150 # number of cc regfile writes
< system.cpu.misc_regfile_reads 348441241 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1521640 # number of misc regfile writes
---
> system.cpu.cc_regfile_reads 502646310 # number of cc regfile reads
> system.cpu.cc_regfile_writes 53156218 # number of cc regfile writes
> system.cpu.misc_regfile_reads 348169816 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1521639 # number of misc regfile writes
841c843
< system.cpu.dcache.tags.total_refs 40093226 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 40093288 # Total number of references to valid blocks.
843c845
< system.cpu.dcache.tags.avg_refs 47.851540 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 47.851614 # Average number of references to valid blocks.
853,862c855,864
< system.cpu.dcache.tags.tag_accesses 179262562 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179262562 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23296906 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23296906 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15545467 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15545467 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 345973 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 345973 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 441682 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 441682 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 179262934 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179262934 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23297038 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23297038 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15545406 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15545406 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 441679 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 441679 # number of LoadLockedReq hits
865,876c867,878
< system.cpu.dcache.demand_hits::cpu.data 38842373 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38842373 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39188346 # number of overall hits
< system.cpu.dcache.overall_hits::total 39188346 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 708692 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 708692 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3602140 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3602140 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 177879 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 177879 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 27097 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 27097 # number of LoadLockedReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 38842444 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38842444 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39188411 # number of overall hits
> system.cpu.dcache.overall_hits::total 39188411 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 708652 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 708652 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3602204 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3602204 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 177882 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 177882 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 27101 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 27101 # number of LoadLockedReq misses
879,902c881,904
< system.cpu.dcache.demand_misses::cpu.data 4310832 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4310832 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4488711 # number of overall misses
< system.cpu.dcache.overall_misses::total 4488711 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11726844500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11726844500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 232349107178 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373049000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 373049000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 244075951678 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 244075951678 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 244075951678 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 244075951678 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24005598 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24005598 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19147607 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19147607 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 523852 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 523852 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 4310856 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4310856 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4488738 # number of overall misses
> system.cpu.dcache.overall_misses::total 4488738 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11718587000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11718587000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 232348383185 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 232348383185 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373073000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 373073000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 244066970185 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 244066970185 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 244066970185 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 244066970185 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24005690 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24005690 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19147610 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19147610 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 523849 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 523849 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468780 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 468780 # number of LoadLockedReq accesses(hits+misses)
905,916c907,918
< system.cpu.dcache.demand_accesses::cpu.data 43153205 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43153205 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43677057 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43677057 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029522 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.029522 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188125 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.188125 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339560 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.339560 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057803 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057803 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 43153300 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43153300 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43677149 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43677149 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029520 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.029520 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188128 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.188128 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339567 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.339567 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057812 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057812 # miss rate for LoadLockedReq accesses
921,935c923,937
< system.cpu.dcache.overall_miss_rate::cpu.data 0.102770 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.102770 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56619.221458 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 54375.510403 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 870696 # number of cycles access was blocked
---
> system.cpu.dcache.overall_miss_rate::cpu.data 0.102771 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.102771 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16536.448073 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16536.448073 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64501.728160 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64501.728160 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.023394 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.023394 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56616.822781 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56616.822781 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54373.182437 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54373.182437 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 869617 # number of cycles access was blocked
937c939
< system.cpu.dcache.blocked::no_mshrs 6851 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 6831 # number of cycles access was blocked
939c941
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.090352 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.304494 # average number of cycles each access was blocked
943,960c945,962
< system.cpu.dcache.writebacks::writebacks 695416 # number of writebacks
< system.cpu.dcache.writebacks::total 695416 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295634 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 295634 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302552 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3302552 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18703 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 18703 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3598186 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3598186 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3598186 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3598186 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413058 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 413058 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299588 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299588 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119604 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 119604 # number of SoftPFReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 695423 # number of writebacks
> system.cpu.dcache.writebacks::total 695423 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295601 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 295601 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302610 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3302610 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18707 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 18707 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3598211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3598211 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3598211 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3598211 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413051 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 413051 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299594 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299594 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119605 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 119605 # number of SoftPFReq MSHR misses
965,966c967,968
< system.cpu.dcache.demand_mshr_misses::cpu.data 712646 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 712646 # number of demand (read+write) MSHR misses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 712645 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 712645 # number of demand (read+write) MSHR misses
975,980c977,982
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391901000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391901000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972155480 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972155480 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1700460500 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1700460500 # number of SoftPFReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391361500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391361500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19958097481 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 19958097481 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699868500 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699868500 # number of SoftPFReq MSHR miss cycles
983,1000c985,1002
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26364056480 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26364056480 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064516980 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28064516980 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276327500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276327500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075770951 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075770951 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098451 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098451 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017207 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017207 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015646 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015646 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228316 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228316 # mshr miss rate for SoftPFReq accesses
---
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 295000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26349458981 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26349458981 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28049327481 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28049327481 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276320000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276320000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075778951 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075778951 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098951 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098951 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017206 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017206 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015647 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015647 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228320 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228320 # mshr miss rate for SoftPFReq accesses
1009,1014c1011,1016
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658 # average SoftPFReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15473.540798 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15473.540798 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66617.146809 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66617.146809 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14212.353162 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14212.353162 # average SoftPFReq mshr miss latency
1017,1028c1019,1030
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329 # average overall mshr uncacheable latency
---
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36974.172247 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36974.172247 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33703.006886 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33703.006886 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201622.923962 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.923962 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184005.037194 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184005.037194 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.691845 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.691845 # average overall mshr uncacheable latency
1030,1034c1032,1036
< system.cpu.icache.tags.replacements 1886675 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.154168 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 64239376 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1887187 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 34.039751 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 1886695 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.154169 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 64239998 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1887207 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 34.039720 # Average number of references to valid blocks.
1036c1038
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.154168 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.154169 # Average occupied blocks per requestor
1045,1070c1047,1072
< system.cpu.icache.tags.tag_accesses 68105664 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 68105664 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 64239376 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 64239376 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 64239376 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 64239376 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 64239376 # number of overall hits
< system.cpu.icache.overall_hits::total 64239376 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1979079 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1979079 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1979079 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1979079 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1979079 # number of overall misses
< system.cpu.icache.overall_misses::total 1979079 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28144068491 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28144068491 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28144068491 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28144068491 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28144068491 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28144068491 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 66218455 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 66218455 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 66218455 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 66218455 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 66218455 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 66218455 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 68106315 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 68106315 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 64239998 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 64239998 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 64239998 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 64239998 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 64239998 # number of overall hits
> system.cpu.icache.overall_hits::total 64239998 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1979089 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1979089 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1979089 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1979089 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1979089 # number of overall misses
> system.cpu.icache.overall_misses::total 1979089 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28142009491 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28142009491 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28142009491 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28142009491 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28142009491 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28142009491 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 66219087 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 66219087 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 66219087 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 66219087 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 66219087 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 66219087 # number of overall (read+write) accesses
1077,1083c1079,1085
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14220.790828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14220.790828 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 5080 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14219.678595 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14219.678595 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14219.678595 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14219.678595 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14219.678595 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14219.678595 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 4519 # number of cycles access was blocked
1085c1087
< system.cpu.icache.blocked::no_mshrs 162 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 161 # number of cycles access was blocked
1087c1089
< system.cpu.icache.avg_blocked_cycles::no_mshrs 31.358025 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.068323 # average number of cycles each access was blocked
1091,1104c1093,1106
< system.cpu.icache.writebacks::writebacks 1886675 # number of writebacks
< system.cpu.icache.writebacks::total 1886675 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91868 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 91868 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 91868 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 91868 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 91868 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 91868 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887211 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1887211 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1887211 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1887211 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1887211 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1887211 # number of overall MSHR misses
---
> system.cpu.icache.writebacks::writebacks 1886695 # number of writebacks
> system.cpu.icache.writebacks::total 1886695 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91859 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 91859 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 91859 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 91859 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 91859 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 91859 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1887230 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1887230 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1887230 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1887230 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1887230 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1887230 # number of overall MSHR misses
1109,1114c1111,1116
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25180995493 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25180995493 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25180995493 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25180995493 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25180995493 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25180995493 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25181096993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25181096993 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25181096993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25181096993 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25181096993 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25181096993 # number of overall MSHR miss cycles
1125,1130c1127,1132
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.967741 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.967741 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.967741 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.967741 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13342.887191 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13342.887191 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13342.887191 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13342.887191 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13342.887191 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13342.887191 # average overall mshr miss latency
1136,1140c1138,1142
< system.cpu.l2cache.tags.replacements 96487 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65023.312748 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4997676 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 161725 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 30.902309 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 96489 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65023.318666 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4997716 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 161727 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 30.902175 # Average number of references to valid blocks.
1142,1146c1144,1148
< system.cpu.l2cache.tags.occ_blocks::writebacks 49475.678025 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.897856 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.835471 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.602046 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.299351 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 49475.697069 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.897858 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 1.835458 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10343.578432 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.309849 # Average occupied blocks per requestor
1150c1152
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157831 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157830 # Average percentage of cache occupancy
1157,1160c1159,1162
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2890 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6640 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2891 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6633 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55534 # Occupied blocks per task id
1163,1171c1165,1173
< system.cpu.l2cache.tags.tag_accesses 44233161 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 44233161 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54581 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11841 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 66422 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 695416 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 695416 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1846676 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1846676 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.tag_accesses 44233569 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 44233569 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54592 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11842 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 66434 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 695423 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 695423 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1846694 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1846694 # number of WritebackClean hits
1176,1191c1178,1193
< system.cpu.l2cache.ReadExReq_hits::cpu.data 161568 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 161568 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867325 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1867325 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527485 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 527485 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 54581 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 11841 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1867325 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 689053 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2622800 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 54581 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 11841 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1867325 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 689053 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2622800 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 161572 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 161572 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1867345 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1867345 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527477 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 527477 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 54592 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 11842 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1867345 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 689049 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2622828 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 54592 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 11842 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1867345 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 689049 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2622828 # number of overall hits
1199,1204c1201,1206
< system.cpu.l2cache.ReadExReq_misses::cpu.data 135393 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 135393 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19844 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 19844 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13444 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 13444 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 135395 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 135395 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19842 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 19842 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13446 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 13446 # number of ReadSharedReq misses
1207,1209c1209,1211
< system.cpu.l2cache.demand_misses::cpu.inst 19844 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 148837 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 168710 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 19842 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 148841 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168712 # number of demand (read+write) misses
1212,1214c1214,1216
< system.cpu.l2cache.overall_misses::cpu.inst 19844 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 148837 # number of overall misses
< system.cpu.l2cache.overall_misses::total 168710 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 19842 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 148841 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168712 # number of overall misses
1218,1219c1220,1221
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2179500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 2179500 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2109500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 2109500 # number of UpgradeReq miss cycles
1222,1227c1224,1229
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17603720000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 17603720000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2626422000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 2626422000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1819515000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1819515000 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17597086000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 17597086000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2626275000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2626275000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1818483500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1818483500 # number of ReadSharedReq miss cycles
1230,1232c1232,1234
< system.cpu.l2cache.demand_miss_latency::cpu.inst 2626422000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 19423235000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22053800000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2626275000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 19415569500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22045987500 # number of demand (read+write) miss cycles
1235,1244c1237,1246
< system.cpu.l2cache.overall_miss_latency::cpu.inst 2626422000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 19423235000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22053800000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54602 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11849 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 66451 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 695416 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 695416 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1846676 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1846676 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2626275000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 19415569500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22045987500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54613 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11850 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 66463 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 695423 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 695423 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1846694 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1846694 # number of WritebackClean accesses(hits+misses)
1249,1257c1251,1259
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296961 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296961 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887169 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1887169 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540929 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 540929 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54602 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 11849 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1887169 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296967 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296967 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887187 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1887187 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540923 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 540923 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54613 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 11850 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1887187 # number of demand (read+write) accesses
1259,1262c1261,1264
< system.cpu.l2cache.demand_accesses::total 2791510 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54602 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 11849 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1887169 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 2791540 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54613 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 11850 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1887187 # number of overall (read+write) accesses
1264c1266
< system.cpu.l2cache.overall_accesses::total 2791510 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 2791540 # number of overall (read+write) accesses
1272,1277c1274,1279
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455929 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.455929 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024854 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024854 # miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455926 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.455926 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010514 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010514 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024858 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024858 # miss rate for ReadSharedReq accesses
1280,1281c1282,1283
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010515 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.177633 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010514 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.177638 # miss rate for demand accesses
1285,1286c1287,1288
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010515 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.177633 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010514 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.177638 # miss rate for overall accesses
1291,1292c1293,1294
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 800.992282 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 800.992282 # average UpgradeReq miss latency
---
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 775.266446 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 775.266446 # average UpgradeReq miss latency
1295,1300c1297,1302
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129968.506961 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129968.506961 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132359.389174 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132359.389174 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135243.455303 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135243.455303 # average ReadSharedReq miss latency
1303,1305c1305,1307
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132359.389174 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130445.035306 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 130672.314358 # average overall miss latency
1308,1310c1310,1312
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132359.389174 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130445.035306 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 130672.314358 # average overall miss latency
1319,1320c1321,1322
< system.cpu.l2cache.writebacks::writebacks 88798 # number of writebacks
< system.cpu.l2cache.writebacks::total 88798 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 88801 # number of writebacks
> system.cpu.l2cache.writebacks::total 88801 # number of writebacks
1338,1343c1340,1345
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135393 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 135393 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13331 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13331 # number of ReadSharedReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135395 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 135395 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19816 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19816 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13333 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13333 # number of ReadSharedReq MSHR misses
1346,1348c1348,1350
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 19818 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 148724 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 168571 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 19816 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 148728 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168573 # number of demand (read+write) MSHR misses
1351,1353c1353,1355
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 19818 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 148724 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 168571 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 19816 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 148728 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168573 # number of overall MSHR misses
1365,1374c1367,1376
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192556500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192556500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16249790000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16249790000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425294500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425294500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1672223500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1672223500 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185063000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185063000 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 209500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 209500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16243136000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16243136000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425381002 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425381002 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1671251000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1671251000 # number of ReadSharedReq MSHR miss cycles
1377,1379c1379,1381
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425294500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17922013500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20351161000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2425381002 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17914387000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20343621002 # number of demand (read+write) MSHR miss cycles
1382,1384c1384,1386
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425294500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17922013500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20351161000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425381002 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17914387000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20343621002 # number of overall MSHR miss cycles
1386,1389c1388,1391
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887205500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227322500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756953000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756953000 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887198000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227315000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756961000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756961000 # number of WriteReq MSHR uncacheable cycles
1391,1392c1393,1394
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644158500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984275500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644159000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984276000 # number of overall MSHR uncacheable cycles
1400,1405c1402,1407
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455929 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455929 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010501 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024645 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024645 # mshr miss rate for ReadSharedReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455926 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455926 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024649 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024649 # mshr miss rate for ReadSharedReq accesses
1408,1409c1410,1411
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for demand accesses
1413,1414c1415,1416
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for overall accesses
1419,1428c1421,1430
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.862918 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.862918 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119968.506961 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119968.506961 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122395.084881 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122395.084881 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125346.958674 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125346.958674 # average ReadSharedReq mshr miss latency
1431,1433c1433,1435
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency
1436,1438c1438,1440
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency
1440,1443c1442,1445
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810 # average WriteReq mshr uncacheable latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.618780 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.650807 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.380823 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.380823 # average WriteReq mshr uncacheable latency
1445,1446c1447,1448
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.261743 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.242231 # average overall mshr uncacheable latency
1448,1449c1450,1451
< system.cpu.toL2Bus.snoop_filter.tot_requests 5483387 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758318 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 5483442 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758353 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1451,1452c1453,1454
< system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1454,1455c1456,1457
< system.cpu.toL2Bus.trans_dist::ReadReq 128004 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2556278 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 128030 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2556317 # Transaction distribution
1458,1460c1460,1462
< system.cpu.toL2Bus.trans_dist::WritebackDirty 820384 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1846676 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 142776 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 820394 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1886695 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 149869 # Transaction distribution
1464,1467c1466,1469
< system.cpu.toL2Bus.trans_dist::ReadExReq 296961 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296961 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887211 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 541178 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 296967 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296967 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887230 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 541172 # Transaction distribution
1469,1482c1471,1484
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627062 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629120 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31258 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129064 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8416504 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239014016 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323369 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47396 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 337603189 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 196948 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3052801 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.025889 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.158805 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667118 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636221 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31264 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129096 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8463699 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241576384 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323817 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47400 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218452 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 340166053 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 196965 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.025894 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.158818 # Request fanout histogram
1484,1485c1486,1487
< system.cpu.toL2Bus.snoop_fanout::0 2973766 97.41% 97.41% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 79035 2.59% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 2973799 97.41% 97.41% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 79049 2.59% 100.00% # Request fanout histogram
1490,1491c1492,1493
< system.cpu.toL2Bus.snoop_fanout::total 3052801 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 5399625997 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 5399685497 # Layer occupancy (ticks)
1495c1497
< system.cpu.toL2Bus.respLayer0.occupancy 2834640846 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2834668847 # Layer occupancy (ticks)
1497c1499
< system.cpu.toL2Bus.respLayer1.occupancy 1303359054 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1303356559 # Layer occupancy (ticks)
1499c1501
< system.cpu.toL2Bus.respLayer2.occupancy 19415986 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 19420986 # Layer occupancy (ticks)
1501c1503
< system.cpu.toL2Bus.respLayer3.occupancy 74513896 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 74535395 # Layer occupancy (ticks)
1553c1555
< system.iobus.reqLayer0.occupancy 43090500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks)
1591c1593
< system.iobus.reqLayer25.occupancy 186380025 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 187182974 # Layer occupancy (ticks)
1598c1600
< system.iocache.tags.tagsinuse 1.005380 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 1.005274 # Cycle average of tags in use
1602,1605c1604,1607
< system.iocache.tags.warmup_cycle 256605907000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.005380 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.062836 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.062836 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 256605904000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.005274 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.062830 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.062830 # Average percentage of cache occupancy
1621,1628c1623,1630
< system.iocache.ReadReq_miss_latency::realview.ide 31316876 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 31316876 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4717082149 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4717082149 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 31316876 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 31316876 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 31316876 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 31316876 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 31308877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 31308877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4546803097 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4546803097 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 31308877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 31308877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 31308877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 31308877 # number of overall miss cycles
1645,1653c1647,1655
< system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 125770.586345 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 125770.586345 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 125770.586345 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 902 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 125738.461847 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 125738.461847 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125619.646277 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 125619.646277 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 125738.461847 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 125738.461847 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1655c1657
< system.iocache.blocked::no_mshrs 96 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1657c1659
< system.iocache.avg_blocked_cycles::no_mshrs 9.395833 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1671,1678c1673,1680
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 18866876 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 18866876 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907332149 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2907332149 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 18866876 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 18866876 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 18866876 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 18866876 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 18858877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 18858877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2735602611 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2735602611 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 18858877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 18858877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 18858877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 18858877 # number of overall MSHR miss cycles
1687,1694c1689,1696
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75738.461847 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 75738.461847 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75579.572068 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.572068 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency
1700,1701c1702,1703
< system.membus.trans_dist::WritebackDirty 124958 # Transaction distribution
< system.membus.trans_dist::CleanEvict 7701 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 124961 # Transaction distribution
> system.membus.trans_dist::CleanEvict 7937 # Transaction distribution
1704,1706c1706,1708
< system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution
< system.membus.trans_dist::ReadExReq 133521 # Transaction distribution
< system.membus.trans_dist::ReadExResp 133521 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
> system.membus.trans_dist::ReadExReq 133523 # Transaction distribution
> system.membus.trans_dist::ReadExResp 133523 # Transaction distribution
1709d1710
< system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution
1713,1717c1714,1718
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 454663 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562233 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 671059 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450075 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557645 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 630513 # Packet count per connected master and slave (bytes)
1721,1722c1722,1723
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16401756 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565161 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402076 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565481 # Cumulative packet size per connected master and slave (bytes)
1725c1726
< system.membus.pkt_size::total 18880361 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 18880681 # Cumulative packet size per connected master and slave (bytes)
1727c1728
< system.membus.snoop_fanout::samples 402363 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 402367 # Request fanout histogram
1732c1733
< system.membus.snoop_fanout::1 402363 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 402367 100.00% 100.00% # Request fanout histogram
1737,1738c1738,1739
< system.membus.snoop_fanout::total 402363 # Request fanout histogram
< system.membus.reqLayer0.occupancy 83709500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 402367 # Request fanout histogram
> system.membus.reqLayer0.occupancy 83710000 # Layer occupancy (ticks)
1742c1743
< system.membus.reqLayer2.occupancy 1749000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1748000 # Layer occupancy (ticks)
1744c1745
< system.membus.reqLayer5.occupancy 873720378 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 873736629 # Layer occupancy (ticks)
1746c1747
< system.membus.respLayer2.occupancy 987389399 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 978197500 # Layer occupancy (ticks)
1748c1749
< system.membus.respLayer3.occupancy 64116283 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks)