3,5c3,5
< sim_seconds 2.827546 # Number of seconds simulated
< sim_ticks 2827546300000 # Number of ticks simulated
< final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.832619 # Number of seconds simulated
> sim_ticks 2832618668500 # Number of ticks simulated
> final_tick 2832618668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 101558 # Simulator instruction rate (inst/s)
< host_op_rate 123188 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2538650252 # Simulator tick rate (ticks/s)
< host_mem_usage 576848 # Number of bytes of host memory used
< host_seconds 1113.80 # Real time elapsed on the host
< sim_insts 113115023 # Number of instructions simulated
< sim_ops 137206411 # Number of ops (including micro ops) simulated
---
> host_inst_rate 90415 # Simulator instruction rate (inst/s)
> host_op_rate 109666 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2263800643 # Simulator tick rate (ticks/s)
> host_mem_usage 628336 # Number of bytes of host memory used
> host_seconds 1251.27 # Real time elapsed on the host
> sim_insts 113133035 # Number of instructions simulated
> sim_ops 137220830 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 1600 # Number of bytes read from this memory
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1321728 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9386216 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 10710952 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1321728 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1321728 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8026688 # Number of bytes written to this memory
26,27c26,27
< system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8044212 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 25 # Number of read requests responded to by this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 22899 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 147180 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 170126 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 125417 # Number of write requests responded to by this memory
35,36c35,36
< system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 129798 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 565 # Total read bandwidth from this memory (bytes/s)
38,48c38,48
< system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 466610 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3313618 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3781290 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 466610 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 466610 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2833663 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 6187 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2839850 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2833663 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 565 # Total bandwidth to/from this memory (bytes/s)
50,97c50,97
< system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 176040 # Number of read requests accepted
< system.physmem.writeReqs 135452 # Number of write requests accepted
< system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 11283 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10909 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10879 # Per bank write bursts
< system.physmem.perBankRdBursts::3 10544 # Per bank write bursts
< system.physmem.perBankRdBursts::4 14049 # Per bank write bursts
< system.physmem.perBankRdBursts::5 11359 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11255 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11497 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10572 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11295 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10218 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9589 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9979 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10701 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10842 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10903 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8346 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8306 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8514 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8219 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8602 # Per bank write bursts
< system.physmem.perBankWrBursts::5 8561 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8053 # Per bank write bursts
< system.physmem.perBankWrBursts::7 8529 # Per bank write bursts
< system.physmem.perBankWrBursts::8 8073 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8804 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7852 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7407 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7747 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8181 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8268 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8079 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 466610 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3319804 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6621140 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 170127 # Number of read requests accepted
> system.physmem.writeReqs 129798 # Number of write requests accepted
> system.physmem.readBursts 170127 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 129798 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 10879424 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8056320 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10711016 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8044212 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 40796 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11277 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10595 # Per bank write bursts
> system.physmem.perBankRdBursts::2 11086 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11282 # Per bank write bursts
> system.physmem.perBankRdBursts::4 12957 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9975 # Per bank write bursts
> system.physmem.perBankRdBursts::6 10510 # Per bank write bursts
> system.physmem.perBankRdBursts::7 10855 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10363 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10082 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10269 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9303 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9940 # Per bank write bursts
> system.physmem.perBankRdBursts::13 11053 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10302 # Per bank write bursts
> system.physmem.perBankRdBursts::15 10142 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8501 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7938 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8637 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8770 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7610 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7376 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7709 # Per bank write bursts
> system.physmem.perBankWrBursts::7 8071 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7782 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7594 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7680 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6982 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7590 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8396 # Per bank write bursts
> system.physmem.perBankWrBursts::14 7757 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7487 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
< system.physmem.totGap 2827546089000 # Total gap between requests
---
> system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
> system.physmem.totGap 2832618457500 # Total gap between requests
105c105
< system.physmem.readPktSize::4 2997 # Read request sizes (log2)
---
> system.physmem.readPktSize::4 2996 # Read request sizes (log2)
107c107
< system.physmem.readPktSize::6 172487 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 166575 # Read request sizes (log2)
114,119c114,119
< system.physmem.writePktSize::6 131071 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 125417 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 150718 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 16419 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2119 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 721 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
162,181c162,181
< system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2020 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5703 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6082 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6948 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 7284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8232 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 8372 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8373 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7455 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7461 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6629 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 258 # What write queue length does an incoming req see
183c183
< system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
185,266c185,265
< system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads
< system.physmem.totQLat 2123501000 # Total ticks spent queuing
< system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::38 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 86 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 70 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 40 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 23 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 34 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 62118 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 304.834026 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 180.217682 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 324.637512 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 23314 37.53% 37.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14709 23.68% 61.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6728 10.83% 72.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3491 5.62% 77.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2622 4.22% 81.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1595 2.57% 84.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1577 2.54% 86.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1006 1.62% 88.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7076 11.39% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62118 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6287 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 27.034993 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 563.024200 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6286 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6287 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6287 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.022268 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.451800 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 12.249481 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5461 86.86% 86.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 111 1.77% 88.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 41 0.65% 89.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 176 2.80% 92.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 30 0.48% 92.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 149 2.37% 94.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 46 0.73% 95.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 9 0.14% 95.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 13 0.21% 96.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 18 0.29% 96.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 5 0.08% 96.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 3 0.05% 96.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 163 2.59% 99.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.06% 99.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 8 0.13% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 20 0.32% 99.52% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 2 0.03% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 3 0.05% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.03% 99.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 1 0.02% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 1 0.02% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 2 0.03% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 13 0.21% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 4 0.06% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6287 # Writes before turning the bus around for reads
> system.physmem.totQLat 2109686750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5297018000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 849955000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12410.58 # Average queueing delay per DRAM burst
268,272c267,271
< system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31160.58 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s
277,295c276,294
< system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing
< system.physmem.readRowHits 144861 # Number of row buffer hits during reads
< system.physmem.writeRowHits 97354 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes
< system.physmem.avgGap 9077427.64 # Average gap between requests
< system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.382186 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states
---
> system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.90 # Average write queue length when enqueuing
> system.physmem.readRowHits 139766 # Number of row buffer hits during reads
> system.physmem.writeRowHits 93986 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.22 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.64 # Row buffer hit rate for writes
> system.physmem.avgGap 9444422.63 # Average gap between requests
> system.physmem.pageHitRate 79.00 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 244301400 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 133299375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 690588600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 418685760 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 83544770610 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1626283896000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1896328144065 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.462100 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2705327267750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94587220000 # Time in different power states
297c296
< system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 32700163500 # Time in different power states
299,309c298,308
< system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.301228 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states
---
> system.physmem_1.actEnergy 225310680 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 122937375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 635333400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 397016640 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 185012602320 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 82147816890 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1627509294000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1896050311305 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.364017 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2707380849000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94587220000 # Time in different power states
311c310
< system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 30650586000 # Time in different power states
331,335c330,334
< system.cpu.branchPred.lookups 46902830 # Number of BP lookups
< system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits
---
> system.cpu.branchPred.lookups 46909632 # Number of BP lookups
> system.cpu.branchPred.condPredicted 24036779 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1233520 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 29533462 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 21344460 # Number of BTB hits
337,339c336,338
< system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.272123 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 11742450 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 33774 # Number of incorrect RAS predictions.
370,416c369,408
< system.cpu.dtb.walker.walks 72877 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution
---
> system.cpu.dtb.walker.walks 71741 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 71741 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29467 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22287 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 19987 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 51754 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 426.227924 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 2584.933278 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-8191 50562 97.70% 97.70% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::8192-16383 857 1.66% 99.35% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::16384-24575 291 0.56% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::24576-32767 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::32768-40959 10 0.02% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::40960-49151 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 51754 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 17702 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 12439.950288 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 9865.120013 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 8642.768996 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-32767 17474 98.71% 98.71% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::32768-65535 221 1.25% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 17702 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 131083168816 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.618031 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.493607 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 131025996816 99.96% 99.96% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 38371000 0.03% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 7847500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 6991500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 1099000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 491500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 1479000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 882500 0.00% 100.00% # Table walker pending requests distribution
418,422c410,414
< system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walksPending::total 131083168816 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6361 82.57% 82.57% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1343 17.43% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7704 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71741 # Table walker requests started/completed, data/inst
424,425c416,417
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71741 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7704 # Table walker requests started/completed, data/inst
427,428c419,420
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7704 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 79445 # Table walker requests started/completed, data/inst
431,434c423,426
< system.cpu.dtb.read_hits 25454298 # DTB read hits
< system.cpu.dtb.read_misses 62609 # DTB read misses
< system.cpu.dtb.write_hits 19910353 # DTB write hits
< system.cpu.dtb.write_misses 10268 # DTB write misses
---
> system.cpu.dtb.read_hits 25458814 # DTB read hits
> system.cpu.dtb.read_misses 61805 # DTB read misses
> system.cpu.dtb.write_hits 19912938 # DTB write hits
> system.cpu.dtb.write_misses 9936 # DTB write misses
439,441c431,433
< system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4319 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 2196 # Number of TLB faults due to prefetch
443,445c435,437
< system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 25516907 # DTB read accesses
< system.cpu.dtb.write_accesses 19920621 # DTB write accesses
---
> system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 25520619 # DTB read accesses
> system.cpu.dtb.write_accesses 19922874 # DTB write accesses
447,449c439,441
< system.cpu.dtb.hits 45364651 # DTB hits
< system.cpu.dtb.misses 72877 # DTB misses
< system.cpu.dtb.accesses 45437528 # DTB accesses
---
> system.cpu.dtb.hits 45371752 # DTB hits
> system.cpu.dtb.misses 71741 # DTB misses
> system.cpu.dtb.accesses 45443493 # DTB accesses
479,518c471,508
< system.cpu.itb.walker.walks 11947 # Table walker walks requested
< system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated
---
> system.cpu.itb.walker.walks 11944 # Table walker walks requested
> system.cpu.itb.walker.walksShort 11944 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 3964 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 7740 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 240 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 11704 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 651.102187 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 2927.030280 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-4095 11135 95.14% 95.14% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::4096-8191 148 1.26% 96.40% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::8192-12287 183 1.56% 97.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::12288-16383 77 0.66% 98.62% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::16384-20479 110 0.94% 99.56% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::20480-24575 40 0.34% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::28672-32767 6 0.05% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 11704 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3569 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 13485.850378 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 10973.901987 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 8473.200886 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-16383 2612 73.19% 73.19% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-32767 916 25.67% 98.85% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::32768-49151 38 1.06% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::131072-147455 3 0.08% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 3569 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 23708925416 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.962784 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.189405 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 882867000 3.72% 3.72% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 22825544916 96.27% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 513500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 23708925416 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 3010 90.42% 90.42% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 319 9.58% 100.00% # Table walker page sizes translated
521,522c511,512
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11944 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 11944 # Table walker requests started/completed, data/inst
526,528c516,518
< system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 66251443 # ITB inst hits
< system.cpu.itb.inst_misses 11947 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin::total 15273 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 66274552 # ITB inst hits
> system.cpu.itb.inst_misses 11944 # ITB inst misses
537c527
< system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB
541c531
< system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 2199 # Number of TLB faults due to permissions restrictions
544,548c534,538
< system.cpu.itb.inst_accesses 66263390 # ITB inst accesses
< system.cpu.itb.hits 66251443 # DTB hits
< system.cpu.itb.misses 11947 # DTB misses
< system.cpu.itb.accesses 66263390 # DTB accesses
< system.cpu.numCycles 263015768 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 66286496 # ITB inst accesses
> system.cpu.itb.hits 66274552 # DTB hits
> system.cpu.itb.misses 11944 # DTB misses
> system.cpu.itb.accesses 66286496 # DTB accesses
> system.cpu.numCycles 277645869 # number of cpu cycles simulated
551,567c541,557
< system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 104816225 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 184723631 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 46909632 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 33086910 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 160672113 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 6155878 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 195967 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 9078 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 333869 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 563276 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 182 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 66274743 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1128462 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5280 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 269668649 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.835474 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.219488 # Number of instructions fetched each cycle (Total)
569,572c559,562
< system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 170383279 63.18% 63.18% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 29238814 10.84% 74.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 14077384 5.22% 79.25% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 55969172 20.75% 100.00% # Number of instructions fetched each cycle (Total)
576,622c566,612
< system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 269668649 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.168955 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.665321 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 77872075 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 120737431 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 64613956 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3845227 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 2599960 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3423402 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 486431 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 157413712 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3694235 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 2599960 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 83719189 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 11483136 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 75823110 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 62612793 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 33430461 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 146780851 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 948885 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 459435 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 64832 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 17222 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 30677805 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 150464365 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 678641295 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 164414257 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 10882 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 141779508 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 8684854 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2843849 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2647501 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13873635 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26407527 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21301019 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1697624 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2214062 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 143514940 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2121406 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 143299756 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 270446 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 8415512 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14711754 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 125531 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 269668649 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.531392 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.866832 # Number of insts issued each cycle
624,629c614,619
< system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 181393020 67.27% 67.27% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45154562 16.74% 84.01% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 32029362 11.88% 95.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10280384 3.81% 99.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 811287 0.30% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle
636c626
< system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 269668649 # Number of insts issued each cycle
638,668c628,658
< system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 7353326 32.78% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 31 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.78% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 5633689 25.11% 57.89% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 9445566 42.11% 100.00% # attempts to use FU when none available
672,673c662,663
< system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 95980665 66.98% 66.98% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 113853 0.08% 67.06% # Type of FU issued
697c687
< system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.07% # Type of FU issued
701,702c691,692
< system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26189090 18.28% 85.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21005231 14.66% 100.00% # Type of FU issued
705,717c695,707
< system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued
< system.cpu.iq.rate 0.544767 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 143299756 # Type of FU issued
> system.cpu.iq.rate 0.516124 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 22432612 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.156543 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 578935614 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 154057233 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 140187198 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 35605 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 13116 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 11364 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 165706663 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 23368 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 323603 # Number of loads that had data forwarded from stores
719,722c709,712
< system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1496259 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 507 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18537 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 706534 # Number of stores squashed
725,726c715,716
< system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 88309 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 6292 # Number of times an access to memory failed due to the cache being blocked
728,731c718,721
< system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 2599960 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1252151 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 541403 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 145836919 # Number of instructions dispatched to IQ
733,744c723,734
< system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 26407527 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21301019 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1096274 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 18146 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 505783 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18537 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 317326 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 471404 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 788730 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 142356745 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25786743 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 871381 # Number of squashed instructions skipped in execute
746,754c736,744
< system.cpu.iew.exec_nop 201061 # number of nop insts executed
< system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed
< system.cpu.iew.exec_branches 26517785 # Number of branches executed
< system.cpu.iew.exec_stores 20872797 # Number of stores executed
< system.cpu.iew.exec_rate 0.541174 # Inst execution rate
< system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 63256602 # num instructions producing a value
< system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 200573 # number of nop insts executed
> system.cpu.iew.exec_refs 46662722 # number of memory reference insts executed
> system.cpu.iew.exec_branches 26519669 # Number of branches executed
> system.cpu.iew.exec_stores 20875979 # Number of stores executed
> system.cpu.iew.exec_rate 0.512728 # Inst execution rate
> system.cpu.iew.wb_sent 141970613 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 140198562 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 63271886 # num instructions producing a value
> system.cpu.iew.wb_consumers 95802115 # num instructions consuming a value
756,757c746,747
< system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.504955 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.660444 # average fanout of values written-back
759,764c749,754
< system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7621436 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1995875 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 755541 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 266730475 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.515036 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.120154 # Number of insts commited each cycle
766,774c756,764
< system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 193314140 72.48% 72.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43245727 16.21% 88.69% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 15468136 5.80% 94.49% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4389606 1.65% 96.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 6355153 2.38% 98.52% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1682348 0.63% 99.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 799161 0.30% 99.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 412032 0.15% 99.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1064172 0.40% 100.00% # Number of insts commited each cycle
778,780c768,770
< system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 113269928 # Number of instructions committed
< system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 266730475 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 113287940 # Number of instructions committed
> system.cpu.commit.committedOps 137375735 # Number of ops (including micro ops) committed
782,788c772,778
< system.cpu.commit.refs 45498874 # Number of memory references committed
< system.cpu.commit.loads 24907631 # Number of loads committed
< system.cpu.commit.membars 814016 # Number of memory barriers committed
< system.cpu.commit.branches 26032948 # Number of branches committed
< system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
< system.cpu.commit.int_insts 120189151 # Number of committed integer instructions.
< system.cpu.commit.function_calls 4888294 # Number of function calls committed.
---
> system.cpu.commit.refs 45505753 # Number of memory references committed
> system.cpu.commit.loads 24911268 # Number of loads committed
> system.cpu.commit.membars 814898 # Number of memory barriers committed
> system.cpu.commit.branches 26034583 # Number of branches committed
> system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions.
> system.cpu.commit.int_insts 120199859 # Number of committed integer instructions.
> system.cpu.commit.function_calls 4887749 # Number of function calls committed.
790,791c780,781
< system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 91748615 66.79% 66.79% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 112788 0.08% 66.87% # Class of committed instruction
815,820c805,810
< system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
< system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
< system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 24911268 18.13% 85.01% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 20594485 14.99% 100.00% # Class of committed instruction
823,838c813,828
< system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 375595727 # The number of ROB reads
< system.cpu.rob.rob_writes 292884314 # The number of ROB writes
< system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 113115023 # Number of Instructions Simulated
< system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 155781292 # number of integer regfile reads
< system.cpu.int_regfile_writes 88602572 # number of integer regfile writes
< system.cpu.fp_regfile_reads 9590 # number of floating regfile reads
---
> system.cpu.commit.op_class_0::total 137375735 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1064172 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 388465780 # The number of ROB reads
> system.cpu.rob.rob_writes 292930075 # The number of ROB writes
> system.cpu.timesIdled 888709 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 7977220 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 5387591469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 113133035 # Number of Instructions Simulated
> system.cpu.committedOps 137220830 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.454154 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.454154 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.407472 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.407472 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 155797969 # number of integer regfile reads
> system.cpu.int_regfile_writes 88612711 # number of integer regfile writes
> system.cpu.fp_regfile_reads 9524 # number of floating regfile reads
840,852c830,842
< system.cpu.cc_regfile_reads 502823661 # number of cc regfile reads
< system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes
< system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 839265 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy
---
> system.cpu.cc_regfile_reads 502896975 # number of cc regfile reads
> system.cpu.cc_regfile_writes 53174784 # number of cc regfile writes
> system.cpu.misc_regfile_reads 347572280 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1521694 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 840044 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.925899 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40105851 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 840556 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 47.713479 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.925899 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy
854,856c844,846
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
858,881c848,871
< system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 459484 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 38846236 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38846236 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39191939 # number of overall hits
< system.cpu.dcache.overall_hits::total 39191939 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 710133 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 710133 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3609878 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3609878 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 177558 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 177558 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 26867 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 26867 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 179336842 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179336842 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23308523 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23308523 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15546666 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15546666 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 346021 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 346021 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 441431 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 441431 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460353 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460353 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 38855189 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38855189 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39201210 # number of overall hits
> system.cpu.dcache.overall_hits::total 39201210 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 708825 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 708825 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3606988 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3606988 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 177865 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 177865 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 27388 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 27388 # number of LoadLockedReq misses
884,921c874,911
< system.cpu.dcache.demand_misses::cpu.data 4320011 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4320011 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4497569 # number of overall misses
< system.cpu.dcache.overall_misses::total 4497569 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10292232000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10292232000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 148465108677 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365302500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 365302500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 158757340677 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 158757340677 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 158757340677 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 158757340677 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24014363 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24014363 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19151884 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19151884 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 523261 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 523261 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467948 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 467948 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 459489 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 459489 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 43166247 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43166247 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43689508 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43689508 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188487 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.188487 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339330 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.339330 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057414 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057414 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_misses::cpu.data 4315813 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4315813 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4493678 # number of overall misses
> system.cpu.dcache.overall_misses::total 4493678 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11757743000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11757743000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 232345213174 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 232345213174 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 375611000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 375611000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 278000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 278000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 244102956174 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 244102956174 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 244102956174 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 244102956174 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24017348 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24017348 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19153654 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19153654 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 523886 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 523886 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468819 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 468819 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460358 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460358 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 43171002 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43171002 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43694888 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43694888 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029513 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.029513 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188319 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.188319 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339511 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.339511 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058419 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058419 # miss rate for LoadLockedReq accesses
924,940c914,930
< system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.099970 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.099970 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.102842 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.102842 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16587.652806 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 16587.652806 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64415.299739 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64415.299739 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13714.436980 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13714.436980 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55600 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55600 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 56560.132743 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 56560.132743 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 54321.416927 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 54321.416927 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 869823 # number of cycles access was blocked
942c932
< system.cpu.dcache.blocked::no_mshrs 7439 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 6812 # number of cycles access was blocked
944c934
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.406775 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.689812 # average number of cycles each access was blocked
948,967c938,957
< system.cpu.dcache.writebacks::writebacks 696043 # number of writebacks
< system.cpu.dcache.writebacks::total 696043 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 414292 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300244 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 300244 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119628 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 119628 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8392 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8392 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 698262 # number of writebacks
> system.cpu.dcache.writebacks::total 698262 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 293573 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 293573 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307033 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3307033 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18933 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 18933 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3600606 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3600606 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3600606 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3600606 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 415252 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 415252 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299955 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299955 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119671 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 119671 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8455 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8455 # number of LoadLockedReq MSHR misses
970,1007c960,997
< system.cpu.dcache.demand_mshr_misses::cpu.data 714536 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 714536 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 834164 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 834164 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
< system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
< system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5857375000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5857375000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13373750471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13373750471 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1627994000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1627994000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 128038500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 715207 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 715207 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 834878 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 834878 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6403711500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6403711500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19964415469 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 19964415469 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1698297000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1698297000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126773500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126773500 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 273000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 273000 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26368126969 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26368126969 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28066423969 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28066423969 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5935894500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5935894500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4789947462 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4789947462 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10725841962 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10725841962 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017290 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017290 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015660 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015660 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228429 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228429 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018035 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018035 # mshr miss rate for LoadLockedReq accesses
1010,1033c1000,1023
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016567 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016567 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019107 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019107 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15421.265882 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15421.265882 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66558.035269 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66558.035269 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14191.383042 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14191.383042 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14993.908930 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14993.908930 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54600 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54600 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36867.825635 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36867.825635 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33617.395558 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 33617.395558 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 190686.963924 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190686.963924 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173643.192387 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173643.192387 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 182679.462513 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 182679.462513 # average overall mshr uncacheable latency
1035,1043c1025,1033
< system.cpu.icache.tags.replacements 1891955 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1889050 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.157898 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 64290369 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1889562 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 34.023953 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 16212707500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.157898 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998355 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998355 # Average percentage of cache occupancy
1046,1048c1036,1038
< system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
1050,1088c1040,1078
< system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits
< system.cpu.icache.overall_hits::total 64263909 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses
< system.cpu.icache.overall_misses::total 1984699 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 68161321 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 68161321 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 64290369 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 64290369 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 64290369 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 64290369 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 64290369 # number of overall hits
> system.cpu.icache.overall_hits::total 64290369 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1981370 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1981370 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1981370 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1981370 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1981370 # number of overall misses
> system.cpu.icache.overall_misses::total 1981370 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28130756994 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28130756994 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28130756994 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28130756994 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28130756994 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28130756994 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 66271739 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 66271739 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 66271739 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 66271739 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 66271739 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 66271739 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029898 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.029898 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.029898 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.029898 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.029898 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.029898 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14197.629415 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14197.629415 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14197.629415 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14197.629415 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14197.629415 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 4834 # number of cycles access was blocked
1090c1080
< system.cpu.icache.blocked::no_mshrs 127 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 167 # number of cycles access was blocked
1092c1082
< system.cpu.icache.avg_blocked_cycles::no_mshrs 19.748031 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 28.946108 # average number of cycles each access was blocked
1096,1137c1086,1127
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92212 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 92212 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 92212 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 92212 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 92212 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 92212 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1892487 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1892487 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1892487 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1892487 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1892487 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1892487 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable
< system.cpu.icache.ReadReq_mshr_uncacheable::total 3005 # number of ReadReq MSHR uncacheable
< system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses
< system.cpu.icache.overall_mshr_uncacheable_misses::total 3005 # number of overall MSHR uncacheable misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24145787497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24145787497 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24145787497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24145787497 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24145787497 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24145787497 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225776500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225776500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225776500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 225776500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028566 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.028566 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.028566 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649 # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649 # average overall mshr uncacheable latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91786 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 91786 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 91786 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 91786 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 91786 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 91786 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1889584 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1889584 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1889584 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1889584 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1889584 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1889584 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25162612496 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 25162612496 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25162612496 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 25162612496 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25162612496 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 25162612496 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377653500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377653500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377653500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 377653500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028513 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.028513 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028513 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.028513 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13316.482621 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13316.482621 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13316.482621 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 13316.482621 # average overall mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125716.877497 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125716.877497 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125716.877497 # average overall mshr uncacheable latency
1139,1143c1129,1133
< system.cpu.l2cache.tags.replacements 103023 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65070.034194 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 5007824 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 168222 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 29.769138 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 96843 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65028.531062 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 5011588 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 162159 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 30.905395 # Average number of references to valid blocks.
1145,1193c1135,1183
< system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.985449 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797952 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5712.105601 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.749720 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000198 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155769 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.087160 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992890 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55225 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000259 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 44376961 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 44376961 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56023 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 68572 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 696043 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 696043 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 157187 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 157187 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1872509 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1872509 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527843 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 527843 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 56023 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1872509 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 685030 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2626111 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 56023 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1872509 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 685030 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2626111 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 49578.198261 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.786082 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 3.639229 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10379.582130 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5055.325361 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.756503 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000180 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000056 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158380 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.077138 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992257 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65300 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2907 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6671 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55556 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996399 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 44337663 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 44337663 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56125 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12636 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 68761 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 698262 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 698262 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 35 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 161870 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 161870 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1869604 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1869604 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 529846 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 529846 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 56125 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 12636 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1869604 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 691716 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2630081 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 56125 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 12636 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1869604 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 691716 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2630081 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 25 # number of ReadReq misses
1195,1206c1185,1196
< system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 140423 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 140423 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19944 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 19944 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14346 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 14346 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::total 32 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2716 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2716 # number of UpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 135463 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 135463 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19932 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 19932 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13403 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 13403 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 25 # number of demand (read+write) misses
1208,1211c1198,1201
< system.cpu.l2cache.demand_misses::cpu.inst 19944 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 154769 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 174741 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 19932 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 148866 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 168830 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 25 # number of overall misses
1213,1245c1203,1235
< system.cpu.l2cache.overall_misses::cpu.inst 19944 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 154769 # number of overall misses
< system.cpu.l2cache.overall_misses::total 174741 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1844500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 579500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2424000 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 955000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 955000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11187095500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 11187095500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1623118000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 1623118000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1226117500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 1226117500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1844500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 579500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1623118000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12413213000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 14038755000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1844500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 579500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1623118000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12413213000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 14038755000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56044 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12556 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 68600 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 696043 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 696043 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2757 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2757 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.inst 19932 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 148866 # number of overall misses
> system.cpu.l2cache.overall_misses::total 168830 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3485500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 928500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 4414000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2825000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 2825000 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17593595500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 17593595500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2641157500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 2641157500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1805154500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 1805154500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3485500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 928500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 2641157500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 19398750000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22044321500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3485500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 928500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 2641157500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 19398750000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22044321500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56150 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12643 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 68793 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 698262 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 698262 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2751 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2751 # number of UpgradeReq accesses(hits+misses)
1248,1309c1238,1299
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 297610 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 297610 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1892453 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1892453 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542189 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 542189 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56044 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 12556 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1892453 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 839799 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2800852 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56044 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 12556 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1892453 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 839799 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2800852 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000558 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000408 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986942 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986942 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.471836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010539 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026459 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026459 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000558 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.184293 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.062389 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000558 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.184293 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.062389 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 350.973907 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 350.973907 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 297333 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 297333 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1889536 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1889536 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 543249 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 543249 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56150 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 12643 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1889536 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 840582 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2798911 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56150 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 12643 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1889536 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 840582 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2798911 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000554 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.000465 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987277 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987277 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455594 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.455594 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010549 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010549 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024672 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024672 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000554 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010549 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.177099 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.060320 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000554 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010549 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.177099 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.060320 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 139420 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132642.857143 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 137937.500000 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1040.132548 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1040.132548 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129877.497915 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129877.497915 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132508.403572 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132508.403572 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134682.869507 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134682.869507 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 139420 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132642.857143 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132508.403572 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130310.144694 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 130571.115915 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 139420 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132642.857143 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132508.403572 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130310.144694 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 130571.115915 # average overall miss latency
1318,1330c1308,1320
< system.cpu.l2cache.writebacks::writebacks 94881 # number of writebacks
< system.cpu.l2cache.writebacks::total 94881 # number of writebacks
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 22 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 133 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 133 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 89227 # number of writebacks
> system.cpu.l2cache.writebacks::total 89227 # number of writebacks
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 112 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 112 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 138 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 138 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 25 # number of ReadReq MSHR misses
1332,1343c1322,1333
< system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140423 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 140423 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19922 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19922 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14235 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14235 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 32 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2716 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2716 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135463 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 135463 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19906 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19906 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13291 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13291 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 25 # number of demand (read+write) MSHR misses
1345,1348c1335,1338
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 19922 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 154658 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 174608 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 19906 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 148754 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 168692 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 25 # number of overall MSHR misses
1350,1445c1340,1435
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 19922 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 154658 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 174608 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61716 # number of overall MSHR uncacheable misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1634500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 509500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2144000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56503000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56503000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 145000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 145000 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9782865500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9782865500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1422648500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1422648500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1076334500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1076334500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1634500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 509500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1422648500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10859200000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 12283992500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1634500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 509500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1422648500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10859200000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 12283992500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 188213500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519024000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5707237500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4252080000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4252080000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 188213500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771104000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9959317500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000408 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986942 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986942 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471836 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471836 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026255 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026255 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.062341 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.062341 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72500 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72500 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303 # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268 # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 19906 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 148754 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 168692 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3004 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3235500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 858500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4094000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192221500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192221500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 213500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 213500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16238965500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16238965500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2439385500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2439385500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658508500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658508500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3235500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 858500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2439385500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17897474000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20340953500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3235500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 858500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2439385500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17897474000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20340953500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340103000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5546780500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5886883500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4471146500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4471146500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340103000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10017927000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10358030000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000465 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987277 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987277 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455594 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455594 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010535 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024466 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024466 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060271 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000554 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010535 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.176965 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.060271 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127937.500000 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70773.748159 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70773.748159 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71166.666667 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71166.666667 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119877.497915 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119877.497915 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122545.237617 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122545.237617 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124784.327741 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124784.327741 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129420 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122642.857143 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122545.237617 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120315.917555 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120580.427643 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 178186.915738 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172468.974306 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 162086.151894 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162086.151894 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113216.711052 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 170622.458017 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 167828.348294 # average overall mshr uncacheable latency
1447,1453c1437,1449
< system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution
---
> system.cpu.toL2Bus.snoop_filter.tot_requests 5492109 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2761974 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 46577 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.trans_dist::ReadReq 127618 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2560581 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 823684 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 1992109 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution
1455,1459c1451,1455
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2756 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 297333 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 297333 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1889584 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 543472 # Transaction distribution
1461,1474c1457,1470
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 201613 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5634635 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2637259 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32087 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130191 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 8434172 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 120978240 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98677545 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50572 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224600 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 219930957 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 194580 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 5786927 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.021369 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.144611 # Request fanout histogram
1476,1478c1472,1474
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5663267 97.86% 97.86% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 123660 2.14% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1480,1483c1476,1479
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 5786927 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3520664000 # Layer occupancy (ticks)
1485c1481
< system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 259127 # Layer occupancy (ticks)
1487c1483
< system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2838013223 # Layer occupancy (ticks)
1489c1485
< system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1307328687 # Layer occupancy (ticks)
1491c1487
< system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 19448990 # Layer occupancy (ticks)
1493c1489
< system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 74088903 # Layer occupancy (ticks)
1495,1496c1491,1492
< system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 30172 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30172 # Transaction distribution
1521,1523c1517,1519
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes)
1546,1548c1542,1544
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes)
1589c1585
< system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 186319025 # Layer occupancy (ticks)
1595c1591
< system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks)
1597,1598c1593,1594
< system.iocache.tags.replacements 36423 # number of replacements
< system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36413 # number of replacements
> system.iocache.tags.tagsinuse 1.005013 # Cycle average of tags in use
1600c1596
< system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks.
1602,1605c1598,1601
< system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 256397447000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.005013 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.062813 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.062813 # Average percentage of cache occupancy
1609,1612c1605,1608
< system.iocache.tags.tag_accesses 328113 # Number of tag accesses
< system.iocache.tags.data_accesses 328113 # Number of data accesses
< system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 233 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 328023 # Number of tag accesses
> system.iocache.tags.data_accesses 328023 # Number of data accesses
> system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 223 # number of ReadReq misses
1615,1628c1611,1624
< system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses
< system.iocache.demand_misses::total 233 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 233 # number of overall misses
< system.iocache.overall_misses::total 233 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 223 # number of demand (read+write) misses
> system.iocache.demand_misses::total 223 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 223 # number of overall misses
> system.iocache.overall_misses::total 223 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 28159877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 28159877 # number of ReadReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 4697532148 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 4697532148 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 28159877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 28159877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 28159877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 28159877 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses)
1631,1634c1627,1630
< system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 223 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 223 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 223 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 223 # number of overall (read+write) accesses
1643,1650c1639,1646
< system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 126277.475336 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 126277.475336 # average ReadReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129680.105676 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 129680.105676 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126277.475336 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 126277.475336 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126277.475336 # average overall miss latency
1661,1662c1657,1658
< system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses
1665,1676c1661,1672
< system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 223 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 223 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 17009877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 17009877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2886332148 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 2886332148 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 17009877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 17009877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 17009877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 17009877 # number of overall MSHR miss cycles
1685,1692c1681,1688
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76277.475336 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 76277.475336 # average ReadReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79680.105676 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79680.105676 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 76277.475336 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76277.475336 # average overall mshr miss latency
1694,1705c1690,1701
< system.membus.trans_dist::ReadReq 34132 # Transaction distribution
< system.membus.trans_dist::ReadResp 68549 # Transaction distribution
< system.membus.trans_dist::WriteReq 27584 # Transaction distribution
< system.membus.trans_dist::WriteResp 27584 # Transaction distribution
< system.membus.trans_dist::Writeback 131071 # Transaction distribution
< system.membus.trans_dist::CleanEvict 8154 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution
< system.membus.trans_dist::ReadExReq 138564 # Transaction distribution
< system.membus.trans_dist::ReadExResp 138564 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 34133 # Transaction distribution
> system.membus.trans_dist::ReadResp 67584 # Transaction distribution
> system.membus.trans_dist::WriteReq 27585 # Transaction distribution
> system.membus.trans_dist::WriteResp 27585 # Transaction distribution
> system.membus.trans_dist::Writeback 125417 # Transaction distribution
> system.membus.trans_dist::CleanEvict 7628 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4571 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4574 # Transaction distribution
> system.membus.trans_dist::ReadExReq 133608 # Transaction distribution
> system.membus.trans_dist::ReadExResp 133608 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 33452 # Transaction distribution
1710,1715c1706,1711
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455251 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562821 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108888 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 108888 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 671709 # Packet count per connected master and slave (bytes)
1718,1720c1714,1716
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16438044 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16601449 # Cumulative packet size per connected master and slave (bytes)
1723,1725c1719,1721
< system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 497 # Total snoops (count)
< system.membus.snoop_fanout::samples 414951 # Request fanout histogram
---
> system.membus.pkt_size::total 18918569 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 487 # Total snoops (count)
> system.membus.snoop_fanout::samples 402837 # Request fanout histogram
1730c1726
< system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 402837 100.00% 100.00% # Request fanout histogram
1735,1736c1731,1732
< system.membus.snoop_fanout::total 414951 # Request fanout histogram
< system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 402837 # Request fanout histogram
> system.membus.reqLayer0.occupancy 83606500 # Layer occupancy (ticks)
1740c1736
< system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1745500 # Layer occupancy (ticks)
1742c1738
< system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 875905157 # Layer occupancy (ticks)
1744c1740
< system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 988369672 # Layer occupancy (ticks)
1746c1742
< system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 64470242 # Layer occupancy (ticks)
1778a1775
> system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1785d1781
< system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
1790c1786
< system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed