7,11c7,11
< host_inst_rate 94820 # Simulator instruction rate (inst/s)
< host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2369528287 # Simulator tick rate (ticks/s)
< host_mem_usage 555256 # Number of bytes of host memory used
< host_seconds 1193.32 # Real time elapsed on the host
---
> host_inst_rate 97479 # Simulator instruction rate (inst/s)
> host_op_rate 118241 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2435971946 # Simulator tick rate (ticks/s)
> host_mem_usage 621864 # Number of bytes of host memory used
> host_seconds 1160.78 # Real time elapsed on the host
19c19
< system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
21c21
< system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
30c30
< system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
32c32
< system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
39c39
< system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
41c41
< system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
51c51
< system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
53,54c53,54
< system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 176173 # Number of read requests accepted
---
> system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 176174 # Number of read requests accepted
56c56
< system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
59c59
< system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
---
> system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
61c61
< system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
63c63
< system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
103c103
< system.physmem.readPktSize::2 541 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 542 # Read request sizes (log2)
268,269c268,269
< system.physmem.totQLat 2104910750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2104913750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
271c271
< system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
273c273
< system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
288c288
< system.physmem.avgGap 8129210.99 # Average gap between requests
---
> system.physmem.avgGap 8129187.62 # Average gap between requests
295,297c295,297
< system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
299c299
< system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
302c302
< system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
309,311c309,311
< system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
313c313
< system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
316c316
< system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
434c434
< system.cpu.dtb.read_hits 25461870 # DTB read hits
---
> system.cpu.dtb.read_hits 25461869 # DTB read hits
447c447
< system.cpu.dtb.read_accesses 25524161 # DTB read accesses
---
> system.cpu.dtb.read_accesses 25524160 # DTB read accesses
450c450
< system.cpu.dtb.hits 45377257 # DTB hits
---
> system.cpu.dtb.hits 45377256 # DTB hits
452c452
< system.cpu.dtb.accesses 45449628 # DTB accesses
---
> system.cpu.dtb.accesses 45449627 # DTB accesses
594c594
< system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
596c596
< system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
---
> system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
602c602
< system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
618c618
< system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
627,628c627,628
< system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
704c704
< system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
708c708
< system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
712c712
< system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
718c718
< system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
728c728
< system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
745,746c745,746
< system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
750c750
< system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
754c754
< system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
---
> system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
839c839
< system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
843c843
< system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads
845c845
< system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
893,894c893,894
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
899,902c899,902
< system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
933,934c933,934
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
939,942c939,942
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
976a977,982
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
979,980c985,986
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
987,992c993,998
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
995,996c1001,1002
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
1013,1014c1019,1020
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
1021,1030c1027,1036
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency
1104a1111,1114
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
1127,1130c1137,1140
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency
1214,1215c1224,1225
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles
1219,1220c1229,1230
< system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles
1224,1225c1234,1235
< system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles
1279,1280c1289,1290
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency
1284,1285c1294,1295
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency
1289,1290c1299,1300
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency
1330a1341,1348
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
1340,1341c1358,1359
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
1345,1346c1363,1364
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
1350,1351c1368,1369
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
1353,1354c1371,1372
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
1358,1359c1376,1377
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
1390,1391c1408,1409
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
1395,1396c1413,1414
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
1400,1409c1418,1427
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
1411,1412c1429,1430
< system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
1423c1441
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
1426c1444
< system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
1428c1446
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
1431c1449
< system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
1433,1435c1451,1453
< system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
1438,1441c1456,1457
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
1443,1446c1459,1462
< system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
1452c1468
< system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
1658,1659c1674,1675
< system.membus.trans_dist::ReadReq 68566 # Transaction distribution
< system.membus.trans_dist::ReadResp 68565 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 68567 # Transaction distribution
> system.membus.trans_dist::ReadResp 68566 # Transaction distribution
1673,1674c1689,1690
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
1677c1693
< system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
1681,1682c1697,1698
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
1685c1701
< system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
1687c1703
< system.membus.snoop_fanout::samples 345038 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 406751 # Request fanout histogram
1692c1708
< system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
1697c1713
< system.membus.snoop_fanout::total 345038 # Request fanout histogram
---
> system.membus.snoop_fanout::total 406751 # Request fanout histogram
1704c1720
< system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
1706c1722
< system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
< host_inst_rate 94820 # Simulator instruction rate (inst/s)
< host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2369528287 # Simulator tick rate (ticks/s)
< host_mem_usage 555256 # Number of bytes of host memory used
< host_seconds 1193.32 # Real time elapsed on the host
---
> host_inst_rate 97479 # Simulator instruction rate (inst/s)
> host_op_rate 118241 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2435971946 # Simulator tick rate (ticks/s)
> host_mem_usage 621864 # Number of bytes of host memory used
> host_seconds 1160.78 # Real time elapsed on the host
19c19
< system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
21c21
< system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
30c30
< system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
32c32
< system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
39c39
< system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
41c41
< system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
51c51
< system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
53,54c53,54
< system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 176173 # Number of read requests accepted
---
> system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 176174 # Number of read requests accepted
56c56
< system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
59c59
< system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
---
> system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
61c61
< system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
63c63
< system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
103c103
< system.physmem.readPktSize::2 541 # Read request sizes (log2)
---
> system.physmem.readPktSize::2 542 # Read request sizes (log2)
268,269c268,269
< system.physmem.totQLat 2104910750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2104913750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
271c271
< system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
273c273
< system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
288c288
< system.physmem.avgGap 8129210.99 # Average gap between requests
---
> system.physmem.avgGap 8129187.62 # Average gap between requests
295,297c295,297
< system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
299c299
< system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
302c302
< system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
309,311c309,311
< system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
---
> system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
313c313
< system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
---
> system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
316c316
< system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
434c434
< system.cpu.dtb.read_hits 25461870 # DTB read hits
---
> system.cpu.dtb.read_hits 25461869 # DTB read hits
447c447
< system.cpu.dtb.read_accesses 25524161 # DTB read accesses
---
> system.cpu.dtb.read_accesses 25524160 # DTB read accesses
450c450
< system.cpu.dtb.hits 45377257 # DTB hits
---
> system.cpu.dtb.hits 45377256 # DTB hits
452c452
< system.cpu.dtb.accesses 45449628 # DTB accesses
---
> system.cpu.dtb.accesses 45449627 # DTB accesses
594c594
< system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
596c596
< system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
---
> system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
602c602
< system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
---
> system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
618c618
< system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
627,628c627,628
< system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
704c704
< system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
708c708
< system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
712c712
< system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
718c718
< system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
728c728
< system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
745,746c745,746
< system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
750c750
< system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
754c754
< system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
---
> system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
839c839
< system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
843c843
< system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
---
> system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads
845c845
< system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
---
> system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
893,894c893,894
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
899,902c899,902
< system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
933,934c933,934
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
939,942c939,942
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
976a977,982
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
979,980c985,986
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
987,992c993,998
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
995,996c1001,1002
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
1013,1014c1019,1020
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
1021,1030c1027,1036
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency
1104a1111,1114
> system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable
> system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses
1127,1130c1137,1140
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency
> system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency
> system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency
1214,1215c1224,1225
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles
1219,1220c1229,1230
< system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles
1224,1225c1234,1235
< system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles
1279,1280c1289,1290
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency
1284,1285c1294,1295
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency
1289,1290c1299,1300
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency
1330a1341,1348
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
1340,1341c1358,1359
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
1345,1346c1363,1364
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
1350,1351c1368,1369
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
1353,1354c1371,1372
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
1358,1359c1376,1377
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
1390,1391c1408,1409
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
1395,1396c1413,1414
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
1400,1409c1418,1427
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
1411,1412c1429,1430
< system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
1423c1441
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
1426c1444
< system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
1428c1446
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
1431c1449
< system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
1433,1435c1451,1453
< system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
1438,1441c1456,1457
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
1443,1446c1459,1462
< system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
1452c1468
< system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
1658,1659c1674,1675
< system.membus.trans_dist::ReadReq 68566 # Transaction distribution
< system.membus.trans_dist::ReadResp 68565 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 68567 # Transaction distribution
> system.membus.trans_dist::ReadResp 68566 # Transaction distribution
1673,1674c1689,1690
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
1677c1693
< system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
1681,1682c1697,1698
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
1685c1701
< system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
1687c1703
< system.membus.snoop_fanout::samples 345038 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 406751 # Request fanout histogram
1692c1708
< system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
1697c1713
< system.membus.snoop_fanout::total 345038 # Request fanout histogram
---
> system.membus.snoop_fanout::total 406751 # Request fanout histogram
1704c1720
< system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
1706c1722
< system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)