3,5c3,5
< sim_seconds 2.827025 # Number of seconds simulated
< sim_ticks 2827025397500 # Number of ticks simulated
< final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.827616 # Number of seconds simulated
> sim_ticks 2827616186000 # Number of ticks simulated
> final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 96738 # Simulator instruction rate (inst/s)
< host_op_rate 117339 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2415768223 # Simulator tick rate (ticks/s)
< host_mem_usage 619580 # Number of bytes of host memory used
< host_seconds 1170.24 # Real time elapsed on the host
< sim_insts 113206948 # Number of instructions simulated
< sim_ops 137314363 # Number of ops (including micro ops) simulated
---
> host_inst_rate 99248 # Simulator instruction rate (inst/s)
> host_op_rate 120386 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2480177298 # Simulator tick rate (ticks/s)
> host_mem_usage 619560 # Number of bytes of host memory used
> host_seconds 1140.09 # Real time elapsed on the host
> sim_insts 113151083 # Number of instructions simulated
> sim_ops 137250963 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
26,27c26,27
< system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
29,30c29,30
< system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
35,36c35,36
< system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
38,39c38,39
< system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
41,48c41,48
< system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
53,97c53,97
< system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 171932 # Number of read requests accepted
< system.physmem.writeReqs 167449 # Number of write requests accepted
< system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue
< system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 11320 # Per bank write bursts
< system.physmem.perBankRdBursts::1 10283 # Per bank write bursts
< system.physmem.perBankRdBursts::2 11137 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11363 # Per bank write bursts
< system.physmem.perBankRdBursts::4 13028 # Per bank write bursts
< system.physmem.perBankRdBursts::5 10237 # Per bank write bursts
< system.physmem.perBankRdBursts::6 10954 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11381 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10407 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11232 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10729 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9386 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9853 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10909 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9951 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9636 # Per bank write bursts
< system.physmem.perBankWrBursts::0 10810 # Per bank write bursts
< system.physmem.perBankWrBursts::1 10132 # Per bank write bursts
< system.physmem.perBankWrBursts::2 10502 # Per bank write bursts
< system.physmem.perBankWrBursts::3 10558 # Per bank write bursts
< system.physmem.perBankWrBursts::4 9654 # Per bank write bursts
< system.physmem.perBankWrBursts::5 9978 # Per bank write bursts
< system.physmem.perBankWrBursts::6 10358 # Per bank write bursts
< system.physmem.perBankWrBursts::7 10535 # Per bank write bursts
< system.physmem.perBankWrBursts::8 10309 # Per bank write bursts
< system.physmem.perBankWrBursts::9 10935 # Per bank write bursts
< system.physmem.perBankWrBursts::10 10009 # Per bank write bursts
< system.physmem.perBankWrBursts::11 9154 # Per bank write bursts
< system.physmem.perBankWrBursts::12 9556 # Per bank write bursts
< system.physmem.perBankWrBursts::13 10555 # Per bank write bursts
< system.physmem.perBankWrBursts::14 9521 # Per bank write bursts
< system.physmem.perBankWrBursts::15 9009 # Per bank write bursts
---
> system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 176173 # Number of read requests accepted
> system.physmem.writeReqs 171661 # Number of write requests accepted
> system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
> system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
> system.physmem.perBankRdBursts::1 10890 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10732 # Per bank write bursts
> system.physmem.perBankRdBursts::3 10393 # Per bank write bursts
> system.physmem.perBankRdBursts::4 14045 # Per bank write bursts
> system.physmem.perBankRdBursts::5 11531 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11498 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11674 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10645 # Per bank write bursts
> system.physmem.perBankRdBursts::9 10993 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10307 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9597 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9956 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10908 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10689 # Per bank write bursts
> system.physmem.perBankRdBursts::15 10844 # Per bank write bursts
> system.physmem.perBankWrBursts::0 9257 # Per bank write bursts
> system.physmem.perBankWrBursts::1 9346 # Per bank write bursts
> system.physmem.perBankWrBursts::2 9336 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8962 # Per bank write bursts
> system.physmem.perBankWrBursts::4 9705 # Per bank write bursts
> system.physmem.perBankWrBursts::5 9746 # Per bank write bursts
> system.physmem.perBankWrBursts::6 9125 # Per bank write bursts
> system.physmem.perBankWrBursts::7 9630 # Per bank write bursts
> system.physmem.perBankWrBursts::8 9307 # Per bank write bursts
> system.physmem.perBankWrBursts::9 9634 # Per bank write bursts
> system.physmem.perBankWrBursts::10 8942 # Per bank write bursts
> system.physmem.perBankWrBursts::11 8449 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8881 # Per bank write bursts
> system.physmem.perBankWrBursts::13 9361 # Per bank write bursts
> system.physmem.perBankWrBursts::14 9018 # Per bank write bursts
> system.physmem.perBankWrBursts::15 9072 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 2827025186500 # Total gap between requests
---
> system.physmem.numWrRetry 58 # Number of times write queue was full causing retry
> system.physmem.totGap 2827615975000 # Total gap between requests
105c105
< system.physmem.readPktSize::4 2993 # Read request sizes (log2)
---
> system.physmem.readPktSize::4 2994 # Read request sizes (log2)
107c107
< system.physmem.readPktSize::6 168384 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 172624 # Read request sizes (log2)
114,118c114,118
< system.physmem.writePktSize::6 163068 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 167280 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see
162,285c162,271
< system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads
< system.physmem.totQLat 2011805750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
> system.physmem.totQLat 2104910750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
287,291c273,277
< system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s
297,314c283,300
< system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing
< system.physmem.readRowHits 141825 # Number of row buffer hits during reads
< system.physmem.writeRowHits 127038 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes
< system.physmem.avgGap 8329945.36 # Average gap between requests
< system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ)
< system.physmem_0.averagePower 669.379373 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states
---
> system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing
> system.physmem.readRowHits 145058 # Number of row buffer hits during reads
> system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
> system.physmem.avgGap 8129210.99 # Average gap between requests
> system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
> system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
> system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
316c302
< system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
318,328c304,314
< system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ)
< system.physmem_1.averagePower 669.289511 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states
< system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states
---
> system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
> system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
> system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
330c316
< system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
350,354c336,340
< system.cpu.branchPred.lookups 46965884 # Number of BP lookups
< system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits
---
> system.cpu.branchPred.lookups 46937284 # Number of BP lookups
> system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits
356,358c342,344
< system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions.
389,407c375,393
< system.cpu.dtb.walker.walks 69937 # Table walker walks requested
< system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors
< system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate
< system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting
< system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu.dtb.walker.walks 72371 # Table walker walks requested
> system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors
> system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate
> system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting
> system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
409,436c395,425
< system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency
< system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency
< system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution
< system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated
< system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated
< system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency
> system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency
> system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution
> system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated
> system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated
> system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst
438,439c427,428
< system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst
441,442c430,431
< system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst
< system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst
---
> system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst
> system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
445,448c434,437
< system.cpu.dtb.read_hits 25472400 # DTB read hits
< system.cpu.dtb.read_misses 60528 # DTB read misses
< system.cpu.dtb.write_hits 19920178 # DTB write hits
< system.cpu.dtb.write_misses 9409 # DTB write misses
---
> system.cpu.dtb.read_hits 25461870 # DTB read hits
> system.cpu.dtb.read_misses 62291 # DTB read misses
> system.cpu.dtb.write_hits 19915387 # DTB write hits
> system.cpu.dtb.write_misses 10080 # DTB write misses
453,455c442,444
< system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions
< system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions
> system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
457,459c446,448
< system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 25532928 # DTB read accesses
< system.cpu.dtb.write_accesses 19929587 # DTB write accesses
---
> system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 25524161 # DTB read accesses
> system.cpu.dtb.write_accesses 19925467 # DTB write accesses
461,463c450,452
< system.cpu.dtb.hits 45392578 # DTB hits
< system.cpu.dtb.misses 69937 # DTB misses
< system.cpu.dtb.accesses 45462515 # DTB accesses
---
> system.cpu.dtb.hits 45377257 # DTB hits
> system.cpu.dtb.misses 72371 # DTB misses
> system.cpu.dtb.accesses 45449628 # DTB accesses
493,505c482,494
< system.cpu.itb.walker.walks 11957 # Table walker walks requested
< system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors
< system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate
< system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting
< system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
---
> system.cpu.itb.walker.walks 11974 # Table walker walks requested
> system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors
> system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate
> system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting
> system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
508,532c497,522
< system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency
< system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency
< system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution
< system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated
< system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated
---
> system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency
> system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency
> system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution
> system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated
> system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated
534,535c524,525
< system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst
---
> system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst
537,541c527,531
< system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst
< system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst
< system.cpu.itb.inst_hits 66242388 # ITB inst hits
< system.cpu.itb.inst_misses 11957 # ITB inst misses
---
> system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst
> system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst
> system.cpu.itb.inst_hits 66270436 # ITB inst hits
> system.cpu.itb.inst_misses 11974 # ITB inst misses
550c540
< system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB
554c544
< system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions
557,561c547,551
< system.cpu.itb.inst_accesses 66254345 # ITB inst accesses
< system.cpu.itb.hits 66242388 # DTB hits
< system.cpu.itb.misses 11957 # DTB misses
< system.cpu.itb.accesses 66254345 # DTB accesses
< system.cpu.numCycles 260505842 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 66282410 # ITB inst accesses
> system.cpu.itb.hits 66270436 # DTB hits
> system.cpu.itb.misses 11974 # DTB misses
> system.cpu.itb.accesses 66282410 # DTB accesses
> system.cpu.numCycles 263104506 # number of cpu cycles simulated
564,580c554,570
< system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total)
582,585c572,575
< system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total)
589,635c579,625
< system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
637,641c627,631
< system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
649c639
< system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle
651,681c641,671
< system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available
685,686c675,676
< system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued
710c700
< system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued
714,715c704,705
< system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
718,730c708,720
< system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued
< system.cpu.iq.rate 0.550386 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
> system.cpu.iq.rate 0.544758 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
732,735c722,725
< system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
738,739c728,729
< system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
741,744c731,734
< system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ
746,757c736,747
< system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
759,767c749,757
< system.cpu.iew.exec_nop 200965 # number of nop insts executed
< system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed
< system.cpu.iew.exec_branches 26544582 # Number of branches executed
< system.cpu.iew.exec_stores 20883032 # Number of stores executed
< system.cpu.iew.exec_rate 0.546767 # Inst execution rate
< system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 63301991 # num instructions producing a value
< system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 201053 # number of nop insts executed
> system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
> system.cpu.iew.exec_branches 26530134 # Number of branches executed
> system.cpu.iew.exec_stores 20877849 # Number of stores executed
> system.cpu.iew.exec_rate 0.541163 # Inst execution rate
> system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 63271750 # num instructions producing a value
> system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
769,770c759,760
< system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back
772,777c762,767
< system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle
779,787c769,777
< system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle
791,793c781,783
< system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 113361853 # Number of instructions committed
< system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 113305988 # Number of instructions committed
> system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed
795,798c785,788
< system.cpu.commit.refs 45532382 # Number of memory references committed
< system.cpu.commit.loads 24928817 # Number of loads committed
< system.cpu.commit.membars 814713 # Number of memory barriers committed
< system.cpu.commit.branches 26060941 # Number of branches committed
---
> system.cpu.commit.refs 45511652 # Number of memory references committed
> system.cpu.commit.loads 24916104 # Number of loads committed
> system.cpu.commit.membars 814017 # Number of memory barriers committed
> system.cpu.commit.branches 26045610 # Number of branches committed
800,801c790,791
< system.cpu.commit.int_insts 120284813 # Number of committed integer instructions.
< system.cpu.commit.function_calls 4896517 # Number of function calls committed.
---
> system.cpu.commit.int_insts 120229462 # Number of committed integer instructions.
> system.cpu.commit.function_calls 4892502 # Number of function calls committed.
803,804c793,794
< system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction
828c818
< system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction
---
> system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction
832,833c822,823
< system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction
836,837c826,827
< system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
839,852c829,842
< system.cpu.rob.rob_reads 373323554 # The number of ROB reads
< system.cpu.rob.rob_writes 293054802 # The number of ROB writes
< system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 113206948 # Number of Instructions Simulated
< system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 155872747 # number of integer regfile reads
< system.cpu.int_regfile_writes 88664446 # number of integer regfile writes
< system.cpu.fp_regfile_reads 9607 # number of floating regfile reads
---
> system.cpu.rob.rob_reads 375672050 # The number of ROB reads
> system.cpu.rob.rob_writes 292972268 # The number of ROB writes
> system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 113151083 # Number of Instructions Simulated
> system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
> system.cpu.int_regfile_writes 88633021 # number of integer regfile writes
> system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
854,866c844,856
< system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads
< system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes
< system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes
< system.cpu.dcache.tags.replacements 837844 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
---
> system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
> system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
> system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
> system.cpu.dcache.tags.replacements 839617 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy
868,870c858,860
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
872,954c862,944
< system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits
< system.cpu.dcache.overall_hits::total 39264228 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses
< system.cpu.dcache.overall_misses::total 4453577 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits
> system.cpu.dcache.overall_hits::total 39222942 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses
> system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
956c946
< system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
958c948
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked
962,1035c952,1025
< system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks
< system.cpu.dcache.writebacks::total 695426 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks
> system.cpu.dcache.writebacks::total 696320 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
1043,1051c1033,1041
< system.cpu.icache.tags.replacements 1894041 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 1892540 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy
1053,1056c1043,1046
< system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
1058,1096c1048,1086
< system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 64258114 # number of overall hits
< system.cpu.icache.overall_hits::total 64258114 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1981572 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1981572 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1981572 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1981572 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1981572 # number of overall misses
< system.cpu.icache.overall_misses::total 1981572 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26765848354 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26765848354 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26765848354 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26765848354 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26765848354 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 66239686 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 66239686 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 66239686 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 66239686 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029915 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.029915 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.029915 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.029915 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.029915 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.029915 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits
> system.cpu.icache.overall_hits::total 64285030 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses
> system.cpu.icache.overall_misses::total 1982600 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked
1098c1088
< system.cpu.icache.blocked::no_mshrs 103 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked
1100c1090
< system.cpu.icache.avg_blocked_cycles::no_mshrs 19.582524 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked
1104,1137c1094,1127
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87002 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 87002 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 87002 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 87002 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 87002 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 87002 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22163460869 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22163460869 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency
1143,1147c1133,1137
< system.cpu.l2cache.tags.replacements 98730 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 163872 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 18.424606 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 103160 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks.
1149,1155c1139,1145
< system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.158546 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798547 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy
1157,1195c1147,1185
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155608 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.079798 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.992968 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65129 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2965 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6995 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54988 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.993790 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 28438035 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 28438035 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53702 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11727 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1874573 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 527970 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2467972 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 695426 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 695426 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 159827 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 159827 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 53702 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 11727 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1874573 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 687797 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2627799 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 53702 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 11727 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1874573 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 687797 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2627799 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 20 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses
1197,1201c1187,1191
< system.cpu.l2cache.ReadReq_misses::cpu.inst 19971 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 13600 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 33598 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2743 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2743 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses
1204,1206c1194,1196
< system.cpu.l2cache.ReadExReq_misses::cpu.data 136984 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 136984 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 20 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses
1208,1211c1198,1201
< system.cpu.l2cache.demand_misses::cpu.inst 19971 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 150584 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 170582 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 20 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses
1213,1301c1203,1291
< system.cpu.l2cache.overall_misses::cpu.inst 19971 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 150584 # number of overall misses
< system.cpu.l2cache.overall_misses::total 170582 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1944750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1503081000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1083875750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2589438250 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 580975 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 580975 # number of UpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9863483701 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9863483701 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1944750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1503081000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10947359451 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12452921951 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1944750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1503081000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10947359451 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12452921951 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53722 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11734 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894544 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 541570 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2501570 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 695426 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 695426 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2775 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2775 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296811 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296811 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53722 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 11734 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1894544 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 838381 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2798381 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53722 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 11734 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1894544 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 838381 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2798381 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000372 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000597 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010541 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025112 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.013431 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988468 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988468 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461519 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.461519 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000372 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000597 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010541 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.179613 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.060957 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000372 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000597 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010541 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.179613 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.060957 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97237.500000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76678.571429 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75263.181613 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79696.746324 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 77071.202155 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 211.802771 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 211.802771 # average UpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72004.640695 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72004.640695 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73002.555668 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses
> system.cpu.l2cache.overall_misses::total 174879 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency
1310,1312c1300,1302
< system.cpu.l2cache.writebacks::writebacks 90654 # number of writebacks
< system.cpu.l2cache.writebacks::total 90654 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks
> system.cpu.l2cache.writebacks::total 94866 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
1314,1315c1304,1305
< system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
1317,1318c1307,1308
< system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
1320,1321c1310,1311
< system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 20 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses
1323,1327c1313,1317
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19946 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13488 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 33461 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2743 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2743 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses
1330,1332c1320,1322
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136984 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 136984 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 20 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses
1334,1337c1324,1327
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 19946 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 150472 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 170445 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 20 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses
1339,1412c1329,1402
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 19946 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 150472 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 170445 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1696750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1250973750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908888250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2162010000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27698243 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27698243 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8149358299 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8149358299 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1696750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1250973750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9058246549 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10311368299 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1696750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107345000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107345000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157876500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494788500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652665000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
1422,1446c1412,1436
< system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 65703 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
1451,1454c1441,1442
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram
1456,1459c1444,1447
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
1461c1449
< system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
1463c1451
< system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
1465c1453
< system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
1467c1455
< system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
1469c1457
< system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks)
1471,1474c1459,1462
< system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22814 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 30182 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30182 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
1476c1464
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
1497,1501c1485,1489
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
1522,1526c1510,1514
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
1566c1554
< system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks)
1570c1558
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
1572c1560
< system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks)
1574,1575c1562,1563
< system.iocache.tags.replacements 36410 # number of replacements
< system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use
---
> system.iocache.tags.replacements 36423 # number of replacements
> system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use
1577c1565
< system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
1579,1582c1567,1570
< system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy
1586,1589c1574,1577
< system.iocache.tags.tag_accesses 327996 # Number of tag accesses
< system.iocache.tags.data_accesses 327996 # Number of data accesses
< system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 220 # number of ReadReq misses
---
> system.iocache.tags.tag_accesses 328113 # Number of tag accesses
> system.iocache.tags.data_accesses 328113 # Number of data accesses
> system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 233 # number of ReadReq misses
1592,1605c1580,1593
< system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses
< system.iocache.demand_misses::total 220 # number of demand (read+write) misses
< system.iocache.overall_misses::realview.ide 220 # number of overall misses
< system.iocache.overall_misses::total 220 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles
< system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles
< system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses
> system.iocache.demand_misses::total 233 # number of demand (read+write) misses
> system.iocache.overall_misses::realview.ide 233 # number of overall misses
> system.iocache.overall_misses::total 233 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles
> system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses)
1608,1611c1596,1599
< system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses
< system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses
> system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses
1620,1628c1608,1616
< system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency
< system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked
1630c1618
< system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked
1632c1620
< system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked
1638,1639c1626,1627
< system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses
1642,1653c1630,1641
< system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles
1662,1669c1650,1657
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
1671,1675c1659,1663
< system.membus.trans_dist::ReadReq 67820 # Transaction distribution
< system.membus.trans_dist::ReadResp 67819 # Transaction distribution
< system.membus.trans_dist::WriteReq 27608 # Transaction distribution
< system.membus.trans_dist::WriteResp 27608 # Transaction distribution
< system.membus.trans_dist::Writeback 126844 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 68566 # Transaction distribution
> system.membus.trans_dist::ReadResp 68565 # Transaction distribution
> system.membus.trans_dist::WriteReq 27584 # Transaction distribution
> system.membus.trans_dist::WriteResp 27584 # Transaction distribution
> system.membus.trans_dist::Writeback 131056 # Transaction distribution
1678c1666
< system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution
1680,1683c1668,1671
< system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution
< system.membus.trans_dist::ReadExReq 135185 # Transaction distribution
< system.membus.trans_dist::ReadExResp 135185 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution
> system.membus.trans_dist::ReadExReq 138681 # Transaction distribution
> system.membus.trans_dist::ReadExResp 138681 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
1686,1691c1674,1679
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
1694,1695c1682,1683
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
1698,1700c1686,1688
< system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 484 # Total snoops (count)
< system.membus.snoop_fanout::samples 336478 # Request fanout histogram
---
> system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 497 # Total snoops (count)
> system.membus.snoop_fanout::samples 345038 # Request fanout histogram
1705c1693
< system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
1710,1711c1698,1699
< system.membus.snoop_fanout::total 336478 # Request fanout histogram
< system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 345038 # Request fanout histogram
> system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
1713c1701
< system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
1715c1703
< system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
1717,1721c1705,1709
< system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
1755c1743
< system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed