7,13c7,13
< host_inst_rate 97337 # Simulator instruction rate (inst/s)
< host_op_rate 118064 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2430592330 # Simulator tick rate (ticks/s)
< host_mem_usage 558776 # Number of bytes of host memory used
< host_seconds 1163.03 # Real time elapsed on the host
< sim_insts 113205077 # Number of instructions simulated
< sim_ops 137311743 # Number of ops (including micro ops) simulated
---
> host_inst_rate 107954 # Simulator instruction rate (inst/s)
> host_op_rate 130942 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2695726613 # Simulator tick rate (ticks/s)
> host_mem_usage 568304 # Number of bytes of host memory used
> host_seconds 1048.64 # Real time elapsed on the host
> sim_insts 113204796 # Number of instructions simulated
> sim_ops 137311416 # Number of ops (including micro ops) simulated
16,28d15
< system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
32a20
> system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
37d24
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
38a26
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
40d27
< system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44a32
> system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
47d34
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
48a36
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
50d37
< system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
54a42
> system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
59d46
< system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
60a48
> system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
63d50
< system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
67a55
> system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
73,74c61,62
< system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
---
> system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
78c66
< system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
90c78
< system.physmem.perBankRdBursts::9 11055 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 11056 # Per bank write bursts
130,131c118,119
< system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see
177,184c165,172
< system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see
186,191c174,179
< system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see
194c182
< system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see
197,202c185,190
< system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
226,231c214,219
< system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation
233,234c221,222
< system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation
236,243c224,231
< system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes
246,252c234,240
< system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads
257,263c245,251
< system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads
281,285c269,273
< system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads
< system.physmem.totQLat 2071957750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads
> system.physmem.totQLat 2072280000 # Total ticks spent queuing
> system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst
287c275
< system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst
298,299c286,287
< system.physmem.readRowHits 141999 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95218 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 142002 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95212 # Number of row buffer hits during writes
303,304c291,292
< system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states
---
> system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states
307c295
< system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states
309,312c297,300
< system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
---
> system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ)
314c302
< system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ)
---
> system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ)
319,409c307,326
< system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.335912 # Core power per rank (mW)
< system.physmem.averagePower::1 669.239814 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 67834 # Transaction distribution
< system.membus.trans_dist::ReadResp 67833 # Transaction distribution
< system.membus.trans_dist::WriteReq 27608 # Transaction distribution
< system.membus.trans_dist::WriteResp 27608 # Transaction distribution
< system.membus.trans_dist::Writeback 90626 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
< system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
< system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 205 # Total snoops (count)
< system.membus.snoop_fanout::samples 300222 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 300222 # Request fanout histogram
< system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
< system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks)
< system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks)
< system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
< system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks)
< system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
< system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
< system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
---
> system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.336036 # Core power per rank (mW)
> system.physmem.averagePower::1 669.240113 # Core power per rank (mW)
> system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
416,523c333,337
< system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
< system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
< system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
< system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
< system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
< system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
< system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
< system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
< system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
< system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
< system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
< system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
< system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
< system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
< system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
< system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
< system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
< system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
< system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
< system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
< system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.branchPred.lookups 46964481 # Number of BP lookups
< system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits
---
> system.cpu.branchPred.lookups 46964274 # Number of BP lookups
> system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits
525,526c339,340
< system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target.
527a342
> system.cpu_clk_domain.clock 500 # Clock period in ticks
551,553c366,368
< system.cpu.dtb.read_hits 25471928 # DTB read hits
< system.cpu.dtb.read_misses 60410 # DTB read misses
< system.cpu.dtb.write_hits 19919780 # DTB write hits
---
> system.cpu.dtb.read_hits 25471879 # DTB read hits
> system.cpu.dtb.read_misses 60408 # DTB read misses
> system.cpu.dtb.write_hits 19919747 # DTB write hits
564,565c379,380
< system.cpu.dtb.read_accesses 25532338 # DTB read accesses
< system.cpu.dtb.write_accesses 19929168 # DTB write accesses
---
> system.cpu.dtb.read_accesses 25532287 # DTB read accesses
> system.cpu.dtb.write_accesses 19929135 # DTB write accesses
567,569c382,384
< system.cpu.dtb.hits 45391708 # DTB hits
< system.cpu.dtb.misses 69798 # DTB misses
< system.cpu.dtb.accesses 45461506 # DTB accesses
---
> system.cpu.dtb.hits 45391626 # DTB hits
> system.cpu.dtb.misses 69796 # DTB misses
> system.cpu.dtb.accesses 45461422 # DTB accesses
591c406
< system.cpu.itb.inst_hits 66240861 # ITB inst hits
---
> system.cpu.itb.inst_hits 66240582 # ITB inst hits
608,609c423,424
< system.cpu.itb.inst_accesses 66252797 # ITB inst accesses
< system.cpu.itb.hits 66240861 # DTB hits
---
> system.cpu.itb.inst_accesses 66252518 # ITB inst accesses
> system.cpu.itb.hits 66240582 # DTB hits
611,612c426,427
< system.cpu.itb.accesses 66252797 # DTB accesses
< system.cpu.numCycles 260549216 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 66252518 # DTB accesses
> system.cpu.numCycles 260548868 # number of cpu cycles simulated
615,620c430,435
< system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing
626,627c441,442
< system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed
---
> system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed
629,630c444,445
< system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total)
633,636c448,451
< system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total)
640,647c455,462
< system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing
---
> system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing
649,660c464,475
< system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full
---
> system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full
663,666c478,481
< system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups
668,677c483,492
< system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec)
679,682c494,497
< system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph
684c499
< system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle
688,692c503,507
< system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle
700c515
< system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle
702c517
< system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available
731,732c546,547
< system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available
736,737c551,552
< system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued
765,766c580,581
< system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued
769c584
< system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued
771,775c586,590
< system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses
779c594
< system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses
781c596
< system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores
785,786c600,601
< system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed
792,795c607,610
< system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ
797,798c612,613
< system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions
801,808c616,623
< system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute
811,813c626,628
< system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed
< system.cpu.iew.exec_branches 26544157 # Number of branches executed
< system.cpu.iew.exec_stores 20882594 # Number of stores executed
---
> system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed
> system.cpu.iew.exec_branches 26544085 # Number of branches executed
> system.cpu.iew.exec_stores 20882571 # Number of stores executed
815,818c630,633
< system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 63301722 # num instructions producing a value
< system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value
---
> system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 63301578 # num instructions producing a value
> system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value
823c638
< system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit
825,826c640,641
< system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle
828c643
< system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle
830,833c645,648
< system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle
835,838c650,653
< system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle
842,844c657,659
< system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 113359982 # Number of instructions committed
< system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 113359701 # Number of instructions committed
> system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed
846,847c661,662
< system.cpu.commit.refs 45531388 # Number of memory references committed
< system.cpu.commit.loads 24928306 # Number of loads committed
---
> system.cpu.commit.refs 45531319 # Number of memory references committed
> system.cpu.commit.loads 24928258 # Number of loads committed
849c664
< system.cpu.commit.branches 26060542 # Number of branches committed
---
> system.cpu.commit.branches 26060472 # Number of branches committed
851,852c666,667
< system.cpu.commit.int_insts 120282409 # Number of committed integer instructions.
< system.cpu.commit.function_calls 4896404 # Number of function calls committed.
---
> system.cpu.commit.int_insts 120282111 # Number of committed integer instructions.
> system.cpu.commit.function_calls 4896381 # Number of function calls committed.
854,855c669,670
< system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction
883,884c698,699
< system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction
887,888c702,703
< system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached
890,898c705,713
< system.cpu.rob.rob_reads 373371044 # The number of ROB reads
< system.cpu.rob.rob_writes 293051212 # The number of ROB writes
< system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 113205077 # Number of Instructions Simulated
< system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads
---
> system.cpu.rob.rob_reads 373370450 # The number of ROB reads
> system.cpu.rob.rob_writes 293050441 # The number of ROB writes
> system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 113204796 # Number of Instructions Simulated
> system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads
901,902c716,717
< system.cpu.int_regfile_reads 155870959 # number of integer regfile reads
< system.cpu.int_regfile_writes 88663005 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 155870535 # number of integer regfile reads
> system.cpu.int_regfile_writes 88662743 # number of integer regfile writes
905,907c720,722
< system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads
< system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes
< system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 503158959 # number of cc regfile reads
> system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes
> system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads
909,958c724,909
< system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
< system.cpu.icache.tags.replacements 1894038 # number of replacements
---
> system.cpu.dcache.tags.replacements 837744 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits
> system.cpu.dcache.overall_hits::total 39265000 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses
> system.cpu.dcache.overall_misses::total 4451395 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks
> system.cpu.dcache.writebacks::total 695413 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
> system.cpu.icache.tags.replacements 1894031 # number of replacements
960,962c911,913
< system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks.
973,998c924,949
< system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits
< system.cpu.icache.overall_hits::total 64256715 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses
< system.cpu.icache.overall_misses::total 1981457 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 64256441 # number of overall hits
> system.cpu.icache.overall_hits::total 64256441 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1981452 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1981452 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1981452 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1981452 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1981452 # number of overall misses
> system.cpu.icache.overall_misses::total 1981452 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26762198879 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26762198879 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26762198879 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26762198879 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26762198879 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses
1005,1010c956,961
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency
1019,1036c970,987
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles
1047,1052c998,1003
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency
1059,1060c1010,1011
< system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks.
1062c1013
< system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks.
1064c1015
< system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor
1067,1068c1018,1019
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor
1085,1087c1036,1038
< system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits
1089,1093c1040,1044
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits
1100c1051
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 53838 # number of demand (read+write) hits
1102,1105c1053,1056
< system.cpu.l2cache.demand_hits::cpu.inst 1874571 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 687724 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2627795 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 53840 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1874564 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 687722 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2627784 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 53838 # number of overall hits
1107,1109c1058,1060
< system.cpu.l2cache.overall_hits::cpu.inst 1874571 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 687724 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2627795 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1874564 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 687722 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2627784 # number of overall hits
1133,1135c1084,1086
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1500107250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078643000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2580745000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1499718000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078687250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2580400000 # number of ReadReq miss cycles
1140,1141c1091,1092
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9922806190 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9922806190 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9923495690 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9923495690 # number of ReadExReq miss cycles
1144,1146c1095,1097
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1500107250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11001449190 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12503551190 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1499718000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11002182940 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12503895690 # number of demand (read+write) miss cycles
1149,1152c1100,1103
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1500107250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11001449190 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12503551190 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53859 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1499718000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11002182940 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12503895690 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53857 # number of ReadReq accesses(hits+misses)
1154,1158c1105,1109
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894537 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 541656 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2501719 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 695414 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 695414 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894530 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 541654 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2501708 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 695413 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 695413 # number of Writeback accesses(hits+misses)
1165c1116
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53859 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53857 # number of demand (read+write) accesses
1167,1170c1118,1121
< system.cpu.l2cache.demand_accesses::cpu.inst 1894537 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 838281 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2798344 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53859 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1894530 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 838279 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2798333 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53857 # number of overall (read+write) accesses
1172,1174c1123,1125
< system.cpu.l2cache.overall_accesses::cpu.inst 1894537 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 838281 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2798344 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1894530 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 838279 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2798333 # number of overall (read+write) accesses
1190c1141
< system.cpu.l2cache.demand_miss_rate::total 0.060946 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.060947 # miss rate for demand accesses
1195c1146
< system.cpu.l2cache.overall_miss_rate::total 0.060946 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::total 0.060947 # miss rate for overall accesses
1198,1200c1149,1151
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75133.088751 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79195.521292 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 76780.465310 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75113.593108 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79198.770191 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76770.201119 # average ReadReq miss latency
1205,1206c1156,1157
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72462.564464 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72462.564464 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72467.599626 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72467.599626 # average ReadExReq miss latency
1209,1211c1160,1162
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73313.541504 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73315.561452 # average overall miss latency
1214,1216c1165,1167
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73313.541504 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75113.593108 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73076.528757 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73315.561452 # average overall miss latency
1259,1261c1210,1212
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1248209500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902938000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152822250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1247817250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902981250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152473250 # number of ReadReq MSHR miss cycles
1266,1267c1217,1218
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8209305810 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8209305810 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8210001310 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8210001310 # number of ReadExReq MSHR miss cycles
1270,1272c1221,1223
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1248209500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112243810 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10362128060 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1247817250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112982560 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10362474560 # number of demand (read+write) MSHR miss cycles
1275,1277c1226,1228
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1248209500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112243810 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10362128060 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1247817250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112982560 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10362474560 # number of overall MSHR miss cycles
1279,1280c1230,1231
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387481250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545358250 # number of ReadReq MSHR uncacheable cycles
---
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387482250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545359250 # number of ReadReq MSHR uncacheable cycles
1284,1285c1235,1236
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494822250 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652699250 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494823250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652700250 # number of overall MSHR uncacheable cycles
1300,1301c1251,1252
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060897 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060898 # mshr miss rate for demand accesses
1305,1306c1256,1257
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.060897 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179469 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.060898 # mshr miss rate for overall accesses
1309,1311c1260,1262
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62595.130635 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66844.684631 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64311.344287 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62575.460107 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66847.886438 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64300.918596 # average ReadReq mshr miss latency
1316,1317c1267,1268
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency
1320,1322c1271,1273
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
1325,1327c1276,1278
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
1337,1521c1288,1438
< system.cpu.dcache.tags.replacements 837746 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits
< system.cpu.dcache.overall_hits::total 39265074 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses
< system.cpu.dcache.overall_misses::total 4451402 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks
< system.cpu.dcache.writebacks::total 695414 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 3525400 98.98% 98.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
> system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
> system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
> system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
> system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
> system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
> system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
> system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
> system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
> system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
> system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
> system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
> system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
> system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
> system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
> system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
> system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
> system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
> system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
> system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
> system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
> system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
1606a1524,1606
> system.membus.trans_dist::ReadReq 67834 # Transaction distribution
> system.membus.trans_dist::ReadResp 67833 # Transaction distribution
> system.membus.trans_dist::WriteReq 27608 # Transaction distribution
> system.membus.trans_dist::WriteResp 27608 # Transaction distribution
> system.membus.trans_dist::Writeback 90626 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
> system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
> system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 205 # Total snoops (count)
> system.membus.snoop_fanout::samples 300222 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 300222 # Request fanout histogram
> system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
> system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks)
> system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
> system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks)
> system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
> system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks)
> system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
> system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
> system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped