3,5c3,5
< sim_seconds 2.826846 # Number of seconds simulated
< sim_ticks 2826845674500 # Number of ticks simulated
< final_tick 2826845674500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.826844 # Number of seconds simulated
> sim_ticks 2826844351500 # Number of ticks simulated
> final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 98010 # Simulator instruction rate (inst/s)
< host_op_rate 118881 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2448127815 # Simulator tick rate (ticks/s)
< host_mem_usage 558668 # Number of bytes of host memory used
< host_seconds 1154.70 # Real time elapsed on the host
< sim_insts 113172343 # Number of instructions simulated
< sim_ops 137271263 # Number of ops (including micro ops) simulated
---
> host_inst_rate 97337 # Simulator instruction rate (inst/s)
> host_op_rate 118064 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2430592330 # Simulator tick rate (ticks/s)
> host_mem_usage 558776 # Number of bytes of host memory used
> host_seconds 1163.03 # Real time elapsed on the host
> sim_insts 113205077 # Number of instructions simulated
> sim_ops 137311743 # Number of ops (including micro ops) simulated
31,36c31,36
< system.physmem.bytes_read::cpu.inst 1324880 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9515236 # Number of bytes read from this memory
< system.physmem.bytes_read::total 10842740 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1324880 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1324880 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5801024 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory
> system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory
39c39
< system.physmem.bytes_written::total 8136884 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory
43,46c43,46
< system.physmem.num_reads::cpu.inst 22946 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 149195 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 172182 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 90641 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory
49c49
< system.physmem.num_writes::total 131246 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory
53,58c53,58
< system.physmem.bw_read::cpu.inst 468678 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3366026 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 3835632 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 468678 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 468678 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2052119 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s)
61,62c61,62
< system.physmem.bw_write::total 2878432 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2052119 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s)
66,78c66,78
< system.physmem.bw_total::cpu.inst 468678 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3372225 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 6714064 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 172183 # Number of read requests accepted
< system.physmem.writeReqs 131246 # Number of write requests accepted
< system.physmem.readBursts 172183 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 131246 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 11011008 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8150720 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 10842804 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8136884 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 172165 # Number of read requests accepted
> system.physmem.writeReqs 131231 # Number of write requests accepted
> system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
81c81
< system.physmem.perBankRdBursts::0 10992 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 10989 # Per bank write bursts
83,84c83,84
< system.physmem.perBankRdBursts::2 11200 # Per bank write bursts
< system.physmem.perBankRdBursts::3 11425 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 11201 # Per bank write bursts
> system.physmem.perBankRdBursts::3 11419 # Per bank write bursts
86,91c86,91
< system.physmem.perBankRdBursts::5 10553 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11175 # Per bank write bursts
< system.physmem.perBankRdBursts::7 11538 # Per bank write bursts
< system.physmem.perBankRdBursts::8 10354 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11059 # Per bank write bursts
< system.physmem.perBankRdBursts::10 10499 # Per bank write bursts
---
> system.physmem.perBankRdBursts::5 10546 # Per bank write bursts
> system.physmem.perBankRdBursts::6 11171 # Per bank write bursts
> system.physmem.perBankRdBursts::7 11539 # Per bank write bursts
> system.physmem.perBankRdBursts::8 10356 # Per bank write bursts
> system.physmem.perBankRdBursts::9 11055 # Per bank write bursts
> system.physmem.perBankRdBursts::10 10496 # Per bank write bursts
96c96
< system.physmem.perBankRdBursts::15 9748 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 9745 # Per bank write bursts
100c100
< system.physmem.perBankWrBursts::3 8608 # Per bank write bursts
---
> system.physmem.perBankWrBursts::3 8604 # Per bank write bursts
102,103c102,103
< system.physmem.perBankWrBursts::5 7956 # Per bank write bursts
< system.physmem.perBankWrBursts::6 8259 # Per bank write bursts
---
> system.physmem.perBankWrBursts::5 7949 # Per bank write bursts
> system.physmem.perBankWrBursts::6 8258 # Per bank write bursts
105,107c105,107
< system.physmem.perBankWrBursts::8 7842 # Per bank write bursts
< system.physmem.perBankWrBursts::9 8532 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7844 # Per bank write bursts
---
> system.physmem.perBankWrBursts::8 7843 # Per bank write bursts
> system.physmem.perBankWrBursts::9 8531 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7842 # Per bank write bursts
112c112
< system.physmem.perBankWrBursts::15 7119 # Per bank write bursts
---
> system.physmem.perBankWrBursts::15 7118 # Per bank write bursts
114,115c114,115
< system.physmem.numWrRetry 6 # Number of times write queue was full causing retry
< system.physmem.totGap 2826845408500 # Total gap between requests
---
> system.physmem.numWrRetry 5 # Number of times write queue was full causing retry
> system.physmem.totGap 2826844140500 # Total gap between requests
122c122
< system.physmem.readPktSize::6 168635 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 168617 # Read request sizes (log2)
129,134c129,134
< system.physmem.writePktSize::6 126865 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 151996 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 15999 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 3230 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 126850 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
177,220c177,220
< system.physmem.wrQLenPdf::15 1978 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2552 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6555 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7265 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7503 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8022 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 8831 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8320 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7973 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6966 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6819 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6815 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6654 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 165 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 130 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 73 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 57 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 50 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 96 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 93 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 78 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 62 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 61 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 43 # What write queue length does an incoming req see
222,223c222,223
< system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
225,243c225,243
< system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 62171 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 308.209036 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 180.794963 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 329.700925 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 23473 37.76% 37.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 14721 23.68% 61.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 6339 10.20% 71.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3681 5.92% 77.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2625 4.22% 81.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1528 2.46% 84.23% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1121 1.80% 86.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1145 1.84% 87.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7538 12.12% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 62171 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 26.780822 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 556.317098 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes
246,283c246,285
< system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.824875 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.368849 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 11.569917 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 5609 87.31% 87.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 57 0.89% 88.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 29 0.45% 88.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 222 3.46% 92.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 216 3.36% 95.47% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 23 0.36% 95.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 19 0.30% 96.12% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 12 0.19% 96.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 14 0.22% 96.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.06% 96.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 4 0.06% 96.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 4 0.06% 96.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 154 2.40% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 11 0.17% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 3 0.05% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 2 0.03% 99.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 10 0.16% 99.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 4 0.06% 99.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 4 0.06% 99.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 3 0.05% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 4 0.06% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 8 0.12% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.03% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads
< system.physmem.totQLat 2068507750 # Total ticks spent queuing
< system.physmem.totMemAccLat 5294389000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 860235000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12022.92 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 10 0.16% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.02% 99.55% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 5 0.08% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 4 0.06% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 2 0.03% 99.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 4 0.06% 99.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 3 0.05% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 1 0.02% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads
> system.physmem.totQLat 2071957750 # Total ticks spent queuing
> system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst
285,286c287,288
< system.physmem.avgMemAccLat 30772.92 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 3.90 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s
295,303c297,305
< system.physmem.avgWrQLen 27.06 # Average write queue length when enqueuing
< system.physmem.readRowHits 142034 # Number of row buffer hits during reads
< system.physmem.writeRowHits 95196 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 74.74 # Row buffer hit rate for writes
< system.physmem.avgGap 9316332.35 # Average gap between requests
< system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2694724296750 # Time in different power states
< system.physmem.memoryStateTime::REF 94394560000 # Time in different power states
---
> system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing
> system.physmem.readRowHits 141999 # Number of row buffer hits during reads
> system.physmem.writeRowHits 95218 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes
> system.physmem.avgGap 9317341.50 # Average gap between requests
> system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states
> system.physmem.memoryStateTime::REF 94394300000 # Time in different power states
305c307
< system.physmem.memoryStateTime::ACT 37726803750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states
307,326c309,328
< system.physmem.actEnergy::0 245851200 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 224161560 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 134145000 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 122310375 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 703053000 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 638905800 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 426345120 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 398915280 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 184635759360 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 184635759360 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 80323317855 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 79082766720 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 1625647965000 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 1626736167750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 1892116436535 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 1891838986845 # Total energy per rank (pJ)
< system.physmem.averagePower::0 669.338580 # Core power per rank (mW)
< system.physmem.averagePower::1 669.240432 # Core power per rank (mW)
< system.membus.trans_dist::ReadReq 67851 # Transaction distribution
< system.membus.trans_dist::ReadResp 67850 # Transaction distribution
---
> system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ)
> system.physmem.averagePower::0 669.335912 # Core power per rank (mW)
> system.physmem.averagePower::1 669.239814 # Core power per rank (mW)
> system.membus.trans_dist::ReadReq 67834 # Transaction distribution
> system.membus.trans_dist::ReadResp 67833 # Transaction distribution
329c331
< system.membus.trans_dist::Writeback 90641 # Transaction distribution
---
> system.membus.trans_dist::Writeback 90626 # Transaction distribution
335,336c337,338
< system.membus.trans_dist::ReadExReq 135128 # Transaction distribution
< system.membus.trans_dist::ReadExResp 135128 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
> system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
340,341c342,343
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452828 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560464 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
344c346
< system.membus.pkt_count::total 633147 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
348,349c350,351
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16660328 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16823793 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
352c354
< system.membus.pkt_size::total 19143089 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
354c356
< system.membus.snoop_fanout::samples 300256 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 300222 # Request fanout histogram
359c361
< system.membus.snoop_fanout::1 300256 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
364,365c366,367
< system.membus.snoop_fanout::total 300256 # Request fanout histogram
< system.membus.reqLayer0.occupancy 94208500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 300222 # Request fanout histogram
> system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks)
369c371
< system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks)
371c373
< system.membus.reqLayer5.occupancy 1358148499 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks)
373c375
< system.membus.respLayer2.occupancy 1678211205 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks)
375c377
< system.membus.respLayer3.occupancy 38219486 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
416c418
< system.iobus.trans_dist::WriteReq 59035 # Transaction distribution
---
> system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
418d419
< system.iobus.trans_dist::WriteInvalidateReq 3 # Transaction distribution
509c510
< system.iobus.reqLayer27.occupancy 326561347 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
515c516
< system.iobus.respLayer3.occupancy 36777514 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
518,522c519,523
< system.cpu.branchPred.lookups 46931803 # Number of BP lookups
< system.cpu.branchPred.condPredicted 24038690 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1232826 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 29540441 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 21359776 # Number of BTB hits
---
> system.cpu.branchPred.lookups 46964481 # Number of BP lookups
> system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits
524,526c525,527
< system.cpu.branchPred.BTBHitPct 72.306896 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 11753594 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 33738 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions.
550,553c551,554
< system.cpu.dtb.read_hits 25464394 # DTB read hits
< system.cpu.dtb.read_misses 60419 # DTB read misses
< system.cpu.dtb.write_hits 19915991 # DTB write hits
< system.cpu.dtb.write_misses 9380 # DTB write misses
---
> system.cpu.dtb.read_hits 25471928 # DTB read hits
> system.cpu.dtb.read_misses 60410 # DTB read misses
> system.cpu.dtb.write_hits 19919780 # DTB write hits
> system.cpu.dtb.write_misses 9388 # DTB write misses
562,564c563,565
< system.cpu.dtb.perms_faults 1298 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 25524813 # DTB read accesses
< system.cpu.dtb.write_accesses 19925371 # DTB write accesses
---
> system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 25532338 # DTB read accesses
> system.cpu.dtb.write_accesses 19929168 # DTB write accesses
566,568c567,569
< system.cpu.dtb.hits 45380385 # DTB hits
< system.cpu.dtb.misses 69799 # DTB misses
< system.cpu.dtb.accesses 45450184 # DTB accesses
---
> system.cpu.dtb.hits 45391708 # DTB hits
> system.cpu.dtb.misses 69798 # DTB misses
> system.cpu.dtb.accesses 45461506 # DTB accesses
590,591c591,592
< system.cpu.itb.inst_hits 66292387 # ITB inst hits
< system.cpu.itb.inst_misses 11931 # ITB inst misses
---
> system.cpu.itb.inst_hits 66240861 # ITB inst hits
> system.cpu.itb.inst_misses 11936 # ITB inst misses
604c605
< system.cpu.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
607,611c608,612
< system.cpu.itb.inst_accesses 66304318 # ITB inst accesses
< system.cpu.itb.hits 66292387 # DTB hits
< system.cpu.itb.misses 11931 # DTB misses
< system.cpu.itb.accesses 66304318 # DTB accesses
< system.cpu.numCycles 260551438 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 66252797 # ITB inst accesses
> system.cpu.itb.hits 66240861 # DTB hits
> system.cpu.itb.misses 11936 # DTB misses
> system.cpu.itb.accesses 66252797 # DTB accesses
> system.cpu.numCycles 260549216 # number of cpu cycles simulated
614,623c615,624
< system.cpu.fetch.icacheStallCycles 104869846 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 184735553 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 46931803 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 33113370 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 145618302 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 6158524 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 168617 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 7866 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 338980 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 503793 # Number of stall cycles due to pending quiesce instructions
---
> system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions
625,630c626,631
< system.cpu.fetch.CacheLines 66292691 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 1129489 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 4986 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 254586778 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.885055 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.237579 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total)
632,635c633,636
< system.cpu.fetch.rateDist::0 155297274 61.00% 61.00% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 29234666 11.48% 72.48% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 14075849 5.53% 78.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 55978989 21.99% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total)
639,665c640,666
< system.cpu.fetch.rateDist::total 254586778 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.180125 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.709018 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 78083511 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 105413176 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 64659521 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 3829076 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 2601494 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 3422198 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 486019 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 157443787 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 3691480 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 2601494 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 83923016 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 10014229 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 74542225 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 62654018 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 20851796 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 146804356 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 950141 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 437053 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 62758 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 16395 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 18089126 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 150489312 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 678755433 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 164431250 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups
667,685c668,686
< system.cpu.rename.CommittedMaps 141833425 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 8655884 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 2845858 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 2649612 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 13844659 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 26410647 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 21300346 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1686617 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2194239 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 143538852 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2120894 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 143334300 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 269212 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 6251138 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 14652316 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 125305 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 254586778 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.563008 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.882453 # Number of insts issued each cycle
---
> system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle
687,691c688,692
< system.cpu.iq.issued_per_cycle::0 166323253 65.33% 65.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 45116884 17.72% 83.05% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 32035807 12.58% 95.64% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10297567 4.04% 99.68% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 813234 0.32% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle
699c700
< system.cpu.iq.issued_per_cycle::total 254586778 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle
701c702
< system.cpu.iq.fu_full::IntAlu 7369685 32.63% 32.63% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available
730,731c731,732
< system.cpu.iq.fu_full::MemRead 5632098 24.94% 57.57% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 9582629 42.43% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available
735,736c736,737
< system.cpu.iq.FU_type_0::IntAlu 96007549 66.98% 66.98% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 113996 0.08% 67.06% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued
764,765c765,766
< system.cpu.iq.FU_type_0::MemRead 26193546 18.27% 85.34% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 21008282 14.66% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued
768,775c769,776
< system.cpu.iq.FU_type_0::total 143334300 # Type of FU issued
< system.cpu.iq.rate 0.550119 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 22584444 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.157565 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 564073322 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 151915928 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 140220511 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 35712 # Number of floating instruction queue reads
---
> system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued
> system.cpu.iq.rate 0.550285 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads
778,780c779,781
< system.cpu.iq.int_alu_accesses 165892999 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 23408 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 324281 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores
782,785c783,786
< system.cpu.iew.lsq.thread0.squashedLoads 1489992 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 534 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 18266 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 701073 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed
788,789c789,790
< system.cpu.iew.lsq.thread0.rescheduledLoads 88010 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 6363 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked
791,794c792,795
< system.cpu.iew.iewSquashCycles 2601494 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 945264 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 289569 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 145860692 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ
796,798c797,799
< system.cpu.iew.iewDispLoadInsts 26410647 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 21300346 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1096041 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions
800,807c801,808
< system.cpu.iew.iewLSQFullEvents 254692 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 18266 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 317528 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 471649 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 789177 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 142391856 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 25792498 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 872750 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute
809,817c810,818
< system.cpu.iew.exec_nop 200946 # number of nop insts executed
< system.cpu.iew.exec_refs 46671293 # number of memory reference insts executed
< system.cpu.iew.exec_branches 26532601 # Number of branches executed
< system.cpu.iew.exec_stores 20878795 # Number of stores executed
< system.cpu.iew.exec_rate 0.546502 # Inst execution rate
< system.cpu.iew.wb_sent 142004641 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 140231942 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 63282838 # num instructions producing a value
< system.cpu.iew.wb_consumers 95859178 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 200927 # number of nop insts executed
> system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed
> system.cpu.iew.exec_branches 26544157 # Number of branches executed
> system.cpu.iew.exec_stores 20882594 # Number of stores executed
> system.cpu.iew.exec_rate 0.546668 # Inst execution rate
> system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 63301722 # num instructions producing a value
> system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value
819,820c820,821
< system.cpu.iew.wb_rate 0.538212 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back
822,827c823,828
< system.cpu.commit.commitSquashedInsts 7590534 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1995589 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 755058 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 251652322 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.546095 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.146746 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle
829,837c830,838
< system.cpu.commit.committed_per_cycle::0 178202586 70.81% 70.81% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 43292722 17.20% 88.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 15476092 6.15% 94.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 4357171 1.73% 95.90% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 6368006 2.53% 98.43% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1679722 0.67% 99.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 777425 0.31% 99.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 414219 0.16% 99.57% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1084379 0.43% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle
841,843c842,844
< system.cpu.commit.committed_per_cycle::total 251652322 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 113327248 # Number of instructions committed
< system.cpu.commit.committedOps 137426168 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 113359982 # Number of instructions committed
> system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed
845,848c846,849
< system.cpu.commit.refs 45519928 # Number of memory references committed
< system.cpu.commit.loads 24920655 # Number of loads committed
< system.cpu.commit.membars 814679 # Number of memory barriers committed
< system.cpu.commit.branches 26048896 # Number of branches committed
---
> system.cpu.commit.refs 45531388 # Number of memory references committed
> system.cpu.commit.loads 24928306 # Number of loads committed
> system.cpu.commit.membars 814674 # Number of memory barriers committed
> system.cpu.commit.branches 26060542 # Number of branches committed
850,851c851,852
< system.cpu.commit.int_insts 120245785 # Number of committed integer instructions.
< system.cpu.commit.function_calls 4892513 # Number of function calls committed.
---
> system.cpu.commit.int_insts 120282409 # Number of committed integer instructions.
> system.cpu.commit.function_calls 4896404 # Number of function calls committed.
853,854c854,855
< system.cpu.commit.op_class_0::IntAlu 91784658 66.79% 66.79% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 112993 0.08% 66.87% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction
882,883c883,884
< system.cpu.commit.op_class_0::MemRead 24920655 18.13% 85.01% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 20599273 14.99% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction
886,887c887,888
< system.cpu.commit.op_class_0::total 137426168 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1084379 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached
889,901c890,902
< system.cpu.rob.rob_reads 373356629 # The number of ROB reads
< system.cpu.rob.rob_writes 292965429 # The number of ROB writes
< system.cpu.timesIdled 892862 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 5964660 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 5393139912 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 113172343 # Number of Instructions Simulated
< system.cpu.committedOps 137271263 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 2.302254 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 2.302254 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.434357 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.434357 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 155828809 # number of integer regfile reads
< system.cpu.int_regfile_writes 88634133 # number of integer regfile writes
---
> system.cpu.rob.rob_reads 373371044 # The number of ROB reads
> system.cpu.rob.rob_writes 293051212 # The number of ROB writes
> system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 113205077 # Number of Instructions Simulated
> system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 155870959 # number of integer regfile reads
> system.cpu.int_regfile_writes 88663005 # number of integer regfile writes
904,909c905,910
< system.cpu.cc_regfile_reads 503010933 # number of cc regfile reads
< system.cpu.cc_regfile_writes 53185281 # number of cc regfile writes
< system.cpu.misc_regfile_reads 444154417 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1521566 # number of misc regfile writes
< system.cpu.toL2Bus.trans_dist::ReadReq 2565070 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2565005 # Transaction distribution
---
> system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads
> system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes
> system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes
> system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution
912,914c913,915
< system.cpu.toL2Bus.trans_dist::Writeback 695424 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2768 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
916,930c917,931
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2773 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 296628 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 296628 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795251 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495257 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31166 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128727 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 6450401 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121302864 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98352737 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46636 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215424 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 219917661 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 65503 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3561986 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram
939,940c940,941
< system.cpu.toL2Bus.snoop_fanout::5 3525536 98.98% 98.98% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36450 1.02% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram
944,945c945,946
< system.cpu.toL2Bus.snoop_fanout::total 3561986 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 2503006527 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks)
949c950
< system.cpu.toL2Bus.respLayer0.occupancy 2849563150 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks)
951c952
< system.cpu.toL2Bus.respLayer1.occupancy 1334496858 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks)
953c954
< system.cpu.toL2Bus.respLayer2.occupancy 19512240 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
955c956
< system.cpu.toL2Bus.respLayer3.occupancy 74894955 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks)
957,961c958,962
< system.cpu.icache.tags.replacements 1894110 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.373809 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 64308148 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1894622 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 33.942469 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 1894038 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks.
963c964
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.373809 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor
972,1010c973,1011
< system.cpu.icache.tags.tag_accesses 68184330 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 68184330 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 64308148 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 64308148 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 64308148 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 64308148 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 64308148 # number of overall hits
< system.cpu.icache.overall_hits::total 64308148 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1981542 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1981542 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1981542 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1981542 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1981542 # number of overall misses
< system.cpu.icache.overall_misses::total 1981542 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763338374 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 26763338374 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 26763338374 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 26763338374 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 26763338374 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 26763338374 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 66289690 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 66289690 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 66289690 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 66289690 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 66289690 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 66289690 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029892 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.029892 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.029892 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.029892 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.029892 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.029892 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.319005 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13506.319005 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13506.319005 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.319005 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13506.319005 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 2089 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits
> system.cpu.icache.overall_hits::total 64256715 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses
> system.cpu.icache.overall_misses::total 1981457 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked
1012c1013
< system.cpu.icache.blocked::no_mshrs 104 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked
1014c1015
< system.cpu.icache.avg_blocked_cycles::no_mshrs 20.086538 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 # average number of cycles each access was blocked
1018,1051c1019,1052
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86900 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 86900 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 86900 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 86900 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 86900 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 86900 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894642 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1894642 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1894642 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1894642 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1894642 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1894642 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22157720096 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22157720096 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22157720096 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22157720096 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22157720096 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22157720096 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202542500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202542500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202542500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 202542500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028581 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.028581 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028581 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.028581 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11694.937669 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11694.937669 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11694.937669 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11694.937669 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency
1057,1061c1058,1062
< system.cpu.l2cache.tags.replacements 98637 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65077.786040 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3021048 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 163850 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 18.437888 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 98619 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks.
1063,1064c1064,1065
< system.cpu.l2cache.tags.occ_blocks::writebacks 49563.565409 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218345 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor
1066,1068c1067,1069
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.530935 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 5190.672892 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.756280 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy
1071,1072c1072,1073
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157326 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.079203 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.157327 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.079218 # Average percentage of cache occupancy
1079,1081c1080,1082
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7016 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55034 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2968 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id
1084,1092c1085,1093
< system.cpu.l2cache.tags.tag_accesses 28438268 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 28438268 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53837 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11652 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1874630 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 528067 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2468186 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 695424 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 695424 # number of Writeback hits
---
> system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits
1097,1108c1098,1109
< system.cpu.l2cache.ReadExReq_hits::cpu.data 159691 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 159691 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 53837 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 11652 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1874630 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 687758 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2627877 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 53837 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 11652 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1874630 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 687758 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2627877 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 11660 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1874571 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 687724 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2627795 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 53840 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 11660 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1874571 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 687724 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2627795 # number of overall hits
1111,1115c1112,1116
< system.cpu.l2cache.ReadReq_misses::cpu.inst 19979 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 13624 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 33629 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2734 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2734 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 19966 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 13620 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 33612 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2733 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2733 # number of UpgradeReq misses
1122,1124c1123,1125
< system.cpu.l2cache.demand_misses::cpu.inst 19979 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 150561 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 170566 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 19966 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 150557 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 170549 # number of demand (read+write) misses
1127,1130c1128,1131
< system.cpu.l2cache.overall_misses::cpu.inst 19979 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 150561 # number of overall misses
< system.cpu.l2cache.overall_misses::total 170566 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1661750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.inst 19966 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 150557 # number of overall misses
> system.cpu.l2cache.overall_misses::total 170549 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1458500 # number of ReadReq miss cycles
1132,1134c1133,1135
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1496766000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1081319750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2580283750 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1500107250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1078643000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2580745000 # number of ReadReq miss cycles
1139,1141c1140,1142
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9921795191 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9921795191 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1661750 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9922806190 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9922806190 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1458500 # number of demand (read+write) miss cycles
1143,1146c1144,1147
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1496766000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11003114941 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 12502078941 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1661750 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1500107250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11001449190 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 12503551190 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1458500 # number of overall miss cycles
1148,1159c1149,1160
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1496766000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11003114941 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 12502078941 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53856 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11659 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894609 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 541691 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2501815 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 695424 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 695424 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2768 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2768 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1500107250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11001449190 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 12503551190 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53859 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11667 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894537 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 541656 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2501719 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 695414 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 695414 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2767 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2767 # number of UpgradeReq accesses(hits+misses)
1162,1173c1163,1174
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 296628 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 296628 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53856 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 11659 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1894609 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 838319 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2798443 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53856 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 11659 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1894609 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 838319 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2798443 # number of overall (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 296625 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 296625 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53859 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 11667 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1894537 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 838281 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2798344 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53859 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 11667 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1894537 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 838281 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2798344 # number of overall (read+write) accesses
1176,1180c1177,1181
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010545 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025151 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.013442 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987717 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987717 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025145 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.013436 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987712 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987712 # miss rate for UpgradeReq accesses
1183,1184c1184,1185
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461646 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.461646 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461650 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.461650 # miss rate for ReadExReq accesses
1187,1189c1188,1190
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010545 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.179599 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.060950 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.179602 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.060946 # miss rate for demand accesses
1192,1195c1193,1196
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010545 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.179599 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.060950 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87460.526316 # average ReadReq miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.179602 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.060946 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 76763.157895 # average ReadReq miss latency
1197,1201c1198,1202
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74916.962811 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79368.742660 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 76727.935710 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.231529 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.231529 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75133.088751 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79195.521292 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 76780.465310 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 213.309550 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 213.309550 # average UpgradeReq miss latency
1204,1206c1205,1207
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72455.181514 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72455.181514 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72462.564464 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72462.564464 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency
1208,1211c1209,1212
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73297.602928 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87460.526316 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73313.541504 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 76763.157895 # average overall miss latency
1213,1215c1214,1216
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74916.962811 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73080.777499 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73297.602928 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75133.088751 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73071.655187 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73313.541504 # average overall miss latency
1224,1225c1225,1226
< system.cpu.l2cache.writebacks::writebacks 90641 # number of writebacks
< system.cpu.l2cache.writebacks::total 90641 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 90626 # number of writebacks
> system.cpu.l2cache.writebacks::total 90626 # number of writebacks
1237,1241c1238,1242
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19954 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13512 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 33492 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2734 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19941 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13508 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 33475 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2733 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2733 # number of UpgradeReq MSHR misses
1248,1250c1249,1251
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 19954 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 150449 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 170429 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 19941 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 150445 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 170412 # number of demand (read+write) MSHR misses
1253,1256c1254,1257
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 19954 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 150449 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 170429 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1426250 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 19941 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 150445 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 170412 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1223500 # number of ReadReq MSHR miss cycles
1258,1262c1259,1263
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1244689750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 905485750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152053000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27405734 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27405734 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1248209500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 902938000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2152822250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27396733 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27396733 # number of UpgradeReq MSHR miss cycles
1265,1267c1266,1268
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8208319809 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8208319809 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1426250 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8209305810 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8209305810 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1223500 # number of demand (read+write) MSHR miss cycles
1269,1272c1270,1273
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1244689750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9113805559 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 10360372809 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1426250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1248209500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9112243810 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 10362128060 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1223500 # number of overall MSHR miss cycles
1274,1284c1275,1285
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1244689750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9113805559 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 10360372809 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157860000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387400000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545260000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107351500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107351500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157860000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494751500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652611500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1248209500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9112243810 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 10362128060 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157877000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387481250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545358250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107341000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107341000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157877000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494822250 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652699250 # number of overall MSHR uncacheable cycles
1287,1291c1288,1292
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024944 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013387 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987717 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987717 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024938 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013381 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.987712 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.987712 # mshr miss rate for UpgradeReq accesses
1294,1295c1295,1296
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461646 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461646 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461650 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461650 # mshr miss rate for ReadExReq accesses
1298,1300c1299,1301
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.060901 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.060897 # mshr miss rate for demand accesses
1303,1306c1304,1307
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010532 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179465 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.060901 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010526 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179468 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.060897 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average ReadReq mshr miss latency
1308,1312c1309,1313
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62377.956801 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67013.451007 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64255.732712 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.043160 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.043160 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62595.130635 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66844.684631 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64311.344287 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10024.417490 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10024.417490 # average UpgradeReq mshr miss latency
1315,1317c1316,1318
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59942.307842 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59942.307842 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
1319,1322c1320,1323
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75065.789474 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
1324,1326c1325,1327
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62377.956801 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60577.375449 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60789.964202 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
1336,1342c1337,1343
< system.cpu.dcache.tags.replacements 837784 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.958472 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 40159350 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 838296 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 47.905931 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 244993250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.958472 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 837746 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
1350,1373c1351,1374
< system.cpu.dcache.tags.tag_accesses 179375223 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179375223 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 23322313 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 23322313 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 15585229 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 15585229 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 346650 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 346650 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 441994 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 441994 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460302 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460302 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 38907542 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 38907542 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 39254192 # number of overall hits
< system.cpu.dcache.overall_hits::total 39254192 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 700487 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 700487 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3573434 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3573434 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 177076 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 177076 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 26736 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 26736 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits
> system.cpu.dcache.overall_hits::total 39265074 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
1376,1385c1377,1386
< system.cpu.dcache.demand_misses::cpu.data 4273921 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 4273921 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 4450997 # number of overall misses
< system.cpu.dcache.overall_misses::total 4450997 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9902093641 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9902093641 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 135168862785 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 135168862785 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 356751499 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 356751499 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses
> system.cpu.dcache.overall_misses::total 4451402 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles
1388,1409c1389,1410
< system.cpu.dcache.demand_miss_latency::cpu.data 145070956426 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 145070956426 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 145070956426 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 145070956426 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24022800 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24022800 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 19158663 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 19158663 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 523726 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 523726 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468730 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 468730 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460307 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460307 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 43181463 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 43181463 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 43705189 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 43705189 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029159 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.029159 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186518 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.186518 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
1412,1413c1413,1414
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057039 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057039 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
1416,1425c1417,1426
< system.cpu.dcache.demand_miss_rate::cpu.data 0.098976 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.098976 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.101841 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.101841 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14136.013432 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14136.013432 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37826.041501 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37826.041501 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13343.488143 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13343.488143 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency
1428,1432c1429,1433
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 33943.293857 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 33943.293857 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.912650 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 32592.912650 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 507999 # number of cycles access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked
1434c1435
< system.cpu.dcache.blocked::no_mshrs 6927 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
1436c1437
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 73.336076 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked
1440,1445c1441,1446
< system.cpu.dcache.writebacks::writebacks 695424 # number of writebacks
< system.cpu.dcache.writebacks::total 695424 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286296 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 286296 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274169 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3274169 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks
> system.cpu.dcache.writebacks::total 695414 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits
1448,1455c1449,1456
< system.cpu.dcache.demand_mshr_hits::cpu.data 3560465 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3560465 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3560465 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3560465 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414191 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 414191 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299265 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 299265 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
1458,1459c1459,1460
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8325 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 8325 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
1462,1473c1463,1474
< system.cpu.dcache.demand_mshr_misses::cpu.data 713456 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 713456 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 832762 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 832762 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5344701667 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5344701667 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11882128205 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11882128205 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479845001 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479845001 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110272000 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110272000 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
1476,1493c1477,1494
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17226829872 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17226829872 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18706674873 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 18706674873 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792653500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792653500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440471453 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440471453 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233124953 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233124953 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017242 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227802 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227802 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017761 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017761 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
1496,1507c1497,1508
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016522 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.016522 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019054 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.019054 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12903.954135 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12903.954135 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39704.369722 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39704.369722 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.776851 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.776851 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13245.885886 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13245.885886 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
1510,1513c1511,1514
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.609361 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.609361 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22463.410762 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 22463.410762 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency
1522c1523
< system.iocache.tags.tagsinuse 0.999683 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use
1527c1528
< system.iocache.tags.occ_blocks::realview.ide 0.999683 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::realview.ide 0.999676 # Average occupied blocks per requestor
1533,1534c1534,1535
< system.iocache.tags.tag_accesses 328020 # Number of tag accesses
< system.iocache.tags.data_accesses 328020 # Number of data accesses
---
> system.iocache.tags.tag_accesses 327996 # Number of tag accesses
> system.iocache.tags.data_accesses 327996 # Number of data accesses
1539,1540d1539
< system.iocache.WriteInvalidateReq_misses::realview.ide 3 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 3 # number of WriteInvalidateReq misses
1545,1550c1544,1549
< system.iocache.ReadReq_miss_latency::realview.ide 26405377 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 26405377 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::realview.ide 26405377 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 26405377 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ide 26405377 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 26405377 # number of overall miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 26406377 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 26406377 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::realview.ide 26406377 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 26406377 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ide 26406377 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 26406377 # number of overall miss cycles
1553,1554c1552,1553
< system.iocache.WriteInvalidateReq_accesses::realview.ide 36227 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 36227 # number of WriteInvalidateReq accesses(hits+misses)
---
> system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
1561,1562d1559
< system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000083 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000083 # miss rate for WriteInvalidateReq accesses
1567,1572c1564,1569
< system.iocache.ReadReq_avg_miss_latency::realview.ide 120024.440909 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 120024.440909 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 120024.440909 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 120024.440909 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 120024.440909 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 120028.986364 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 120028.986364 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 120028.986364 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 120028.986364 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 120028.986364 # average overall miss latency
1587,1594c1584,1591
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 14964377 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 14964377 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2231467484 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2231467484 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 14964377 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 14964377 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 14964377 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 14964377 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 14965377 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 14965377 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2230292235 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2230292235 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 14965377 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 14965377 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 14965377 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 14965377 # number of overall MSHR miss cycles
1601,1602c1598,1599
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68019.895455 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 68019.895455 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68024.440909 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 68024.440909 # average ReadReq mshr miss latency
1605,1608c1602,1605
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 68019.895455 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 68019.895455 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency