3,5c3,5
< sim_seconds 2.542203 # Number of seconds simulated
< sim_ticks 2542202956000 # Number of ticks simulated
< final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.542157 # Number of seconds simulated
> sim_ticks 2542156879500 # Number of ticks simulated
> final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 47189 # Simulator instruction rate (inst/s)
< host_op_rate 56852 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1989066585 # Simulator tick rate (ticks/s)
< host_mem_usage 412724 # Number of bytes of host memory used
< host_seconds 1278.09 # Real time elapsed on the host
< sim_insts 60311945 # Number of instructions simulated
< sim_ops 72661478 # Number of ops (including micro ops) simulated
---
> host_inst_rate 53622 # Simulator instruction rate (inst/s)
> host_op_rate 64601 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2260157205 # Simulator tick rate (ticks/s)
> host_mem_usage 463148 # Number of bytes of host memory used
> host_seconds 1124.77 # Real time elapsed on the host
> sim_insts 60311972 # Number of instructions simulated
> sim_ops 72661518 # Number of ops (including micro ops) simulated
19,23c19,23
< system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory
< system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory
> system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory
30,32c30,32
< system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory
36c36
< system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s)
39,48c39,48
< system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s)
51,54c51,54
< system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15295607 # Number of read requests accepted
---
> system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15295608 # Number of read requests accepted
56c56
< system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue
58,61c58,61
< system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side
---
> system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side
63,64c63,64
< system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one
66c66
< system.physmem.perBankRdBursts::0 955786 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 955787 # Per bank write bursts
68,74c68,74
< system.physmem.perBankRdBursts::2 953003 # Per bank write bursts
< system.physmem.perBankRdBursts::3 951059 # Per bank write bursts
< system.physmem.perBankRdBursts::4 958601 # Per bank write bursts
< system.physmem.perBankRdBursts::5 955602 # Per bank write bursts
< system.physmem.perBankRdBursts::6 952653 # Per bank write bursts
< system.physmem.perBankRdBursts::7 950407 # Per bank write bursts
< system.physmem.perBankRdBursts::8 956154 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 953511 # Per bank write bursts
> system.physmem.perBankRdBursts::3 951566 # Per bank write bursts
> system.physmem.perBankRdBursts::4 958612 # Per bank write bursts
> system.physmem.perBankRdBursts::5 955530 # Per bank write bursts
> system.physmem.perBankRdBursts::6 953056 # Per bank write bursts
> system.physmem.perBankRdBursts::7 951020 # Per bank write bursts
> system.physmem.perBankRdBursts::8 956158 # Per bank write bursts
76,77c76,77
< system.physmem.perBankRdBursts::10 952889 # Per bank write bursts
< system.physmem.perBankRdBursts::11 950148 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 952686 # Per bank write bursts
> system.physmem.perBankRdBursts::11 950200 # Per bank write bursts
80,97c80,97
< system.physmem.perBankRdBursts::14 953918 # Per bank write bursts
< system.physmem.perBankRdBursts::15 950940 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6546 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6352 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6488 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6518 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6421 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6701 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6665 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6611 # Per bank write bursts
< system.physmem.perBankWrBursts::8 6966 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6759 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6421 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6055 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7037 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6645 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6920 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6806 # Per bank write bursts
---
> system.physmem.perBankRdBursts::14 953812 # Per bank write bursts
> system.physmem.perBankRdBursts::15 951254 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6556 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6344 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6481 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6512 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6422 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6709 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6691 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6631 # Per bank write bursts
> system.physmem.perBankWrBursts::8 6968 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6764 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6424 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6068 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7033 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6638 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6915 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6799 # Per bank write bursts
100c100
< system.physmem.totGap 2542201638000 # Total gap between requests
---
> system.physmem.totGap 2542155562500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 153412 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 153413 # Read request sizes (log2)
115,134c115,134
< system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
162,183c162,183
< system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
211,228c211,228
< system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes
232,251c232,254
< system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads
< system.physmem.totQLat 395449280750 # Total ticks spent queuing
< system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads
> system.physmem.totQLat 395458190750 # Total ticks spent queuing
> system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst
253,254c256,257
< system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s
262,265c265,268
< system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing
< system.physmem.readRowHits 14269193 # Number of row buffer hits during reads
< system.physmem.writeRowHits 90708 # Number of row buffer hits during writes
---
> system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
> system.physmem.readRowHits 14271218 # Number of row buffer hits during reads
> system.physmem.writeRowHits 90719 # Number of row buffer hits during writes
267,271c270,274
< system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes
< system.physmem.avgGap 157821.19 # Average gap between requests
< system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states
< system.physmem.memoryStateTime::REF 84889480000 # Time in different power states
---
> system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes
> system.physmem.avgGap 157818.32 # Average gap between requests
> system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states
> system.physmem.memoryStateTime::REF 84888180000 # Time in different power states
273c276
< system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states
287,289c290,291
< system.membus.throughput 55125441 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 16348039 # Transaction distribution
< system.membus.trans_dist::ReadResp 16348039 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 16348037 # Transaction distribution
> system.membus.trans_dist::ReadResp 16348037 # Transaction distribution
295,296c297,298
< system.membus.trans_dist::ReadExReq 131651 # Transaction distribution
< system.membus.trans_dist::ReadExResp 131651 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 131654 # Transaction distribution
> system.membus.trans_dist::ReadExResp 131654 # Transaction distribution
301,302c303,304
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes)
305,317c307,329
< system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 140140058 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks)
---
> system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 216513 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 216513 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks)
321c333
< system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks)
325c337
< system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks)
327c339
< system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks)
329c341
< system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks)
337d348
< system.iobus.throughput 48580309 # Throughput (bytes/s)
369,396c380,406
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 123501006 # Total data (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes)
443,444c453,454
< system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
< system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
---
> system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks)
> system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
447c457
< system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks)
450,454c460,464
< system.cpu.branchPred.lookups 13201290 # Number of BP lookups
< system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits
---
> system.cpu.branchPred.lookups 13200672 # Number of BP lookups
> system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits
456,458c466,468
< system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions.
482,485c492,495
< system.cpu.dtb.read_hits 31642294 # DTB read hits
< system.cpu.dtb.read_misses 39524 # DTB read misses
< system.cpu.dtb.write_hits 11381361 # DTB write hits
< system.cpu.dtb.write_misses 10135 # DTB write misses
---
> system.cpu.dtb.read_hits 31644036 # DTB read hits
> system.cpu.dtb.read_misses 39518 # DTB read misses
> system.cpu.dtb.write_hits 11381434 # DTB write hits
> system.cpu.dtb.write_misses 10146 # DTB write misses
490,491c500,501
< system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions
---
> system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
495,496c505,506
< system.cpu.dtb.read_accesses 31681818 # DTB read accesses
< system.cpu.dtb.write_accesses 11391496 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31683554 # DTB read accesses
> system.cpu.dtb.write_accesses 11391580 # DTB write accesses
498,500c508,510
< system.cpu.dtb.hits 43023655 # DTB hits
< system.cpu.dtb.misses 49659 # DTB misses
< system.cpu.dtb.accesses 43073314 # DTB accesses
---
> system.cpu.dtb.hits 43025470 # DTB hits
> system.cpu.dtb.misses 49664 # DTB misses
> system.cpu.dtb.accesses 43075134 # DTB accesses
522,523c532,533
< system.cpu.itb.inst_hits 24159481 # ITB inst hits
< system.cpu.itb.inst_misses 10516 # ITB inst misses
---
> system.cpu.itb.inst_hits 24158829 # ITB inst hits
> system.cpu.itb.inst_misses 10513 # ITB inst misses
532c542
< system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB
536c546
< system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions
---
> system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions
539,543c549,553
< system.cpu.itb.inst_accesses 24169997 # ITB inst accesses
< system.cpu.itb.hits 24159481 # DTB hits
< system.cpu.itb.misses 10516 # DTB misses
< system.cpu.itb.accesses 24169997 # DTB accesses
< system.cpu.numCycles 499350041 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 24169342 # ITB inst accesses
> system.cpu.itb.hits 24158829 # DTB hits
> system.cpu.itb.misses 10513 # DTB misses
> system.cpu.itb.accesses 24169342 # DTB accesses
> system.cpu.numCycles 499362415 # number of cpu cycles simulated
546,562c556,572
< system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total)
564,567c574,577
< system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total)
571,597c581,607
< system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups
599,615c609,625
< system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle
---
> system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle
617c627
< system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle
619,623c629,633
< system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle
631c641
< system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle
633,663c643,673
< system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available
667,668c677,678
< system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued
692,697c702,707
< system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued
700,706c710,716
< system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued
< system.cpu.iq.rate 0.188050 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued
> system.cpu.iq.rate 0.188049 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses
710c720
< system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses
712c722
< system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores
714,717c724,727
< system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed
720,721c730,731
< system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked
723,726c733,736
< system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ
728,739c738,749
< system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute
741,749c751,759
< system.cpu.iew.exec_nop 176010 # number of nop insts executed
< system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed
< system.cpu.iew.exec_branches 10791342 # Number of branches executed
< system.cpu.iew.exec_stores 11888889 # Number of stores executed
< system.cpu.iew.exec_rate 0.186738 # Inst execution rate
< system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 35465784 # num instructions producing a value
< system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 176011 # number of nop insts executed
> system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed
> system.cpu.iew.exec_branches 10791373 # Number of branches executed
> system.cpu.iew.exec_stores 11888962 # Number of stores executed
> system.cpu.iew.exec_rate 0.186737 # Inst execution rate
> system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 35461894 # num instructions producing a value
> system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value
751,752c761,762
< system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back
754c764
< system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit
756,759c766,769
< system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle
761,769c771,779
< system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle
773,775c783,785
< system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 60462326 # Number of instructions committed
< system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 60462353 # Number of instructions committed
> system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed
777,778c787,788
< system.cpu.commit.refs 25244569 # Number of memory references committed
< system.cpu.commit.loads 13512926 # Number of loads committed
---
> system.cpu.commit.refs 25244590 # Number of memory references committed
> system.cpu.commit.loads 13512938 # Number of loads committed
780c790
< system.cpu.commit.branches 10308073 # Number of branches committed
---
> system.cpu.commit.branches 10308077 # Number of branches committed
782c792
< system.cpu.commit.int_insts 64250122 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 64250158 # Number of committed integer instructions.
785,786c795,796
< system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction
< system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction
---
> system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction
814,815c824,825
< system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction
< system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction
---
> system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction
818,819c828,829
< system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction
< system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached
---
> system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction
> system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached
821,833c831,843
< system.cpu.rob.rob_reads 568287463 # The number of ROB reads
< system.cpu.rob.rob_writes 154414560 # The number of ROB writes
< system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 60311945 # Number of Instructions Simulated
< system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated
< system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 109116898 # number of integer regfile reads
< system.cpu.int_regfile_writes 47012340 # number of integer regfile writes
---
> system.cpu.rob.rob_reads 568215140 # The number of ROB reads
> system.cpu.rob.rob_writes 154414029 # The number of ROB writes
> system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 60311972 # Number of Instructions Simulated
> system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated
> system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 109116744 # number of integer regfile reads
> system.cpu.int_regfile_writes 47012206 # number of integer regfile writes
836,842c846,851
< system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads
< system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes
< system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes
< system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution
---
> system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads
> system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes
> system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes
> system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution
845c854
< system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution
849,863c858,886
< system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 26770 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks)
865c888
< system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks)
867c890
< system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks)
869c892
< system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks)
871c894
< system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks)
873,879c896,902
< system.cpu.icache.tags.replacements 959881 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.replacements 959838 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor
888,913c911,936
< system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits
< system.cpu.icache.overall_hits::total 23149457 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses
< system.cpu.icache.overall_misses::total 1005369 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits
> system.cpu.icache.overall_hits::total 23148830 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses
> system.cpu.icache.overall_misses::total 1005344 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 13667748229 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 13667748229 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 24154174 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 24154174 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 24154174 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 24154174 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 24154174 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 24154174 # number of overall (read+write) accesses
920,926c943,949
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked
928c951
< system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked
930c953
< system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked
934,967c957,990
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency
973,980c996,1003
< system.cpu.l2cache.tags.replacements 63302 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.replacements 63303 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 37301.769799 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.815946 # Average occupied blocks per requestor
982,984c1005,1007
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 7723.154288 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.165612 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.569193 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 7722.177507 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6096.159639 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.569180 # Average percentage of cache occupancy
987c1010
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117846 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.117831 # Average percentage of cache occupancy
989c1012
< system.cpu.l2cache.tags.occ_percent::total 0.780163 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.780135 # Average percentage of cache occupancy
994,997c1017,1020
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3024 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6221 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55835 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3025 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6220 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55834 # Occupied blocks per task id
1000,1008c1023,1031
< system.cpu.l2cache.tags.tag_accesses 18316308 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18316308 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33888 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9476 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 947771 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 377103 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1368238 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 599976 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 599976 # number of Writeback hits
---
> system.cpu.l2cache.tags.tag_accesses 18315394 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18315394 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 33880 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 9473 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 947730 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 377075 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1368158 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 599947 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 599947 # number of Writeback hits
1013,1024c1036,1047
< system.cpu.l2cache.ReadExReq_hits::cpu.data 113216 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 113216 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 33888 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 9476 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 947771 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 490319 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1481454 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 33888 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 9476 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 947771 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 490319 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1481454 # number of overall hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 113210 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 113210 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 33880 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 9473 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 947730 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 490285 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1481368 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 33880 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 9473 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 947730 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 490285 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1481368 # number of overall hits
1027c1050
< system.cpu.l2cache.ReadReq_misses::cpu.inst 11654 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 11652 # number of ReadReq misses
1029c1052
< system.cpu.l2cache.ReadReq_misses::total 21816 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 21814 # number of ReadReq misses
1032,1033c1055,1056
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133354 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133354 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133357 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133357 # number of ReadExReq misses
1036,1038c1059,1061
< system.cpu.l2cache.demand_misses::cpu.inst 11654 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143502 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 155170 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 11652 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143505 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 155171 # number of demand (read+write) misses
1041,1069c1064,1092
< system.cpu.l2cache.overall_misses::cpu.inst 11654 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143502 # number of overall misses
< system.cpu.l2cache.overall_misses::total 155170 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 830265249 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 761175750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1592469999 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 348485 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 348485 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9338459797 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9338459797 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 830265249 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10099635547 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10930929796 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 830265249 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10099635547 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10930929796 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33899 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9479 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 959425 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 387251 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1390054 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 599976 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 599976 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.inst 11652 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143505 # number of overall misses
> system.cpu.l2cache.overall_misses::total 155171 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 790750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 238250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 835556749 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 759914000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1596499749 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 349485 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 349485 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9345897297 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9345897297 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 790750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 238250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 835556749 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10105811297 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10942397046 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 790750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 238250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 835556749 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10105811297 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10942397046 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 33891 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 9476 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 959382 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 387223 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1389972 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 599947 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 599947 # number of Writeback accesses(hits+misses)
1074,1089c1097,1112
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 246570 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 246570 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33899 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 9479 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 959425 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 633821 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1636624 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33899 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 9479 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 959425 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 633821 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1636624 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000316 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012147 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026205 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 246567 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 246567 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 33891 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 9476 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 959382 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 633790 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1636539 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 33891 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 9476 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 959382 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 633790 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1636539 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000325 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000317 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012145 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
1093,1123c1116,1146
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.540836 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000316 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012147 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.226408 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.094811 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000316 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012147 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.226408 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.094811 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71840.909091 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79583.333333 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71242.942252 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75007.464525 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72995.507838 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 119.795462 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 119.795462 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70027.594200 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70027.594200 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70444.865605 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71840.909091 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79583.333333 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71242.942252 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70379.754617 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70444.865605 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540855 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.540855 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000325 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000317 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012145 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.226424 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.094817 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000325 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000317 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012145 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.226424 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.094817 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 71886.363636 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79416.666667 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71709.298747 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74883.129681 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73186.932658 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 120.139223 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 120.139223 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70081.790210 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70081.790210 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70518.312352 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 71886.363636 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79416.666667 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71709.298747 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70421.318400 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70518.312352 # average overall miss latency
1148c1171
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11640 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 11638 # number of ReadReq MSHR misses
1150c1173
< system.cpu.l2cache.ReadReq_mshr_misses::total 21761 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::total 21759 # number of ReadReq MSHR misses
1153,1154c1176,1177
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133354 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133354 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133357 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133357 # number of ReadExReq MSHR misses
1157,1159c1180,1182
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 11640 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143462 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 155115 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 11638 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143465 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 155116 # number of demand (read+write) MSHR misses
1162,1164c1185,1187
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 11640 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143462 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 155115 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 11638 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143465 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 155116 # number of overall MSHR misses
1167,1173c1190,1196
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683475499 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 632292750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1316565749 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29106909 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29106909 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7676486703 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7676486703 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 688774749 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 631278500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1320850749 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29121909 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29121909 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7684221703 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7684221703 # number of ReadExReq MSHR miss cycles
1176,1178c1199,1201
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683475499 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8308779453 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 8993052452 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 688774749 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8315500203 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9005072452 # number of demand (read+write) MSHR miss cycles
1181,1191c1204,1214
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683475499 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8308779453 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 8993052452 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174348000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167014389750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167188737750 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17147727018 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17147727018 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174348000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184162116768 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184336464768 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 688774749 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8315500203 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9005072452 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 174356000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167012344750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles
1193,1196c1216,1219
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses
1199,1200c1222,1223
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540836 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540855 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540855 # mshr miss rate for ReadExReq accesses
1202,1205c1225,1228
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.094777 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses
1207,1210c1230,1233
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses
1213,1219c1236,1242
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57564.727740 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59183.257347 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62453.353779 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60703.651317 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency
1222,1224c1245,1247
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency
1227,1229c1250,1252
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency
1239,1243c1262,1266
< system.cpu.dcache.tags.replacements 633309 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.949942 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 19068560 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 633821 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 30.085087 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 633278 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.949941 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 19068568 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks.
1245c1268
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor
1249,1250c1272,1273
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
1253,1262c1276,1285
< system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits
1265,1276c1288,1299
< system.cpu.dcache.demand_hits::cpu.data 18520698 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 18520698 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 18581521 # number of overall hits
< system.cpu.dcache.overall_hits::total 18581521 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 573261 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 573261 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3012484 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3012484 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 126501 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 126501 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 12988 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 12988 # number of LoadLockedReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 18520726 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 18520726 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 18581554 # number of overall hits
> system.cpu.dcache.overall_hits::total 18581554 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 573243 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 573243 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3012489 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3012489 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 126499 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 126499 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 12987 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 12987 # number of LoadLockedReq misses
1279,1288c1302,1311
< system.cpu.dcache.demand_misses::cpu.data 3585745 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3585745 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3712246 # number of overall misses
< system.cpu.dcache.overall_misses::total 3712246 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7216358166 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7216358166 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 126016512064 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 126016512064 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 178185500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 178185500 # number of LoadLockedReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 3585732 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3585732 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3712231 # number of overall misses
> system.cpu.dcache.overall_misses::total 3712231 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7223298916 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7223298916 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 126143348315 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 126143348315 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 177246500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 177246500 # number of LoadLockedReq miss cycles
1291,1302c1314,1325
< system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 187324 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 187324 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249432 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 249432 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 133366647231 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 133366647231 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 133366647231 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 133366647231 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 11884506 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 11884506 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10221952 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10221952 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 187327 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 187327 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 249406 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 249406 # number of LoadLockedReq accesses(hits+misses)
1305,1310c1328,1333
< system.cpu.dcache.demand_accesses::cpu.data 22106443 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 22106443 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses
1313,1316c1336,1339
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses
1319,1328c1342,1351
< system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency
1331,1340c1354,1363
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 459 # average number of cycles each access was blocked
1343,1348c1366,1371
< system.cpu.dcache.writebacks::writebacks 599976 # number of writebacks
< system.cpu.dcache.writebacks::total 599976 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271755 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 271755 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763119 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2763119 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 599947 # number of writebacks
> system.cpu.dcache.writebacks::total 599947 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 271762 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 271762 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits
1351,1362c1374,1385
< system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 249365 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74145 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 74145 # number of SoftPFReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11755 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 11755 # number of LoadLockedReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 3034890 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3034890 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3034890 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3034890 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301481 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 301481 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249361 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 249361 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 74144 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 74144 # number of SoftPFReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11754 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 11754 # number of LoadLockedReq MSHR misses
1365,1376c1388,1399
< system.cpu.dcache.demand_mshr_misses::cpu.data 550871 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 550871 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 625016 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 625016 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569781578 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569781578 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10783879319 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10783879319 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1231283000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1231283000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140188500 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140188500 # number of LoadLockedReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 550842 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles
1379,1390c1402,1413
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses
1393,1396c1416,1419
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses
1399,1410c1422,1433
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency
1413,1416c1436,1439
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency
1440,1443c1463,1466
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles
1450c1473
< system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed