3,5c3,5
< sim_seconds 2.526170 # Number of seconds simulated
< sim_ticks 2526169857500 # Number of ticks simulated
< final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.526192 # Number of seconds simulated
> sim_ticks 2526192217500 # Number of ticks simulated
> final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 58326 # Simulator instruction rate (inst/s)
< host_op_rate 75048 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2443063970 # Simulator tick rate (ticks/s)
< host_mem_usage 467448 # Number of bytes of host memory used
< host_seconds 1034.02 # Real time elapsed on the host
< sim_insts 60309637 # Number of instructions simulated
< sim_ops 77601213 # Number of ops (including micro ops) simulated
---
> host_inst_rate 56578 # Simulator instruction rate (inst/s)
> host_op_rate 72800 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2369913329 # Simulator tick rate (ticks/s)
> host_mem_usage 467016 # Number of bytes of host memory used
> host_seconds 1065.94 # Real time elapsed on the host
> sim_insts 60309034 # Number of instructions simulated
> sim_ops 77600502 # Number of ops (including micro ops) simulated
17c17
< system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
19,24c19,24
< system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory
< system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory
> system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory
28c28
< system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
30,33c30,33
< system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory
35,37c35,37
< system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
< system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory
> system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s)
39,49c39,49
< system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s)
51,97c51,97
< system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 15096868 # Number of read requests accepted
< system.physmem.writeReqs 813159 # Number of write requests accepted
< system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue
< system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 943297 # Per bank write bursts
< system.physmem.perBankRdBursts::1 937033 # Per bank write bursts
< system.physmem.perBankRdBursts::2 936962 # Per bank write bursts
< system.physmem.perBankRdBursts::3 936535 # Per bank write bursts
< system.physmem.perBankRdBursts::4 942693 # Per bank write bursts
< system.physmem.perBankRdBursts::5 936569 # Per bank write bursts
< system.physmem.perBankRdBursts::6 936319 # Per bank write bursts
< system.physmem.perBankRdBursts::7 936043 # Per bank write bursts
< system.physmem.perBankRdBursts::8 943596 # Per bank write bursts
< system.physmem.perBankRdBursts::9 936992 # Per bank write bursts
< system.physmem.perBankRdBursts::10 936414 # Per bank write bursts
< system.physmem.perBankRdBursts::11 935912 # Per bank write bursts
< system.physmem.perBankRdBursts::12 943556 # Per bank write bursts
< system.physmem.perBankRdBursts::13 937007 # Per bank write bursts
< system.physmem.perBankRdBursts::14 937039 # Per bank write bursts
< system.physmem.perBankRdBursts::15 936676 # Per bank write bursts
< system.physmem.perBankWrBursts::0 6606 # Per bank write bursts
< system.physmem.perBankWrBursts::1 6375 # Per bank write bursts
< system.physmem.perBankWrBursts::2 6521 # Per bank write bursts
< system.physmem.perBankWrBursts::3 6552 # Per bank write bursts
< system.physmem.perBankWrBursts::4 6461 # Per bank write bursts
< system.physmem.perBankWrBursts::5 6711 # Per bank write bursts
< system.physmem.perBankWrBursts::6 6720 # Per bank write bursts
< system.physmem.perBankWrBursts::7 6668 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7045 # Per bank write bursts
< system.physmem.perBankWrBursts::9 6826 # Per bank write bursts
< system.physmem.perBankWrBursts::10 6497 # Per bank write bursts
< system.physmem.perBankWrBursts::11 6136 # Per bank write bursts
< system.physmem.perBankWrBursts::12 7072 # Per bank write bursts
< system.physmem.perBankWrBursts::13 6672 # Per bank write bursts
< system.physmem.perBankWrBursts::14 6956 # Per bank write bursts
< system.physmem.perBankWrBursts::15 6819 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 15096864 # Number of read requests accepted
> system.physmem.writeReqs 813148 # Number of write requests accepted
> system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue
> system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 943480 # Per bank write bursts
> system.physmem.perBankRdBursts::1 937980 # Per bank write bursts
> system.physmem.perBankRdBursts::2 937559 # Per bank write bursts
> system.physmem.perBankRdBursts::3 937528 # Per bank write bursts
> system.physmem.perBankRdBursts::4 943087 # Per bank write bursts
> system.physmem.perBankRdBursts::5 937982 # Per bank write bursts
> system.physmem.perBankRdBursts::6 937070 # Per bank write bursts
> system.physmem.perBankRdBursts::7 936990 # Per bank write bursts
> system.physmem.perBankRdBursts::8 943982 # Per bank write bursts
> system.physmem.perBankRdBursts::9 938303 # Per bank write bursts
> system.physmem.perBankRdBursts::10 937119 # Per bank write bursts
> system.physmem.perBankRdBursts::11 936407 # Per bank write bursts
> system.physmem.perBankRdBursts::12 943924 # Per bank write bursts
> system.physmem.perBankRdBursts::13 938214 # Per bank write bursts
> system.physmem.perBankRdBursts::14 937241 # Per bank write bursts
> system.physmem.perBankRdBursts::15 937211 # Per bank write bursts
> system.physmem.perBankWrBursts::0 6601 # Per bank write bursts
> system.physmem.perBankWrBursts::1 6388 # Per bank write bursts
> system.physmem.perBankWrBursts::2 6528 # Per bank write bursts
> system.physmem.perBankWrBursts::3 6554 # Per bank write bursts
> system.physmem.perBankWrBursts::4 6464 # Per bank write bursts
> system.physmem.perBankWrBursts::5 6726 # Per bank write bursts
> system.physmem.perBankWrBursts::6 6713 # Per bank write bursts
> system.physmem.perBankWrBursts::7 6652 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7031 # Per bank write bursts
> system.physmem.perBankWrBursts::9 6803 # Per bank write bursts
> system.physmem.perBankWrBursts::10 6461 # Per bank write bursts
> system.physmem.perBankWrBursts::11 6104 # Per bank write bursts
> system.physmem.perBankWrBursts::12 7064 # Per bank write bursts
> system.physmem.perBankWrBursts::13 6684 # Per bank write bursts
> system.physmem.perBankWrBursts::14 6965 # Per bank write bursts
> system.physmem.perBankWrBursts::15 6836 # Per bank write bursts
100c100
< system.physmem.totGap 2526168741500 # Total gap between requests
---
> system.physmem.totGap 2526191083500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 154622 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 154618 # Read request sizes (log2)
114,134c114,134
< system.physmem.writePktSize::6 59141 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 59130 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
162,202c162,202
< system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
211,229c211,229
< system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
232,268c232,251
< system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads
< system.physmem.totQLat 571195583500 # Total ticks spent queuing
< system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks
< system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads
> system.physmem.totQLat 389908010000 # Total ticks spent queuing
> system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst
270,271c253,254
< system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s
279,287c262,274
< system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing
< system.physmem.readRowHits 14041195 # Number of row buffer hits during reads
< system.physmem.writeRowHits 91389 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes
< system.physmem.avgGap 158778.41 # Average gap between requests
< system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state
---
> system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing
> system.physmem.readRowHits 14044000 # Number of row buffer hits during reads
> system.physmem.writeRowHits 91096 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes
> system.physmem.avgGap 158779.96 # Average gap between requests
> system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states
> system.physmem.memoryStateTime::REF 84354920000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
300,302c287,289
< system.membus.throughput 54878638 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 16149508 # Transaction distribution
< system.membus.trans_dist::ReadResp 16149508 # Transaction distribution
---
> system.membus.throughput 54877773 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 16149486 # Transaction distribution
> system.membus.trans_dist::ReadResp 16149486 # Transaction distribution
305,306c292,293
< system.membus.trans_dist::Writeback 59141 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution
---
> system.membus.trans_dist::Writeback 59130 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution
308,310c295,297
< system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution
< system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
< system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution
> system.membus.trans_dist::ReadExReq 131451 # Transaction distribution
> system.membus.trans_dist::ReadExResp 131451 # Transaction distribution
315,316c302,303
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes)
319c306
< system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes)
324,325c311,312
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes)
328,329c315,316
< system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 138632762 # Total data (bytes)
---
> system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 138631802 # Total data (bytes)
331c318
< system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks)
335c322
< system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks)
339c326
< system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks)
---
> system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks)
341c328
< system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks)
343c330
< system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks)
351c338
< system.iobus.throughput 48266001 # Throughput (bytes/s)
---
> system.iobus.throughput 48265574 # Throughput (bytes/s)
461c448
< system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks)
464,468c451,455
< system.cpu.branchPred.lookups 14755327 # Number of BP lookups
< system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits
---
> system.cpu.branchPred.lookups 14753661 # Number of BP lookups
> system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits
470,472c457,459
< system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions.
496,499c483,486
< system.cpu.dtb.read_hits 51187284 # DTB read hits
< system.cpu.dtb.read_misses 65383 # DTB read misses
< system.cpu.dtb.write_hits 11703682 # DTB write hits
< system.cpu.dtb.write_misses 15916 # DTB write misses
---
> system.cpu.dtb.read_hits 51183231 # DTB read hits
> system.cpu.dtb.read_misses 65223 # DTB read misses
> system.cpu.dtb.write_hits 11700953 # DTB write hits
> system.cpu.dtb.write_misses 15725 # DTB write misses
504,505c491,492
< system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
< system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions
---
> system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB
> system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions
508,510c495,497
< system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
< system.cpu.dtb.read_accesses 51252667 # DTB read accesses
< system.cpu.dtb.write_accesses 11719598 # DTB write accesses
---
> system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions
> system.cpu.dtb.read_accesses 51248454 # DTB read accesses
> system.cpu.dtb.write_accesses 11716678 # DTB write accesses
512,514c499,501
< system.cpu.dtb.hits 62890966 # DTB hits
< system.cpu.dtb.misses 81299 # DTB misses
< system.cpu.dtb.accesses 62972265 # DTB accesses
---
> system.cpu.dtb.hits 62884184 # DTB hits
> system.cpu.dtb.misses 80948 # DTB misses
> system.cpu.dtb.accesses 62965132 # DTB accesses
536,537c523,524
< system.cpu.itb.inst_hits 11527099 # ITB inst hits
< system.cpu.itb.inst_misses 11249 # ITB inst misses
---
> system.cpu.itb.inst_hits 11525561 # ITB inst hits
> system.cpu.itb.inst_misses 11159 # ITB inst misses
546c533
< system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB
---
> system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB
553,557c540,544
< system.cpu.itb.inst_accesses 11538348 # ITB inst accesses
< system.cpu.itb.hits 11527099 # DTB hits
< system.cpu.itb.misses 11249 # DTB misses
< system.cpu.itb.accesses 11538348 # DTB accesses
< system.cpu.numCycles 477119451 # number of cpu cycles simulated
---
> system.cpu.itb.inst_accesses 11536720 # ITB inst accesses
> system.cpu.itb.hits 11525561 # DTB hits
> system.cpu.itb.misses 11159 # DTB misses
> system.cpu.itb.accesses 11536720 # DTB accesses
> system.cpu.numCycles 477128882 # number of cpu cycles simulated
560,577c547,564
< system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing
< system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb
< system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps
< system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions
< system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed
< system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps
> system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions
> system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total)
579,587c566,574
< system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total)
591,636c578,623
< system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle
638,646c625,633
< system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle
650c637
< system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle
652c639
< system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available
681,682c668,669
< system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available
686,687c673,674
< system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued
700c687
< system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued
704c691
< system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued
713c700
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued
715,716c702,703
< system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued
719,731c706,718
< system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued
< system.cpu.iq.rate 0.257655 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued
> system.cpu.iq.rate 0.257622 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores
733,736c720,723
< system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed
739,740c726,727
< system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked
742,758c729,745
< system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute
760,768c747,755
< system.cpu.iew.exec_nop 221278 # number of nop insts executed
< system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed
< system.cpu.iew.exec_branches 11821235 # Number of branches executed
< system.cpu.iew.exec_stores 12215513 # Number of stores executed
< system.cpu.iew.exec_rate 0.253301 # Inst execution rate
< system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 47029089 # num instructions producing a value
< system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 222849 # number of nop insts executed
> system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed
> system.cpu.iew.exec_branches 11822089 # Number of branches executed
> system.cpu.iew.exec_stores 12212847 # Number of stores executed
> system.cpu.iew.exec_rate 0.253272 # Inst execution rate
> system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 47017508 # num instructions producing a value
> system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value
770,771c757,758
< system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back
773,778c760,765
< system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle
---
> system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle
780,788c767,775
< system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle
792,794c779,781
< system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 60460018 # Number of instructions committed
< system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 60459415 # Number of instructions committed
> system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed
796,799c783,786
< system.cpu.commit.refs 27386851 # Number of memory references committed
< system.cpu.commit.loads 15654790 # Number of loads committed
< system.cpu.commit.membars 403577 # Number of memory barriers committed
< system.cpu.commit.branches 10306380 # Number of branches committed
---
> system.cpu.commit.refs 27386618 # Number of memory references committed
> system.cpu.commit.loads 15654647 # Number of loads committed
> system.cpu.commit.membars 403571 # Number of memory barriers committed
> system.cpu.commit.branches 10306311 # Number of branches committed
801,803c788,825
< system.cpu.commit.int_insts 69191623 # Number of committed integer instructions.
< system.cpu.commit.function_calls 991253 # Number of function calls committed.
< system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached
---
> system.cpu.commit.int_insts 69190973 # Number of committed integer instructions.
> system.cpu.commit.function_calls 991245 # Number of function calls committed.
> system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction
> system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached
805,825c827,847
< system.cpu.rob.rob_reads 242979782 # The number of ROB reads
< system.cpu.rob.rob_writes 196005989 # The number of ROB writes
< system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu.committedInsts 60309637 # Number of Instructions Simulated
< system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated
< system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 548697999 # number of integer regfile reads
< system.cpu.int_regfile_writes 87552825 # number of integer regfile writes
< system.cpu.fp_regfile_reads 8408 # number of floating regfile reads
< system.cpu.fp_regfile_writes 2932 # number of floating regfile writes
< system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads
< system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes
< system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution
---
> system.cpu.rob.rob_reads 243007370 # The number of ROB reads
> system.cpu.rob.rob_writes 195993770 # The number of ROB writes
> system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu.committedInsts 60309034 # Number of Instructions Simulated
> system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated
> system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 548643015 # number of integer regfile reads
> system.cpu.int_regfile_writes 87545924 # number of integer regfile writes
> system.cpu.fp_regfile_reads 8332 # number of floating regfile reads
> system.cpu.fp_regfile_writes 2902 # number of floating regfile writes
> system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads
> system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes
> system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution
828,846c850,868
< system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks)
848c870
< system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks)
850c872
< system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks)
852c874
< system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks)
854c876
< system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks)
856,864c878,886
< system.cpu.icache.tags.replacements 980897 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 981488 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy
866,868c888,890
< system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id
871,909c893,931
< system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits
< system.cpu.icache.overall_hits::total 10462766 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses
< system.cpu.icache.overall_misses::total 1060743 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits
> system.cpu.icache.overall_hits::total 10460581 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses
> system.cpu.icache.overall_misses::total 1061360 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked
911c933
< system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked
913c935
< system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked
917,950c939,972
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency
956,968c978,990
< system.cpu.l2cache.tags.replacements 64391 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 51374.630920 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 1887139 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 129786 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 14.540390 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 2490832751500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 36918.668159 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 31.305745 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000374 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 8179.061871 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 6245.594773 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.563334 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000478 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 64387 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy
970,1008c992,1031
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124803 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.095300 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.783915 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65372 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3052 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6933 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54996 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997498 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 18788998 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 18788998 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53598 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10246 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 967912 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 386978 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 1418734 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 607635 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 607635 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 46 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 46 # number of UpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits
< system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 112878 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 112878 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 53598 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 10246 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 967912 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 499856 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 1531612 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 53598 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 10246 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 967912 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 499856 # number of overall hits
< system.cpu.l2cache.overall_hits::total 1531612 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 45 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
> system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits
> system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses
1010,1014c1033,1037
< system.cpu.l2cache.ReadReq_misses::cpu.inst 12357 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 10744 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 23148 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2913 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2913 # number of UpgradeReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses
1017,1019c1040,1042
< system.cpu.l2cache.ReadExReq_misses::cpu.data 133191 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 133191 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 45 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses
1021,1024c1044,1047
< system.cpu.l2cache.demand_misses::cpu.inst 12357 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 143935 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 156339 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 45 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses
1026,1110c1049,1133
< system.cpu.l2cache.overall_misses::cpu.inst 12357 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 143935 # number of overall misses
< system.cpu.l2cache.overall_misses::total 156339 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3974500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 412000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 905251250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 810262998 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 1719900748 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 510978 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 510978 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9827066492 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 9827066492 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3974500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 412000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 905251250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10637329490 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 11546967240 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3974500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 412000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 905251250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10637329490 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 11546967240 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53643 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10248 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 980269 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 397722 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 1441882 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 607635 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 607635 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2959 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2959 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 246069 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 246069 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53643 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 10248 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 980269 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 643791 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1687951 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53643 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 10248 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 980269 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 643791 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1687951 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000839 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000195 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012606 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.027014 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.016054 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984454 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984454 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541275 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.541275 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000839 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000195 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012606 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.223574 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.092621 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000839 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000195 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012606 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.223574 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.092621 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88322.222222 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 206000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73258.173505 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75415.394453 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74300.187835 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 175.412976 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 175.412976 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73781.760720 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73781.760720 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 73858.520523 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88322.222222 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 206000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73258.173505 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73903.702991 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 73858.520523 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses
> system.cpu.l2cache.overall_misses::total 156349 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency
1119,1130c1142,1153
< system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks
< system.cpu.l2cache.writebacks::total 59141 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 45 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks
> system.cpu.l2cache.writebacks::total 59130 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
1132,1136c1155,1159
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12342 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10679 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 23068 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2913 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 2913 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses
1139,1141c1162,1164
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133191 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 133191 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 45 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133222 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
1143,1146c1166,1169
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 12342 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 143870 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 156259 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 45 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12332 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 143881 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
1148,1157c1171,1180
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 12342 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 143870 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 156259 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3417500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 749197750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 673040498 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1426043248 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29132913 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29132913 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12332 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 143881 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles
1160,1207c1183,1230
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8170239508 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8170239508 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3417500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 749197750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8843280006 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9596282756 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3417500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 749197750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8843280006 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9596282756 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6814499 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942562250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166949376749 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17458567530 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17458567530 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6814499 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184401129780 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184407944279 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026850 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015999 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984454 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984454 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541275 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541275 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.092573 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000195 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012590 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223473 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.092573 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 193750 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60703.107276 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63024.674408 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61819.110803 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency
1210,1221c1233,1244
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency
1231,1237c1254,1260
< system.cpu.dcache.tags.replacements 643279 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.993228 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 21514190 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 643791 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 33.417973 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 43094250 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.993228 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.replacements 643320 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor
1242,1243c1265,1266
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
1245,1324c1268,1347
< system.cpu.dcache.tags.tag_accesses 101537487 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 101537487 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 13760648 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13760648 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 7259865 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 7259865 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 242998 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 242998 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247594 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 21020513 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 21020513 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 21020513 # number of overall hits
< system.cpu.dcache.overall_hits::total 21020513 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 736359 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 736359 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2962417 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2962417 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 13527 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 13527 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 3698776 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 3698776 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 3698776 # number of overall misses
< system.cpu.dcache.overall_misses::total 3698776 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles
< system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 149727245915 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 149727245915 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 149727245915 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 14497007 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 14497007 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10222282 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10222282 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256525 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 256525 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247610 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247610 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 24719289 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.149631 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.149631 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.149631 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.149631 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13556.991000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13556.991000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.438444 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.438444 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13697.567827 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13697.567827 # average LoadLockedReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15343.937500 # average StoreCondReq miss latency
< system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked
---
> system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits
> system.cpu.dcache.overall_hits::total 21015072 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses
> system.cpu.dcache.overall_misses::total 3699212 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles
> system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency
> system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked
1327,1392c1350,1415
< system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks
< system.cpu.dcache.writebacks::total 607635 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses
< system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency
< system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks
> system.cpu.dcache.writebacks::total 607456 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses
> system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency
1416,1419c1439,1442
< system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles
< system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles
< system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles
---
> system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles
> system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles
> system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles
1426c1449
< system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
---
> system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed