1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.537930 # Number of seconds simulated
4sim_ticks 2537929870500 # Number of ticks simulated
5final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 62423 # Simulator instruction rate (inst/s)
8host_op_rate 80294 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2613828720 # Simulator tick rate (ticks/s)
10host_mem_usage 387060 # Number of bytes of host memory used
11host_seconds 970.96 # Real time elapsed on the host
12sim_insts 60609996 # Number of instructions simulated
13sim_ops 77962726 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory
19system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s)
52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.537930 # Number of seconds simulated
4sim_ticks 2537929870500 # Number of ticks simulated
5final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 62423 # Simulator instruction rate (inst/s)
8host_op_rate 80294 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2613828720 # Simulator tick rate (ticks/s)
10host_mem_usage 387060 # Number of bytes of host memory used
11host_seconds 970.96 # Real time elapsed on the host
12sim_insts 60609996 # Number of instructions simulated
13sim_ops 77962726 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory
19system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s)
52system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
|
64system.l2c.replacements 64349 # number of replacements
65system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use
66system.l2c.total_refs 1931844 # Total number of references to valid blocks.
67system.l2c.sampled_refs 129748 # Sample count of references to valid blocks.
68system.l2c.avg_refs 14.889201 # Average number of references to valid blocks.
69system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
70system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
71system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
72system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
73system.l2c.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
74system.l2c.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
75system.l2c.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
76system.l2c.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
77system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
78system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
79system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
80system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy
81system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits
82system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits
83system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
84system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
85system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits
86system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits
87system.l2c.Writeback_hits::total 609524 # number of Writeback hits
88system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
89system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits
90system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
91system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
92system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
93system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits
94system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits
95system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits
96system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
97system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits
98system.l2c.demand_hits::total 1576793 # number of demand (read+write) hits
99system.l2c.overall_hits::cpu.dtb.walker 84751 # number of overall hits
100system.l2c.overall_hits::cpu.itb.walker 12176 # number of overall hits
101system.l2c.overall_hits::cpu.inst 977692 # number of overall hits
102system.l2c.overall_hits::cpu.data 502174 # number of overall hits
103system.l2c.overall_hits::total 1576793 # number of overall hits
104system.l2c.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
105system.l2c.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
106system.l2c.ReadReq_misses::cpu.inst 12366 # number of ReadReq misses
107system.l2c.ReadReq_misses::cpu.data 10706 # number of ReadReq misses
108system.l2c.ReadReq_misses::total 23139 # number of ReadReq misses
109system.l2c.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
110system.l2c.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
111system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
112system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
113system.l2c.ReadExReq_misses::cpu.data 133143 # number of ReadExReq misses
114system.l2c.ReadExReq_misses::total 133143 # number of ReadExReq misses
115system.l2c.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses
119system.l2c.demand_misses::total 156282 # number of demand (read+write) misses
120system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses
121system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses
122system.l2c.overall_misses::cpu.inst 12366 # number of overall misses
123system.l2c.overall_misses::cpu.data 143849 # number of overall misses
124system.l2c.overall_misses::total 156282 # number of overall misses
125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
126system.l2c.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
127system.l2c.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
128system.l2c.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
129system.l2c.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
130system.l2c.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
131system.l2c.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
132system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
133system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
134system.l2c.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
135system.l2c.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
136system.l2c.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
137system.l2c.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
138system.l2c.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
139system.l2c.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
140system.l2c.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
141system.l2c.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
142system.l2c.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
143system.l2c.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
144system.l2c.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
145system.l2c.overall_miss_latency::total 8295680990 # number of overall miss cycles
146system.l2c.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
147system.l2c.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
148system.l2c.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
149system.l2c.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
150system.l2c.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
151system.l2c.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
152system.l2c.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
153system.l2c.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
154system.l2c.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
155system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
156system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
157system.l2c.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
158system.l2c.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
159system.l2c.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
160system.l2c.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
161system.l2c.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
162system.l2c.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
163system.l2c.demand_accesses::total 1733075 # number of demand (read+write) accesses
164system.l2c.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
165system.l2c.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
166system.l2c.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
167system.l2c.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
168system.l2c.overall_accesses::total 1733075 # number of overall (read+write) accesses
169system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
170system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
171system.l2c.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
172system.l2c.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
173system.l2c.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
174system.l2c.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
175system.l2c.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
176system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
177system.l2c.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
178system.l2c.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
179system.l2c.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
180system.l2c.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
181system.l2c.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
182system.l2c.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
183system.l2c.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
184system.l2c.demand_miss_rate::total 0.090176 # miss rate for demand accesses
185system.l2c.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
186system.l2c.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
187system.l2c.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
188system.l2c.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
189system.l2c.overall_miss_rate::total 0.090176 # miss rate for overall accesses
190system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
191system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
192system.l2c.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
193system.l2c.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
194system.l2c.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
195system.l2c.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
196system.l2c.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
197system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
198system.l2c.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
199system.l2c.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
200system.l2c.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
201system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
202system.l2c.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
203system.l2c.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
204system.l2c.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
205system.l2c.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
206system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
207system.l2c.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
208system.l2c.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
209system.l2c.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
210system.l2c.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
211system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
212system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
213system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
214system.l2c.blocked::no_targets 0 # number of cycles access was blocked
215system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
216system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
217system.l2c.fast_writes 0 # number of fast writes performed
218system.l2c.cache_copies 0 # number of cache copies performed
219system.l2c.writebacks::writebacks 59057 # number of writebacks
220system.l2c.writebacks::total 59057 # number of writebacks
221system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
222system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
223system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
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228system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
229system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits
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234system.l2c.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
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236system.l2c.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
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238system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
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240system.l2c.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
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246system.l2c.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
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248system.l2c.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
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250system.l2c.overall_mshr_misses::total 156212 # number of overall MSHR misses
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252system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
253system.l2c.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
254system.l2c.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
255system.l2c.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
256system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
257system.l2c.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
258system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
259system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
260system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
261system.l2c.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
262system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
263system.l2c.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
264system.l2c.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
265system.l2c.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
266system.l2c.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
267system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
268system.l2c.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
269system.l2c.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
270system.l2c.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
271system.l2c.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
272system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
273system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
274system.l2c.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
275system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
276system.l2c.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
277system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
278system.l2c.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
279system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
280system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
281system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
282system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
283system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
284system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
285system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
286system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
287system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
288system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
289system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
290system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
291system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
292system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
293system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
294system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
295system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
296system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
297system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
298system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
299system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
300system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
301system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
302system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
303system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
304system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
305system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
306system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
307system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
308system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
309system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
310system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
311system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
312system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
313system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
314system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
315system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
316system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
317system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
318system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
319system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
320system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
321system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
322system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
323system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
324system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
325system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
326system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
327system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
328system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
329system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
330system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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65system.cpu.l2cache.tagsinuse 51364.190937 # Cycle average of tags in use
66system.cpu.l2cache.total_refs 1931844 # Total number of references to valid blocks.
67system.cpu.l2cache.sampled_refs 129748 # Sample count of references to valid blocks.
68system.cpu.l2cache.avg_refs 14.889201 # Average number of references to valid blocks.
69system.cpu.l2cache.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit.
70system.cpu.l2cache.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor
71system.cpu.l2cache.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor
72system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor
73system.cpu.l2cache.occ_blocks::cpu.inst 8179.867206 # Average occupied blocks per requestor
74system.cpu.l2cache.occ_blocks::cpu.data 6231.906599 # Average occupied blocks per requestor
75system.cpu.l2cache.occ_percent::writebacks 0.563050 # Average percentage of cache occupancy
76system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000799 # Average percentage of cache occupancy
77system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
78system.cpu.l2cache.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy
79system.cpu.l2cache.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy
80system.cpu.l2cache.occ_percent::total 0.783755 # Average percentage of cache occupancy
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83system.cpu.l2cache.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits
84system.cpu.l2cache.ReadReq_hits::cpu.data 389039 # number of ReadReq hits
85system.cpu.l2cache.ReadReq_hits::total 1463658 # number of ReadReq hits
86system.cpu.l2cache.Writeback_hits::writebacks 609524 # number of Writeback hits
87system.cpu.l2cache.Writeback_hits::total 609524 # number of Writeback hits
88system.cpu.l2cache.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits
89system.cpu.l2cache.UpgradeReq_hits::total 48 # number of UpgradeReq hits
90system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits
91system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
92system.cpu.l2cache.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits
93system.cpu.l2cache.ReadExReq_hits::total 113135 # number of ReadExReq hits
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96system.cpu.l2cache.demand_hits::cpu.inst 977692 # number of demand (read+write) hits
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101system.cpu.l2cache.overall_hits::cpu.inst 977692 # number of overall hits
102system.cpu.l2cache.overall_hits::cpu.data 502174 # number of overall hits
103system.cpu.l2cache.overall_hits::total 1576793 # number of overall hits
104system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 65 # number of ReadReq misses
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109system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
110system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
111system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
112system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
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114system.cpu.l2cache.ReadExReq_misses::total 133143 # number of ReadExReq misses
115system.cpu.l2cache.demand_misses::cpu.dtb.walker 65 # number of demand (read+write) misses
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117system.cpu.l2cache.demand_misses::cpu.inst 12366 # number of demand (read+write) misses
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120system.cpu.l2cache.overall_misses::cpu.dtb.walker 65 # number of overall misses
121system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
122system.cpu.l2cache.overall_misses::cpu.inst 12366 # number of overall misses
123system.cpu.l2cache.overall_misses::cpu.data 143849 # number of overall misses
124system.cpu.l2cache.overall_misses::total 156282 # number of overall misses
125system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3412000 # number of ReadReq miss cycles
126system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 112500 # number of ReadReq miss cycles
127system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 658599996 # number of ReadReq miss cycles
128system.cpu.l2cache.ReadReq_miss_latency::cpu.data 563085498 # number of ReadReq miss cycles
129system.cpu.l2cache.ReadReq_miss_latency::total 1225209994 # number of ReadReq miss cycles
130system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1357500 # number of UpgradeReq miss cycles
131system.cpu.l2cache.UpgradeReq_miss_latency::total 1357500 # number of UpgradeReq miss cycles
132system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles
133system.cpu.l2cache.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles
134system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7070470996 # number of ReadExReq miss cycles
135system.cpu.l2cache.ReadExReq_miss_latency::total 7070470996 # number of ReadExReq miss cycles
136system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3412000 # number of demand (read+write) miss cycles
137system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 112500 # number of demand (read+write) miss cycles
138system.cpu.l2cache.demand_miss_latency::cpu.inst 658599996 # number of demand (read+write) miss cycles
139system.cpu.l2cache.demand_miss_latency::cpu.data 7633556494 # number of demand (read+write) miss cycles
140system.cpu.l2cache.demand_miss_latency::total 8295680990 # number of demand (read+write) miss cycles
141system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3412000 # number of overall miss cycles
142system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 112500 # number of overall miss cycles
143system.cpu.l2cache.overall_miss_latency::cpu.inst 658599996 # number of overall miss cycles
144system.cpu.l2cache.overall_miss_latency::cpu.data 7633556494 # number of overall miss cycles
145system.cpu.l2cache.overall_miss_latency::total 8295680990 # number of overall miss cycles
146system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 84816 # number of ReadReq accesses(hits+misses)
147system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12178 # number of ReadReq accesses(hits+misses)
148system.cpu.l2cache.ReadReq_accesses::cpu.inst 990058 # number of ReadReq accesses(hits+misses)
149system.cpu.l2cache.ReadReq_accesses::cpu.data 399745 # number of ReadReq accesses(hits+misses)
150system.cpu.l2cache.ReadReq_accesses::total 1486797 # number of ReadReq accesses(hits+misses)
151system.cpu.l2cache.Writeback_accesses::writebacks 609524 # number of Writeback accesses(hits+misses)
152system.cpu.l2cache.Writeback_accesses::total 609524 # number of Writeback accesses(hits+misses)
153system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2968 # number of UpgradeReq accesses(hits+misses)
154system.cpu.l2cache.UpgradeReq_accesses::total 2968 # number of UpgradeReq accesses(hits+misses)
155system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
156system.cpu.l2cache.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
157system.cpu.l2cache.ReadExReq_accesses::cpu.data 246278 # number of ReadExReq accesses(hits+misses)
158system.cpu.l2cache.ReadExReq_accesses::total 246278 # number of ReadExReq accesses(hits+misses)
159system.cpu.l2cache.demand_accesses::cpu.dtb.walker 84816 # number of demand (read+write) accesses
160system.cpu.l2cache.demand_accesses::cpu.itb.walker 12178 # number of demand (read+write) accesses
161system.cpu.l2cache.demand_accesses::cpu.inst 990058 # number of demand (read+write) accesses
162system.cpu.l2cache.demand_accesses::cpu.data 646023 # number of demand (read+write) accesses
163system.cpu.l2cache.demand_accesses::total 1733075 # number of demand (read+write) accesses
164system.cpu.l2cache.overall_accesses::cpu.dtb.walker 84816 # number of overall (read+write) accesses
165system.cpu.l2cache.overall_accesses::cpu.itb.walker 12178 # number of overall (read+write) accesses
166system.cpu.l2cache.overall_accesses::cpu.inst 990058 # number of overall (read+write) accesses
167system.cpu.l2cache.overall_accesses::cpu.data 646023 # number of overall (read+write) accesses
168system.cpu.l2cache.overall_accesses::total 1733075 # number of overall (read+write) accesses
169system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000766 # miss rate for ReadReq accesses
170system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000164 # miss rate for ReadReq accesses
171system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012490 # miss rate for ReadReq accesses
172system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026782 # miss rate for ReadReq accesses
173system.cpu.l2cache.ReadReq_miss_rate::total 0.015563 # miss rate for ReadReq accesses
174system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.983827 # miss rate for UpgradeReq accesses
175system.cpu.l2cache.UpgradeReq_miss_rate::total 0.983827 # miss rate for UpgradeReq accesses
176system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.230769 # miss rate for SCUpgradeReq accesses
177system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.230769 # miss rate for SCUpgradeReq accesses
178system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.540621 # miss rate for ReadExReq accesses
179system.cpu.l2cache.ReadExReq_miss_rate::total 0.540621 # miss rate for ReadExReq accesses
180system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000766 # miss rate for demand accesses
181system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000164 # miss rate for demand accesses
182system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012490 # miss rate for demand accesses
183system.cpu.l2cache.demand_miss_rate::cpu.data 0.222669 # miss rate for demand accesses
184system.cpu.l2cache.demand_miss_rate::total 0.090176 # miss rate for demand accesses
185system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000766 # miss rate for overall accesses
186system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000164 # miss rate for overall accesses
187system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012490 # miss rate for overall accesses
188system.cpu.l2cache.overall_miss_rate::cpu.data 0.222669 # miss rate for overall accesses
189system.cpu.l2cache.overall_miss_rate::total 0.090176 # miss rate for overall accesses
190system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52492.307692 # average ReadReq miss latency
191system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 56250 # average ReadReq miss latency
192system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53258.935468 # average ReadReq miss latency
193system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52595.320194 # average ReadReq miss latency
194system.cpu.l2cache.ReadReq_avg_miss_latency::total 52949.997580 # average ReadReq miss latency
195system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 464.897260 # average UpgradeReq miss latency
196system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 464.897260 # average UpgradeReq miss latency
197system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333 # average SCUpgradeReq miss latency
198system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 17333.333333 # average SCUpgradeReq miss latency
199system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53104.338914 # average ReadExReq miss latency
200system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53104.338914 # average ReadExReq miss latency
201system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
202system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
203system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
204system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
205system.cpu.l2cache.demand_avg_miss_latency::total 53081.487247 # average overall miss latency
206system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52492.307692 # average overall miss latency
207system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 56250 # average overall miss latency
208system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53258.935468 # average overall miss latency
209system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53066.455061 # average overall miss latency
210system.cpu.l2cache.overall_avg_miss_latency::total 53081.487247 # average overall miss latency
211system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
212system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
213system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
214system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
215system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
216system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
217system.cpu.l2cache.fast_writes 0 # number of fast writes performed
218system.cpu.l2cache.cache_copies 0 # number of cache copies performed
219system.cpu.l2cache.writebacks::writebacks 59057 # number of writebacks
220system.cpu.l2cache.writebacks::total 59057 # number of writebacks
221system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
222system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
223system.cpu.l2cache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
224system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
225system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
226system.cpu.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
227system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
228system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
229system.cpu.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits
230system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 65 # number of ReadReq MSHR misses
231system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
232system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12358 # number of ReadReq MSHR misses
233system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10644 # number of ReadReq MSHR misses
234system.cpu.l2cache.ReadReq_mshr_misses::total 23069 # number of ReadReq MSHR misses
235system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
236system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
237system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
238system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
239system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133143 # number of ReadExReq MSHR misses
240system.cpu.l2cache.ReadExReq_mshr_misses::total 133143 # number of ReadExReq MSHR misses
241system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 65 # number of demand (read+write) MSHR misses
242system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
243system.cpu.l2cache.demand_mshr_misses::cpu.inst 12358 # number of demand (read+write) MSHR misses
244system.cpu.l2cache.demand_mshr_misses::cpu.data 143787 # number of demand (read+write) MSHR misses
245system.cpu.l2cache.demand_mshr_misses::total 156212 # number of demand (read+write) MSHR misses
246system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 65 # number of overall MSHR misses
247system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
248system.cpu.l2cache.overall_mshr_misses::cpu.inst 12358 # number of overall MSHR misses
249system.cpu.l2cache.overall_mshr_misses::cpu.data 143787 # number of overall MSHR misses
250system.cpu.l2cache.overall_mshr_misses::total 156212 # number of overall MSHR misses
251system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2621000 # number of ReadReq MSHR miss cycles
252system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 88000 # number of ReadReq MSHR miss cycles
253system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 507385499 # number of ReadReq MSHR miss cycles
254system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 430816500 # number of ReadReq MSHR miss cycles
255system.cpu.l2cache.ReadReq_mshr_miss_latency::total 940910999 # number of ReadReq MSHR miss cycles
256system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 117082500 # number of UpgradeReq MSHR miss cycles
257system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 117082500 # number of UpgradeReq MSHR miss cycles
258system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles
259system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles
260system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5437705996 # number of ReadExReq MSHR miss cycles
261system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5437705996 # number of ReadExReq MSHR miss cycles
262system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2621000 # number of demand (read+write) MSHR miss cycles
263system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
264system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 507385499 # number of demand (read+write) MSHR miss cycles
265system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5868522496 # number of demand (read+write) MSHR miss cycles
266system.cpu.l2cache.demand_mshr_miss_latency::total 6378616995 # number of demand (read+write) MSHR miss cycles
267system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2621000 # number of overall MSHR miss cycles
268system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 88000 # number of overall MSHR miss cycles
269system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 507385499 # number of overall MSHR miss cycles
270system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5868522496 # number of overall MSHR miss cycles
271system.cpu.l2cache.overall_mshr_miss_latency::total 6378616995 # number of overall MSHR miss cycles
272system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5274000 # number of ReadReq MSHR uncacheable cycles
273system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166745935000 # number of ReadReq MSHR uncacheable cycles
274system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166751209000 # number of ReadReq MSHR uncacheable cycles
275system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 32089389588 # number of WriteReq MSHR uncacheable cycles
276system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32089389588 # number of WriteReq MSHR uncacheable cycles
277system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5274000 # number of overall MSHR uncacheable cycles
278system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 198835324588 # number of overall MSHR uncacheable cycles
279system.cpu.l2cache.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles
280system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses
281system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses
282system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses
283system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses
284system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses
285system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses
286system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses
287system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses
288system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses
289system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses
290system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses
291system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses
292system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses
293system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses
294system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses
295system.cpu.l2cache.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses
296system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses
297system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses
298system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses
299system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses
300system.cpu.l2cache.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses
301system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency
302system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency
303system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency
304system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency
305system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency
306system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency
307system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency
308system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
309system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency
311system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency
312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
313system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
316system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
317system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency
318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency
319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency
320system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency
321system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency
322system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
323system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
324system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
325system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
326system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
327system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
328system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
329system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
330system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
336system.cf0.dma_write_txs 0 # Number of DMA write transactions.
337system.cpu.dtb.inst_hits 0 # ITB inst hits
338system.cpu.dtb.inst_misses 0 # ITB inst misses
339system.cpu.dtb.read_hits 51757171 # DTB read hits
340system.cpu.dtb.read_misses 78755 # DTB read misses
341system.cpu.dtb.write_hits 11824944 # DTB write hits
342system.cpu.dtb.write_misses 17612 # DTB write misses
343system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
344system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
345system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
346system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
347system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB
348system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions
349system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
350system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
351system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions
352system.cpu.dtb.read_accesses 51835926 # DTB read accesses
353system.cpu.dtb.write_accesses 11842556 # DTB write accesses
354system.cpu.dtb.inst_accesses 0 # ITB inst accesses
355system.cpu.dtb.hits 63582115 # DTB hits
356system.cpu.dtb.misses 96367 # DTB misses
357system.cpu.dtb.accesses 63678482 # DTB accesses
358system.cpu.itb.inst_hits 13115769 # ITB inst hits
359system.cpu.itb.inst_misses 12252 # ITB inst misses
360system.cpu.itb.read_hits 0 # DTB read hits
361system.cpu.itb.read_misses 0 # DTB read misses
362system.cpu.itb.write_hits 0 # DTB write hits
363system.cpu.itb.write_misses 0 # DTB write misses
364system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
366system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
367system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
368system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB
369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
372system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 13128021 # ITB inst accesses
376system.cpu.itb.hits 13115769 # DTB hits
377system.cpu.itb.misses 12252 # DTB misses
378system.cpu.itb.accesses 13128021 # DTB accesses
379system.cpu.numCycles 487049956 # number of cpu cycles simulated
380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
382system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups
383system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted
384system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect
385system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups
386system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits
387system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
388system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target.
389system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions.
390system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss
391system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed
392system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered
393system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken
394system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked
395system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing
396system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb
397system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked
398system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
399system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps
400system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions
401system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
402system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched
403system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed
404system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed
405system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total)
411system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total)
412system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total)
413system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total)
414system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total)
415system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total)
416system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total)
417system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total)
418system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
419system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
420system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total)
422system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle
423system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle
424system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle
425system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked
426system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running
427system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking
428system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing
429system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch
430system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction
431system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode
432system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode
433system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing
434system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle
435system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking
436system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst
437system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running
438system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking
439system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename
440system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full
441system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full
442system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full
443system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers
444system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed
445system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made
446system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups
447system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups
448system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed
449system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing
450system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed
451system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed
452system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer
453system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit.
454system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit.
455system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads.
456system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores.
457system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec)
458system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ
459system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued
460system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued
461system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling
462system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph
463system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed
464system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle
471system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle
472system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle
473system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle
474system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle
475system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle
476system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle
477system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
478system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
479system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle
481system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
482system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available
483system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available
484system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
485system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available
486system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available
487system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available
488system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available
489system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available
490system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available
501system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available
502system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available
503system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
511system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available
512system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available
513system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
514system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
515system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
516system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued
517system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued
518system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued
519system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued
520system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued
521system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued
522system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued
523system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued
524system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued
535system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued
536system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued
537system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued
538system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued
539system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued
540system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued
541system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued
545system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued
546system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued
547system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
548system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
549system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued
550system.cpu.iq.rate 0.259310 # Inst issue rate
551system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested
552system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst)
553system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads
554system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes
555system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses
556system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads
557system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes
558system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses
559system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses
560system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses
561system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores
562system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
563system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed
564system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed
565system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations
566system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed
567system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
568system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
569system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled
570system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked
571system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
572system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing
573system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking
574system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking
575system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ
576system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch
577system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions
578system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions
579system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions
580system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall
581system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall
582system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations
583system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly
584system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly
585system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute
586system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions
587system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed
588system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute
589system.cpu.iew.exec_swp 0 # number of swp insts executed
590system.cpu.iew.exec_nop 226495 # number of nop insts executed
591system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed
592system.cpu.iew.exec_branches 11753944 # Number of branches executed
593system.cpu.iew.exec_stores 12337385 # Number of stores executed
594system.cpu.iew.exec_rate 0.252721 # Inst execution rate
595system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit
596system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back
597system.cpu.iew.wb_producers 47490892 # num instructions producing a value
598system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value
599system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
600system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle
601system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back
602system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
603system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit
604system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards
605system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted
606system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle
611system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle
612system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle
613system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle
614system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle
615system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle
617system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle
618system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle
619system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
620system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
621system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
622system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle
623system.cpu.commit.committedInsts 60760377 # Number of instructions committed
624system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed
625system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
626system.cpu.commit.refs 27521116 # Number of memory references committed
627system.cpu.commit.loads 15720306 # Number of loads committed
628system.cpu.commit.membars 413361 # Number of memory barriers committed
629system.cpu.commit.branches 10025135 # Number of branches committed
630system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
631system.cpu.commit.int_insts 69149691 # Number of committed integer instructions.
632system.cpu.commit.function_calls 996276 # Number of function calls committed.
633system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached
634system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
635system.cpu.rob.rob_reads 256258159 # The number of ROB reads
636system.cpu.rob.rob_writes 209428063 # The number of ROB writes
637system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself
638system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling
639system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
640system.cpu.committedInsts 60609996 # Number of Instructions Simulated
641system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated
642system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated
643system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction
644system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads
645system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle
646system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads
647system.cpu.int_regfile_reads 557221649 # number of integer regfile reads
648system.cpu.int_regfile_writes 90065135 # number of integer regfile writes
649system.cpu.fp_regfile_reads 8220 # number of floating regfile reads
650system.cpu.fp_regfile_writes 2852 # number of floating regfile writes
651system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads
652system.cpu.misc_regfile_writes 913466 # number of misc regfile writes
653system.cpu.icache.replacements 990831 # number of replacements
654system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use
655system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks.
656system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks.
657system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks.
658system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit.
659system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor
660system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy
661system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy
662system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits
663system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits
664system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits
665system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits
666system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits
667system.cpu.icache.overall_hits::total 12036161 # number of overall hits
668system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses
669system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses
670system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses
671system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses
672system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses
673system.cpu.icache.overall_misses::total 1075440 # number of overall misses
674system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles
675system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles
676system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles
677system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles
678system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles
679system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles
680system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses)
681system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses)
682system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses
683system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses
684system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses
685system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses
686system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses
687system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses
688system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses
689system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses
690system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses
691system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses
692system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency
693system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency
694system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
695system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency
696system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
697system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency
698system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked
699system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked
701system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
702system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked
703system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704system.cpu.icache.fast_writes 0 # number of fast writes performed
705system.cpu.icache.cache_copies 0 # number of cache copies performed
706system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits
707system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits
708system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits
709system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits
710system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits
711system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits
712system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses
713system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses
714system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses
715system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses
716system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses
717system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses
718system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles
719system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles
720system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles
721system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles
722system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles
723system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles
724system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles
725system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles
726system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles
727system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles
728system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses
729system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses
730system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses
731system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses
732system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses
733system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses
734system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency
735system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency
736system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
737system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
738system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
739system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
740system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
741system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
742system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
743system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
744system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
745system.cpu.dcache.replacements 645511 # number of replacements
746system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use
747system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks.
748system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks.
749system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks.
750system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit.
751system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor
752system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy
753system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy
754system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits
755system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits
756system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits
757system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits
758system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits
759system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits
760system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits
761system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits
762system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits
763system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits
764system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits
765system.cpu.dcache.overall_hits::total 21154214 # number of overall hits
766system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses
767system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses
768system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses
769system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses
770system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses
771system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses
772system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
773system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
774system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses
775system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses
776system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses
777system.cpu.dcache.overall_misses::total 3765402 # number of overall misses
778system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles
779system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles
780system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles
781system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles
782system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles
783system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles
784system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles
785system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles
786system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles
787system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles
788system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles
789system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles
790system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses)
791system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses)
792system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses)
793system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses)
794system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses)
795system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses)
796system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses)
797system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses)
798system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses
799system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses
800system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses
801system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses
802system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses
803system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses
804system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses
805system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses
806system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses
807system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses
808system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses
809system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses
810system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses
811system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses
812system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses
813system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses
814system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency
815system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency
816system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency
817system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency
818system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency
819system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency
820system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency
821system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency
822system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
823system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency
824system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
825system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency
826system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked
827system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked
828system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked
829system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked
830system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked
831system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked
832system.cpu.dcache.fast_writes 0 # number of fast writes performed
833system.cpu.dcache.cache_copies 0 # number of cache copies performed
834system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks
835system.cpu.dcache.writebacks::total 609524 # number of writebacks
836system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits
837system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits
838system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits
840system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits
841system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits
842system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits
843system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits
844system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits
845system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits
846system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses
847system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses
848system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses
849system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses
850system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses
851system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses
852system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
853system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
854system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses
855system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses
856system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses
857system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses
858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles
859system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles
860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles
861system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles
862system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles
863system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles
864system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles
865system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles
866system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles
867system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles
868system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles
869system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles
870system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles
871system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles
872system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles
873system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles
874system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles
875system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles
876system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses
877system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses
878system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses
879system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses
880system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses
881system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses
882system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses
883system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses
884system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses
885system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses
886system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses
887system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses
888system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency
889system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency
890system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency
891system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency
892system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency
893system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency
894system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency
895system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency
896system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
897system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
898system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
899system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
900system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
901system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
902system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
903system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
904system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
905system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
906system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
907system.iocache.replacements 0 # number of replacements
908system.iocache.tagsinuse 0 # Cycle average of tags in use
909system.iocache.total_refs 0 # Total number of references to valid blocks.
910system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
911system.iocache.avg_refs nan # Average number of references to valid blocks.
912system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
913system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
914system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
915system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
916system.iocache.blocked::no_targets 0 # number of cycles access was blocked
917system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
918system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
919system.iocache.fast_writes 0 # number of fast writes performed
920system.iocache.cache_copies 0 # number of cache copies performed
921system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles
922system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles
923system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles
924system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles
925system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
926system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
927system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
928system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
929system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
930system.cpu.kern.inst.arm 0 # number of arm instructions executed
931system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed
932
933---------- End Simulation Statistics ----------
| 331system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
332system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
333system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
334system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
335system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
336system.cf0.dma_write_txs 0 # Number of DMA write transactions.
337system.cpu.dtb.inst_hits 0 # ITB inst hits
338system.cpu.dtb.inst_misses 0 # ITB inst misses
339system.cpu.dtb.read_hits 51757171 # DTB read hits
340system.cpu.dtb.read_misses 78755 # DTB read misses
341system.cpu.dtb.write_hits 11824944 # DTB write hits
342system.cpu.dtb.write_misses 17612 # DTB write misses
343system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
344system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
345system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
346system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
347system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB
348system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions
349system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch
350system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
351system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions
352system.cpu.dtb.read_accesses 51835926 # DTB read accesses
353system.cpu.dtb.write_accesses 11842556 # DTB write accesses
354system.cpu.dtb.inst_accesses 0 # ITB inst accesses
355system.cpu.dtb.hits 63582115 # DTB hits
356system.cpu.dtb.misses 96367 # DTB misses
357system.cpu.dtb.accesses 63678482 # DTB accesses
358system.cpu.itb.inst_hits 13115769 # ITB inst hits
359system.cpu.itb.inst_misses 12252 # ITB inst misses
360system.cpu.itb.read_hits 0 # DTB read hits
361system.cpu.itb.read_misses 0 # DTB read misses
362system.cpu.itb.write_hits 0 # DTB write hits
363system.cpu.itb.write_misses 0 # DTB write misses
364system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
365system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
366system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
367system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
368system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB
369system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
370system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
371system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
372system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions
373system.cpu.itb.read_accesses 0 # DTB read accesses
374system.cpu.itb.write_accesses 0 # DTB write accesses
375system.cpu.itb.inst_accesses 13128021 # ITB inst accesses
376system.cpu.itb.hits 13115769 # DTB hits
377system.cpu.itb.misses 12252 # DTB misses
378system.cpu.itb.accesses 13128021 # DTB accesses
379system.cpu.numCycles 487049956 # number of cpu cycles simulated
380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
382system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups
383system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted
384system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect
385system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups
386system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits
387system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
388system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target.
389system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions.
390system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss
391system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed
392system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered
393system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken
394system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked
395system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing
396system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb
397system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked
398system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
399system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps
400system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions
401system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
402system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched
403system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed
404system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed
405system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total)
407system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total)
408system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total)
411system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total)
412system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total)
413system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total)
414system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total)
415system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total)
416system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total)
417system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total)
418system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
419system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
420system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total)
422system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle
423system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle
424system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle
425system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked
426system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running
427system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking
428system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing
429system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch
430system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction
431system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode
432system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode
433system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing
434system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle
435system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking
436system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst
437system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running
438system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking
439system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename
440system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full
441system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full
442system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full
443system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers
444system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed
445system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made
446system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups
447system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups
448system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed
449system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing
450system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed
451system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed
452system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer
453system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit.
454system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit.
455system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads.
456system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores.
457system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec)
458system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ
459system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued
460system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued
461system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling
462system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph
463system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed
464system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle
465system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle
466system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle
467system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle
471system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle
472system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle
473system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle
474system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle
475system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle
476system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle
477system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
478system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
479system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle
481system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
482system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available
483system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available
484system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available
485system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available
486system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available
487system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available
488system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available
489system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available
490system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available
501system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available
502system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available
503system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available
511system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available
512system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available
513system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
514system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
515system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
516system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued
517system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued
518system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued
519system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued
520system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued
521system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued
522system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued
523system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued
524system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued
535system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued
536system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued
537system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued
538system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued
539system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued
540system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued
541system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued
545system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued
546system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued
547system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
548system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
549system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued
550system.cpu.iq.rate 0.259310 # Inst issue rate
551system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested
552system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst)
553system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads
554system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes
555system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses
556system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads
557system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes
558system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses
559system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses
560system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses
561system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores
562system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
563system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed
564system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed
565system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations
566system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed
567system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
568system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
569system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled
570system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked
571system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
572system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing
573system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking
574system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking
575system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ
576system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch
577system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions
578system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions
579system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions
580system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall
581system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall
582system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations
583system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly
584system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly
585system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute
586system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions
587system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed
588system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute
589system.cpu.iew.exec_swp 0 # number of swp insts executed
590system.cpu.iew.exec_nop 226495 # number of nop insts executed
591system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed
592system.cpu.iew.exec_branches 11753944 # Number of branches executed
593system.cpu.iew.exec_stores 12337385 # Number of stores executed
594system.cpu.iew.exec_rate 0.252721 # Inst execution rate
595system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit
596system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back
597system.cpu.iew.wb_producers 47490892 # num instructions producing a value
598system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value
599system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
600system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle
601system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back
602system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
603system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit
604system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards
605system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted
606system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle
607system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle
608system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle
609system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
610system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle
611system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle
612system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle
613system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle
614system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle
615system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle
617system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle
618system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle
619system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
620system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
621system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
622system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle
623system.cpu.commit.committedInsts 60760377 # Number of instructions committed
624system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed
625system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
626system.cpu.commit.refs 27521116 # Number of memory references committed
627system.cpu.commit.loads 15720306 # Number of loads committed
628system.cpu.commit.membars 413361 # Number of memory barriers committed
629system.cpu.commit.branches 10025135 # Number of branches committed
630system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
631system.cpu.commit.int_insts 69149691 # Number of committed integer instructions.
632system.cpu.commit.function_calls 996276 # Number of function calls committed.
633system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached
634system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
635system.cpu.rob.rob_reads 256258159 # The number of ROB reads
636system.cpu.rob.rob_writes 209428063 # The number of ROB writes
637system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself
638system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling
639system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
640system.cpu.committedInsts 60609996 # Number of Instructions Simulated
641system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated
642system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated
643system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction
644system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads
645system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle
646system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads
647system.cpu.int_regfile_reads 557221649 # number of integer regfile reads
648system.cpu.int_regfile_writes 90065135 # number of integer regfile writes
649system.cpu.fp_regfile_reads 8220 # number of floating regfile reads
650system.cpu.fp_regfile_writes 2852 # number of floating regfile writes
651system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads
652system.cpu.misc_regfile_writes 913466 # number of misc regfile writes
653system.cpu.icache.replacements 990831 # number of replacements
654system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use
655system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks.
656system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks.
657system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks.
658system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit.
659system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor
660system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy
661system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy
662system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits
663system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits
664system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits
665system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits
666system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits
667system.cpu.icache.overall_hits::total 12036161 # number of overall hits
668system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses
669system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses
670system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses
671system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses
672system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses
673system.cpu.icache.overall_misses::total 1075440 # number of overall misses
674system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles
675system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles
676system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles
677system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles
678system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles
679system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles
680system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses)
681system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses)
682system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses
683system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses
684system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses
685system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses
686system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses
687system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses
688system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses
689system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses
690system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses
691system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses
692system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency
693system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency
694system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
695system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency
696system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency
697system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency
698system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked
699system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
700system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked
701system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
702system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked
703system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
704system.cpu.icache.fast_writes 0 # number of fast writes performed
705system.cpu.icache.cache_copies 0 # number of cache copies performed
706system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits
707system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits
708system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits
709system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits
710system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits
711system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits
712system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses
713system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses
714system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses
715system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses
716system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses
717system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses
718system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles
719system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles
720system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles
721system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles
722system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles
723system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles
724system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles
725system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles
726system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles
727system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles
728system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses
729system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses
730system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses
731system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses
732system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses
733system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses
734system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency
735system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency
736system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
737system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
738system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency
739system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency
740system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
741system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
742system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
743system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
744system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
745system.cpu.dcache.replacements 645511 # number of replacements
746system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use
747system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks.
748system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks.
749system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks.
750system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit.
751system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor
752system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy
753system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy
754system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits
755system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits
756system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits
757system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits
758system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits
759system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits
760system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits
761system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits
762system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits
763system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits
764system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits
765system.cpu.dcache.overall_hits::total 21154214 # number of overall hits
766system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses
767system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses
768system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses
769system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses
770system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses
771system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses
772system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
773system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
774system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses
775system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses
776system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses
777system.cpu.dcache.overall_misses::total 3765402 # number of overall misses
778system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles
779system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles
780system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles
781system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles
782system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles
783system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles
784system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles
785system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles
786system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles
787system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles
788system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles
789system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles
790system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses)
791system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses)
792system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses)
793system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses)
794system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses)
795system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses)
796system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses)
797system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses)
798system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses
799system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses
800system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses
801system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses
802system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses
803system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses
804system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses
805system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses
806system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses
807system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses
808system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses
809system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses
810system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses
811system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses
812system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses
813system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses
814system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency
815system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency
816system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency
817system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency
818system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency
819system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency
820system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency
821system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency
822system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
823system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency
824system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency
825system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency
826system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked
827system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked
828system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked
829system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked
830system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked
831system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked
832system.cpu.dcache.fast_writes 0 # number of fast writes performed
833system.cpu.dcache.cache_copies 0 # number of cache copies performed
834system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks
835system.cpu.dcache.writebacks::total 609524 # number of writebacks
836system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits
837system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits
838system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits
840system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits
841system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits
842system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits
843system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits
844system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits
845system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits
846system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses
847system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses
848system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses
849system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses
850system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses
851system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses
852system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
853system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
854system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses
855system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses
856system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses
857system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses
858system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles
859system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles
860system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles
861system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles
862system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles
863system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles
864system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles
865system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles
866system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles
867system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles
868system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles
869system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles
870system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles
871system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles
872system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles
873system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles
874system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles
875system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles
876system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses
877system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses
878system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses
879system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses
880system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses
881system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses
882system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses
883system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses
884system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses
885system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses
886system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses
887system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses
888system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency
889system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency
890system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency
891system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency
892system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency
893system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency
894system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency
895system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency
896system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
897system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
898system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency
899system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency
900system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
901system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
902system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
903system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
904system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
905system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
906system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
907system.iocache.replacements 0 # number of replacements
908system.iocache.tagsinuse 0 # Cycle average of tags in use
909system.iocache.total_refs 0 # Total number of references to valid blocks.
910system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
911system.iocache.avg_refs nan # Average number of references to valid blocks.
912system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
913system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
914system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
915system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
916system.iocache.blocked::no_targets 0 # number of cycles access was blocked
917system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
918system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
919system.iocache.fast_writes 0 # number of fast writes performed
920system.iocache.cache_copies 0 # number of cache copies performed
921system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles
922system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles
923system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles
924system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles
925system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
926system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
927system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
928system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
929system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
930system.cpu.kern.inst.arm 0 # number of arm instructions executed
931system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed
932
933---------- End Simulation Statistics ----------
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