1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.501686 # Number of seconds simulated
4sim_ticks 2501685689500 # Number of ticks simulated
5final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.501686 # Number of seconds simulated
4sim_ticks 2501685689500 # Number of ticks simulated
5final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 62639 # Simulator instruction rate (inst/s)
8host_op_rate 80877 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2630163340 # Simulator tick rate (ticks/s)
10host_mem_usage 384244 # Number of bytes of host memory used
11host_seconds 951.15 # Real time elapsed on the host
| 7host_inst_rate 57858 # Simulator instruction rate (inst/s)
8host_op_rate 74704 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2429415836 # Simulator tick rate (ticks/s)
10host_mem_usage 387132 # Number of bytes of host memory used
11host_seconds 1029.75 # Real time elapsed on the host
|
12sim_insts 59579009 # Number of instructions simulated
13sim_ops 76926775 # Number of ops (including micro ops) simulated
| 12sim_insts 59579009 # Number of instructions simulated
13sim_ops 76926775 # Number of ops (including micro ops) simulated
|
14system.physmem.bytes_read 129658608 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 9585736 # Number of bytes written to this memory
17system.physmem.num_reads 14980335 # Number of read requests responded to by this memory
18system.physmem.num_writes 856669 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s)
| 14system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
15system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
16system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
17system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
18system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
19system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
20system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s)
21system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s)
22system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s)
23system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s)
25system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s)
26system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory
27system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory
28system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory
29system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory
30system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory
31system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory
32system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory
33system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory
34system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory
35system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
36system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory
37system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
45system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory
46system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s)
55system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s)
56system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s)
58system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s)
59system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s)
|
33system.l2c.replacements 119797 # number of replacements
34system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
35system.l2c.total_refs 1834134 # Total number of references to valid blocks.
36system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
37system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
41system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
42system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
43system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
44system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
45system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
46system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
47system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
48system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
49system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
50system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
51system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits
52system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits
53system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits
54system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
55system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits
56system.l2c.Writeback_hits::total 635023 # number of Writeback hits
57system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
58system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
59system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
60system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
61system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits
62system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits
63system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits
64system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits
65system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
66system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits
67system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits
68system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits
69system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits
70system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
71system.l2c.overall_hits::cpu.data 484171 # number of overall hits
72system.l2c.overall_hits::total 1642008 # number of overall hits
73system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses
74system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses
75system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses
76system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses
77system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses
78system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses
79system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses
80system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
81system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
82system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses
83system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses
84system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses
85system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses
86system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses
87system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses
88system.l2c.demand_misses::total 177053 # number of demand (read+write) misses
89system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses
90system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses
91system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
92system.l2c.overall_misses::cpu.data 159472 # number of overall misses
93system.l2c.overall_misses::total 177053 # number of overall misses
94system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles
95system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles
96system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
97system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles
98system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
99system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles
100system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
101system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles
102system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
103system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles
104system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
105system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles
106system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles
107system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
108system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
109system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
110system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
111system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
112system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
113system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
114system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
115system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
116system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
117system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
118system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
119system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
120system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
121system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
122system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
123system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
124system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
125system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
126system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
127system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
128system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
129system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
130system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
131system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
132system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
133system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
134system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
135system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
136system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
137system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
138system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
139system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
140system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
141system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
| 64system.l2c.replacements 119797 # number of replacements
65system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use
66system.l2c.total_refs 1834134 # Total number of references to valid blocks.
67system.l2c.sampled_refs 150735 # Sample count of references to valid blocks.
68system.l2c.avg_refs 12.167937 # Average number of references to valid blocks.
69system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
70system.l2c.occ_blocks::writebacks 14260.921168 # Average occupied blocks per requestor
71system.l2c.occ_blocks::cpu.dtb.walker 79.122472 # Average occupied blocks per requestor
72system.l2c.occ_blocks::cpu.itb.walker 1.014068 # Average occupied blocks per requestor
73system.l2c.occ_blocks::cpu.inst 6176.146101 # Average occupied blocks per requestor
74system.l2c.occ_blocks::cpu.data 5505.607200 # Average occupied blocks per requestor
75system.l2c.occ_percent::writebacks 0.217604 # Average percentage of cache occupancy
76system.l2c.occ_percent::cpu.dtb.walker 0.001207 # Average percentage of cache occupancy
77system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
78system.l2c.occ_percent::cpu.inst 0.094241 # Average percentage of cache occupancy
79system.l2c.occ_percent::cpu.data 0.084009 # Average percentage of cache occupancy
80system.l2c.occ_percent::total 0.397077 # Average percentage of cache occupancy
81system.l2c.ReadReq_hits::cpu.dtb.walker 144170 # number of ReadReq hits
82system.l2c.ReadReq_hits::cpu.itb.walker 12492 # number of ReadReq hits
83system.l2c.ReadReq_hits::cpu.inst 1001175 # number of ReadReq hits
84system.l2c.ReadReq_hits::cpu.data 378296 # number of ReadReq hits
85system.l2c.ReadReq_hits::total 1536133 # number of ReadReq hits
86system.l2c.Writeback_hits::writebacks 635023 # number of Writeback hits
87system.l2c.Writeback_hits::total 635023 # number of Writeback hits
88system.l2c.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits
89system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits
90system.l2c.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
91system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
92system.l2c.ReadExReq_hits::cpu.data 105875 # number of ReadExReq hits
93system.l2c.ReadExReq_hits::total 105875 # number of ReadExReq hits
94system.l2c.demand_hits::cpu.dtb.walker 144170 # number of demand (read+write) hits
95system.l2c.demand_hits::cpu.itb.walker 12492 # number of demand (read+write) hits
96system.l2c.demand_hits::cpu.inst 1001175 # number of demand (read+write) hits
97system.l2c.demand_hits::cpu.data 484171 # number of demand (read+write) hits
98system.l2c.demand_hits::total 1642008 # number of demand (read+write) hits
99system.l2c.overall_hits::cpu.dtb.walker 144170 # number of overall hits
100system.l2c.overall_hits::cpu.itb.walker 12492 # number of overall hits
101system.l2c.overall_hits::cpu.inst 1001175 # number of overall hits
102system.l2c.overall_hits::cpu.data 484171 # number of overall hits
103system.l2c.overall_hits::total 1642008 # number of overall hits
104system.l2c.ReadReq_misses::cpu.dtb.walker 189 # number of ReadReq misses
105system.l2c.ReadReq_misses::cpu.itb.walker 14 # number of ReadReq misses
106system.l2c.ReadReq_misses::cpu.inst 17378 # number of ReadReq misses
107system.l2c.ReadReq_misses::cpu.data 19180 # number of ReadReq misses
108system.l2c.ReadReq_misses::total 36761 # number of ReadReq misses
109system.l2c.UpgradeReq_misses::cpu.data 3300 # number of UpgradeReq misses
110system.l2c.UpgradeReq_misses::total 3300 # number of UpgradeReq misses
111system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses
112system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses
113system.l2c.ReadExReq_misses::cpu.data 140292 # number of ReadExReq misses
114system.l2c.ReadExReq_misses::total 140292 # number of ReadExReq misses
115system.l2c.demand_misses::cpu.dtb.walker 189 # number of demand (read+write) misses
116system.l2c.demand_misses::cpu.itb.walker 14 # number of demand (read+write) misses
117system.l2c.demand_misses::cpu.inst 17378 # number of demand (read+write) misses
118system.l2c.demand_misses::cpu.data 159472 # number of demand (read+write) misses
119system.l2c.demand_misses::total 177053 # number of demand (read+write) misses
120system.l2c.overall_misses::cpu.dtb.walker 189 # number of overall misses
121system.l2c.overall_misses::cpu.itb.walker 14 # number of overall misses
122system.l2c.overall_misses::cpu.inst 17378 # number of overall misses
123system.l2c.overall_misses::cpu.data 159472 # number of overall misses
124system.l2c.overall_misses::total 177053 # number of overall misses
125system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500 # number of ReadReq miss cycles
126system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000 # number of ReadReq miss cycles
127system.l2c.ReadReq_miss_latency::cpu.inst 910079500 # number of ReadReq miss cycles
128system.l2c.ReadReq_miss_latency::cpu.data 1002096000 # number of ReadReq miss cycles
129system.l2c.ReadReq_miss_latency::total 1922778000 # number of ReadReq miss cycles
130system.l2c.UpgradeReq_miss_latency::cpu.data 996000 # number of UpgradeReq miss cycles
131system.l2c.UpgradeReq_miss_latency::total 996000 # number of UpgradeReq miss cycles
132system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000 # number of SCUpgradeReq miss cycles
133system.l2c.SCUpgradeReq_miss_latency::total 104000 # number of SCUpgradeReq miss cycles
134system.l2c.ReadExReq_miss_latency::cpu.data 7365557000 # number of ReadExReq miss cycles
135system.l2c.ReadExReq_miss_latency::total 7365557000 # number of ReadExReq miss cycles
136system.l2c.demand_miss_latency::cpu.dtb.walker 9850500 # number of demand (read+write) miss cycles
137system.l2c.demand_miss_latency::cpu.itb.walker 752000 # number of demand (read+write) miss cycles
138system.l2c.demand_miss_latency::cpu.inst 910079500 # number of demand (read+write) miss cycles
139system.l2c.demand_miss_latency::cpu.data 8367653000 # number of demand (read+write) miss cycles
140system.l2c.demand_miss_latency::total 9288335000 # number of demand (read+write) miss cycles
141system.l2c.overall_miss_latency::cpu.dtb.walker 9850500 # number of overall miss cycles
142system.l2c.overall_miss_latency::cpu.itb.walker 752000 # number of overall miss cycles
143system.l2c.overall_miss_latency::cpu.inst 910079500 # number of overall miss cycles
144system.l2c.overall_miss_latency::cpu.data 8367653000 # number of overall miss cycles
145system.l2c.overall_miss_latency::total 9288335000 # number of overall miss cycles
146system.l2c.ReadReq_accesses::cpu.dtb.walker 144359 # number of ReadReq accesses(hits+misses)
147system.l2c.ReadReq_accesses::cpu.itb.walker 12506 # number of ReadReq accesses(hits+misses)
148system.l2c.ReadReq_accesses::cpu.inst 1018553 # number of ReadReq accesses(hits+misses)
149system.l2c.ReadReq_accesses::cpu.data 397476 # number of ReadReq accesses(hits+misses)
150system.l2c.ReadReq_accesses::total 1572894 # number of ReadReq accesses(hits+misses)
151system.l2c.Writeback_accesses::writebacks 635023 # number of Writeback accesses(hits+misses)
152system.l2c.Writeback_accesses::total 635023 # number of Writeback accesses(hits+misses)
153system.l2c.UpgradeReq_accesses::cpu.data 3345 # number of UpgradeReq accesses(hits+misses)
154system.l2c.UpgradeReq_accesses::total 3345 # number of UpgradeReq accesses(hits+misses)
155system.l2c.SCUpgradeReq_accesses::cpu.data 13 # number of SCUpgradeReq accesses(hits+misses)
156system.l2c.SCUpgradeReq_accesses::total 13 # number of SCUpgradeReq accesses(hits+misses)
157system.l2c.ReadExReq_accesses::cpu.data 246167 # number of ReadExReq accesses(hits+misses)
158system.l2c.ReadExReq_accesses::total 246167 # number of ReadExReq accesses(hits+misses)
159system.l2c.demand_accesses::cpu.dtb.walker 144359 # number of demand (read+write) accesses
160system.l2c.demand_accesses::cpu.itb.walker 12506 # number of demand (read+write) accesses
161system.l2c.demand_accesses::cpu.inst 1018553 # number of demand (read+write) accesses
162system.l2c.demand_accesses::cpu.data 643643 # number of demand (read+write) accesses
163system.l2c.demand_accesses::total 1819061 # number of demand (read+write) accesses
164system.l2c.overall_accesses::cpu.dtb.walker 144359 # number of overall (read+write) accesses
165system.l2c.overall_accesses::cpu.itb.walker 12506 # number of overall (read+write) accesses
166system.l2c.overall_accesses::cpu.inst 1018553 # number of overall (read+write) accesses
167system.l2c.overall_accesses::cpu.data 643643 # number of overall (read+write) accesses
168system.l2c.overall_accesses::total 1819061 # number of overall (read+write) accesses
169system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 # miss rate for ReadReq accesses
170system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses
171system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses
172system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses
|
| 173system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses
|
142system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
| 174system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses
|
| 175system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses
|
143system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
| 176system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses
|
| 177system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses
|
144system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
| 178system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses
|
| 179system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses
|
145system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
146system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
147system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
148system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
| 180system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses
181system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses
182system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses
183system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses
|
| 184system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses
|
149system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
150system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
151system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
152system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
| 185system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses
186system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses
187system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses
188system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses
|
| 189system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses
|
153system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
154system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
155system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
156system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
| 190system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency
191system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency
192system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency
193system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency
|
| 194system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency
|
157system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
| 195system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency
|
| 196system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency
|
158system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
| 197system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency
|
| 198system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency
|
159system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
| 199system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency
|
| 200system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency
|
160system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
161system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
162system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
163system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
| 201system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
202system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
203system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
204system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
| 205system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency
|
164system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
165system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
166system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
167system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
| 206system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency
207system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency
208system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency
209system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency
|
| 210system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency
|
168system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
169system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
170system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
171system.l2c.blocked::no_targets 0 # number of cycles access was blocked
172system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
173system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
174system.l2c.fast_writes 0 # number of fast writes performed
175system.l2c.cache_copies 0 # number of cache copies performed
176system.l2c.writebacks::writebacks 102651 # number of writebacks
177system.l2c.writebacks::total 102651 # number of writebacks
178system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
179system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
180system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits
181system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
182system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
183system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
184system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits
185system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
186system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
187system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
188system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits
189system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits
190system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses
191system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses
192system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses
193system.l2c.ReadReq_mshr_misses::cpu.data 19094 # number of ReadReq MSHR misses
194system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses
195system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses
196system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses
197system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
198system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
199system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses
200system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses
201system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses
202system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses
203system.l2c.demand_mshr_misses::cpu.inst 17364 # number of demand (read+write) MSHR misses
204system.l2c.demand_mshr_misses::cpu.data 159386 # number of demand (read+write) MSHR misses
205system.l2c.demand_mshr_misses::total 176952 # number of demand (read+write) MSHR misses
206system.l2c.overall_mshr_misses::cpu.dtb.walker 188 # number of overall MSHR misses
207system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses
208system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
209system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
210system.l2c.overall_mshr_misses::total 176952 # number of overall MSHR misses
211system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 7532000 # number of ReadReq MSHR miss cycles
212system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles
213system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles
214system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles
215system.l2c.ReadReq_mshr_miss_latency::total 1471125000 # number of ReadReq MSHR miss cycles
216system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles
217system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles
218system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles
219system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles
220system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles
221system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles
222system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles
223system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles
224system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles
225system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles
226system.l2c.demand_mshr_miss_latency::total 7093247500 # number of demand (read+write) MSHR miss cycles
227system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
228system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles
229system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles
230system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles
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232system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
233system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles
234system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
235system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
236system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
237system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
238system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
239system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
240system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
241system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
242system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
243system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
| 211system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
212system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
213system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
214system.l2c.blocked::no_targets 0 # number of cycles access was blocked
215system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
216system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
217system.l2c.fast_writes 0 # number of fast writes performed
218system.l2c.cache_copies 0 # number of cache copies performed
219system.l2c.writebacks::writebacks 102651 # number of writebacks
220system.l2c.writebacks::total 102651 # number of writebacks
221system.l2c.ReadReq_mshr_hits::cpu.dtb.walker 1 # number of ReadReq MSHR hits
222system.l2c.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits
223system.l2c.ReadReq_mshr_hits::cpu.data 86 # number of ReadReq MSHR hits
224system.l2c.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
225system.l2c.demand_mshr_hits::cpu.dtb.walker 1 # number of demand (read+write) MSHR hits
226system.l2c.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits
227system.l2c.demand_mshr_hits::cpu.data 86 # number of demand (read+write) MSHR hits
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229system.l2c.overall_mshr_hits::cpu.dtb.walker 1 # number of overall MSHR hits
230system.l2c.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
231system.l2c.overall_mshr_hits::cpu.data 86 # number of overall MSHR hits
232system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits
233system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 188 # number of ReadReq MSHR misses
234system.l2c.ReadReq_mshr_misses::cpu.itb.walker 14 # number of ReadReq MSHR misses
235system.l2c.ReadReq_mshr_misses::cpu.inst 17364 # number of ReadReq MSHR misses
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237system.l2c.ReadReq_mshr_misses::total 36660 # number of ReadReq MSHR misses
238system.l2c.UpgradeReq_mshr_misses::cpu.data 3300 # number of UpgradeReq MSHR misses
239system.l2c.UpgradeReq_mshr_misses::total 3300 # number of UpgradeReq MSHR misses
240system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses
241system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses
242system.l2c.ReadExReq_mshr_misses::cpu.data 140292 # number of ReadExReq MSHR misses
243system.l2c.ReadExReq_mshr_misses::total 140292 # number of ReadExReq MSHR misses
244system.l2c.demand_mshr_misses::cpu.dtb.walker 188 # number of demand (read+write) MSHR misses
245system.l2c.demand_mshr_misses::cpu.itb.walker 14 # number of demand (read+write) MSHR misses
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250system.l2c.overall_mshr_misses::cpu.itb.walker 14 # number of overall MSHR misses
251system.l2c.overall_mshr_misses::cpu.inst 17364 # number of overall MSHR misses
252system.l2c.overall_mshr_misses::cpu.data 159386 # number of overall MSHR misses
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255system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 584000 # number of ReadReq MSHR miss cycles
256system.l2c.ReadReq_mshr_miss_latency::cpu.inst 697406000 # number of ReadReq MSHR miss cycles
257system.l2c.ReadReq_mshr_miss_latency::cpu.data 765603000 # number of ReadReq MSHR miss cycles
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259system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 132880000 # number of UpgradeReq MSHR miss cycles
260system.l2c.UpgradeReq_mshr_miss_latency::total 132880000 # number of UpgradeReq MSHR miss cycles
261system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles
262system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles
263system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5622122500 # number of ReadExReq MSHR miss cycles
264system.l2c.ReadExReq_mshr_miss_latency::total 5622122500 # number of ReadExReq MSHR miss cycles
265system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 7532000 # number of demand (read+write) MSHR miss cycles
266system.l2c.demand_mshr_miss_latency::cpu.itb.walker 584000 # number of demand (read+write) MSHR miss cycles
267system.l2c.demand_mshr_miss_latency::cpu.inst 697406000 # number of demand (read+write) MSHR miss cycles
268system.l2c.demand_mshr_miss_latency::cpu.data 6387725500 # number of demand (read+write) MSHR miss cycles
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270system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 7532000 # number of overall MSHR miss cycles
271system.l2c.overall_mshr_miss_latency::cpu.itb.walker 584000 # number of overall MSHR miss cycles
272system.l2c.overall_mshr_miss_latency::cpu.inst 697406000 # number of overall MSHR miss cycles
273system.l2c.overall_mshr_miss_latency::cpu.data 6387725500 # number of overall MSHR miss cycles
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275system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5427000 # number of ReadReq MSHR uncacheable cycles
276system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131758586500 # number of ReadReq MSHR uncacheable cycles
277system.l2c.ReadReq_mshr_uncacheable_latency::total 131764013500 # number of ReadReq MSHR uncacheable cycles
278system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32346095899 # number of WriteReq MSHR uncacheable cycles
279system.l2c.WriteReq_mshr_uncacheable_latency::total 32346095899 # number of WriteReq MSHR uncacheable cycles
280system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5427000 # number of overall MSHR uncacheable cycles
281system.l2c.overall_mshr_uncacheable_latency::cpu.data 164104682399 # number of overall MSHR uncacheable cycles
282system.l2c.overall_mshr_uncacheable_latency::total 164110109399 # number of overall MSHR uncacheable cycles
283system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for ReadReq accesses
284system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses
285system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses
286system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses
|
| 287system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses
|
244system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
| 288system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses
|
| 289system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses
|
245system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
| 290system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
| 291system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses
|
246system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
| 292system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses
|
| 293system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses
|
247system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
248system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
249system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
250system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
| 294system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses
295system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses
296system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses
297system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses
|
| 298system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses
|
251system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
252system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
253system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
254system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
| 299system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses
300system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses
301system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses
302system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses
|
| 303system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses
|
255system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
256system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
257system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
258system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
| 304system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency
305system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency
306system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency
307system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency
|
| 308system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency
|
259system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
| 309system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency
|
| 310system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency
|
260system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
| 311system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
|
| 312system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
|
261system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
| 313system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency
|
| 314system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency
|
262system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
263system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
264system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
265system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
| 315system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
316system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
317system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
318system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
| 319system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
266system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
267system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
268system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
269system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
| 320system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency
321system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency
322system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency
323system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency
|
| 324system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency
|
270system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
271system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
| 325system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
326system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
| 327system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
272system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
| 328system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
| 329system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
273system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
274system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
| 330system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
331system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
| 332system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
275system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
276system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
277system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
278system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
279system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
280system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
281system.cf0.dma_write_txs 0 # Number of DMA write transactions.
282system.cpu.dtb.inst_hits 0 # ITB inst hits
283system.cpu.dtb.inst_misses 0 # ITB inst misses
284system.cpu.dtb.read_hits 52103903 # DTB read hits
285system.cpu.dtb.read_misses 93079 # DTB read misses
286system.cpu.dtb.write_hits 11946241 # DTB write hits
287system.cpu.dtb.write_misses 25022 # DTB write misses
288system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
289system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
290system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
291system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
292system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB
293system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
294system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
295system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
296system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
297system.cpu.dtb.read_accesses 52196982 # DTB read accesses
298system.cpu.dtb.write_accesses 11971263 # DTB write accesses
299system.cpu.dtb.inst_accesses 0 # ITB inst accesses
300system.cpu.dtb.hits 64050144 # DTB hits
301system.cpu.dtb.misses 118101 # DTB misses
302system.cpu.dtb.accesses 64168245 # DTB accesses
303system.cpu.itb.inst_hits 13717584 # ITB inst hits
304system.cpu.itb.inst_misses 12272 # ITB inst misses
305system.cpu.itb.read_hits 0 # DTB read hits
306system.cpu.itb.read_misses 0 # DTB read misses
307system.cpu.itb.write_hits 0 # DTB write hits
308system.cpu.itb.write_misses 0 # DTB write misses
309system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
310system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
311system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
312system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
313system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB
314system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
315system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
316system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
317system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
318system.cpu.itb.read_accesses 0 # DTB read accesses
319system.cpu.itb.write_accesses 0 # DTB write accesses
320system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
321system.cpu.itb.hits 13717584 # DTB hits
322system.cpu.itb.misses 12272 # DTB misses
323system.cpu.itb.accesses 13729856 # DTB accesses
324system.cpu.numCycles 411352060 # number of cpu cycles simulated
325system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
326system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
327system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
328system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
329system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
330system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
331system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
332system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
333system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
334system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
335system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
336system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
337system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
338system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
339system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
340system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
341system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
342system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
343system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
344system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
345system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
346system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
347system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
348system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
349system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
350system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
351system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
352system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
353system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
354system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
355system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
356system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
357system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
358system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
359system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
360system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
361system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
362system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
363system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
364system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
365system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
366system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
367system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
368system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
369system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
370system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
371system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
372system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
373system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
374system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
375system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
376system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
377system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
378system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
379system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
380system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
381system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
382system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
383system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
384system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
385system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
386system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
387system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
388system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
389system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
390system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
391system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
392system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
393system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
394system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
395system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
396system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
397system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
398system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
399system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
400system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
401system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
402system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
403system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
404system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
405system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
406system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
407system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
408system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
409system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
410system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
411system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
412system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
413system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
414system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
415system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
416system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
417system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
418system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
419system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
420system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
421system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
422system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
423system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
424system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
425system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
426system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
427system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
428system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
429system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
430system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
431system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
432system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
433system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
434system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
435system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
438system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
439system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
440system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
441system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
442system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
443system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
444system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
445system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
446system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
447system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
448system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
449system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
450system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
451system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
452system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
453system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
454system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
455system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
456system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
457system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
458system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
459system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
460system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
461system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
462system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
463system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
464system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
465system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
466system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
467system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
468system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
469system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
476system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
477system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
478system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
479system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
480system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
481system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
482system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
483system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
484system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
485system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
486system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
487system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
488system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
489system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
490system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
491system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
492system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
493system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
494system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
495system.cpu.iq.rate 0.307159 # Inst issue rate
496system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
497system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
498system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
499system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
500system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
501system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
502system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
503system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
504system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
505system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
506system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
507system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
508system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
509system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
510system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
511system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
512system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
513system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
514system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
515system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
516system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
517system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
518system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
519system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
520system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
521system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
522system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
523system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
524system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
525system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
526system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
527system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
528system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
529system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
530system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
531system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
532system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
533system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
534system.cpu.iew.exec_swp 0 # number of swp insts executed
535system.cpu.iew.exec_nop 261908 # number of nop insts executed
536system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
537system.cpu.iew.exec_branches 11601340 # Number of branches executed
538system.cpu.iew.exec_stores 12455688 # Number of stores executed
539system.cpu.iew.exec_rate 0.299278 # Inst execution rate
540system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
541system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
542system.cpu.iew.wb_producers 47546734 # num instructions producing a value
543system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
544system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
545system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
546system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
547system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
548system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
549system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
550system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
551system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
552system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
553system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
554system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
555system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
556system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
557system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
558system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
559system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
560system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
561system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
562system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
563system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
564system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
565system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
566system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
567system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
568system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
569system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
570system.cpu.commit.committedInsts 59729390 # Number of instructions committed
571system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
572system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
573system.cpu.commit.refs 27513639 # Number of memory references committed
574system.cpu.commit.loads 15715354 # Number of loads committed
575system.cpu.commit.membars 413068 # Number of memory barriers committed
576system.cpu.commit.branches 9904424 # Number of branches committed
577system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
578system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
579system.cpu.commit.function_calls 995976 # Number of function calls committed.
580system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
581system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
582system.cpu.rob.rob_reads 245922084 # The number of ROB reads
583system.cpu.rob.rob_writes 212744706 # The number of ROB writes
584system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
585system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
586system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
587system.cpu.committedInsts 59579009 # Number of Instructions Simulated
588system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
589system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
590system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
591system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
592system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
593system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
594system.cpu.int_regfile_reads 558200782 # number of integer regfile reads
595system.cpu.int_regfile_writes 89400906 # number of integer regfile writes
596system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
597system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
598system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
599system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
600system.cpu.icache.replacements 1019271 # number of replacements
601system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
602system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
603system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
604system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
605system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
606system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
607system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
608system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
609system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
610system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
611system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
612system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
613system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
614system.cpu.icache.overall_hits::total 12598089 # number of overall hits
615system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
616system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
617system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
618system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
619system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
620system.cpu.icache.overall_misses::total 1111711 # number of overall misses
621system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
622system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
623system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
624system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
625system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
626system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
627system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
628system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
629system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
630system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
631system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
632system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
633system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
| 333system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
334system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
335system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
336system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
337system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
338system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
339system.cf0.dma_write_txs 0 # Number of DMA write transactions.
340system.cpu.dtb.inst_hits 0 # ITB inst hits
341system.cpu.dtb.inst_misses 0 # ITB inst misses
342system.cpu.dtb.read_hits 52103903 # DTB read hits
343system.cpu.dtb.read_misses 93079 # DTB read misses
344system.cpu.dtb.write_hits 11946241 # DTB write hits
345system.cpu.dtb.write_misses 25022 # DTB write misses
346system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
348system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
349system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
350system.cpu.dtb.flush_entries 4532 # Number of entries that have been flushed from TLB
351system.cpu.dtb.align_faults 5562 # Number of TLB faults due to alignment restrictions
352system.cpu.dtb.prefetch_faults 707 # Number of TLB faults due to prefetch
353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
354system.cpu.dtb.perms_faults 2799 # Number of TLB faults due to permissions restrictions
355system.cpu.dtb.read_accesses 52196982 # DTB read accesses
356system.cpu.dtb.write_accesses 11971263 # DTB write accesses
357system.cpu.dtb.inst_accesses 0 # ITB inst accesses
358system.cpu.dtb.hits 64050144 # DTB hits
359system.cpu.dtb.misses 118101 # DTB misses
360system.cpu.dtb.accesses 64168245 # DTB accesses
361system.cpu.itb.inst_hits 13717584 # ITB inst hits
362system.cpu.itb.inst_misses 12272 # ITB inst misses
363system.cpu.itb.read_hits 0 # DTB read hits
364system.cpu.itb.read_misses 0 # DTB read misses
365system.cpu.itb.write_hits 0 # DTB write hits
366system.cpu.itb.write_misses 0 # DTB write misses
367system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
368system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
369system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
370system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
371system.cpu.itb.flush_entries 2655 # Number of entries that have been flushed from TLB
372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
373system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
374system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
375system.cpu.itb.perms_faults 6863 # Number of TLB faults due to permissions restrictions
376system.cpu.itb.read_accesses 0 # DTB read accesses
377system.cpu.itb.write_accesses 0 # DTB write accesses
378system.cpu.itb.inst_accesses 13729856 # ITB inst accesses
379system.cpu.itb.hits 13717584 # DTB hits
380system.cpu.itb.misses 12272 # DTB misses
381system.cpu.itb.accesses 13729856 # DTB accesses
382system.cpu.numCycles 411352060 # number of cpu cycles simulated
383system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
384system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
385system.cpu.BPredUnit.lookups 15654738 # Number of BP lookups
386system.cpu.BPredUnit.condPredicted 12362397 # Number of conditional branches predicted
387system.cpu.BPredUnit.condIncorrect 932839 # Number of conditional branches incorrect
388system.cpu.BPredUnit.BTBLookups 10530768 # Number of BTB lookups
389system.cpu.BPredUnit.BTBHits 8288874 # Number of BTB hits
390system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
391system.cpu.BPredUnit.usedRAS 1329017 # Number of times the RAS was used to get a target.
392system.cpu.BPredUnit.RASInCorrect 195537 # Number of incorrect RAS predictions.
393system.cpu.fetch.icacheStallCycles 33116930 # Number of cycles fetch is stalled on an Icache miss
394system.cpu.fetch.Insts 103031700 # Number of instructions fetch has processed
395system.cpu.fetch.Branches 15654738 # Number of branches that fetch encountered
396system.cpu.fetch.predictedBranches 9617891 # Number of branches that fetch has predicted taken
397system.cpu.fetch.Cycles 22620194 # Number of cycles fetch has run and was not squashing or blocked
398system.cpu.fetch.SquashCycles 6706106 # Number of cycles fetch has spent squashing
399system.cpu.fetch.TlbCycles 163882 # Number of cycles fetch has spent waiting for tlb
400system.cpu.fetch.BlockedCycles 89861042 # Number of cycles fetch has spent blocked
401system.cpu.fetch.MiscStallCycles 2823 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
402system.cpu.fetch.PendingTrapStallCycles 147160 # Number of stall cycles due to pending traps
403system.cpu.fetch.PendingQuiesceStallCycles 218224 # Number of stall cycles due to pending quiesce instructions
404system.cpu.fetch.IcacheWaitRetryStallCycles 462 # Number of stall cycles due to full MSHR
405system.cpu.fetch.CacheLines 13709942 # Number of cache lines fetched
406system.cpu.fetch.IcacheSquashes 998560 # Number of outstanding Icache misses that were squashed
407system.cpu.fetch.ItlbSquashes 6868 # Number of outstanding ITLB misses that were squashed
408system.cpu.fetch.rateDist::samples 150746244 # Number of instructions fetched each cycle (Total)
409system.cpu.fetch.rateDist::mean 0.848897 # Number of instructions fetched each cycle (Total)
410system.cpu.fetch.rateDist::stdev 2.234280 # Number of instructions fetched each cycle (Total)
411system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
412system.cpu.fetch.rateDist::0 128142810 85.01% 85.01% # Number of instructions fetched each cycle (Total)
413system.cpu.fetch.rateDist::1 1478319 0.98% 85.99% # Number of instructions fetched each cycle (Total)
414system.cpu.fetch.rateDist::2 1855018 1.23% 87.22% # Number of instructions fetched each cycle (Total)
415system.cpu.fetch.rateDist::3 2695901 1.79% 89.01% # Number of instructions fetched each cycle (Total)
416system.cpu.fetch.rateDist::4 1893540 1.26% 90.26% # Number of instructions fetched each cycle (Total)
417system.cpu.fetch.rateDist::5 1191101 0.79% 91.05% # Number of instructions fetched each cycle (Total)
418system.cpu.fetch.rateDist::6 2951659 1.96% 93.01% # Number of instructions fetched each cycle (Total)
419system.cpu.fetch.rateDist::7 850848 0.56% 93.57% # Number of instructions fetched each cycle (Total)
420system.cpu.fetch.rateDist::8 9687048 6.43% 100.00% # Number of instructions fetched each cycle (Total)
421system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
422system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
423system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
424system.cpu.fetch.rateDist::total 150746244 # Number of instructions fetched each cycle (Total)
425system.cpu.fetch.branchRate 0.038057 # Number of branch fetches per cycle
426system.cpu.fetch.rate 0.250471 # Number of inst fetches per cycle
427system.cpu.decode.IdleCycles 35228906 # Number of cycles decode is idle
428system.cpu.decode.BlockedCycles 89710063 # Number of cycles decode is blocked
429system.cpu.decode.RunCycles 20347806 # Number of cycles decode is running
430system.cpu.decode.UnblockCycles 1026685 # Number of cycles decode is unblocking
431system.cpu.decode.SquashCycles 4432784 # Number of cycles decode is squashing
432system.cpu.decode.BranchResolved 2275641 # Number of times decode resolved a branch
433system.cpu.decode.BranchMispred 186729 # Number of times decode detected a branch misprediction
434system.cpu.decode.DecodedInsts 120042439 # Number of instructions handled by decode
435system.cpu.decode.SquashedInsts 604390 # Number of squashed instructions handled by decode
436system.cpu.rename.SquashCycles 4432784 # Number of cycles rename is squashing
437system.cpu.rename.IdleCycles 37305734 # Number of cycles rename is idle
438system.cpu.rename.BlockCycles 37165628 # Number of cycles rename is blocking
439system.cpu.rename.serializeStallCycles 46502465 # count of cycles rename stalled for serializing inst
440system.cpu.rename.RunCycles 19251695 # Number of cycles rename is running
441system.cpu.rename.UnblockCycles 6087938 # Number of cycles rename is unblocking
442system.cpu.rename.RenamedInsts 112539597 # Number of instructions processed by rename
443system.cpu.rename.ROBFullEvents 3873 # Number of times rename has blocked due to ROB full
444system.cpu.rename.IQFullEvents 1013212 # Number of times rename has blocked due to IQ full
445system.cpu.rename.LSQFullEvents 4109157 # Number of times rename has blocked due to LSQ full
446system.cpu.rename.FullRegisterEvents 45575 # Number of times there has been no free registers
447system.cpu.rename.RenamedOperands 117156815 # Number of destination operands rename has renamed
448system.cpu.rename.RenameLookups 517555842 # Number of register rename lookups that rename has made
449system.cpu.rename.int_rename_lookups 517460811 # Number of integer rename lookups
450system.cpu.rename.fp_rename_lookups 95031 # Number of floating rename lookups
451system.cpu.rename.CommittedMaps 77687687 # Number of HB maps that are committed
452system.cpu.rename.UndoneMaps 39469127 # Number of HB maps that are undone due to squashing
453system.cpu.rename.serializingInsts 939790 # count of serializing insts renamed
454system.cpu.rename.tempSerializingInsts 835958 # count of temporary serializing insts renamed
455system.cpu.rename.skidInsts 12443241 # count of insts added to the skid buffer
456system.cpu.memDep0.insertedLoads 21685850 # Number of loads inserted to the mem dependence unit.
457system.cpu.memDep0.insertedStores 14072237 # Number of stores inserted to the mem dependence unit.
458system.cpu.memDep0.conflictingLoads 1938675 # Number of conflicting loads.
459system.cpu.memDep0.conflictingStores 2482763 # Number of conflicting stores.
460system.cpu.iq.iqInstsAdded 102391550 # Number of instructions added to the IQ (excludes non-spec)
461system.cpu.iq.iqNonSpecInstsAdded 1619583 # Number of non-speculative instructions added to the IQ
462system.cpu.iq.iqInstsIssued 126350622 # Number of instructions issued
463system.cpu.iq.iqSquashedInstsIssued 234593 # Number of squashed instructions issued
464system.cpu.iq.iqSquashedInstsExamined 26254924 # Number of squashed instructions iterated over during squash; mainly for profiling
465system.cpu.iq.iqSquashedOperandsExamined 71509700 # Number of squashed operands that are examined and possibly removed from graph
466system.cpu.iq.iqSquashedNonSpecRemoved 332277 # Number of squashed non-spec instructions that were removed
467system.cpu.iq.issued_per_cycle::samples 150746244 # Number of insts issued each cycle
468system.cpu.iq.issued_per_cycle::mean 0.838168 # Number of insts issued each cycle
469system.cpu.iq.issued_per_cycle::stdev 1.542455 # Number of insts issued each cycle
470system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
471system.cpu.iq.issued_per_cycle::0 105470655 69.97% 69.97% # Number of insts issued each cycle
472system.cpu.iq.issued_per_cycle::1 14086510 9.34% 79.31% # Number of insts issued each cycle
473system.cpu.iq.issued_per_cycle::2 7371222 4.89% 84.20% # Number of insts issued each cycle
474system.cpu.iq.issued_per_cycle::3 5923402 3.93% 88.13% # Number of insts issued each cycle
475system.cpu.iq.issued_per_cycle::4 12762751 8.47% 96.60% # Number of insts issued each cycle
476system.cpu.iq.issued_per_cycle::5 2810704 1.86% 98.46% # Number of insts issued each cycle
477system.cpu.iq.issued_per_cycle::6 1735902 1.15% 99.61% # Number of insts issued each cycle
478system.cpu.iq.issued_per_cycle::7 449258 0.30% 99.91% # Number of insts issued each cycle
479system.cpu.iq.issued_per_cycle::8 135840 0.09% 100.00% # Number of insts issued each cycle
480system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
481system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
482system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
483system.cpu.iq.issued_per_cycle::total 150746244 # Number of insts issued each cycle
484system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
485system.cpu.iq.fu_full::IntAlu 61043 0.69% 0.69% # attempts to use FU when none available
486system.cpu.iq.fu_full::IntMult 4 0.00% 0.69% # attempts to use FU when none available
487system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
488system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
489system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
490system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
491system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
492system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
493system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
495system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
496system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
497system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
498system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
499system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
500system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
501system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
502system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
503system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
504system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
505system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
506system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
507system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
508system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
509system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
510system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
511system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
512system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
513system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
514system.cpu.iq.fu_full::MemRead 8421186 94.66% 95.34% # attempts to use FU when none available
515system.cpu.iq.fu_full::MemWrite 414230 4.66% 100.00% # attempts to use FU when none available
516system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
517system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
518system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued
519system.cpu.iq.FU_type_0::IntAlu 59762768 47.30% 47.38% # Type of FU issued
520system.cpu.iq.FU_type_0::IntMult 95812 0.08% 47.46% # Type of FU issued
521system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.46% # Type of FU issued
522system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.46% # Type of FU issued
523system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.46% # Type of FU issued
524system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.46% # Type of FU issued
525system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.46% # Type of FU issued
526system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.46% # Type of FU issued
527system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.46% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.46% # Type of FU issued
529system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.46% # Type of FU issued
530system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.46% # Type of FU issued
531system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.46% # Type of FU issued
532system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.46% # Type of FU issued
533system.cpu.iq.FU_type_0::SimdMisc 38 0.00% 47.46% # Type of FU issued
534system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.46% # Type of FU issued
535system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.46% # Type of FU issued
536system.cpu.iq.FU_type_0::SimdShift 45 0.00% 47.46% # Type of FU issued
537system.cpu.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.46% # Type of FU issued
538system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.46% # Type of FU issued
539system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.46% # Type of FU issued
540system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.46% # Type of FU issued
541system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.46% # Type of FU issued
542system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.46% # Type of FU issued
543system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.46% # Type of FU issued
544system.cpu.iq.FU_type_0::SimdFloatMisc 2279 0.00% 47.46% # Type of FU issued
545system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued
546system.cpu.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.46% # Type of FU issued
547system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued
548system.cpu.iq.FU_type_0::MemRead 53776494 42.56% 90.02% # Type of FU issued
549system.cpu.iq.FU_type_0::MemWrite 12606638 9.98% 100.00% # Type of FU issued
550system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
551system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
552system.cpu.iq.FU_type_0::total 126350622 # Type of FU issued
553system.cpu.iq.rate 0.307159 # Inst issue rate
554system.cpu.iq.fu_busy_cnt 8896463 # FU busy when requested
555system.cpu.iq.fu_busy_rate 0.070411 # FU busy rate (busy events/executed inst)
556system.cpu.iq.int_inst_queue_reads 412671946 # Number of integer instruction queue reads
557system.cpu.iq.int_inst_queue_writes 130285978 # Number of integer instruction queue writes
558system.cpu.iq.int_inst_queue_wakeup_accesses 87040433 # Number of integer instruction queue wakeup accesses
559system.cpu.iq.fp_inst_queue_reads 24078 # Number of floating instruction queue reads
560system.cpu.iq.fp_inst_queue_writes 13182 # Number of floating instruction queue writes
561system.cpu.iq.fp_inst_queue_wakeup_accesses 10434 # Number of floating instruction queue wakeup accesses
562system.cpu.iq.int_alu_accesses 135127716 # Number of integer alu accesses
563system.cpu.iq.fp_alu_accesses 12839 # Number of floating point alu accesses
564system.cpu.iew.lsq.thread0.forwLoads 636069 # Number of loads that had data forwarded from stores
565system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
566system.cpu.iew.lsq.thread0.squashedLoads 5970496 # Number of loads squashed
567system.cpu.iew.lsq.thread0.ignoredResponses 11101 # Number of memory responses ignored because the instruction is squashed
568system.cpu.iew.lsq.thread0.memOrderViolation 34253 # Number of memory ordering violations
569system.cpu.iew.lsq.thread0.squashedStores 2273952 # Number of stores squashed
570system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
571system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
572system.cpu.iew.lsq.thread0.rescheduledLoads 34114355 # Number of loads that were rescheduled
573system.cpu.iew.lsq.thread0.cacheBlocked 1152098 # Number of times an access to memory failed due to the cache being blocked
574system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
575system.cpu.iew.iewSquashCycles 4432784 # Number of cycles IEW is squashing
576system.cpu.iew.iewBlockCycles 28604721 # Number of cycles IEW is blocking
577system.cpu.iew.iewUnblockCycles 436722 # Number of cycles IEW is unblocking
578system.cpu.iew.iewDispatchedInsts 104273041 # Number of instructions dispatched to IQ
579system.cpu.iew.iewDispSquashedInsts 335924 # Number of squashed instructions skipped by dispatch
580system.cpu.iew.iewDispLoadInsts 21685850 # Number of dispatched load instructions
581system.cpu.iew.iewDispStoreInsts 14072237 # Number of dispatched store instructions
582system.cpu.iew.iewDispNonSpecInsts 992808 # Number of dispatched non-speculative instructions
583system.cpu.iew.iewIQFullEvents 95700 # Number of times the IQ has become full, causing a stall
584system.cpu.iew.iewLSQFullEvents 11591 # Number of times the LSQ has become full, causing a stall
585system.cpu.iew.memOrderViolationEvents 34253 # Number of memory order violations
586system.cpu.iew.predictedTakenIncorrect 552378 # Number of branches that were predicted taken incorrectly
587system.cpu.iew.predictedNotTakenIncorrect 346914 # Number of branches that were predicted not taken incorrectly
588system.cpu.iew.branchMispredicts 899292 # Number of branch mispredicts detected at execute
589system.cpu.iew.iewExecutedInsts 123108789 # Number of executed instructions
590system.cpu.iew.iewExecLoadInsts 52799372 # Number of load instructions executed
591system.cpu.iew.iewExecSquashedInsts 3241833 # Number of squashed instructions skipped in execute
592system.cpu.iew.exec_swp 0 # number of swp insts executed
593system.cpu.iew.exec_nop 261908 # number of nop insts executed
594system.cpu.iew.exec_refs 65255060 # number of memory reference insts executed
595system.cpu.iew.exec_branches 11601340 # Number of branches executed
596system.cpu.iew.exec_stores 12455688 # Number of stores executed
597system.cpu.iew.exec_rate 0.299278 # Inst execution rate
598system.cpu.iew.wb_sent 121555618 # cumulative count of insts sent to commit
599system.cpu.iew.wb_count 87050867 # cumulative count of insts written-back
600system.cpu.iew.wb_producers 47546734 # num instructions producing a value
601system.cpu.iew.wb_consumers 88572059 # num instructions consuming a value
602system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
603system.cpu.iew.wb_rate 0.211621 # insts written-back per cycle
604system.cpu.iew.wb_fanout 0.536814 # average fanout of values written-back
605system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
606system.cpu.commit.commitCommittedInsts 59729390 # The number of committed instructions
607system.cpu.commit.commitCommittedOps 77077156 # The number of committed instructions
608system.cpu.commit.commitSquashedInsts 27015439 # The number of squashed insts skipped by commit
609system.cpu.commit.commitNonSpecStalls 1287306 # The number of times commit has been forced to stall to communicate backwards
610system.cpu.commit.branchMispredicts 793496 # The number of times a branch was mispredicted
611system.cpu.commit.committed_per_cycle::samples 146395876 # Number of insts commited each cycle
612system.cpu.commit.committed_per_cycle::mean 0.526498 # Number of insts commited each cycle
613system.cpu.commit.committed_per_cycle::stdev 1.504904 # Number of insts commited each cycle
614system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
615system.cpu.commit.committed_per_cycle::0 118626341 81.03% 81.03% # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::1 13714527 9.37% 90.40% # Number of insts commited each cycle
617system.cpu.commit.committed_per_cycle::2 3991808 2.73% 93.13% # Number of insts commited each cycle
618system.cpu.commit.committed_per_cycle::3 2249419 1.54% 94.66% # Number of insts commited each cycle
619system.cpu.commit.committed_per_cycle::4 1746576 1.19% 95.86% # Number of insts commited each cycle
620system.cpu.commit.committed_per_cycle::5 1042045 0.71% 96.57% # Number of insts commited each cycle
621system.cpu.commit.committed_per_cycle::6 1550885 1.06% 97.63% # Number of insts commited each cycle
622system.cpu.commit.committed_per_cycle::7 665283 0.45% 98.08% # Number of insts commited each cycle
623system.cpu.commit.committed_per_cycle::8 2808992 1.92% 100.00% # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
626system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::total 146395876 # Number of insts commited each cycle
628system.cpu.commit.committedInsts 59729390 # Number of instructions committed
629system.cpu.commit.committedOps 77077156 # Number of ops (including micro ops) committed
630system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
631system.cpu.commit.refs 27513639 # Number of memory references committed
632system.cpu.commit.loads 15715354 # Number of loads committed
633system.cpu.commit.membars 413068 # Number of memory barriers committed
634system.cpu.commit.branches 9904424 # Number of branches committed
635system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
636system.cpu.commit.int_insts 68617835 # Number of committed integer instructions.
637system.cpu.commit.function_calls 995976 # Number of function calls committed.
638system.cpu.commit.bw_lim_events 2808992 # number cycles where commit BW limit reached
639system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
640system.cpu.rob.rob_reads 245922084 # The number of ROB reads
641system.cpu.rob.rob_writes 212744706 # The number of ROB writes
642system.cpu.timesIdled 1895448 # Number of times that the entire CPU went into an idle state and unscheduled itself
643system.cpu.idleCycles 260605816 # Total number of cycles that the CPU has spent unscheduled due to idling
644system.cpu.quiesceCycles 4591931267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
645system.cpu.committedInsts 59579009 # Number of Instructions Simulated
646system.cpu.committedOps 76926775 # Number of Ops (including micro ops) Simulated
647system.cpu.committedInsts_total 59579009 # Number of Instructions Simulated
648system.cpu.cpi 6.904312 # CPI: Cycles Per Instruction
649system.cpu.cpi_total 6.904312 # CPI: Total CPI of All Threads
650system.cpu.ipc 0.144837 # IPC: Instructions Per Cycle
651system.cpu.ipc_total 0.144837 # IPC: Total IPC of All Threads
652system.cpu.int_regfile_reads 558200782 # number of integer regfile reads
653system.cpu.int_regfile_writes 89400906 # number of integer regfile writes
654system.cpu.fp_regfile_reads 8900 # number of floating regfile reads
655system.cpu.fp_regfile_writes 2982 # number of floating regfile writes
656system.cpu.misc_regfile_reads 135543435 # number of misc regfile reads
657system.cpu.misc_regfile_writes 912729 # number of misc regfile writes
658system.cpu.icache.replacements 1019271 # number of replacements
659system.cpu.icache.tagsinuse 511.444719 # Cycle average of tags in use
660system.cpu.icache.total_refs 12598089 # Total number of references to valid blocks.
661system.cpu.icache.sampled_refs 1019783 # Sample count of references to valid blocks.
662system.cpu.icache.avg_refs 12.353696 # Average number of references to valid blocks.
663system.cpu.icache.warmup_cycle 6290137000 # Cycle when the warmup percentage was hit.
664system.cpu.icache.occ_blocks::cpu.inst 511.444719 # Average occupied blocks per requestor
665system.cpu.icache.occ_percent::cpu.inst 0.998915 # Average percentage of cache occupancy
666system.cpu.icache.occ_percent::total 0.998915 # Average percentage of cache occupancy
667system.cpu.icache.ReadReq_hits::cpu.inst 12598089 # number of ReadReq hits
668system.cpu.icache.ReadReq_hits::total 12598089 # number of ReadReq hits
669system.cpu.icache.demand_hits::cpu.inst 12598089 # number of demand (read+write) hits
670system.cpu.icache.demand_hits::total 12598089 # number of demand (read+write) hits
671system.cpu.icache.overall_hits::cpu.inst 12598089 # number of overall hits
672system.cpu.icache.overall_hits::total 12598089 # number of overall hits
673system.cpu.icache.ReadReq_misses::cpu.inst 1111711 # number of ReadReq misses
674system.cpu.icache.ReadReq_misses::total 1111711 # number of ReadReq misses
675system.cpu.icache.demand_misses::cpu.inst 1111711 # number of demand (read+write) misses
676system.cpu.icache.demand_misses::total 1111711 # number of demand (read+write) misses
677system.cpu.icache.overall_misses::cpu.inst 1111711 # number of overall misses
678system.cpu.icache.overall_misses::total 1111711 # number of overall misses
679system.cpu.icache.ReadReq_miss_latency::cpu.inst 16369836984 # number of ReadReq miss cycles
680system.cpu.icache.ReadReq_miss_latency::total 16369836984 # number of ReadReq miss cycles
681system.cpu.icache.demand_miss_latency::cpu.inst 16369836984 # number of demand (read+write) miss cycles
682system.cpu.icache.demand_miss_latency::total 16369836984 # number of demand (read+write) miss cycles
683system.cpu.icache.overall_miss_latency::cpu.inst 16369836984 # number of overall miss cycles
684system.cpu.icache.overall_miss_latency::total 16369836984 # number of overall miss cycles
685system.cpu.icache.ReadReq_accesses::cpu.inst 13709800 # number of ReadReq accesses(hits+misses)
686system.cpu.icache.ReadReq_accesses::total 13709800 # number of ReadReq accesses(hits+misses)
687system.cpu.icache.demand_accesses::cpu.inst 13709800 # number of demand (read+write) accesses
688system.cpu.icache.demand_accesses::total 13709800 # number of demand (read+write) accesses
689system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses
690system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses
691system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses
|
| 692system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses
|
634system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
| 693system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses
|
| 694system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses
|
635system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
| 695system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses
|
| 696system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses
|
636system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
| 697system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency
|
| 698system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency
|
637system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
| 699system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
| 700system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency
|
638system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
| 701system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency
|
| 702system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency
|
639system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
640system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
641system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
642system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
643system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
644system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
645system.cpu.icache.fast_writes 0 # number of fast writes performed
646system.cpu.icache.cache_copies 0 # number of cache copies performed
647system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
648system.cpu.icache.writebacks::total 60091 # number of writebacks
649system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
650system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
651system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
652system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
653system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
654system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
655system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
656system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
657system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
658system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
659system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
660system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
661system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
662system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
663system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
664system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
665system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
666system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
667system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
668system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
669system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
670system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
671system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
| 703system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked
704system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
705system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked
706system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
707system.cpu.icache.avg_blocked_cycles::no_mshrs 7566.117048 # average number of cycles each access was blocked
708system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
709system.cpu.icache.fast_writes 0 # number of fast writes performed
710system.cpu.icache.cache_copies 0 # number of cache copies performed
711system.cpu.icache.writebacks::writebacks 60091 # number of writebacks
712system.cpu.icache.writebacks::total 60091 # number of writebacks
713system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91891 # number of ReadReq MSHR hits
714system.cpu.icache.ReadReq_mshr_hits::total 91891 # number of ReadReq MSHR hits
715system.cpu.icache.demand_mshr_hits::cpu.inst 91891 # number of demand (read+write) MSHR hits
716system.cpu.icache.demand_mshr_hits::total 91891 # number of demand (read+write) MSHR hits
717system.cpu.icache.overall_mshr_hits::cpu.inst 91891 # number of overall MSHR hits
718system.cpu.icache.overall_mshr_hits::total 91891 # number of overall MSHR hits
719system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1019820 # number of ReadReq MSHR misses
720system.cpu.icache.ReadReq_mshr_misses::total 1019820 # number of ReadReq MSHR misses
721system.cpu.icache.demand_mshr_misses::cpu.inst 1019820 # number of demand (read+write) MSHR misses
722system.cpu.icache.demand_mshr_misses::total 1019820 # number of demand (read+write) MSHR misses
723system.cpu.icache.overall_mshr_misses::cpu.inst 1019820 # number of overall MSHR misses
724system.cpu.icache.overall_mshr_misses::total 1019820 # number of overall MSHR misses
725system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12187570984 # number of ReadReq MSHR miss cycles
726system.cpu.icache.ReadReq_mshr_miss_latency::total 12187570984 # number of ReadReq MSHR miss cycles
727system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12187570984 # number of demand (read+write) MSHR miss cycles
728system.cpu.icache.demand_mshr_miss_latency::total 12187570984 # number of demand (read+write) MSHR miss cycles
729system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12187570984 # number of overall MSHR miss cycles
730system.cpu.icache.overall_mshr_miss_latency::total 12187570984 # number of overall MSHR miss cycles
731system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7292000 # number of ReadReq MSHR uncacheable cycles
732system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 # number of ReadReq MSHR uncacheable cycles
733system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles
734system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles
735system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses
|
| 736system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses
|
672system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
| 737system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses
|
| 738system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses
|
673system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
| 739system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses
|
| 740system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses
|
674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
| 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency
|
| 742system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency
|
675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
| 743system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
| 744system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
| 745system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency
|
| 746system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency
|
677system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
| 747system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
| 748system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
678system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
| 749system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
| 750system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
679system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
680system.cpu.dcache.replacements 645895 # number of replacements
681system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
682system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
683system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
684system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
685system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
686system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
687system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
688system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
689system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
690system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
691system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
692system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
693system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
694system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
695system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
696system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
697system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
698system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
699system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
700system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
701system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
702system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
703system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
704system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
705system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
706system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
707system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
708system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
709system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
710system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
711system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
712system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
713system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
714system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
715system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
716system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
717system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
718system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
719system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
720system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
721system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
722system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
723system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
724system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
725system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
726system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
727system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
728system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
729system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
730system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
731system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
732system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
733system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
734system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
735system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
736system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
737system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
| 751system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
752system.cpu.dcache.replacements 645895 # number of replacements
753system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use
754system.cpu.dcache.total_refs 22075422 # Total number of references to valid blocks.
755system.cpu.dcache.sampled_refs 646407 # Sample count of references to valid blocks.
756system.cpu.dcache.avg_refs 34.150964 # Average number of references to valid blocks.
757system.cpu.dcache.warmup_cycle 49188000 # Cycle when the warmup percentage was hit.
758system.cpu.dcache.occ_blocks::cpu.data 511.991565 # Average occupied blocks per requestor
759system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy
760system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy
761system.cpu.dcache.ReadReq_hits::cpu.data 14216478 # number of ReadReq hits
762system.cpu.dcache.ReadReq_hits::total 14216478 # number of ReadReq hits
763system.cpu.dcache.WriteReq_hits::cpu.data 7283636 # number of WriteReq hits
764system.cpu.dcache.WriteReq_hits::total 7283636 # number of WriteReq hits
765system.cpu.dcache.LoadLockedReq_hits::cpu.data 286092 # number of LoadLockedReq hits
766system.cpu.dcache.LoadLockedReq_hits::total 286092 # number of LoadLockedReq hits
767system.cpu.dcache.StoreCondReq_hits::cpu.data 285655 # number of StoreCondReq hits
768system.cpu.dcache.StoreCondReq_hits::total 285655 # number of StoreCondReq hits
769system.cpu.dcache.demand_hits::cpu.data 21500114 # number of demand (read+write) hits
770system.cpu.dcache.demand_hits::total 21500114 # number of demand (read+write) hits
771system.cpu.dcache.overall_hits::cpu.data 21500114 # number of overall hits
772system.cpu.dcache.overall_hits::total 21500114 # number of overall hits
773system.cpu.dcache.ReadReq_misses::cpu.data 747655 # number of ReadReq misses
774system.cpu.dcache.ReadReq_misses::total 747655 # number of ReadReq misses
775system.cpu.dcache.WriteReq_misses::cpu.data 2966865 # number of WriteReq misses
776system.cpu.dcache.WriteReq_misses::total 2966865 # number of WriteReq misses
777system.cpu.dcache.LoadLockedReq_misses::cpu.data 13747 # number of LoadLockedReq misses
778system.cpu.dcache.LoadLockedReq_misses::total 13747 # number of LoadLockedReq misses
779system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses
780system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses
781system.cpu.dcache.demand_misses::cpu.data 3714520 # number of demand (read+write) misses
782system.cpu.dcache.demand_misses::total 3714520 # number of demand (read+write) misses
783system.cpu.dcache.overall_misses::cpu.data 3714520 # number of overall misses
784system.cpu.dcache.overall_misses::total 3714520 # number of overall misses
785system.cpu.dcache.ReadReq_miss_latency::cpu.data 11237363500 # number of ReadReq miss cycles
786system.cpu.dcache.ReadReq_miss_latency::total 11237363500 # number of ReadReq miss cycles
787system.cpu.dcache.WriteReq_miss_latency::cpu.data 110154178240 # number of WriteReq miss cycles
788system.cpu.dcache.WriteReq_miss_latency::total 110154178240 # number of WriteReq miss cycles
789system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224042000 # number of LoadLockedReq miss cycles
790system.cpu.dcache.LoadLockedReq_miss_latency::total 224042000 # number of LoadLockedReq miss cycles
791system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 394000 # number of StoreCondReq miss cycles
792system.cpu.dcache.StoreCondReq_miss_latency::total 394000 # number of StoreCondReq miss cycles
793system.cpu.dcache.demand_miss_latency::cpu.data 121391541740 # number of demand (read+write) miss cycles
794system.cpu.dcache.demand_miss_latency::total 121391541740 # number of demand (read+write) miss cycles
795system.cpu.dcache.overall_miss_latency::cpu.data 121391541740 # number of overall miss cycles
796system.cpu.dcache.overall_miss_latency::total 121391541740 # number of overall miss cycles
797system.cpu.dcache.ReadReq_accesses::cpu.data 14964133 # number of ReadReq accesses(hits+misses)
798system.cpu.dcache.ReadReq_accesses::total 14964133 # number of ReadReq accesses(hits+misses)
799system.cpu.dcache.WriteReq_accesses::cpu.data 10250501 # number of WriteReq accesses(hits+misses)
800system.cpu.dcache.WriteReq_accesses::total 10250501 # number of WriteReq accesses(hits+misses)
801system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299839 # number of LoadLockedReq accesses(hits+misses)
802system.cpu.dcache.LoadLockedReq_accesses::total 299839 # number of LoadLockedReq accesses(hits+misses)
803system.cpu.dcache.StoreCondReq_accesses::cpu.data 285668 # number of StoreCondReq accesses(hits+misses)
804system.cpu.dcache.StoreCondReq_accesses::total 285668 # number of StoreCondReq accesses(hits+misses)
805system.cpu.dcache.demand_accesses::cpu.data 25214634 # number of demand (read+write) accesses
806system.cpu.dcache.demand_accesses::total 25214634 # number of demand (read+write) accesses
807system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses
808system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses
809system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses
|
| 810system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses
|
738system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
| 811system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses
|
| 812system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses
|
739system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
| 813system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses
|
| 814system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses
|
740system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
| 815system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses
|
| 816system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
|
741system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
| 817system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses
|
| 818system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses
|
742system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
| 819system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses
|
| 820system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses
|
743system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
| 821system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency
|
| 822system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency
|
744system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
| 823system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency
|
| 824system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency
|
745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
| 825system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency
|
| 826system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency
|
746system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
| 827system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency
|
| 828system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency
|
747system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
| 829system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
| 830system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency
|
748system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
| 831system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency
|
| 832system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency
|
749system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
750system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
751system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
752system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
753system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
754system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
755system.cpu.dcache.fast_writes 0 # number of fast writes performed
756system.cpu.dcache.cache_copies 0 # number of cache copies performed
757system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
758system.cpu.dcache.writebacks::total 574932 # number of writebacks
759system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
760system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
761system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
762system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
763system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
764system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
765system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
766system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
767system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
768system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
769system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
770system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
771system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
772system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
773system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
774system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
775system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
776system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
777system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
778system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
779system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
780system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
782system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
784system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
785system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
786system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
787system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
788system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
789system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
790system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
791system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
792system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
793system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
794system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
795system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
796system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
797system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
798system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
799system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
| 833system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked
834system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked
835system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked
836system.cpu.dcache.blocked::no_targets 268 # number of cycles access was blocked
837system.cpu.dcache.avg_blocked_cycles::no_mshrs 5651.930225 # average number of cycles each access was blocked
838system.cpu.dcache.avg_blocked_cycles::no_targets 28386.194030 # average number of cycles each access was blocked
839system.cpu.dcache.fast_writes 0 # number of fast writes performed
840system.cpu.dcache.cache_copies 0 # number of cache copies performed
841system.cpu.dcache.writebacks::writebacks 574932 # number of writebacks
842system.cpu.dcache.writebacks::total 574932 # number of writebacks
843system.cpu.dcache.ReadReq_mshr_hits::cpu.data 359686 # number of ReadReq MSHR hits
844system.cpu.dcache.ReadReq_mshr_hits::total 359686 # number of ReadReq MSHR hits
845system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2717440 # number of WriteReq MSHR hits
846system.cpu.dcache.WriteReq_mshr_hits::total 2717440 # number of WriteReq MSHR hits
847system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1386 # number of LoadLockedReq MSHR hits
848system.cpu.dcache.LoadLockedReq_mshr_hits::total 1386 # number of LoadLockedReq MSHR hits
849system.cpu.dcache.demand_mshr_hits::cpu.data 3077126 # number of demand (read+write) MSHR hits
850system.cpu.dcache.demand_mshr_hits::total 3077126 # number of demand (read+write) MSHR hits
851system.cpu.dcache.overall_mshr_hits::cpu.data 3077126 # number of overall MSHR hits
852system.cpu.dcache.overall_mshr_hits::total 3077126 # number of overall MSHR hits
853system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387969 # number of ReadReq MSHR misses
854system.cpu.dcache.ReadReq_mshr_misses::total 387969 # number of ReadReq MSHR misses
855system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249425 # number of WriteReq MSHR misses
856system.cpu.dcache.WriteReq_mshr_misses::total 249425 # number of WriteReq MSHR misses
857system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12361 # number of LoadLockedReq MSHR misses
858system.cpu.dcache.LoadLockedReq_mshr_misses::total 12361 # number of LoadLockedReq MSHR misses
859system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses
860system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
861system.cpu.dcache.demand_mshr_misses::cpu.data 637394 # number of demand (read+write) MSHR misses
862system.cpu.dcache.demand_mshr_misses::total 637394 # number of demand (read+write) MSHR misses
863system.cpu.dcache.overall_mshr_misses::cpu.data 637394 # number of overall MSHR misses
864system.cpu.dcache.overall_mshr_misses::total 637394 # number of overall MSHR misses
865system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5287973500 # number of ReadReq MSHR miss cycles
866system.cpu.dcache.ReadReq_mshr_miss_latency::total 5287973500 # number of ReadReq MSHR miss cycles
867system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8908906437 # number of WriteReq MSHR miss cycles
868system.cpu.dcache.WriteReq_mshr_miss_latency::total 8908906437 # number of WriteReq MSHR miss cycles
869system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 165672500 # number of LoadLockedReq MSHR miss cycles
870system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 165672500 # number of LoadLockedReq MSHR miss cycles
871system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 351500 # number of StoreCondReq MSHR miss cycles
872system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 351500 # number of StoreCondReq MSHR miss cycles
873system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14196879937 # number of demand (read+write) MSHR miss cycles
874system.cpu.dcache.demand_mshr_miss_latency::total 14196879937 # number of demand (read+write) MSHR miss cycles
875system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14196879937 # number of overall MSHR miss cycles
876system.cpu.dcache.overall_mshr_miss_latency::total 14196879937 # number of overall MSHR miss cycles
877system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147151877500 # number of ReadReq MSHR uncacheable cycles
878system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147151877500 # number of ReadReq MSHR uncacheable cycles
879system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42255772015 # number of WriteReq MSHR uncacheable cycles
880system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 # number of WriteReq MSHR uncacheable cycles
881system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles
882system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles
883system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses
|
| 884system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses
|
800system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
| 885system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses
|
| 886system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses
|
801system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
| 887system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses
|
| 888system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses
|
802system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
| 889system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses
|
| 890system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
|
803system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
| 891system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses
|
| 892system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses
|
804system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
| 893system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses
|
| 894system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses
|
805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
| 895system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency
|
| 896system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency
|
806system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
| 897system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency
|
| 898system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency
|
807system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
| 899system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency
|
| 900system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency
|
808system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
| 901system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency
|
| 902system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency
|
809system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
| 903system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
| 904system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
810system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
| 905system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency
|
| 906system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency
|
811system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
| 907system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
| 908system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
812system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
| 909system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
| 910system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
813system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
| 911system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
| 912system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
814system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
815system.iocache.replacements 0 # number of replacements
816system.iocache.tagsinuse 0 # Cycle average of tags in use
817system.iocache.total_refs 0 # Total number of references to valid blocks.
818system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
819system.iocache.avg_refs nan # Average number of references to valid blocks.
820system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
821system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
822system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
823system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
824system.iocache.blocked::no_targets 0 # number of cycles access was blocked
825system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
826system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
827system.iocache.fast_writes 0 # number of fast writes performed
828system.iocache.cache_copies 0 # number of cache copies performed
829system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
830system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
831system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
832system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
833system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
| 913system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
914system.iocache.replacements 0 # number of replacements
915system.iocache.tagsinuse 0 # Cycle average of tags in use
916system.iocache.total_refs 0 # Total number of references to valid blocks.
917system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
918system.iocache.avg_refs nan # Average number of references to valid blocks.
919system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
920system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
921system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
922system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
923system.iocache.blocked::no_targets 0 # number of cycles access was blocked
924system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
925system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
926system.iocache.fast_writes 0 # number of fast writes performed
927system.iocache.cache_copies 0 # number of cache copies performed
928system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of ReadReq MSHR uncacheable cycles
929system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 # number of ReadReq MSHR uncacheable cycles
930system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles
931system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles
932system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
| 933system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
834system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
| 934system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
| 935system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
835system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
836system.cpu.kern.inst.arm 0 # number of arm instructions executed
837system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
838
839---------- End Simulation Statistics ----------
| 936system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
937system.cpu.kern.inst.arm 0 # number of arm instructions executed
938system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed
939
940---------- End Simulation Statistics ----------
|