Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.832863 # Number of seconds simulated 4sim_ticks 2832862976500 # Number of ticks simulated 5final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 159277 # Simulator instruction rate (inst/s) 8host_op_rate 193189 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3989457396 # Simulator tick rate (ticks/s) 10host_mem_usage 626716 # Number of bytes of host memory used 11host_seconds 710.09 # Real time elapsed on the host	7host_inst_rate 93807 # Simulator instruction rate (inst/s) 8host_op_rate 113780 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2349621266 # Simulator tick rate (ticks/s) 10host_mem_usage 586720 # Number of bytes of host memory used 11host_seconds 1205.67 # Real time elapsed on the host
12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170065 # Number of read requests accepted 56system.physmem.writeReqs 129793 # Number of write requests accepted 57system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 11272 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10588 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10986 # Per bank write bursts 70system.physmem.perBankRdBursts::3 11169 # Per bank write bursts 71system.physmem.perBankRdBursts::4 12952 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9956 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10481 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10743 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10600 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10174 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10343 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9301 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10025 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11028 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10189 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10128 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8502 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7941 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8563 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8669 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7608 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7365 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7699 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7999 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7959 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7673 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7751 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6981 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7672 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8384 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7646 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7477 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 20 # Number of times write queue was full causing retry 101system.physmem.totGap 2832862744500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 2996 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 166513 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 125412 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 150612 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 16390 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 2189 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 728 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 1890 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2879 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6620 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6141 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 7081 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6533 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6367 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7195 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6951 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7619 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8448 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7506 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7828 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8947 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7499 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7258 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7266 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1259 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 262 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 216 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 208 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 107 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 131 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 120 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 102 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads 268system.physmem.totQLat 2126742000 # Total ticks spent queuing 269system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.05 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing 284system.physmem.readRowHits 139707 # Number of row buffer hits during reads 285system.physmem.writeRowHits 94201 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes 288system.physmem.avgGap 9447347.56 # Average gap between requests 289system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ) 298system.physmem_0.averagePower 669.453835 # Core power per rank (mW) 299system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states 300system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 302system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) 312system.physmem_1.averagePower 669.365771 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states 314system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 319system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 320system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 321system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 322system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 323system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 324system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 325system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 330system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) 331system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 332system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 333system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 334system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 335system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 336system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 337system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 338system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 339system.cf0.dma_write_txs 631 # Number of DMA write transactions. 340system.cpu.branchPred.lookups 46806016 # Number of BP lookups 341system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted 342system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect 343system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups 344system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits 345system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 346system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage 347system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. 348system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. 349system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. 350system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. 351system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. 352system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. 353system.cpu_clk_domain.clock 500 # Clock period in ticks 354system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 355system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 385system.cpu.dtb.walker.walks 72368 # Table walker walks requested 386system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors 387system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate 388system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate 389system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting 390system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution 417system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution 427system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated 428system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated 429system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated 430system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst 433system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst 434system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 435system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst 436system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst 437system.cpu.dtb.inst_hits 0 # ITB inst hits 438system.cpu.dtb.inst_misses 0 # ITB inst misses 439system.cpu.dtb.read_hits 25410890 # DTB read hits 440system.cpu.dtb.read_misses 62740 # DTB read misses 441system.cpu.dtb.write_hits 19865163 # DTB write hits 442system.cpu.dtb.write_misses 9628 # DTB write misses 443system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 444system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 113100501 # Number of instructions simulated 13sim_ops 137180951 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1320384 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9384040 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 10706984 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1320384 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1320384 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8026368 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8043892 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 22878 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 147146 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 170064 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 125412 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 129793 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 429 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 136 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 466095 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3312564 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 3779563 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 466095 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 466095 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2833306 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2839492 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2833306 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 429 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 136 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 466095 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3318750 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 6619055 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 170065 # Number of read requests accepted 56system.physmem.writeReqs 129793 # Number of write requests accepted 57system.physmem.readBursts 170065 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 129793 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 10875840 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue 61system.physmem.bytesWritten 8056896 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 10707048 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 8043892 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 11272 # Per bank write bursts 68system.physmem.perBankRdBursts::1 10588 # Per bank write bursts 69system.physmem.perBankRdBursts::2 10986 # Per bank write bursts 70system.physmem.perBankRdBursts::3 11169 # Per bank write bursts 71system.physmem.perBankRdBursts::4 12952 # Per bank write bursts 72system.physmem.perBankRdBursts::5 9956 # Per bank write bursts 73system.physmem.perBankRdBursts::6 10481 # Per bank write bursts 74system.physmem.perBankRdBursts::7 10743 # Per bank write bursts 75system.physmem.perBankRdBursts::8 10600 # Per bank write bursts 76system.physmem.perBankRdBursts::9 10174 # Per bank write bursts 77system.physmem.perBankRdBursts::10 10343 # Per bank write bursts 78system.physmem.perBankRdBursts::11 9301 # Per bank write bursts 79system.physmem.perBankRdBursts::12 10025 # Per bank write bursts 80system.physmem.perBankRdBursts::13 11028 # Per bank write bursts 81system.physmem.perBankRdBursts::14 10189 # Per bank write bursts 82system.physmem.perBankRdBursts::15 10128 # Per bank write bursts 83system.physmem.perBankWrBursts::0 8502 # Per bank write bursts 84system.physmem.perBankWrBursts::1 7941 # Per bank write bursts 85system.physmem.perBankWrBursts::2 8563 # Per bank write bursts 86system.physmem.perBankWrBursts::3 8669 # Per bank write bursts 87system.physmem.perBankWrBursts::4 7608 # Per bank write bursts 88system.physmem.perBankWrBursts::5 7365 # Per bank write bursts 89system.physmem.perBankWrBursts::6 7699 # Per bank write bursts 90system.physmem.perBankWrBursts::7 7999 # Per bank write bursts 91system.physmem.perBankWrBursts::8 7959 # Per bank write bursts 92system.physmem.perBankWrBursts::9 7673 # Per bank write bursts 93system.physmem.perBankWrBursts::10 7751 # Per bank write bursts 94system.physmem.perBankWrBursts::11 6981 # Per bank write bursts 95system.physmem.perBankWrBursts::12 7672 # Per bank write bursts 96system.physmem.perBankWrBursts::13 8384 # Per bank write bursts 97system.physmem.perBankWrBursts::14 7646 # Per bank write bursts 98system.physmem.perBankWrBursts::15 7477 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 20 # Number of times write queue was full causing retry 101system.physmem.totGap 2832862744500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 542 # Read request sizes (log2) 105system.physmem.readPktSize::3 14 # Read request sizes (log2) 106system.physmem.readPktSize::4 2996 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 166513 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 4381 # Write request sizes (log2) 112system.physmem.writePktSize::3 0 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 125412 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 150612 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 16390 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 2189 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 728 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 1890 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 2879 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 6620 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 6141 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 7081 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 6533 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 6367 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 7195 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 6951 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 7619 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 8448 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 7506 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 7828 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 8947 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 7499 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 7258 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 7266 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 1259 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 366 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 262 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 216 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 208 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 170 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 110 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 191 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 107 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 125 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 131 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 120 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 102 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 95 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 61915 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 305.784899 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 180.937223 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 324.895489 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 23052 37.23% 37.23% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 14889 24.05% 61.28% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 6490 10.48% 71.76% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 3653 5.90% 77.66% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 2551 4.12% 81.78% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 1649 2.66% 84.44% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 1497 2.42% 86.86% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 1106 1.79% 88.65% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 7028 11.35% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 61915 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 6142 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 27.666884 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 569.620654 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-2047 6141 99.98% 99.98% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 6142 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 6142 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 20.496418 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 18.503929 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 14.596363 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16-19 5449 88.72% 88.72% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::20-23 115 1.87% 90.59% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::24-27 28 0.46% 91.05% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::28-31 44 0.72% 91.76% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32-35 34 0.55% 92.32% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::36-39 18 0.29% 92.61% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::40-43 53 0.86% 93.47% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::44-47 7 0.11% 93.59% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::48-51 141 2.30% 95.88% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::52-55 11 0.18% 96.06% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-59 8 0.13% 96.19% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::60-63 8 0.13% 96.32% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::64-67 63 1.03% 97.35% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::68-71 7 0.11% 97.46% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::72-75 8 0.13% 97.59% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::76-79 25 0.41% 98.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::80-83 94 1.53% 99.53% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::84-87 1 0.02% 99.54% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 1 0.02% 99.56% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 1 0.02% 99.58% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 1 0.02% 99.59% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.02% 99.61% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 1 0.02% 99.63% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 7 0.11% 99.74% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::140-143 1 0.02% 99.76% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::144-147 6 0.10% 99.85% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::156-159 1 0.02% 99.87% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::176-179 5 0.08% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::180-183 1 0.02% 99.97% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::188-191 1 0.02% 99.98% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::204-207 1 0.02% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::total 6142 # Writes before turning the bus around for reads 268system.physmem.totQLat 2126742000 # Total ticks spent queuing 269system.physmem.totMemAccLat 5313023250 # Total ticks spent from burst creation until serviced by the DRAM 270system.physmem.totBusLat 849675000 # Total ticks spent in databus transfers 271system.physmem.avgQLat 12515.03 # Average queueing delay per DRAM burst 272system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 273system.physmem.avgMemAccLat 31265.03 # Average memory access latency per DRAM burst 274system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s 275system.physmem.avgWrBW 2.84 # Average achieved write bandwidth in MiByte/s 276system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s 277system.physmem.avgWrBWSys 2.84 # Average system write bandwidth in MiByte/s 278system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 279system.physmem.busUtil 0.05 # Data bus utilization in percentage 280system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 281system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 282system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 283system.physmem.avgWrQLen 23.43 # Average write queue length when enqueuing 284system.physmem.readRowHits 139707 # Number of row buffer hits during reads 285system.physmem.writeRowHits 94201 # Number of row buffer hits during writes 286system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads 287system.physmem.writeRowHitRate 74.82 # Row buffer hit rate for writes 288system.physmem.avgGap 9447347.56 # Average gap between requests 289system.physmem.pageHitRate 79.07 # Row buffer hit rate, read and write combined 290system.physmem_0.actEnergy 242207280 # Energy for activate commands per rank (pJ) 291system.physmem_0.preEnergy 132156750 # Energy for precharge commands per rank (pJ) 292system.physmem_0.readEnergy 687546600 # Energy for read commands per rank (pJ) 293system.physmem_0.writeEnergy 416962080 # Energy for write commands per rank (pJ) 294system.physmem_0.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) 295system.physmem_0.actBackEnergy 83427429555 # Energy for active background per rank (pJ) 296system.physmem_0.preBackEnergy 1626531651000 # Energy for precharge background per rank (pJ) 297system.physmem_0.totalEnergy 1896466320945 # Total energy per rank (pJ) 298system.physmem_0.averagePower 669.453835 # Core power per rank (mW) 299system.physmem_0.memoryStateTime::IDLE 2705741524500 # Time in different power states 300system.physmem_0.memoryStateTime::REF 94595280000 # Time in different power states 301system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 302system.physmem_0.memoryStateTime::ACT 32519220500 # Time in different power states 303system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 304system.physmem_1.actEnergy 225870120 # Energy for activate commands per rank (pJ) 305system.physmem_1.preEnergy 123242625 # Energy for precharge commands per rank (pJ) 306system.physmem_1.readEnergy 637938600 # Energy for read commands per rank (pJ) 307system.physmem_1.writeEnergy 398798640 # Energy for write commands per rank (pJ) 308system.physmem_1.refreshEnergy 185028367680 # Energy for refresh commands per rank (pJ) 309system.physmem_1.actBackEnergy 82153488960 # Energy for active background per rank (pJ) 310system.physmem_1.preBackEnergy 1627649142750 # Energy for precharge background per rank (pJ) 311system.physmem_1.totalEnergy 1896216849375 # Total energy per rank (pJ) 312system.physmem_1.averagePower 669.365771 # Core power per rank (mW) 313system.physmem_1.memoryStateTime::IDLE 2707616089750 # Time in different power states 314system.physmem_1.memoryStateTime::REF 94595280000 # Time in different power states 315system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 316system.physmem_1.memoryStateTime::ACT 30651593250 # Time in different power states 317system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 318system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 319system.realview.nvmem.bytes_read::cpu.inst 112 # Number of bytes read from this memory 320system.realview.nvmem.bytes_read::total 112 # Number of bytes read from this memory 321system.realview.nvmem.bytes_inst_read::cpu.inst 112 # Number of instructions bytes read from this memory 322system.realview.nvmem.bytes_inst_read::total 112 # Number of instructions bytes read from this memory 323system.realview.nvmem.num_reads::cpu.inst 7 # Number of read requests responded to by this memory 324system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory 325system.realview.nvmem.bw_read::cpu.inst 40 # Total read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_read::total 40 # Total read bandwidth from this memory (bytes/s) 327system.realview.nvmem.bw_inst_read::cpu.inst 40 # Instruction read bandwidth from this memory (bytes/s) 328system.realview.nvmem.bw_inst_read::total 40 # Instruction read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_total::cpu.inst 40 # Total bandwidth to/from this memory (bytes/s) 330system.realview.nvmem.bw_total::total 40 # Total bandwidth to/from this memory (bytes/s) 331system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 332system.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 333system.bridge.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 334system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 335system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 336system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 337system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 338system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 339system.cf0.dma_write_txs 631 # Number of DMA write transactions. 340system.cpu.branchPred.lookups 46806016 # Number of BP lookups 341system.cpu.branchPred.condPredicted 23977735 # Number of conditional branches predicted 342system.cpu.branchPred.condIncorrect 1175497 # Number of conditional branches incorrect 343system.cpu.branchPred.BTBLookups 29454915 # Number of BTB lookups 344system.cpu.branchPred.BTBHits 13525299 # Number of BTB hits 345system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 346system.cpu.branchPred.BTBHitPct 45.918649 # BTB Hit Percentage 347system.cpu.branchPred.usedRAS 11724113 # Number of times the RAS was used to get a target. 348system.cpu.branchPred.RASInCorrect 34916 # Number of incorrect RAS predictions. 349system.cpu.branchPred.indirectLookups 7913969 # Number of indirect predictor lookups. 350system.cpu.branchPred.indirectHits 7767748 # Number of indirect target hits. 351system.cpu.branchPred.indirectMisses 146221 # Number of indirect misses. 352system.cpu.branchPredindirectMispredicted 60350 # Number of mispredicted indirect branches. 353system.cpu_clk_domain.clock 500 # Clock period in ticks 354system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 355system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 385system.cpu.dtb.walker.walks 72368 # Table walker walks requested 386system.cpu.dtb.walker.walksShort 72368 # Table walker walks initiated with short descriptors 387system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29394 # Level at which table walker walks with short descriptors terminate 388system.cpu.dtb.walker.walksShortTerminationLevel::Level2 23209 # Level at which table walker walks with short descriptors terminate 389system.cpu.dtb.walker.walksSquashedBefore 19765 # Table walks squashed before starting 390system.cpu.dtb.walker.walkWaitTime::samples 52603 # Table walker wait (enqueue to first request) latency 391system.cpu.dtb.walker.walkWaitTime::mean 464.308119 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::stdev 2802.300904 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::0-8191 51295 97.51% 97.51% # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::8192-16383 909 1.73% 99.24% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::16384-24575 317 0.60% 99.84% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::24576-32767 38 0.07% 99.92% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::32768-40959 17 0.03% 99.95% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.99% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::57344-65535 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::90112-98303 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 52603 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 17713 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 12609.213572 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 10088.702316 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 8411.296807 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-32767 17487 98.72% 98.72% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::32768-65535 220 1.24% 99.97% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::total 17713 # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walksPending::samples 131327462316 # Table walker pending requests distribution 415system.cpu.dtb.walker.walksPending::mean 0.619046 # Table walker pending requests distribution 416system.cpu.dtb.walker.walksPending::stdev 0.492812 # Table walker pending requests distribution 417system.cpu.dtb.walker.walksPending::0-1 131267362816 99.95% 99.95% # Table walker pending requests distribution 418system.cpu.dtb.walker.walksPending::2-3 40987500 0.03% 99.99% # Table walker pending requests distribution 419system.cpu.dtb.walker.walksPending::4-5 8789000 0.01% 99.99% # Table walker pending requests distribution 420system.cpu.dtb.walker.walksPending::6-7 6827500 0.01% 100.00% # Table walker pending requests distribution 421system.cpu.dtb.walker.walksPending::8-9 1022500 0.00% 100.00% # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::10-11 578500 0.00% 100.00% # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::12-13 1418000 0.00% 100.00% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::14-15 467000 0.00% 100.00% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::16-17 9500 0.00% 100.00% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::total 131327462316 # Table walker pending requests distribution 427system.cpu.dtb.walker.walkPageSizes::4K 6375 82.60% 82.60% # Table walker page sizes translated 428system.cpu.dtb.walker.walkPageSizes::1M 1343 17.40% 100.00% # Table walker page sizes translated 429system.cpu.dtb.walker.walkPageSizes::total 7718 # Table walker page sizes translated 430system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72368 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72368 # Table walker requests started/completed, data/inst 433system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7718 # Table walker requests started/completed, data/inst 434system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 435system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7718 # Table walker requests started/completed, data/inst 436system.cpu.dtb.walker.walkRequestOrigin::total 80086 # Table walker requests started/completed, data/inst 437system.cpu.dtb.inst_hits 0 # ITB inst hits 438system.cpu.dtb.inst_misses 0 # ITB inst misses 439system.cpu.dtb.read_hits 25410890 # DTB read hits 440system.cpu.dtb.read_misses 62740 # DTB read misses 441system.cpu.dtb.write_hits 19865163 # DTB write hits 442system.cpu.dtb.write_misses 9628 # DTB write misses 443system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 444system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 445system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 446system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
447system.cpu.dtb.flush_entries 4317 # Number of entries that have been flushed from TLB	447system.cpu.dtb.flush_entries 4253 # Number of entries that have been flushed from TLB
448system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 449system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 450system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 451system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 452system.cpu.dtb.read_accesses 25473630 # DTB read accesses 453system.cpu.dtb.write_accesses 19874791 # DTB write accesses 454system.cpu.dtb.inst_accesses 0 # ITB inst accesses 455system.cpu.dtb.hits 45276053 # DTB hits 456system.cpu.dtb.misses 72368 # DTB misses 457system.cpu.dtb.accesses 45348421 # DTB accesses 458system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 459system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 468system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 469system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 470system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 471system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 472system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 473system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 474system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 475system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 476system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 477system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 478system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 479system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 480system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 481system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 482system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 483system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 484system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 485system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 486system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 487system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 488system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 489system.cpu.itb.walker.walks 12817 # Table walker walks requested 490system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors 491system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate 492system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate 493system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting 494system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency 495system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency 497system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution 522system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution 523system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution 529system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated 530system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated 531system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated 532system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 533system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst 534system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst 535system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 536system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst 537system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst 538system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst 539system.cpu.itb.inst_hits 65995629 # ITB inst hits 540system.cpu.itb.inst_misses 12817 # ITB inst misses 541system.cpu.itb.read_hits 0 # DTB read hits 542system.cpu.itb.read_misses 0 # DTB read misses 543system.cpu.itb.write_hits 0 # DTB write hits 544system.cpu.itb.write_misses 0 # DTB write misses 545system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 546system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 547system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 548system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	448system.cpu.dtb.align_faults 362 # Number of TLB faults due to alignment restrictions 449system.cpu.dtb.prefetch_faults 2060 # Number of TLB faults due to prefetch 450system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 451system.cpu.dtb.perms_faults 1318 # Number of TLB faults due to permissions restrictions 452system.cpu.dtb.read_accesses 25473630 # DTB read accesses 453system.cpu.dtb.write_accesses 19874791 # DTB write accesses 454system.cpu.dtb.inst_accesses 0 # ITB inst accesses 455system.cpu.dtb.hits 45276053 # DTB hits 456system.cpu.dtb.misses 72368 # DTB misses 457system.cpu.dtb.accesses 45348421 # DTB accesses 458system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 459system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 468system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 469system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 470system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 471system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 472system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 473system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 474system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 475system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 476system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 477system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 478system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 479system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 480system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 481system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 482system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 483system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 484system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 485system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 486system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 487system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 488system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 489system.cpu.itb.walker.walks 12817 # Table walker walks requested 490system.cpu.itb.walker.walksShort 12817 # Table walker walks initiated with short descriptors 491system.cpu.itb.walker.walksShortTerminationLevel::Level1 3368 # Level at which table walker walks with short descriptors terminate 492system.cpu.itb.walker.walksShortTerminationLevel::Level2 7731 # Level at which table walker walks with short descriptors terminate 493system.cpu.itb.walker.walksSquashedBefore 1718 # Table walks squashed before starting 494system.cpu.itb.walker.walkWaitTime::samples 11099 # Table walker wait (enqueue to first request) latency 495system.cpu.itb.walker.walkWaitTime::mean 753.896747 # Table walker wait (enqueue to first request) latency 496system.cpu.itb.walker.walkWaitTime::stdev 3151.109885 # Table walker wait (enqueue to first request) latency 497system.cpu.itb.walker.walkWaitTime::0-4095 10511 94.70% 94.70% # Table walker wait (enqueue to first request) latency 498system.cpu.itb.walker.walkWaitTime::4096-8191 118 1.06% 95.77% # Table walker wait (enqueue to first request) latency 499system.cpu.itb.walker.walkWaitTime::8192-12287 237 2.14% 97.90% # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::12288-16383 123 1.11% 99.01% # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::16384-20479 46 0.41% 99.42% # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::20480-24575 47 0.42% 99.85% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.95% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::32768-36863 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::36864-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::53248-57343 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::total 11099 # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkCompletionTime::samples 5044 # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::mean 12037.073751 # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::gmean 9689.647863 # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::stdev 7634.465398 # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::0-16383 4079 80.87% 80.87% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::16384-32767 946 18.75% 99.62% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::32768-49151 16 0.32% 99.94% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::49152-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.04% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::total 5044 # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walksPending::samples 23953217916 # Table walker pending requests distribution 522system.cpu.itb.walker.walksPending::mean 0.646337 # Table walker pending requests distribution 523system.cpu.itb.walker.walksPending::stdev 0.478297 # Table walker pending requests distribution 524system.cpu.itb.walker.walksPending::0 8473460000 35.38% 35.38% # Table walker pending requests distribution 525system.cpu.itb.walker.walksPending::1 15477752916 64.62% 99.99% # Table walker pending requests distribution 526system.cpu.itb.walker.walksPending::2 1917000 0.01% 100.00% # Table walker pending requests distribution 527system.cpu.itb.walker.walksPending::3 88000 0.00% 100.00% # Table walker pending requests distribution 528system.cpu.itb.walker.walksPending::total 23953217916 # Table walker pending requests distribution 529system.cpu.itb.walker.walkPageSizes::4K 2992 89.96% 89.96% # Table walker page sizes translated 530system.cpu.itb.walker.walkPageSizes::1M 334 10.04% 100.00% # Table walker page sizes translated 531system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated 532system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 533system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 12817 # Table walker requests started/completed, data/inst 534system.cpu.itb.walker.walkRequestOrigin_Requested::total 12817 # Table walker requests started/completed, data/inst 535system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 536system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst 537system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst 538system.cpu.itb.walker.walkRequestOrigin::total 16143 # Table walker requests started/completed, data/inst 539system.cpu.itb.inst_hits 65995629 # ITB inst hits 540system.cpu.itb.inst_misses 12817 # ITB inst misses 541system.cpu.itb.read_hits 0 # DTB read hits 542system.cpu.itb.read_misses 0 # DTB read misses 543system.cpu.itb.write_hits 0 # DTB write hits 544system.cpu.itb.write_misses 0 # DTB write misses 545system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 546system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 547system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 548system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
549system.cpu.itb.flush_entries 3089 # Number of entries that have been flushed from TLB	549system.cpu.itb.flush_entries 3025 # Number of entries that have been flushed from TLB
550system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 554system.cpu.itb.read_accesses 0 # DTB read accesses 555system.cpu.itb.write_accesses 0 # DTB write accesses 556system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 557system.cpu.itb.hits 65995629 # DTB hits 558system.cpu.itb.misses 12817 # DTB misses 559system.cpu.itb.accesses 66008446 # DTB accesses 560system.cpu.numPwrStateTransitions 6074 # Number of power state transitions 561system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state 572system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states 573system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states 574system.cpu.numCycles 278423951 # number of cpu cycles simulated 575system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 576system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 577system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss 578system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 579system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 580system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 581system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked 582system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing 583system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb 584system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 585system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps 586system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions 587system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR 588system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched 589system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed 590system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed 591system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle 604system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle 605system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle 606system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked 607system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running 608system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking 609system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing 610system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch 611system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction 612system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode 613system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode 614system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing 615system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle 616system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking 617system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst 618system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running 619system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking 620system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename 621system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename 622system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full 623system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full 624system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full 625system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full 626system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed 627system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made 628system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups 629system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups 630system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed 631system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing 632system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed 633system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed 634system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer 635system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit. 636system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit. 637system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads. 638system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. 639system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) 640system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ 641system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued 642system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued 643system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling 644system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph 645system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed 646system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle 663system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 664system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available 665system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 666system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 667system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 668system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 669system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 670system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available 672system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 693system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available 694system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available 695system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 696system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 697system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 698system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued 699system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued 700system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 701system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 702system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 703system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 704system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 706system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued 727system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued 728system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued 729system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 730system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 731system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued 732system.cpu.iq.rate 0.513744 # Inst issue rate 733system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested 734system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) 735system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads 736system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes 737system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses 738system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads 739system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes 740system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses 741system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses 742system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses 743system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores 744system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 745system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed 746system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed 747system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations 748system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed 749system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 750system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 751system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled 752system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked 753system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 754system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing 755system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking 756system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking 757system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ 758system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 759system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions 760system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions 761system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions 762system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall 763system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall 764system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations 765system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly 766system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly 767system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute 768system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions 769system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed 770system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute 771system.cpu.iew.exec_swp 0 # number of swp insts executed 772system.cpu.iew.exec_nop 180634 # number of nop insts executed 773system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed 774system.cpu.iew.exec_branches 26490215 # Number of branches executed 775system.cpu.iew.exec_stores 20827406 # Number of stores executed 776system.cpu.iew.exec_rate 0.510511 # Inst execution rate 777system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit 778system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back 779system.cpu.iew.wb_producers 63237137 # num instructions producing a value 780system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value 781system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle 782system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back 783system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit 784system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards 785system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted 786system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle 793system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle 803system.cpu.commit.committedInsts 113255406 # Number of instructions committed 804system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed 805system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 806system.cpu.commit.refs 45494106 # Number of memory references committed 807system.cpu.commit.loads 24903571 # Number of loads committed 808system.cpu.commit.membars 814876 # Number of memory barriers committed 809system.cpu.commit.branches 26023568 # Number of branches committed 810system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 811system.cpu.commit.int_insts 120163713 # Number of committed integer instructions. 812system.cpu.commit.function_calls 4884102 # Number of function calls committed. 813system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 814system.cpu.commit.op_class_0::IntAlu 91720354 66.79% 66.79% # Class of committed instruction 815system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction 816system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 817system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 818system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 819system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 820system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 843system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction 844system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction 845system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 846system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 847system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction 848system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached 849system.cpu.rob.rob_reads 389119868 # The number of ROB reads 850system.cpu.rob.rob_writes 292294903 # The number of ROB writes 851system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself 852system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling 853system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 854system.cpu.committedInsts 113100501 # Number of Instructions Simulated 855system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated 856system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction 857system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads 858system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle 859system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads 860system.cpu.int_regfile_reads 155524954 # number of integer regfile reads 861system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 862system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 863system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 864system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads 865system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes 866system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads 867system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes 868system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 869system.cpu.dcache.tags.replacements 838747 # number of replacements 870system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use 871system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. 872system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. 873system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. 874system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 875system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 876system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 877system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 878system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 882system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 883system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses 884system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses 885system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 886system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits 887system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits 888system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits 889system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits 890system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 891system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 892system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 893system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits 894system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits 895system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits 896system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits 897system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits 898system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits 899system.cpu.dcache.overall_hits::total 39152132 # number of overall hits 900system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses 901system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses 902system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses 903system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses 904system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses 905system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses 906system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses 907system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses 908system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 909system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 910system.cpu.dcache.demand_misses::cpu.data 4312561 # number of demand (read+write) misses 911system.cpu.dcache.demand_misses::total 4312561 # number of demand (read+write) misses 912system.cpu.dcache.overall_misses::cpu.data 4490273 # number of overall misses 913system.cpu.dcache.overall_misses::total 4490273 # number of overall misses 914system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711380000 # number of ReadReq miss cycles 915system.cpu.dcache.ReadReq_miss_latency::total 11711380000 # number of ReadReq miss cycles 916system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697 # number of WriteReq miss cycles 917system.cpu.dcache.WriteReq_miss_latency::total 232487777697 # number of WriteReq miss cycles 918system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles 919system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles 920system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles 921system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles 922system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles 923system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles 924system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles 925system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles 926system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) 927system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) 928system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) 929system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) 930system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) 931system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) 932system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) 933system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) 934system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) 935system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) 936system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses 937system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses 938system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses 939system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses 940system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses 941system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses 942system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses 943system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses 944system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses 945system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses 946system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses 947system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses 948system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 949system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 950system.cpu.dcache.demand_miss_rate::cpu.data 0.100015 # miss rate for demand accesses 951system.cpu.dcache.demand_miss_rate::total 0.100015 # miss rate for demand accesses 952system.cpu.dcache.overall_miss_rate::cpu.data 0.102888 # miss rate for overall accesses 953system.cpu.dcache.overall_miss_rate::total 0.102888 # miss rate for overall accesses 954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688 # average ReadReq miss latency 955system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688 # average ReadReq miss latency 956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548 # average WriteReq miss latency 957system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency 958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794 # average LoadLockedReq miss latency 959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794 # average LoadLockedReq miss latency 960system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency 961system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 56625.090682 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 54384.033598 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 6856 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.095391 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 972system.cpu.dcache.writebacks::writebacks 696773 # number of writebacks 973system.cpu.dcache.writebacks::total 696773 # number of writebacks 974system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291027 # number of ReadReq MSHR hits 975system.cpu.dcache.ReadReq_mshr_hits::total 291027 # number of ReadReq MSHR hits 976system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307518 # number of WriteReq MSHR hits 977system.cpu.dcache.WriteReq_mshr_hits::total 3307518 # number of WriteReq MSHR hits 978system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18885 # number of LoadLockedReq MSHR hits 979system.cpu.dcache.LoadLockedReq_mshr_hits::total 18885 # number of LoadLockedReq MSHR hits 980system.cpu.dcache.demand_mshr_hits::cpu.data 3598545 # number of demand (read+write) MSHR hits 981system.cpu.dcache.demand_mshr_hits::total 3598545 # number of demand (read+write) MSHR hits 982system.cpu.dcache.overall_mshr_hits::cpu.data 3598545 # number of overall MSHR hits 983system.cpu.dcache.overall_mshr_hits::total 3598545 # number of overall MSHR hits 984system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414107 # number of ReadReq MSHR misses 985system.cpu.dcache.ReadReq_mshr_misses::total 414107 # number of ReadReq MSHR misses 986system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299909 # number of WriteReq MSHR misses 987system.cpu.dcache.WriteReq_mshr_misses::total 299909 # number of WriteReq MSHR misses 988system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119568 # number of SoftPFReq MSHR misses 989system.cpu.dcache.SoftPFReq_mshr_misses::total 119568 # number of SoftPFReq MSHR misses 990system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8478 # number of LoadLockedReq MSHR misses 991system.cpu.dcache.LoadLockedReq_mshr_misses::total 8478 # number of LoadLockedReq MSHR misses 992system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 993system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 994system.cpu.dcache.demand_mshr_misses::cpu.data 714016 # number of demand (read+write) MSHR misses 995system.cpu.dcache.demand_mshr_misses::total 714016 # number of demand (read+write) MSHR misses 996system.cpu.dcache.overall_mshr_misses::cpu.data 833584 # number of overall MSHR misses 997system.cpu.dcache.overall_mshr_misses::total 833584 # number of overall MSHR misses 998system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 999system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 1000system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1001system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1002system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1003system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 1004system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386388500 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386388500 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19974009472 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 19974009472 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699913000 # number of SoftPFReq MSHR miss cycles 1009system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699913000 # number of SoftPFReq MSHR miss cycles 1010system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127031000 # number of LoadLockedReq MSHR miss cycles 1011system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127031000 # number of LoadLockedReq MSHR miss cycles 1012system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles 1013system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles 1014system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26360397972 # number of demand (read+write) MSHR miss cycles 1015system.cpu.dcache.demand_mshr_miss_latency::total 26360397972 # number of demand (read+write) MSHR miss cycles 1016system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28060310972 # number of overall MSHR miss cycles 1017system.cpu.dcache.overall_mshr_miss_latency::total 28060310972 # number of overall MSHR miss cycles 1018system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276272000 # number of ReadReq MSHR uncacheable cycles 1019system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276272000 # number of ReadReq MSHR uncacheable cycles 1020system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276272000 # number of overall MSHR uncacheable cycles 1021system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276272000 # number of overall MSHR uncacheable cycles 1022system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017277 # mshr miss rate for ReadReq accesses 1023system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017277 # mshr miss rate for ReadReq accesses 1024system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses 1025system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses 1026system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228440 # mshr miss rate for SoftPFReq accesses 1027system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228440 # mshr miss rate for SoftPFReq accesses 1028system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses 1029system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses 1030system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1031system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1032system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016559 # mshr miss rate for demand accesses 1033system.cpu.dcache.demand_mshr_miss_rate::total 0.016559 # mshr miss rate for demand accesses 1034system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019100 # mshr miss rate for overall accesses 1035system.cpu.dcache.overall_mshr_miss_rate::total 0.019100 # mshr miss rate for overall accesses 1036system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281 # average ReadReq mshr miss latency 1037system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281 # average ReadReq mshr miss latency 1038system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644 # average WriteReq mshr miss latency 1039system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644 # average WriteReq mshr miss latency 1040system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311 # average SoftPFReq mshr miss latency 1041system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311 # average SoftPFReq mshr miss latency 1042system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624 # average LoadLockedReq mshr miss latency 1043system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624 # average LoadLockedReq mshr miss latency 1044system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency 1045system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency 1046system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency 1047system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency 1048system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency 1049system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency 1050system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency 1051system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency 1052system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency 1053system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency 1054system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1055system.cpu.icache.tags.replacements 1886245 # number of replacements 1056system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use 1057system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. 1058system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. 1059system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. 1060system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. 1061system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor 1062system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1063system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1064system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1065system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1066system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 1067system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1068system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1069system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1070system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses 1071system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses 1072system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1073system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits 1074system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits 1075system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits 1076system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits 1077system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits 1078system.cpu.icache.overall_hits::total 64013417 # number of overall hits 1079system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses 1080system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses 1081system.cpu.icache.demand_misses::cpu.inst 1977977 # number of demand (read+write) misses 1082system.cpu.icache.demand_misses::total 1977977 # number of demand (read+write) misses 1083system.cpu.icache.overall_misses::cpu.inst 1977977 # number of overall misses 1084system.cpu.icache.overall_misses::total 1977977 # number of overall misses 1085system.cpu.icache.ReadReq_miss_latency::cpu.inst 28160163493 # number of ReadReq miss cycles 1086system.cpu.icache.ReadReq_miss_latency::total 28160163493 # number of ReadReq miss cycles 1087system.cpu.icache.demand_miss_latency::cpu.inst 28160163493 # number of demand (read+write) miss cycles 1088system.cpu.icache.demand_miss_latency::total 28160163493 # number of demand (read+write) miss cycles 1089system.cpu.icache.overall_miss_latency::cpu.inst 28160163493 # number of overall miss cycles 1090system.cpu.icache.overall_miss_latency::total 28160163493 # number of overall miss cycles 1091system.cpu.icache.ReadReq_accesses::cpu.inst 65991394 # number of ReadReq accesses(hits+misses) 1092system.cpu.icache.ReadReq_accesses::total 65991394 # number of ReadReq accesses(hits+misses) 1093system.cpu.icache.demand_accesses::cpu.inst 65991394 # number of demand (read+write) accesses 1094system.cpu.icache.demand_accesses::total 65991394 # number of demand (read+write) accesses 1095system.cpu.icache.overall_accesses::cpu.inst 65991394 # number of overall (read+write) accesses 1096system.cpu.icache.overall_accesses::total 65991394 # number of overall (read+write) accesses 1097system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029973 # miss rate for ReadReq accesses 1098system.cpu.icache.ReadReq_miss_rate::total 0.029973 # miss rate for ReadReq accesses 1099system.cpu.icache.demand_miss_rate::cpu.inst 0.029973 # miss rate for demand accesses 1100system.cpu.icache.demand_miss_rate::total 0.029973 # miss rate for demand accesses 1101system.cpu.icache.overall_miss_rate::cpu.inst 0.029973 # miss rate for overall accesses 1102system.cpu.icache.overall_miss_rate::total 0.029973 # miss rate for overall accesses 1103system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829 # average ReadReq miss latency 1104system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829 # average ReadReq miss latency 1105system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency 1106system.cpu.icache.demand_avg_miss_latency::total 14236.850829 # average overall miss latency 1107system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency 1108system.cpu.icache.overall_avg_miss_latency::total 14236.850829 # average overall miss latency 1109system.cpu.icache.blocked_cycles::no_mshrs 6440 # number of cycles access was blocked 1110system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked 1112system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu.icache.avg_blocked_cycles::no_mshrs 33.894737 # average number of cycles each access was blocked 1114system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu.icache.writebacks::writebacks 1886245 # number of writebacks 1116system.cpu.icache.writebacks::total 1886245 # number of writebacks 1117system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91172 # number of ReadReq MSHR hits 1118system.cpu.icache.ReadReq_mshr_hits::total 91172 # number of ReadReq MSHR hits 1119system.cpu.icache.demand_mshr_hits::cpu.inst 91172 # number of demand (read+write) MSHR hits 1120system.cpu.icache.demand_mshr_hits::total 91172 # number of demand (read+write) MSHR hits 1121system.cpu.icache.overall_mshr_hits::cpu.inst 91172 # number of overall MSHR hits 1122system.cpu.icache.overall_mshr_hits::total 91172 # number of overall MSHR hits 1123system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1886805 # number of ReadReq MSHR misses 1124system.cpu.icache.ReadReq_mshr_misses::total 1886805 # number of ReadReq MSHR misses 1125system.cpu.icache.demand_mshr_misses::cpu.inst 1886805 # number of demand (read+write) MSHR misses 1126system.cpu.icache.demand_mshr_misses::total 1886805 # number of demand (read+write) MSHR misses 1127system.cpu.icache.overall_mshr_misses::cpu.inst 1886805 # number of overall MSHR misses 1128system.cpu.icache.overall_mshr_misses::total 1886805 # number of overall MSHR misses 1129system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1130system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1131system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1132system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1133system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25187429497 # number of ReadReq MSHR miss cycles 1134system.cpu.icache.ReadReq_mshr_miss_latency::total 25187429497 # number of ReadReq MSHR miss cycles 1135system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25187429497 # number of demand (read+write) MSHR miss cycles 1136system.cpu.icache.demand_mshr_miss_latency::total 25187429497 # number of demand (read+write) MSHR miss cycles 1137system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25187429497 # number of overall MSHR miss cycles 1138system.cpu.icache.overall_mshr_miss_latency::total 25187429497 # number of overall MSHR miss cycles 1139system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles 1140system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles 1141system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles 1142system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles 1143system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for ReadReq accesses 1144system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028592 # mshr miss rate for ReadReq accesses 1145system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for demand accesses 1146system.cpu.icache.demand_mshr_miss_rate::total 0.028592 # mshr miss rate for demand accesses 1147system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for overall accesses 1148system.cpu.icache.overall_mshr_miss_rate::total 0.028592 # mshr miss rate for overall accesses 1149system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861 # average ReadReq mshr miss latency 1150system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861 # average ReadReq mshr miss latency 1151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1152system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1154system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1155system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency 1156system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency 1157system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency 1158system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency 1159system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1160system.cpu.l2cache.tags.replacements 96776 # number of replacements 1161system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use 1162system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. 1163system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks. 1164system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks. 1165system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1166system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor 1167system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor 1168system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.672900 # Average occupied blocks per requestor 1169system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431 # Average occupied blocks per requestor 1170system.cpu.l2cache.tags.occ_blocks::cpu.data 5025.112172 # Average occupied blocks per requestor 1171system.cpu.l2cache.tags.occ_percent::writebacks 0.757146 # Average percentage of cache occupancy 1172system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000164 # Average percentage of cache occupancy 1173system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy 1174system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158233 # Average percentage of cache occupancy 1175system.cpu.l2cache.tags.occ_percent::cpu.data 0.076677 # Average percentage of cache occupancy 1176system.cpu.l2cache.tags.occ_percent::total 0.992260 # Average percentage of cache occupancy 1177system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1178system.cpu.l2cache.tags.occ_task_id_blocks::1024 65312 # Occupied blocks per task id 1179system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1180system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 1181system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id 1185system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1186system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id 1187system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses 1188system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses 1189system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1190system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits 1191system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits 1192system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits 1193system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits 1194system.cpu.l2cache.WritebackDirty_hits::total 696773 # number of WritebackDirty hits 1195system.cpu.l2cache.WritebackClean_hits::writebacks 1848340 # number of WritebackClean hits 1196system.cpu.l2cache.WritebackClean_hits::total 1848340 # number of WritebackClean hits 1197system.cpu.l2cache.UpgradeReq_hits::cpu.data 62 # number of UpgradeReq hits 1198system.cpu.l2cache.UpgradeReq_hits::total 62 # number of UpgradeReq hits 1199system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1200system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1201system.cpu.l2cache.ReadExReq_hits::cpu.data 161752 # number of ReadExReq hits 1202system.cpu.l2cache.ReadExReq_hits::total 161752 # number of ReadExReq hits 1203system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866806 # number of ReadCleanReq hits 1204system.cpu.l2cache.ReadCleanReq_hits::total 1866806 # number of ReadCleanReq hits 1205system.cpu.l2cache.ReadSharedReq_hits::cpu.data 528684 # number of ReadSharedReq hits 1206system.cpu.l2cache.ReadSharedReq_hits::total 528684 # number of ReadSharedReq hits 1207system.cpu.l2cache.demand_hits::cpu.dtb.walker 58073 # number of demand (read+write) hits 1208system.cpu.l2cache.demand_hits::cpu.itb.walker 12060 # number of demand (read+write) hits 1209system.cpu.l2cache.demand_hits::cpu.inst 1866806 # number of demand (read+write) hits 1210system.cpu.l2cache.demand_hits::cpu.data 690436 # number of demand (read+write) hits 1211system.cpu.l2cache.demand_hits::total 2627375 # number of demand (read+write) hits 1212system.cpu.l2cache.overall_hits::cpu.dtb.walker 58073 # number of overall hits 1213system.cpu.l2cache.overall_hits::cpu.itb.walker 12060 # number of overall hits 1214system.cpu.l2cache.overall_hits::cpu.inst 1866806 # number of overall hits 1215system.cpu.l2cache.overall_hits::cpu.data 690436 # number of overall hits 1216system.cpu.l2cache.overall_hits::total 2627375 # number of overall hits 1217system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1218system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1219system.cpu.l2cache.ReadReq_misses::total 25 # number of ReadReq misses 1220system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 1221system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 1222system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1223system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1224system.cpu.l2cache.ReadExReq_misses::cpu.data 135508 # number of ReadExReq misses 1225system.cpu.l2cache.ReadExReq_misses::total 135508 # number of ReadExReq misses 1226system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19911 # number of ReadCleanReq misses 1227system.cpu.l2cache.ReadCleanReq_misses::total 19911 # number of ReadCleanReq misses 1228system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13337 # number of ReadSharedReq misses 1229system.cpu.l2cache.ReadSharedReq_misses::total 13337 # number of ReadSharedReq misses 1230system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1231system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1232system.cpu.l2cache.demand_misses::cpu.inst 19911 # number of demand (read+write) misses 1233system.cpu.l2cache.demand_misses::cpu.data 148845 # number of demand (read+write) misses 1234system.cpu.l2cache.demand_misses::total 168781 # number of demand (read+write) misses 1235system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1236system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1237system.cpu.l2cache.overall_misses::cpu.inst 19911 # number of overall misses 1238system.cpu.l2cache.overall_misses::cpu.data 148845 # number of overall misses 1239system.cpu.l2cache.overall_misses::total 168781 # number of overall misses 1240system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2632000 # number of ReadReq miss cycles 1241system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 795500 # number of ReadReq miss cycles 1242system.cpu.l2cache.ReadReq_miss_latency::total 3427500 # number of ReadReq miss cycles 1243system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2731500 # number of UpgradeReq miss cycles 1244system.cpu.l2cache.UpgradeReq_miss_latency::total 2731500 # number of UpgradeReq miss cycles 1245system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1246system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1247system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17610608500 # number of ReadExReq miss cycles 1248system.cpu.l2cache.ReadExReq_miss_latency::total 17610608500 # number of ReadExReq miss cycles 1249system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2638749000 # number of ReadCleanReq miss cycles 1250system.cpu.l2cache.ReadCleanReq_miss_latency::total 2638749000 # number of ReadCleanReq miss cycles 1251system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1798280000 # number of ReadSharedReq miss cycles 1252system.cpu.l2cache.ReadSharedReq_miss_latency::total 1798280000 # number of ReadSharedReq miss cycles 1253system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2632000 # number of demand (read+write) miss cycles 1254system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 795500 # number of demand (read+write) miss cycles 1255system.cpu.l2cache.demand_miss_latency::cpu.inst 2638749000 # number of demand (read+write) miss cycles 1256system.cpu.l2cache.demand_miss_latency::cpu.data 19408888500 # number of demand (read+write) miss cycles 1257system.cpu.l2cache.demand_miss_latency::total 22051065000 # number of demand (read+write) miss cycles 1258system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2632000 # number of overall miss cycles 1259system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 795500 # number of overall miss cycles 1260system.cpu.l2cache.overall_miss_latency::cpu.inst 2638749000 # number of overall miss cycles 1261system.cpu.l2cache.overall_miss_latency::cpu.data 19408888500 # number of overall miss cycles 1262system.cpu.l2cache.overall_miss_latency::total 22051065000 # number of overall miss cycles 1263system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 58092 # number of ReadReq accesses(hits+misses) 1264system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12066 # number of ReadReq accesses(hits+misses) 1265system.cpu.l2cache.ReadReq_accesses::total 70158 # number of ReadReq accesses(hits+misses) 1266system.cpu.l2cache.WritebackDirty_accesses::writebacks 696773 # number of WritebackDirty accesses(hits+misses) 1267system.cpu.l2cache.WritebackDirty_accesses::total 696773 # number of WritebackDirty accesses(hits+misses) 1268system.cpu.l2cache.WritebackClean_accesses::writebacks 1848340 # number of WritebackClean accesses(hits+misses) 1269system.cpu.l2cache.WritebackClean_accesses::total 1848340 # number of WritebackClean accesses(hits+misses) 1270system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2781 # number of UpgradeReq accesses(hits+misses) 1271system.cpu.l2cache.UpgradeReq_accesses::total 2781 # number of UpgradeReq accesses(hits+misses) 1272system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1273system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1274system.cpu.l2cache.ReadExReq_accesses::cpu.data 297260 # number of ReadExReq accesses(hits+misses) 1275system.cpu.l2cache.ReadExReq_accesses::total 297260 # number of ReadExReq accesses(hits+misses) 1276system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886717 # number of ReadCleanReq accesses(hits+misses) 1277system.cpu.l2cache.ReadCleanReq_accesses::total 1886717 # number of ReadCleanReq accesses(hits+misses) 1278system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542021 # number of ReadSharedReq accesses(hits+misses) 1279system.cpu.l2cache.ReadSharedReq_accesses::total 542021 # number of ReadSharedReq accesses(hits+misses) 1280system.cpu.l2cache.demand_accesses::cpu.dtb.walker 58092 # number of demand (read+write) accesses 1281system.cpu.l2cache.demand_accesses::cpu.itb.walker 12066 # number of demand (read+write) accesses 1282system.cpu.l2cache.demand_accesses::cpu.inst 1886717 # number of demand (read+write) accesses 1283system.cpu.l2cache.demand_accesses::cpu.data 839281 # number of demand (read+write) accesses 1284system.cpu.l2cache.demand_accesses::total 2796156 # number of demand (read+write) accesses 1285system.cpu.l2cache.overall_accesses::cpu.dtb.walker 58092 # number of overall (read+write) accesses 1286system.cpu.l2cache.overall_accesses::cpu.itb.walker 12066 # number of overall (read+write) accesses 1287system.cpu.l2cache.overall_accesses::cpu.inst 1886717 # number of overall (read+write) accesses 1288system.cpu.l2cache.overall_accesses::cpu.data 839281 # number of overall (read+write) accesses 1289system.cpu.l2cache.overall_accesses::total 2796156 # number of overall (read+write) accesses 1290system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000327 # miss rate for ReadReq accesses 1291system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000497 # miss rate for ReadReq accesses 1292system.cpu.l2cache.ReadReq_miss_rate::total 0.000356 # miss rate for ReadReq accesses 1293system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.977706 # miss rate for UpgradeReq accesses 1294system.cpu.l2cache.UpgradeReq_miss_rate::total 0.977706 # miss rate for UpgradeReq accesses 1295system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 1296system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 1297system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455857 # miss rate for ReadExReq accesses 1298system.cpu.l2cache.ReadExReq_miss_rate::total 0.455857 # miss rate for ReadExReq accesses 1299system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010553 # miss rate for ReadCleanReq accesses 1300system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010553 # miss rate for ReadCleanReq accesses 1301system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024606 # miss rate for ReadSharedReq accesses 1302system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024606 # miss rate for ReadSharedReq accesses 1303system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000327 # miss rate for demand accesses 1304system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000497 # miss rate for demand accesses 1305system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010553 # miss rate for demand accesses 1306system.cpu.l2cache.demand_miss_rate::cpu.data 0.177348 # miss rate for demand accesses 1307system.cpu.l2cache.demand_miss_rate::total 0.060362 # miss rate for demand accesses 1308system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000327 # miss rate for overall accesses 1309system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000497 # miss rate for overall accesses 1310system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010553 # miss rate for overall accesses 1311system.cpu.l2cache.overall_miss_rate::cpu.data 0.177348 # miss rate for overall accesses 1312system.cpu.l2cache.overall_miss_rate::total 0.060362 # miss rate for overall accesses 1313system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138526.315789 # average ReadReq miss latency 1314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132583.333333 # average ReadReq miss latency 1315system.cpu.l2cache.ReadReq_avg_miss_latency::total 137100 # average ReadReq miss latency 1316system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1004.597278 # average UpgradeReq miss latency 1317system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1004.597278 # average UpgradeReq miss latency 1318system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1319system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1320system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129959.917496 # average ReadExReq miss latency 1321system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129959.917496 # average ReadExReq miss latency 1322system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132527.196022 # average ReadCleanReq miss latency 1323system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132527.196022 # average ReadCleanReq miss latency 1324system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134833.920672 # average ReadSharedReq miss latency 1325system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134833.920672 # average ReadSharedReq miss latency 1326system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency 1327system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency 1328system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency 1329system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency 1330system.cpu.l2cache.demand_avg_miss_latency::total 130648.977077 # average overall miss latency 1331system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency 1332system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency 1333system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency 1334system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency 1335system.cpu.l2cache.overall_avg_miss_latency::total 130648.977077 # average overall miss latency 1336system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1337system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1338system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1339system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1340system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1341system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1342system.cpu.l2cache.writebacks::writebacks 89222 # number of writebacks 1343system.cpu.l2cache.writebacks::total 89222 # number of writebacks 1344system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1345system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits 1346system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits 1347system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits 1348system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits 1349system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits 1350system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits 1351system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits 1352system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits 1353system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits 1354system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses 1355system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1356system.cpu.l2cache.ReadReq_mshr_misses::total 25 # number of ReadReq MSHR misses 1357system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses 1358system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses 1359system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1360system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1361system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135508 # number of ReadExReq MSHR misses 1362system.cpu.l2cache.ReadExReq_mshr_misses::total 135508 # number of ReadExReq MSHR misses 1363system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19885 # number of ReadCleanReq MSHR misses 1364system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19885 # number of ReadCleanReq MSHR misses 1365system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13226 # number of ReadSharedReq MSHR misses 1366system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13226 # number of ReadSharedReq MSHR misses 1367system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1368system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1369system.cpu.l2cache.demand_mshr_misses::cpu.inst 19885 # number of demand (read+write) MSHR misses 1370system.cpu.l2cache.demand_mshr_misses::cpu.data 148734 # number of demand (read+write) MSHR misses 1371system.cpu.l2cache.demand_mshr_misses::total 168644 # number of demand (read+write) MSHR misses 1372system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1373system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1374system.cpu.l2cache.overall_mshr_misses::cpu.inst 19885 # number of overall MSHR misses 1375system.cpu.l2cache.overall_mshr_misses::cpu.data 148734 # number of overall MSHR misses 1376system.cpu.l2cache.overall_mshr_misses::total 168644 # number of overall MSHR misses 1377system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1378system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1379system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable 1380system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1381system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1382system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1383system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1384system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses 1385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2442000 # number of ReadReq MSHR miss cycles 1386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 735500 # number of ReadReq MSHR miss cycles 1387system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3177500 # number of ReadReq MSHR miss cycles 1388system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 184950500 # number of UpgradeReq MSHR miss cycles 1389system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 184950500 # number of UpgradeReq MSHR miss cycles 1390system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211500 # number of SCUpgradeReq MSHR miss cycles 1391system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211500 # number of SCUpgradeReq MSHR miss cycles 1392system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16255528500 # number of ReadExReq MSHR miss cycles 1393system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16255528500 # number of ReadExReq MSHR miss cycles 1394system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2436802003 # number of ReadCleanReq MSHR miss cycles 1395system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2436802003 # number of ReadCleanReq MSHR miss cycles 1396system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652257000 # number of ReadSharedReq MSHR miss cycles 1397system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652257000 # number of ReadSharedReq MSHR miss cycles 1398system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2442000 # number of demand (read+write) MSHR miss cycles 1399system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 735500 # number of demand (read+write) MSHR miss cycles 1400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2436802003 # number of demand (read+write) MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17907785500 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::total 20347765003 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles 1404system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 735500 # number of overall MSHR miss cycles 1405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2436802003 # number of overall MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17907785500 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::total 20347765003 # number of overall MSHR miss cycles 1408system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles 1409system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887147000 # number of ReadReq MSHR uncacheable cycles 1410system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227214500 # number of ReadReq MSHR uncacheable cycles 1411system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles 1412system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887147000 # number of overall MSHR uncacheable cycles 1413system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227214500 # number of overall MSHR uncacheable cycles 1414system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses 1415system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for ReadReq accesses 1416system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses 1417system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.977706 # mshr miss rate for UpgradeReq accesses 1418system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.977706 # mshr miss rate for UpgradeReq accesses 1419system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 1420system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 1421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455857 # mshr miss rate for ReadExReq accesses 1422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455857 # mshr miss rate for ReadExReq accesses 1423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for ReadCleanReq accesses 1424system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010539 # mshr miss rate for ReadCleanReq accesses 1425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024401 # mshr miss rate for ReadSharedReq accesses 1426system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024401 # mshr miss rate for ReadSharedReq accesses 1427system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses 1428system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for demand accesses 1429system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for demand accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::total 0.060313 # mshr miss rate for demand accesses 1432system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses 1433system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for overall accesses 1434system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for overall accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::total 0.060313 # mshr miss rate for overall accesses 1437system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency 1438system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average ReadReq mshr miss latency 1439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127100 # average ReadReq mshr miss latency 1440system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263 # average UpgradeReq mshr miss latency 1441system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263 # average UpgradeReq mshr miss latency 1442system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1443system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496 # average ReadExReq mshr miss latency 1445system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency 1446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361 # average ReadCleanReq mshr miss latency 1447system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency 1448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency 1449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency 1450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency 1451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency 1452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency 1455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency 1456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency 1457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency 1460system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency 1461system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency 1462system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency 1463system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency 1464system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency 1465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency 1466system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. 1467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1469system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1473system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution 1475system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution 1484system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution 1485system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution 1486system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution 1487system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1488system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes) 1489system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes) 1490system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes) 1491system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes) 1493system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.snoops 194360 # Total snoops (count) 1499system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram 1500system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram 1501system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1503system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram 1504system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1506system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1509system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram 1510system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks) 1511system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1512system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) 1513system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1514system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) 1515system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1516system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) 1517system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1518system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) 1519system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1520system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) 1521system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1522system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1523system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1524system.iobus.trans_dist::ReadResp 30172 # Transaction distribution 1525system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1526system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1527system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1536system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1537system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1538system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1539system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1540system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1541system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1542system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1543system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1562system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1563system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks) 1574system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1575system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) 1576system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1577system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) 1578system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1579system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) 1580system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1581system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 1582system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1583system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) 1584system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer8.occupancy 652000 # Layer occupancy (ticks) 1586system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1587system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1588system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1589system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 1590system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1591system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1592system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1593system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 1594system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1595system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) 1596system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1597system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1598system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1599system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) 1600system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1601system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1602system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1603system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1604system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1605system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) 1606system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1607system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) 1608system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1609system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) 1610system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1611system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) 1612system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1613system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1614system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1615system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) 1616system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1617system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1618system.iocache.tags.replacements 36413 # number of replacements 1619system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use 1620system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1621system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. 1622system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1623system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. 1624system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor 1625system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy 1626system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy 1627system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1628system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1629system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1630system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1631system.iocache.tags.data_accesses 328023 # Number of data accesses 1632system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1633system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1634system.iocache.ReadReq_misses::total 223 # number of ReadReq misses 1635system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1636system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1637system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses 1638system.iocache.demand_misses::total 36447 # number of demand (read+write) misses 1639system.iocache.overall_misses::realview.ide 36447 # number of overall misses 1640system.iocache.overall_misses::total 36447 # number of overall misses 1641system.iocache.ReadReq_miss_latency::realview.ide 28153877 # number of ReadReq miss cycles 1642system.iocache.ReadReq_miss_latency::total 28153877 # number of ReadReq miss cycles 1643system.iocache.WriteLineReq_miss_latency::realview.ide 4551268111 # number of WriteLineReq miss cycles 1644system.iocache.WriteLineReq_miss_latency::total 4551268111 # number of WriteLineReq miss cycles 1645system.iocache.demand_miss_latency::realview.ide 4579421988 # number of demand (read+write) miss cycles 1646system.iocache.demand_miss_latency::total 4579421988 # number of demand (read+write) miss cycles 1647system.iocache.overall_miss_latency::realview.ide 4579421988 # number of overall miss cycles 1648system.iocache.overall_miss_latency::total 4579421988 # number of overall miss cycles 1649system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) 1650system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) 1651system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1652system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1653system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses 1654system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses 1655system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses 1656system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses 1657system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1658system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1659system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1660system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1661system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1662system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1663system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1664system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1665system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507 # average ReadReq miss latency 1666system.iocache.ReadReq_avg_miss_latency::total 126250.569507 # average ReadReq miss latency 1667system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637 # average WriteLineReq miss latency 1668system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637 # average WriteLineReq miss latency 1669system.iocache.demand_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency 1670system.iocache.demand_avg_miss_latency::total 125646.061075 # average overall miss latency 1671system.iocache.overall_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency 1672system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency 1673system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1674system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1675system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1676system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1677system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1678system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1679system.iocache.writebacks::writebacks 36190 # number of writebacks 1680system.iocache.writebacks::total 36190 # number of writebacks 1681system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses 1682system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses 1683system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1684system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1685system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses 1686system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses 1687system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses 1688system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses 1689system.iocache.ReadReq_mshr_miss_latency::realview.ide 17003877 # number of ReadReq MSHR miss cycles 1690system.iocache.ReadReq_mshr_miss_latency::total 17003877 # number of ReadReq MSHR miss cycles 1691system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738656099 # number of WriteLineReq MSHR miss cycles 1692system.iocache.WriteLineReq_mshr_miss_latency::total 2738656099 # number of WriteLineReq MSHR miss cycles 1693system.iocache.demand_mshr_miss_latency::realview.ide 2755659976 # number of demand (read+write) MSHR miss cycles 1694system.iocache.demand_mshr_miss_latency::total 2755659976 # number of demand (read+write) MSHR miss cycles 1695system.iocache.overall_mshr_miss_latency::realview.ide 2755659976 # number of overall MSHR miss cycles 1696system.iocache.overall_mshr_miss_latency::total 2755659976 # number of overall MSHR miss cycles 1697system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1698system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1699system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1700system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1701system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1702system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1703system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1704system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1705system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency 1706system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency 1707system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency 1708system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency 1709system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1710system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1711system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1712system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1713system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1714system.membus.trans_dist::ReadReq 34132 # Transaction distribution 1715system.membus.trans_dist::ReadResp 67490 # Transaction distribution 1716system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1717system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1718system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution 1719system.membus.trans_dist::CleanEvict 7777 # Transaction distribution 1720system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution 1721system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1722system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1723system.membus.trans_dist::ReadExReq 133639 # Transaction distribution 1724system.membus.trans_dist::ReadExResp 133639 # Transaction distribution 1725system.membus.trans_dist::ReadSharedReq 33359 # Transaction distribution 1726system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1727system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1728system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1729system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1730system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450505 # Packet count per connected master and slave (bytes) 1731system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558073 # Packet count per connected master and slave (bytes) 1732system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) 1733system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) 1734system.membus.pkt_count::total 630948 # Packet count per connected master and slave (bytes) 1735system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1736system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) 1737system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1738system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16433756 # Cumulative packet size per connected master and slave (bytes) 1739system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes) 1740system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1741system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1742system.membus.pkt_size::total 18914265 # Cumulative packet size per connected master and slave (bytes) 1743system.membus.snoops 487 # Total snoops (count) 1744system.membus.snoop_fanout::samples 402739 # Request fanout histogram 1745system.membus.snoop_fanout::mean 1 # Request fanout histogram 1746system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1747system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1748system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1749system.membus.snoop_fanout::1 402739 100.00% 100.00% # Request fanout histogram 1750system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1751system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1752system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1753system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1754system.membus.snoop_fanout::total 402739 # Request fanout histogram 1755system.membus.reqLayer0.occupancy 83678000 # Layer occupancy (ticks) 1756system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1757system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1758system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1759system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) 1760system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1761system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) 1762system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1763system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) 1764system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1765system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) 1766system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1767system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1768system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1769system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1770system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1771system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1772system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1773system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1774system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1775system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1776system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1777system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1778system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1779system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1780system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1781system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1782system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1783system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1784system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1785system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1786system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1787system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1788system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1789system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1790system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1791system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1792system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1793system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1794system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1795system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1796system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1797system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1798system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1799system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1800system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1801system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1802system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1803system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1804system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1805system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1806system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1807system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1808system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1809system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1810system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1811system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1812system.realview.ethernet.droppedPackets 0 # number of packets dropped 1813system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1814system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1815system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1816system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1817system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1818system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1819system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1820system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1821system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1822system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1823system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1824system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1825system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1826system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1827system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1828system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1829system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1830system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1831system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1832system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1833system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1834system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1835system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1836system.cpu.kern.inst.arm 0 # number of arm instructions executed 1837system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1838 1839---------- End Simulation Statistics ----------	550system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu.itb.perms_faults 2166 # Number of TLB faults due to permissions restrictions 554system.cpu.itb.read_accesses 0 # DTB read accesses 555system.cpu.itb.write_accesses 0 # DTB write accesses 556system.cpu.itb.inst_accesses 66008446 # ITB inst accesses 557system.cpu.itb.hits 65995629 # DTB hits 558system.cpu.itb.misses 12817 # DTB misses 559system.cpu.itb.accesses 66008446 # DTB accesses 560system.cpu.numPwrStateTransitions 6074 # Number of power state transitions 561system.cpu.pwrStateClkGateDist::samples 3037 # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::mean 886944690.993085 # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::stdev 17421692807.288013 # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::underflows 2966 97.66% 97.66% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::1000-5e+10 65 2.14% 99.80% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.07% 99.90% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::max_value 499972175752 # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::total 3037 # Distribution of time spent in the clock gated state 572system.cpu.pwrStateResidencyTicks::ON 139211949954 # Cumulative time (in ticks) in various power states 573system.cpu.pwrStateResidencyTicks::CLK_GATED 2693651026546 # Cumulative time (in ticks) in various power states 574system.cpu.numCycles 278423951 # number of cpu cycles simulated 575system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 576system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 577system.cpu.fetch.icacheStallCycles 104963927 # Number of cycles fetch is stalled on an Icache miss 578system.cpu.fetch.Insts 184057531 # Number of instructions fetch has processed 579system.cpu.fetch.Branches 46806016 # Number of branches that fetch encountered 580system.cpu.fetch.predictedBranches 33017160 # Number of branches that fetch has predicted taken 581system.cpu.fetch.Cycles 161476606 # Number of cycles fetch has run and was not squashing or blocked 582system.cpu.fetch.SquashCycles 6057796 # Number of cycles fetch has spent squashing 583system.cpu.fetch.TlbCycles 189442 # Number of cycles fetch has spent waiting for tlb 584system.cpu.fetch.MiscStallCycles 8697 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 585system.cpu.fetch.PendingTrapStallCycles 337421 # Number of stall cycles due to pending traps 586system.cpu.fetch.PendingQuiesceStallCycles 555442 # Number of stall cycles due to pending quiesce instructions 587system.cpu.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR 588system.cpu.fetch.CacheLines 65994399 # Number of cache lines fetched 589system.cpu.fetch.IcacheSquashes 1047621 # Number of outstanding Icache misses that were squashed 590system.cpu.fetch.ItlbSquashes 6260 # Number of outstanding ITLB misses that were squashed 591system.cpu.fetch.rateDist::samples 270560621 # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::mean 0.829508 # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::stdev 1.217052 # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::0 171637464 63.44% 63.44% # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::1 29152121 10.77% 74.21% # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::2 14032929 5.19% 79.40% # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::3 55738107 20.60% 100.00% # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 602system.cpu.fetch.rateDist::total 270560621 # Number of instructions fetched each cycle (Total) 603system.cpu.fetch.branchRate 0.168111 # Number of branch fetches per cycle 604system.cpu.fetch.rate 0.661069 # Number of inst fetches per cycle 605system.cpu.decode.IdleCycles 77946488 # Number of cycles decode is idle 606system.cpu.decode.BlockedCycles 121877263 # Number of cycles decode is blocked 607system.cpu.decode.RunCycles 64301274 # Number of cycles decode is running 608system.cpu.decode.UnblockCycles 3866559 # Number of cycles decode is unblocking 609system.cpu.decode.SquashCycles 2569037 # Number of cycles decode is squashing 610system.cpu.decode.BranchResolved 3407655 # Number of times decode resolved a branch 611system.cpu.decode.BranchMispred 467954 # Number of times decode detected a branch misprediction 612system.cpu.decode.DecodedInsts 156976144 # Number of instructions handled by decode 613system.cpu.decode.SquashedInsts 3511593 # Number of squashed instructions handled by decode 614system.cpu.rename.SquashCycles 2569037 # Number of cycles rename is squashing 615system.cpu.rename.IdleCycles 83703989 # Number of cycles rename is idle 616system.cpu.rename.BlockCycles 11810773 # Number of cycles rename is blocking 617system.cpu.rename.serializeStallCycles 76556801 # count of cycles rename stalled for serializing inst 618system.cpu.rename.RunCycles 62410429 # Number of cycles rename is running 619system.cpu.rename.UnblockCycles 33509592 # Number of cycles rename is unblocking 620system.cpu.rename.RenamedInsts 146427061 # Number of instructions processed by rename 621system.cpu.rename.SquashedInsts 918712 # Number of squashed instructions processed by rename 622system.cpu.rename.ROBFullEvents 467058 # Number of times rename has blocked due to ROB full 623system.cpu.rename.IQFullEvents 65507 # Number of times rename has blocked due to IQ full 624system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full 625system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full 626system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed 627system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made 628system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups 629system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups 630system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed 631system.cpu.rename.UndoneMaps 8483639 # Number of HB maps that are undone due to squashing 632system.cpu.rename.serializingInsts 2839333 # count of serializing insts renamed 633system.cpu.rename.tempSerializingInsts 2643784 # count of temporary serializing insts renamed 634system.cpu.rename.skidInsts 13883095 # count of insts added to the skid buffer 635system.cpu.memDep0.insertedLoads 26339486 # Number of loads inserted to the mem dependence unit. 636system.cpu.memDep0.insertedStores 21214202 # Number of stores inserted to the mem dependence unit. 637system.cpu.memDep0.conflictingLoads 1704469 # Number of conflicting loads. 638system.cpu.memDep0.conflictingStores 2149070 # Number of conflicting stores. 639system.cpu.iq.iqInstsAdded 143218821 # Number of instructions added to the IQ (excludes non-spec) 640system.cpu.iq.iqNonSpecInstsAdded 2117732 # Number of non-speculative instructions added to the IQ 641system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued 642system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued 643system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling 644system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph 645system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed 646system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::stdev 0.865256 # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::0 182379693 67.41% 67.41% # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::1 45219625 16.71% 84.12% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::2 31881925 11.78% 95.91% # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::3 10262342 3.79% 99.70% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::4 817003 0.30% 100.00% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 662system.cpu.iq.issued_per_cycle::total 270560621 # Number of insts issued each cycle 663system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 664system.cpu.iq.fu_full::IntAlu 7341670 32.77% 32.77% # attempts to use FU when none available 665system.cpu.iq.fu_full::IntMult 32 0.00% 32.77% # attempts to use FU when none available 666system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available 667system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available 668system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available 669system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available 670system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available 672system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available 692system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available 693system.cpu.iq.fu_full::MemRead 5623214 25.10% 57.86% # attempts to use FU when none available 694system.cpu.iq.fu_full::MemWrite 9441955 42.14% 100.00% # attempts to use FU when none available 695system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 696system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 697system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued 698system.cpu.iq.FU_type_0::IntAlu 95844496 67.01% 67.01% # Type of FU issued 699system.cpu.iq.FU_type_0::IntMult 114325 0.08% 67.09% # Type of FU issued 700system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued 701system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued 702system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued 703system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued 704system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued 706system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.09% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.09% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatMisc 8580 0.01% 67.09% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.09% # Type of FU issued 726system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued 727system.cpu.iq.FU_type_0::MemRead 26129578 18.27% 85.36% # Type of FU issued 728system.cpu.iq.FU_type_0::MemWrite 20939362 14.64% 100.00% # Type of FU issued 729system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 730system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 731system.cpu.iq.FU_type_0::total 143038678 # Type of FU issued 732system.cpu.iq.rate 0.513744 # Inst issue rate 733system.cpu.iq.fu_busy_cnt 22406871 # FU busy when requested 734system.cpu.iq.fu_busy_rate 0.156649 # FU busy rate (busy events/executed inst) 735system.cpu.iq.int_inst_queue_reads 579270175 # Number of integer instruction queue reads 736system.cpu.iq.int_inst_queue_writes 153497654 # Number of integer instruction queue writes 737system.cpu.iq.int_inst_queue_wakeup_accesses 139987851 # Number of integer instruction queue wakeup accesses 738system.cpu.iq.fp_inst_queue_reads 35641 # Number of floating instruction queue reads 739system.cpu.iq.fp_inst_queue_writes 13126 # Number of floating instruction queue writes 740system.cpu.iq.fp_inst_queue_wakeup_accesses 11370 # Number of floating instruction queue wakeup accesses 741system.cpu.iq.int_alu_accesses 165419813 # Number of integer alu accesses 742system.cpu.iq.fp_alu_accesses 23399 # Number of floating point alu accesses 743system.cpu.iew.lsq.thread0.forwLoads 323906 # Number of loads that had data forwarded from stores 744system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 745system.cpu.iew.lsq.thread0.squashedLoads 1435915 # Number of loads squashed 746system.cpu.iew.lsq.thread0.ignoredResponses 710 # Number of memory responses ignored because the instruction is squashed 747system.cpu.iew.lsq.thread0.memOrderViolation 18680 # Number of memory ordering violations 748system.cpu.iew.lsq.thread0.squashedStores 623667 # Number of stores squashed 749system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 750system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 751system.cpu.iew.lsq.thread0.rescheduledLoads 88637 # Number of loads that were rescheduled 752system.cpu.iew.lsq.thread0.cacheBlocked 6231 # Number of times an access to memory failed due to the cache being blocked 753system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 754system.cpu.iew.iewSquashCycles 2569037 # Number of cycles IEW is squashing 755system.cpu.iew.iewBlockCycles 1239960 # Number of cycles IEW is blocking 756system.cpu.iew.iewUnblockCycles 546279 # Number of cycles IEW is unblocking 757system.cpu.iew.iewDispatchedInsts 145517187 # Number of instructions dispatched to IQ 758system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 759system.cpu.iew.iewDispLoadInsts 26339486 # Number of dispatched load instructions 760system.cpu.iew.iewDispStoreInsts 21214202 # Number of dispatched store instructions 761system.cpu.iew.iewDispNonSpecInsts 1094236 # Number of dispatched non-speculative instructions 762system.cpu.iew.iewIQFullEvents 17880 # Number of times the IQ has become full, causing a stall 763system.cpu.iew.iewLSQFullEvents 509843 # Number of times the LSQ has become full, causing a stall 764system.cpu.iew.memOrderViolationEvents 18680 # Number of memory order violations 765system.cpu.iew.predictedTakenIncorrect 277456 # Number of branches that were predicted taken incorrectly 766system.cpu.iew.predictedNotTakenIncorrect 471588 # Number of branches that were predicted not taken incorrectly 767system.cpu.iew.branchMispredicts 749044 # Number of branch mispredicts detected at execute 768system.cpu.iew.iewExecutedInsts 142138491 # Number of executed instructions 769system.cpu.iew.iewExecLoadInsts 25734027 # Number of load instructions executed 770system.cpu.iew.iewExecSquashedInsts 827925 # Number of squashed instructions skipped in execute 771system.cpu.iew.exec_swp 0 # number of swp insts executed 772system.cpu.iew.exec_nop 180634 # number of nop insts executed 773system.cpu.iew.exec_refs 46561433 # number of memory reference insts executed 774system.cpu.iew.exec_branches 26490215 # Number of branches executed 775system.cpu.iew.exec_stores 20827406 # Number of stores executed 776system.cpu.iew.exec_rate 0.510511 # Inst execution rate 777system.cpu.iew.wb_sent 141769563 # cumulative count of insts sent to commit 778system.cpu.iew.wb_count 139999221 # cumulative count of insts written-back 779system.cpu.iew.wb_producers 63237137 # num instructions producing a value 780system.cpu.iew.wb_consumers 95708450 # num instructions consuming a value 781system.cpu.iew.wb_rate 0.502828 # insts written-back per cycle 782system.cpu.iew.wb_fanout 0.660727 # average fanout of values written-back 783system.cpu.commit.commitSquashedInsts 7372199 # The number of squashed insts skipped by commit 784system.cpu.commit.commitNonSpecStalls 1995871 # The number of times commit has been forced to stall to communicate backwards 785system.cpu.commit.branchMispredicts 715636 # The number of times a branch was mispredicted 786system.cpu.commit.committed_per_cycle::samples 267668722 # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::mean 0.513081 # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::stdev 1.118378 # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::0 194241019 72.57% 72.57% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::1 43280697 16.17% 88.74% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::2 15455980 5.77% 94.51% # Number of insts commited each cycle 793system.cpu.commit.committed_per_cycle::3 4372366 1.63% 96.14% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::4 6407128 2.39% 98.54% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::5 1628567 0.61% 99.15% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::6 798346 0.30% 99.45% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::7 412274 0.15% 99.60% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::8 1072345 0.40% 100.00% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 802system.cpu.commit.committed_per_cycle::total 267668722 # Number of insts commited each cycle 803system.cpu.commit.committedInsts 113255406 # Number of instructions committed 804system.cpu.commit.committedOps 137335856 # Number of ops (including micro ops) committed 805system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 806system.cpu.commit.refs 45494106 # Number of memory references committed 807system.cpu.commit.loads 24903571 # Number of loads committed 808system.cpu.commit.membars 814876 # Number of memory barriers committed 809system.cpu.commit.branches 26023568 # Number of branches committed 810system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. 811system.cpu.commit.int_insts 120163713 # Number of committed integer instructions. 812system.cpu.commit.function_calls 4884102 # Number of function calls committed. 813system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 814system.cpu.commit.op_class_0::IntAlu 91720354 66.79% 66.79% # Class of committed instruction 815system.cpu.commit.op_class_0::IntMult 112817 0.08% 66.87% # Class of committed instruction 816system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction 817system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction 818system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction 819system.cpu.commit.op_class_0::FloatCvt 0 0.00% 66.87% # Class of committed instruction 820system.cpu.commit.op_class_0::FloatMult 0 0.00% 66.87% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatDiv 0 0.00% 66.87% # Class of committed instruction 822system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.87% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.87% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.87% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.87% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.87% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.87% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.87% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.87% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.87% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.87% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.87% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.87% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.87% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatMisc 8579 0.01% 66.87% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction 842system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction 843system.cpu.commit.op_class_0::MemRead 24903571 18.13% 85.01% # Class of committed instruction 844system.cpu.commit.op_class_0::MemWrite 20590535 14.99% 100.00% # Class of committed instruction 845system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 846system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 847system.cpu.commit.op_class_0::total 137335856 # Class of committed instruction 848system.cpu.commit.bw_lim_events 1072345 # number cycles where commit BW limit reached 849system.cpu.rob.rob_reads 389119868 # The number of ROB reads 850system.cpu.rob.rob_writes 292294903 # The number of ROB writes 851system.cpu.timesIdled 890799 # Number of times that the entire CPU went into an idle state and unscheduled itself 852system.cpu.idleCycles 7863330 # Total number of cycles that the CPU has spent unscheduled due to idling 853system.cpu.quiesceCycles 5387302003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 854system.cpu.committedInsts 113100501 # Number of Instructions Simulated 855system.cpu.committedOps 137180951 # Number of Ops (including micro ops) Simulated 856system.cpu.cpi 2.461739 # CPI: Cycles Per Instruction 857system.cpu.cpi_total 2.461739 # CPI: Total CPI of All Threads 858system.cpu.ipc 0.406217 # IPC: Instructions Per Cycle 859system.cpu.ipc_total 0.406217 # IPC: Total IPC of All Threads 860system.cpu.int_regfile_reads 155524954 # number of integer regfile reads 861system.cpu.int_regfile_writes 88488761 # number of integer regfile writes 862system.cpu.fp_regfile_reads 9529 # number of floating regfile reads 863system.cpu.fp_regfile_writes 2716 # number of floating regfile writes 864system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads 865system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes 866system.cpu.misc_regfile_reads 459440694 # number of misc regfile reads 867system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes 868system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 869system.cpu.dcache.tags.replacements 838747 # number of replacements 870system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use 871system.cpu.dcache.tags.total_refs 40056711 # Total number of references to valid blocks. 872system.cpu.dcache.tags.sampled_refs 839259 # Sample count of references to valid blocks. 873system.cpu.dcache.tags.avg_refs 47.728664 # Average number of references to valid blocks. 874system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. 875system.cpu.dcache.tags.occ_blocks::cpu.data 511.925928 # Average occupied blocks per requestor 876system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy 877system.cpu.dcache.tags.occ_percent::total 0.999855 # Average percentage of cache occupancy 878system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 880system.cpu.dcache.tags.age_task_id_blocks_1024::1 356 # Occupied blocks per task id 881system.cpu.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 882system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 883system.cpu.dcache.tags.tag_accesses 179125109 # Number of tag accesses 884system.cpu.dcache.tags.data_accesses 179125109 # Number of data accesses 885system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 886system.cpu.dcache.ReadReq_hits::cpu.data 23264148 # number of ReadReq hits 887system.cpu.dcache.ReadReq_hits::total 23264148 # number of ReadReq hits 888system.cpu.dcache.WriteReq_hits::cpu.data 15542286 # number of WriteReq hits 889system.cpu.dcache.WriteReq_hits::total 15542286 # number of WriteReq hits 890system.cpu.dcache.SoftPFReq_hits::cpu.data 345698 # number of SoftPFReq hits 891system.cpu.dcache.SoftPFReq_hits::total 345698 # number of SoftPFReq hits 892system.cpu.dcache.LoadLockedReq_hits::cpu.data 441334 # number of LoadLockedReq hits 893system.cpu.dcache.LoadLockedReq_hits::total 441334 # number of LoadLockedReq hits 894system.cpu.dcache.StoreCondReq_hits::cpu.data 460350 # number of StoreCondReq hits 895system.cpu.dcache.StoreCondReq_hits::total 460350 # number of StoreCondReq hits 896system.cpu.dcache.demand_hits::cpu.data 38806434 # number of demand (read+write) hits 897system.cpu.dcache.demand_hits::total 38806434 # number of demand (read+write) hits 898system.cpu.dcache.overall_hits::cpu.data 39152132 # number of overall hits 899system.cpu.dcache.overall_hits::total 39152132 # number of overall hits 900system.cpu.dcache.ReadReq_misses::cpu.data 705134 # number of ReadReq misses 901system.cpu.dcache.ReadReq_misses::total 705134 # number of ReadReq misses 902system.cpu.dcache.WriteReq_misses::cpu.data 3607427 # number of WriteReq misses 903system.cpu.dcache.WriteReq_misses::total 3607427 # number of WriteReq misses 904system.cpu.dcache.SoftPFReq_misses::cpu.data 177712 # number of SoftPFReq misses 905system.cpu.dcache.SoftPFReq_misses::total 177712 # number of SoftPFReq misses 906system.cpu.dcache.LoadLockedReq_misses::cpu.data 27363 # number of LoadLockedReq misses 907system.cpu.dcache.LoadLockedReq_misses::total 27363 # number of LoadLockedReq misses 908system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 909system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 910system.cpu.dcache.demand_misses::cpu.data 4312561 # number of demand (read+write) misses 911system.cpu.dcache.demand_misses::total 4312561 # number of demand (read+write) misses 912system.cpu.dcache.overall_misses::cpu.data 4490273 # number of overall misses 913system.cpu.dcache.overall_misses::total 4490273 # number of overall misses 914system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711380000 # number of ReadReq miss cycles 915system.cpu.dcache.ReadReq_miss_latency::total 11711380000 # number of ReadReq miss cycles 916system.cpu.dcache.WriteReq_miss_latency::cpu.data 232487777697 # number of WriteReq miss cycles 917system.cpu.dcache.WriteReq_miss_latency::total 232487777697 # number of WriteReq miss cycles 918system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376699000 # number of LoadLockedReq miss cycles 919system.cpu.dcache.LoadLockedReq_miss_latency::total 376699000 # number of LoadLockedReq miss cycles 920system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276000 # number of StoreCondReq miss cycles 921system.cpu.dcache.StoreCondReq_miss_latency::total 276000 # number of StoreCondReq miss cycles 922system.cpu.dcache.demand_miss_latency::cpu.data 244199157697 # number of demand (read+write) miss cycles 923system.cpu.dcache.demand_miss_latency::total 244199157697 # number of demand (read+write) miss cycles 924system.cpu.dcache.overall_miss_latency::cpu.data 244199157697 # number of overall miss cycles 925system.cpu.dcache.overall_miss_latency::total 244199157697 # number of overall miss cycles 926system.cpu.dcache.ReadReq_accesses::cpu.data 23969282 # number of ReadReq accesses(hits+misses) 927system.cpu.dcache.ReadReq_accesses::total 23969282 # number of ReadReq accesses(hits+misses) 928system.cpu.dcache.WriteReq_accesses::cpu.data 19149713 # number of WriteReq accesses(hits+misses) 929system.cpu.dcache.WriteReq_accesses::total 19149713 # number of WriteReq accesses(hits+misses) 930system.cpu.dcache.SoftPFReq_accesses::cpu.data 523410 # number of SoftPFReq accesses(hits+misses) 931system.cpu.dcache.SoftPFReq_accesses::total 523410 # number of SoftPFReq accesses(hits+misses) 932system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468697 # number of LoadLockedReq accesses(hits+misses) 933system.cpu.dcache.LoadLockedReq_accesses::total 468697 # number of LoadLockedReq accesses(hits+misses) 934system.cpu.dcache.StoreCondReq_accesses::cpu.data 460355 # number of StoreCondReq accesses(hits+misses) 935system.cpu.dcache.StoreCondReq_accesses::total 460355 # number of StoreCondReq accesses(hits+misses) 936system.cpu.dcache.demand_accesses::cpu.data 43118995 # number of demand (read+write) accesses 937system.cpu.dcache.demand_accesses::total 43118995 # number of demand (read+write) accesses 938system.cpu.dcache.overall_accesses::cpu.data 43642405 # number of overall (read+write) accesses 939system.cpu.dcache.overall_accesses::total 43642405 # number of overall (read+write) accesses 940system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029418 # miss rate for ReadReq accesses 941system.cpu.dcache.ReadReq_miss_rate::total 0.029418 # miss rate for ReadReq accesses 942system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188380 # miss rate for WriteReq accesses 943system.cpu.dcache.WriteReq_miss_rate::total 0.188380 # miss rate for WriteReq accesses 944system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339527 # miss rate for SoftPFReq accesses 945system.cpu.dcache.SoftPFReq_miss_rate::total 0.339527 # miss rate for SoftPFReq accesses 946system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.058381 # miss rate for LoadLockedReq accesses 947system.cpu.dcache.LoadLockedReq_miss_rate::total 0.058381 # miss rate for LoadLockedReq accesses 948system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses 949system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses 950system.cpu.dcache.demand_miss_rate::cpu.data 0.100015 # miss rate for demand accesses 951system.cpu.dcache.demand_miss_rate::total 0.100015 # miss rate for demand accesses 952system.cpu.dcache.overall_miss_rate::cpu.data 0.102888 # miss rate for overall accesses 953system.cpu.dcache.overall_miss_rate::total 0.102888 # miss rate for overall accesses 954system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16608.729688 # average ReadReq miss latency 955system.cpu.dcache.ReadReq_avg_miss_latency::total 16608.729688 # average ReadReq miss latency 956system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64446.980548 # average WriteReq miss latency 957system.cpu.dcache.WriteReq_avg_miss_latency::total 64446.980548 # average WriteReq miss latency 958system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.728794 # average LoadLockedReq miss latency 959system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.728794 # average LoadLockedReq miss latency 960system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 55200 # average StoreCondReq miss latency 961system.cpu.dcache.StoreCondReq_avg_miss_latency::total 55200 # average StoreCondReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 56625.090682 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 56625.090682 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 54384.033598 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 54384.033598 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 871366 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 6856 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.095391 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 972system.cpu.dcache.writebacks::writebacks 696773 # number of writebacks 973system.cpu.dcache.writebacks::total 696773 # number of writebacks 974system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291027 # number of ReadReq MSHR hits 975system.cpu.dcache.ReadReq_mshr_hits::total 291027 # number of ReadReq MSHR hits 976system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3307518 # number of WriteReq MSHR hits 977system.cpu.dcache.WriteReq_mshr_hits::total 3307518 # number of WriteReq MSHR hits 978system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18885 # number of LoadLockedReq MSHR hits 979system.cpu.dcache.LoadLockedReq_mshr_hits::total 18885 # number of LoadLockedReq MSHR hits 980system.cpu.dcache.demand_mshr_hits::cpu.data 3598545 # number of demand (read+write) MSHR hits 981system.cpu.dcache.demand_mshr_hits::total 3598545 # number of demand (read+write) MSHR hits 982system.cpu.dcache.overall_mshr_hits::cpu.data 3598545 # number of overall MSHR hits 983system.cpu.dcache.overall_mshr_hits::total 3598545 # number of overall MSHR hits 984system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414107 # number of ReadReq MSHR misses 985system.cpu.dcache.ReadReq_mshr_misses::total 414107 # number of ReadReq MSHR misses 986system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299909 # number of WriteReq MSHR misses 987system.cpu.dcache.WriteReq_mshr_misses::total 299909 # number of WriteReq MSHR misses 988system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119568 # number of SoftPFReq MSHR misses 989system.cpu.dcache.SoftPFReq_mshr_misses::total 119568 # number of SoftPFReq MSHR misses 990system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8478 # number of LoadLockedReq MSHR misses 991system.cpu.dcache.LoadLockedReq_mshr_misses::total 8478 # number of LoadLockedReq MSHR misses 992system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 993system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 994system.cpu.dcache.demand_mshr_misses::cpu.data 714016 # number of demand (read+write) MSHR misses 995system.cpu.dcache.demand_mshr_misses::total 714016 # number of demand (read+write) MSHR misses 996system.cpu.dcache.overall_mshr_misses::cpu.data 833584 # number of overall MSHR misses 997system.cpu.dcache.overall_mshr_misses::total 833584 # number of overall MSHR misses 998system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 999system.cpu.dcache.ReadReq_mshr_uncacheable::total 31129 # number of ReadReq MSHR uncacheable 1000system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1001system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1002system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1003system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses 1004system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6386388500 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_latency::total 6386388500 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19974009472 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 19974009472 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699913000 # number of SoftPFReq MSHR miss cycles 1009system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699913000 # number of SoftPFReq MSHR miss cycles 1010system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 127031000 # number of LoadLockedReq MSHR miss cycles 1011system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 127031000 # number of LoadLockedReq MSHR miss cycles 1012system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271000 # number of StoreCondReq MSHR miss cycles 1013system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271000 # number of StoreCondReq MSHR miss cycles 1014system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26360397972 # number of demand (read+write) MSHR miss cycles 1015system.cpu.dcache.demand_mshr_miss_latency::total 26360397972 # number of demand (read+write) MSHR miss cycles 1016system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28060310972 # number of overall MSHR miss cycles 1017system.cpu.dcache.overall_mshr_miss_latency::total 28060310972 # number of overall MSHR miss cycles 1018system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276272000 # number of ReadReq MSHR uncacheable cycles 1019system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276272000 # number of ReadReq MSHR uncacheable cycles 1020system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6276272000 # number of overall MSHR uncacheable cycles 1021system.cpu.dcache.overall_mshr_uncacheable_latency::total 6276272000 # number of overall MSHR uncacheable cycles 1022system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017277 # mshr miss rate for ReadReq accesses 1023system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017277 # mshr miss rate for ReadReq accesses 1024system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015661 # mshr miss rate for WriteReq accesses 1025system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015661 # mshr miss rate for WriteReq accesses 1026system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228440 # mshr miss rate for SoftPFReq accesses 1027system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228440 # mshr miss rate for SoftPFReq accesses 1028system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018088 # mshr miss rate for LoadLockedReq accesses 1029system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018088 # mshr miss rate for LoadLockedReq accesses 1030system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses 1031system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses 1032system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016559 # mshr miss rate for demand accesses 1033system.cpu.dcache.demand_mshr_miss_rate::total 0.016559 # mshr miss rate for demand accesses 1034system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019100 # mshr miss rate for overall accesses 1035system.cpu.dcache.overall_mshr_miss_rate::total 0.019100 # mshr miss rate for overall accesses 1036system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15422.073281 # average ReadReq mshr miss latency 1037system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15422.073281 # average ReadReq mshr miss latency 1038system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66600.233644 # average WriteReq mshr miss latency 1039system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66600.233644 # average WriteReq mshr miss latency 1040system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.123311 # average SoftPFReq mshr miss latency 1041system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.123311 # average SoftPFReq mshr miss latency 1042system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14983.604624 # average LoadLockedReq mshr miss latency 1043system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14983.604624 # average LoadLockedReq mshr miss latency 1044system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54200 # average StoreCondReq mshr miss latency 1045system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54200 # average StoreCondReq mshr miss latency 1046system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36918.497585 # average overall mshr miss latency 1047system.cpu.dcache.demand_avg_mshr_miss_latency::total 36918.497585 # average overall mshr miss latency 1048system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33662.247562 # average overall mshr miss latency 1049system.cpu.dcache.overall_avg_mshr_miss_latency::total 33662.247562 # average overall mshr miss latency 1050system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201621.381991 # average ReadReq mshr uncacheable latency 1051system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201621.381991 # average ReadReq mshr uncacheable latency 1052system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 106895.663726 # average overall mshr uncacheable latency 1053system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 106895.663726 # average overall mshr uncacheable latency 1054system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1055system.cpu.icache.tags.replacements 1886245 # number of replacements 1056system.cpu.icache.tags.tagsinuse 511.154077 # Cycle average of tags in use 1057system.cpu.icache.tags.total_refs 64013417 # Total number of references to valid blocks. 1058system.cpu.icache.tags.sampled_refs 1886757 # Sample count of references to valid blocks. 1059system.cpu.icache.tags.avg_refs 33.927749 # Average number of references to valid blocks. 1060system.cpu.icache.tags.warmup_cycle 16319051500 # Cycle when the warmup percentage was hit. 1061system.cpu.icache.tags.occ_blocks::cpu.inst 511.154077 # Average occupied blocks per requestor 1062system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy 1063system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy 1064system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1065system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 1066system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 1067system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id 1068system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1069system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1070system.cpu.icache.tags.tag_accesses 67878198 # Number of tag accesses 1071system.cpu.icache.tags.data_accesses 67878198 # Number of data accesses 1072system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1073system.cpu.icache.ReadReq_hits::cpu.inst 64013417 # number of ReadReq hits 1074system.cpu.icache.ReadReq_hits::total 64013417 # number of ReadReq hits 1075system.cpu.icache.demand_hits::cpu.inst 64013417 # number of demand (read+write) hits 1076system.cpu.icache.demand_hits::total 64013417 # number of demand (read+write) hits 1077system.cpu.icache.overall_hits::cpu.inst 64013417 # number of overall hits 1078system.cpu.icache.overall_hits::total 64013417 # number of overall hits 1079system.cpu.icache.ReadReq_misses::cpu.inst 1977977 # number of ReadReq misses 1080system.cpu.icache.ReadReq_misses::total 1977977 # number of ReadReq misses 1081system.cpu.icache.demand_misses::cpu.inst 1977977 # number of demand (read+write) misses 1082system.cpu.icache.demand_misses::total 1977977 # number of demand (read+write) misses 1083system.cpu.icache.overall_misses::cpu.inst 1977977 # number of overall misses 1084system.cpu.icache.overall_misses::total 1977977 # number of overall misses 1085system.cpu.icache.ReadReq_miss_latency::cpu.inst 28160163493 # number of ReadReq miss cycles 1086system.cpu.icache.ReadReq_miss_latency::total 28160163493 # number of ReadReq miss cycles 1087system.cpu.icache.demand_miss_latency::cpu.inst 28160163493 # number of demand (read+write) miss cycles 1088system.cpu.icache.demand_miss_latency::total 28160163493 # number of demand (read+write) miss cycles 1089system.cpu.icache.overall_miss_latency::cpu.inst 28160163493 # number of overall miss cycles 1090system.cpu.icache.overall_miss_latency::total 28160163493 # number of overall miss cycles 1091system.cpu.icache.ReadReq_accesses::cpu.inst 65991394 # number of ReadReq accesses(hits+misses) 1092system.cpu.icache.ReadReq_accesses::total 65991394 # number of ReadReq accesses(hits+misses) 1093system.cpu.icache.demand_accesses::cpu.inst 65991394 # number of demand (read+write) accesses 1094system.cpu.icache.demand_accesses::total 65991394 # number of demand (read+write) accesses 1095system.cpu.icache.overall_accesses::cpu.inst 65991394 # number of overall (read+write) accesses 1096system.cpu.icache.overall_accesses::total 65991394 # number of overall (read+write) accesses 1097system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029973 # miss rate for ReadReq accesses 1098system.cpu.icache.ReadReq_miss_rate::total 0.029973 # miss rate for ReadReq accesses 1099system.cpu.icache.demand_miss_rate::cpu.inst 0.029973 # miss rate for demand accesses 1100system.cpu.icache.demand_miss_rate::total 0.029973 # miss rate for demand accesses 1101system.cpu.icache.overall_miss_rate::cpu.inst 0.029973 # miss rate for overall accesses 1102system.cpu.icache.overall_miss_rate::total 0.029973 # miss rate for overall accesses 1103system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14236.850829 # average ReadReq miss latency 1104system.cpu.icache.ReadReq_avg_miss_latency::total 14236.850829 # average ReadReq miss latency 1105system.cpu.icache.demand_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency 1106system.cpu.icache.demand_avg_miss_latency::total 14236.850829 # average overall miss latency 1107system.cpu.icache.overall_avg_miss_latency::cpu.inst 14236.850829 # average overall miss latency 1108system.cpu.icache.overall_avg_miss_latency::total 14236.850829 # average overall miss latency 1109system.cpu.icache.blocked_cycles::no_mshrs 6440 # number of cycles access was blocked 1110system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1111system.cpu.icache.blocked::no_mshrs 190 # number of cycles access was blocked 1112system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1113system.cpu.icache.avg_blocked_cycles::no_mshrs 33.894737 # average number of cycles each access was blocked 1114system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu.icache.writebacks::writebacks 1886245 # number of writebacks 1116system.cpu.icache.writebacks::total 1886245 # number of writebacks 1117system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91172 # number of ReadReq MSHR hits 1118system.cpu.icache.ReadReq_mshr_hits::total 91172 # number of ReadReq MSHR hits 1119system.cpu.icache.demand_mshr_hits::cpu.inst 91172 # number of demand (read+write) MSHR hits 1120system.cpu.icache.demand_mshr_hits::total 91172 # number of demand (read+write) MSHR hits 1121system.cpu.icache.overall_mshr_hits::cpu.inst 91172 # number of overall MSHR hits 1122system.cpu.icache.overall_mshr_hits::total 91172 # number of overall MSHR hits 1123system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1886805 # number of ReadReq MSHR misses 1124system.cpu.icache.ReadReq_mshr_misses::total 1886805 # number of ReadReq MSHR misses 1125system.cpu.icache.demand_mshr_misses::cpu.inst 1886805 # number of demand (read+write) MSHR misses 1126system.cpu.icache.demand_mshr_misses::total 1886805 # number of demand (read+write) MSHR misses 1127system.cpu.icache.overall_mshr_misses::cpu.inst 1886805 # number of overall MSHR misses 1128system.cpu.icache.overall_mshr_misses::total 1886805 # number of overall MSHR misses 1129system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1130system.cpu.icache.ReadReq_mshr_uncacheable::total 3003 # number of ReadReq MSHR uncacheable 1131system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1132system.cpu.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses 1133system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25187429497 # number of ReadReq MSHR miss cycles 1134system.cpu.icache.ReadReq_mshr_miss_latency::total 25187429497 # number of ReadReq MSHR miss cycles 1135system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25187429497 # number of demand (read+write) MSHR miss cycles 1136system.cpu.icache.demand_mshr_miss_latency::total 25187429497 # number of demand (read+write) MSHR miss cycles 1137system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25187429497 # number of overall MSHR miss cycles 1138system.cpu.icache.overall_mshr_miss_latency::total 25187429497 # number of overall MSHR miss cycles 1139system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 377605500 # number of ReadReq MSHR uncacheable cycles 1140system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 377605500 # number of ReadReq MSHR uncacheable cycles 1141system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 377605500 # number of overall MSHR uncacheable cycles 1142system.cpu.icache.overall_mshr_uncacheable_latency::total 377605500 # number of overall MSHR uncacheable cycles 1143system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for ReadReq accesses 1144system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028592 # mshr miss rate for ReadReq accesses 1145system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for demand accesses 1146system.cpu.icache.demand_mshr_miss_rate::total 0.028592 # mshr miss rate for demand accesses 1147system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028592 # mshr miss rate for overall accesses 1148system.cpu.icache.overall_mshr_miss_rate::total 0.028592 # mshr miss rate for overall accesses 1149system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13349.248861 # average ReadReq mshr miss latency 1150system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13349.248861 # average ReadReq mshr miss latency 1151system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1152system.cpu.icache.demand_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1153system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13349.248861 # average overall mshr miss latency 1154system.cpu.icache.overall_avg_mshr_miss_latency::total 13349.248861 # average overall mshr miss latency 1155system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average ReadReq mshr uncacheable latency 1156system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 125742.757243 # average ReadReq mshr uncacheable latency 1157system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 125742.757243 # average overall mshr uncacheable latency 1158system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 125742.757243 # average overall mshr uncacheable latency 1159system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1160system.cpu.l2cache.tags.replacements 96776 # number of replacements 1161system.cpu.l2cache.tags.tagsinuse 65028.780058 # Cycle average of tags in use 1162system.cpu.l2cache.tags.total_refs 5006507 # Total number of references to valid blocks. 1163system.cpu.l2cache.tags.sampled_refs 162101 # Sample count of references to valid blocks. 1164system.cpu.l2cache.tags.avg_refs 30.885109 # Average number of references to valid blocks. 1165system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1166system.cpu.l2cache.tags.occ_blocks::writebacks 49620.305059 # Average occupied blocks per requestor 1167system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.737497 # Average occupied blocks per requestor 1168system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.672900 # Average occupied blocks per requestor 1169system.cpu.l2cache.tags.occ_blocks::cpu.inst 10369.952431 # Average occupied blocks per requestor 1170system.cpu.l2cache.tags.occ_blocks::cpu.data 5025.112172 # Average occupied blocks per requestor 1171system.cpu.l2cache.tags.occ_percent::writebacks 0.757146 # Average percentage of cache occupancy 1172system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000164 # Average percentage of cache occupancy 1173system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000041 # Average percentage of cache occupancy 1174system.cpu.l2cache.tags.occ_percent::cpu.inst 0.158233 # Average percentage of cache occupancy 1175system.cpu.l2cache.tags.occ_percent::cpu.data 0.076677 # Average percentage of cache occupancy 1176system.cpu.l2cache.tags.occ_percent::total 0.992260 # Average percentage of cache occupancy 1177system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1178system.cpu.l2cache.tags.occ_task_id_blocks::1024 65312 # Occupied blocks per task id 1179system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1180system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 1181system.cpu.l2cache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id 1182system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1183system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6691 # Occupied blocks per task id 1184system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55601 # Occupied blocks per task id 1185system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id 1186system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996582 # Percentage of cache occupancy per task id 1187system.cpu.l2cache.tags.tag_accesses 44296182 # Number of tag accesses 1188system.cpu.l2cache.tags.data_accesses 44296182 # Number of data accesses 1189system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1190system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 58073 # number of ReadReq hits 1191system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12060 # number of ReadReq hits 1192system.cpu.l2cache.ReadReq_hits::total 70133 # number of ReadReq hits 1193system.cpu.l2cache.WritebackDirty_hits::writebacks 696773 # number of WritebackDirty hits 1194system.cpu.l2cache.WritebackDirty_hits::total 696773 # number of WritebackDirty hits 1195system.cpu.l2cache.WritebackClean_hits::writebacks 1848340 # number of WritebackClean hits 1196system.cpu.l2cache.WritebackClean_hits::total 1848340 # number of WritebackClean hits 1197system.cpu.l2cache.UpgradeReq_hits::cpu.data 62 # number of UpgradeReq hits 1198system.cpu.l2cache.UpgradeReq_hits::total 62 # number of UpgradeReq hits 1199system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1200system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1201system.cpu.l2cache.ReadExReq_hits::cpu.data 161752 # number of ReadExReq hits 1202system.cpu.l2cache.ReadExReq_hits::total 161752 # number of ReadExReq hits 1203system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1866806 # number of ReadCleanReq hits 1204system.cpu.l2cache.ReadCleanReq_hits::total 1866806 # number of ReadCleanReq hits 1205system.cpu.l2cache.ReadSharedReq_hits::cpu.data 528684 # number of ReadSharedReq hits 1206system.cpu.l2cache.ReadSharedReq_hits::total 528684 # number of ReadSharedReq hits 1207system.cpu.l2cache.demand_hits::cpu.dtb.walker 58073 # number of demand (read+write) hits 1208system.cpu.l2cache.demand_hits::cpu.itb.walker 12060 # number of demand (read+write) hits 1209system.cpu.l2cache.demand_hits::cpu.inst 1866806 # number of demand (read+write) hits 1210system.cpu.l2cache.demand_hits::cpu.data 690436 # number of demand (read+write) hits 1211system.cpu.l2cache.demand_hits::total 2627375 # number of demand (read+write) hits 1212system.cpu.l2cache.overall_hits::cpu.dtb.walker 58073 # number of overall hits 1213system.cpu.l2cache.overall_hits::cpu.itb.walker 12060 # number of overall hits 1214system.cpu.l2cache.overall_hits::cpu.inst 1866806 # number of overall hits 1215system.cpu.l2cache.overall_hits::cpu.data 690436 # number of overall hits 1216system.cpu.l2cache.overall_hits::total 2627375 # number of overall hits 1217system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 1218system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 1219system.cpu.l2cache.ReadReq_misses::total 25 # number of ReadReq misses 1220system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 1221system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 1222system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1223system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1224system.cpu.l2cache.ReadExReq_misses::cpu.data 135508 # number of ReadExReq misses 1225system.cpu.l2cache.ReadExReq_misses::total 135508 # number of ReadExReq misses 1226system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19911 # number of ReadCleanReq misses 1227system.cpu.l2cache.ReadCleanReq_misses::total 19911 # number of ReadCleanReq misses 1228system.cpu.l2cache.ReadSharedReq_misses::cpu.data 13337 # number of ReadSharedReq misses 1229system.cpu.l2cache.ReadSharedReq_misses::total 13337 # number of ReadSharedReq misses 1230system.cpu.l2cache.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 1231system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 1232system.cpu.l2cache.demand_misses::cpu.inst 19911 # number of demand (read+write) misses 1233system.cpu.l2cache.demand_misses::cpu.data 148845 # number of demand (read+write) misses 1234system.cpu.l2cache.demand_misses::total 168781 # number of demand (read+write) misses 1235system.cpu.l2cache.overall_misses::cpu.dtb.walker 19 # number of overall misses 1236system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 1237system.cpu.l2cache.overall_misses::cpu.inst 19911 # number of overall misses 1238system.cpu.l2cache.overall_misses::cpu.data 148845 # number of overall misses 1239system.cpu.l2cache.overall_misses::total 168781 # number of overall misses 1240system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2632000 # number of ReadReq miss cycles 1241system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 795500 # number of ReadReq miss cycles 1242system.cpu.l2cache.ReadReq_miss_latency::total 3427500 # number of ReadReq miss cycles 1243system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 2731500 # number of UpgradeReq miss cycles 1244system.cpu.l2cache.UpgradeReq_miss_latency::total 2731500 # number of UpgradeReq miss cycles 1245system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162000 # number of SCUpgradeReq miss cycles 1246system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles 1247system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 17610608500 # number of ReadExReq miss cycles 1248system.cpu.l2cache.ReadExReq_miss_latency::total 17610608500 # number of ReadExReq miss cycles 1249system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2638749000 # number of ReadCleanReq miss cycles 1250system.cpu.l2cache.ReadCleanReq_miss_latency::total 2638749000 # number of ReadCleanReq miss cycles 1251system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1798280000 # number of ReadSharedReq miss cycles 1252system.cpu.l2cache.ReadSharedReq_miss_latency::total 1798280000 # number of ReadSharedReq miss cycles 1253system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2632000 # number of demand (read+write) miss cycles 1254system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 795500 # number of demand (read+write) miss cycles 1255system.cpu.l2cache.demand_miss_latency::cpu.inst 2638749000 # number of demand (read+write) miss cycles 1256system.cpu.l2cache.demand_miss_latency::cpu.data 19408888500 # number of demand (read+write) miss cycles 1257system.cpu.l2cache.demand_miss_latency::total 22051065000 # number of demand (read+write) miss cycles 1258system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2632000 # number of overall miss cycles 1259system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 795500 # number of overall miss cycles 1260system.cpu.l2cache.overall_miss_latency::cpu.inst 2638749000 # number of overall miss cycles 1261system.cpu.l2cache.overall_miss_latency::cpu.data 19408888500 # number of overall miss cycles 1262system.cpu.l2cache.overall_miss_latency::total 22051065000 # number of overall miss cycles 1263system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 58092 # number of ReadReq accesses(hits+misses) 1264system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12066 # number of ReadReq accesses(hits+misses) 1265system.cpu.l2cache.ReadReq_accesses::total 70158 # number of ReadReq accesses(hits+misses) 1266system.cpu.l2cache.WritebackDirty_accesses::writebacks 696773 # number of WritebackDirty accesses(hits+misses) 1267system.cpu.l2cache.WritebackDirty_accesses::total 696773 # number of WritebackDirty accesses(hits+misses) 1268system.cpu.l2cache.WritebackClean_accesses::writebacks 1848340 # number of WritebackClean accesses(hits+misses) 1269system.cpu.l2cache.WritebackClean_accesses::total 1848340 # number of WritebackClean accesses(hits+misses) 1270system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2781 # number of UpgradeReq accesses(hits+misses) 1271system.cpu.l2cache.UpgradeReq_accesses::total 2781 # number of UpgradeReq accesses(hits+misses) 1272system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1273system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1274system.cpu.l2cache.ReadExReq_accesses::cpu.data 297260 # number of ReadExReq accesses(hits+misses) 1275system.cpu.l2cache.ReadExReq_accesses::total 297260 # number of ReadExReq accesses(hits+misses) 1276system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1886717 # number of ReadCleanReq accesses(hits+misses) 1277system.cpu.l2cache.ReadCleanReq_accesses::total 1886717 # number of ReadCleanReq accesses(hits+misses) 1278system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542021 # number of ReadSharedReq accesses(hits+misses) 1279system.cpu.l2cache.ReadSharedReq_accesses::total 542021 # number of ReadSharedReq accesses(hits+misses) 1280system.cpu.l2cache.demand_accesses::cpu.dtb.walker 58092 # number of demand (read+write) accesses 1281system.cpu.l2cache.demand_accesses::cpu.itb.walker 12066 # number of demand (read+write) accesses 1282system.cpu.l2cache.demand_accesses::cpu.inst 1886717 # number of demand (read+write) accesses 1283system.cpu.l2cache.demand_accesses::cpu.data 839281 # number of demand (read+write) accesses 1284system.cpu.l2cache.demand_accesses::total 2796156 # number of demand (read+write) accesses 1285system.cpu.l2cache.overall_accesses::cpu.dtb.walker 58092 # number of overall (read+write) accesses 1286system.cpu.l2cache.overall_accesses::cpu.itb.walker 12066 # number of overall (read+write) accesses 1287system.cpu.l2cache.overall_accesses::cpu.inst 1886717 # number of overall (read+write) accesses 1288system.cpu.l2cache.overall_accesses::cpu.data 839281 # number of overall (read+write) accesses 1289system.cpu.l2cache.overall_accesses::total 2796156 # number of overall (read+write) accesses 1290system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000327 # miss rate for ReadReq accesses 1291system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000497 # miss rate for ReadReq accesses 1292system.cpu.l2cache.ReadReq_miss_rate::total 0.000356 # miss rate for ReadReq accesses 1293system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.977706 # miss rate for UpgradeReq accesses 1294system.cpu.l2cache.UpgradeReq_miss_rate::total 0.977706 # miss rate for UpgradeReq accesses 1295system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 1296system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 1297system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455857 # miss rate for ReadExReq accesses 1298system.cpu.l2cache.ReadExReq_miss_rate::total 0.455857 # miss rate for ReadExReq accesses 1299system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010553 # miss rate for ReadCleanReq accesses 1300system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010553 # miss rate for ReadCleanReq accesses 1301system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024606 # miss rate for ReadSharedReq accesses 1302system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024606 # miss rate for ReadSharedReq accesses 1303system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000327 # miss rate for demand accesses 1304system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000497 # miss rate for demand accesses 1305system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010553 # miss rate for demand accesses 1306system.cpu.l2cache.demand_miss_rate::cpu.data 0.177348 # miss rate for demand accesses 1307system.cpu.l2cache.demand_miss_rate::total 0.060362 # miss rate for demand accesses 1308system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000327 # miss rate for overall accesses 1309system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000497 # miss rate for overall accesses 1310system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010553 # miss rate for overall accesses 1311system.cpu.l2cache.overall_miss_rate::cpu.data 0.177348 # miss rate for overall accesses 1312system.cpu.l2cache.overall_miss_rate::total 0.060362 # miss rate for overall accesses 1313system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 138526.315789 # average ReadReq miss latency 1314system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132583.333333 # average ReadReq miss latency 1315system.cpu.l2cache.ReadReq_avg_miss_latency::total 137100 # average ReadReq miss latency 1316system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 1004.597278 # average UpgradeReq miss latency 1317system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 1004.597278 # average UpgradeReq miss latency 1318system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency 1319system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency 1320system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129959.917496 # average ReadExReq miss latency 1321system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129959.917496 # average ReadExReq miss latency 1322system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132527.196022 # average ReadCleanReq miss latency 1323system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132527.196022 # average ReadCleanReq miss latency 1324system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134833.920672 # average ReadSharedReq miss latency 1325system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134833.920672 # average ReadSharedReq miss latency 1326system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency 1327system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency 1328system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency 1329system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency 1330system.cpu.l2cache.demand_avg_miss_latency::total 130648.977077 # average overall miss latency 1331system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 138526.315789 # average overall miss latency 1332system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132583.333333 # average overall miss latency 1333system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132527.196022 # average overall miss latency 1334system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130396.644160 # average overall miss latency 1335system.cpu.l2cache.overall_avg_miss_latency::total 130648.977077 # average overall miss latency 1336system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1337system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1338system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1339system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1340system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1341system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1342system.cpu.l2cache.writebacks::writebacks 89222 # number of writebacks 1343system.cpu.l2cache.writebacks::total 89222 # number of writebacks 1344system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits 1345system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits 1346system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits 1347system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits 1348system.cpu.l2cache.demand_mshr_hits::cpu.inst 26 # number of demand (read+write) MSHR hits 1349system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits 1350system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits 1351system.cpu.l2cache.overall_mshr_hits::cpu.inst 26 # number of overall MSHR hits 1352system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits 1353system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits 1354system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 19 # number of ReadReq MSHR misses 1355system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 1356system.cpu.l2cache.ReadReq_mshr_misses::total 25 # number of ReadReq MSHR misses 1357system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses 1358system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses 1359system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1360system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1361system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135508 # number of ReadExReq MSHR misses 1362system.cpu.l2cache.ReadExReq_mshr_misses::total 135508 # number of ReadExReq MSHR misses 1363system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19885 # number of ReadCleanReq MSHR misses 1364system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19885 # number of ReadCleanReq MSHR misses 1365system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13226 # number of ReadSharedReq MSHR misses 1366system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13226 # number of ReadSharedReq MSHR misses 1367system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 19 # number of demand (read+write) MSHR misses 1368system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 1369system.cpu.l2cache.demand_mshr_misses::cpu.inst 19885 # number of demand (read+write) MSHR misses 1370system.cpu.l2cache.demand_mshr_misses::cpu.data 148734 # number of demand (read+write) MSHR misses 1371system.cpu.l2cache.demand_mshr_misses::total 168644 # number of demand (read+write) MSHR misses 1372system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 19 # number of overall MSHR misses 1373system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 1374system.cpu.l2cache.overall_mshr_misses::cpu.inst 19885 # number of overall MSHR misses 1375system.cpu.l2cache.overall_mshr_misses::cpu.data 148734 # number of overall MSHR misses 1376system.cpu.l2cache.overall_mshr_misses::total 168644 # number of overall MSHR misses 1377system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3003 # number of ReadReq MSHR uncacheable 1378system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable 1379system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable 1380system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27585 # number of WriteReq MSHR uncacheable 1381system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable 1382system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3003 # number of overall MSHR uncacheable misses 1383system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses 1384system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61717 # number of overall MSHR uncacheable misses 1385system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2442000 # number of ReadReq MSHR miss cycles 1386system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 735500 # number of ReadReq MSHR miss cycles 1387system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3177500 # number of ReadReq MSHR miss cycles 1388system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 184950500 # number of UpgradeReq MSHR miss cycles 1389system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 184950500 # number of UpgradeReq MSHR miss cycles 1390system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 211500 # number of SCUpgradeReq MSHR miss cycles 1391system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 211500 # number of SCUpgradeReq MSHR miss cycles 1392system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16255528500 # number of ReadExReq MSHR miss cycles 1393system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16255528500 # number of ReadExReq MSHR miss cycles 1394system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2436802003 # number of ReadCleanReq MSHR miss cycles 1395system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2436802003 # number of ReadCleanReq MSHR miss cycles 1396system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652257000 # number of ReadSharedReq MSHR miss cycles 1397system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652257000 # number of ReadSharedReq MSHR miss cycles 1398system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2442000 # number of demand (read+write) MSHR miss cycles 1399system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 735500 # number of demand (read+write) MSHR miss cycles 1400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2436802003 # number of demand (read+write) MSHR miss cycles 1401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17907785500 # number of demand (read+write) MSHR miss cycles 1402system.cpu.l2cache.demand_mshr_miss_latency::total 20347765003 # number of demand (read+write) MSHR miss cycles 1403system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2442000 # number of overall MSHR miss cycles 1404system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 735500 # number of overall MSHR miss cycles 1405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2436802003 # number of overall MSHR miss cycles 1406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17907785500 # number of overall MSHR miss cycles 1407system.cpu.l2cache.overall_mshr_miss_latency::total 20347765003 # number of overall MSHR miss cycles 1408system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340067500 # number of ReadReq MSHR uncacheable cycles 1409system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887147000 # number of ReadReq MSHR uncacheable cycles 1410system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227214500 # number of ReadReq MSHR uncacheable cycles 1411system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340067500 # number of overall MSHR uncacheable cycles 1412system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5887147000 # number of overall MSHR uncacheable cycles 1413system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6227214500 # number of overall MSHR uncacheable cycles 1414system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses 1415system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for ReadReq accesses 1416system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000356 # mshr miss rate for ReadReq accesses 1417system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.977706 # mshr miss rate for UpgradeReq accesses 1418system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.977706 # mshr miss rate for UpgradeReq accesses 1419system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 1420system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 1421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455857 # mshr miss rate for ReadExReq accesses 1422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455857 # mshr miss rate for ReadExReq accesses 1423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for ReadCleanReq accesses 1424system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010539 # mshr miss rate for ReadCleanReq accesses 1425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024401 # mshr miss rate for ReadSharedReq accesses 1426system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024401 # mshr miss rate for ReadSharedReq accesses 1427system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for demand accesses 1428system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for demand accesses 1429system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for demand accesses 1430system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for demand accesses 1431system.cpu.l2cache.demand_mshr_miss_rate::total 0.060313 # mshr miss rate for demand accesses 1432system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000327 # mshr miss rate for overall accesses 1433system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000497 # mshr miss rate for overall accesses 1434system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010539 # mshr miss rate for overall accesses 1435system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177216 # mshr miss rate for overall accesses 1436system.cpu.l2cache.overall_mshr_miss_rate::total 0.060313 # mshr miss rate for overall accesses 1437system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average ReadReq mshr miss latency 1438system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average ReadReq mshr miss latency 1439system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127100 # average ReadReq mshr miss latency 1440system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68021.515263 # average UpgradeReq mshr miss latency 1441system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68021.515263 # average UpgradeReq mshr miss latency 1442system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1443system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1444system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119959.917496 # average ReadExReq mshr miss latency 1445system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119959.917496 # average ReadExReq mshr miss latency 1446system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122544.732361 # average ReadCleanReq mshr miss latency 1447system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122544.732361 # average ReadCleanReq mshr miss latency 1448system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124924.920611 # average ReadSharedReq mshr miss latency 1449system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124924.920611 # average ReadSharedReq mshr miss latency 1450system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency 1451system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency 1452system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency 1453system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency 1454system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency 1455system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128526.315789 # average overall mshr miss latency 1456system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122583.333333 # average overall mshr miss latency 1457system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122544.732361 # average overall mshr miss latency 1458system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120401.424691 # average overall mshr miss latency 1459system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120655.137467 # average overall mshr miss latency 1460system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average ReadReq mshr uncacheable latency 1461system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.980436 # average ReadReq mshr uncacheable latency 1462system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182445.051565 # average ReadReq mshr uncacheable latency 1463system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113242.590743 # average overall mshr uncacheable latency 1464system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 100268.198385 # average overall mshr uncacheable latency 1465system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 100899.500948 # average overall mshr uncacheable latency 1466system.cpu.toL2Bus.snoop_filter.tot_requests 5483921 # Total number of requests made to the snoop filter. 1467system.cpu.toL2Bus.snoop_filter.hit_single_requests 2757867 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1468system.cpu.toL2Bus.snoop_filter.hit_multi_requests 44951 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1469system.cpu.toL2Bus.snoop_filter.tot_snoops 378 # Total number of snoops made to the snoop filter. 1470system.cpu.toL2Bus.snoop_filter.hit_single_snoops 378 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1471system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1472system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1473system.cpu.toL2Bus.trans_dist::ReadReq 128774 # Transaction distribution 1474system.cpu.toL2Bus.trans_dist::ReadResp 2557731 # Transaction distribution 1475system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution 1476system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution 1477system.cpu.toL2Bus.trans_dist::WritebackDirty 822205 # Transaction distribution 1478system.cpu.toL2Bus.trans_dist::WritebackClean 1886245 # Transaction distribution 1479system.cpu.toL2Bus.trans_dist::CleanEvict 149751 # Transaction distribution 1480system.cpu.toL2Bus.trans_dist::UpgradeReq 2781 # Transaction distribution 1481system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1482system.cpu.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution 1483system.cpu.toL2Bus.trans_dist::ReadExReq 297260 # Transaction distribution 1484system.cpu.toL2Bus.trans_dist::ReadExResp 297260 # Transaction distribution 1485system.cpu.toL2Bus.trans_dist::ReadCleanReq 1886805 # Transaction distribution 1486system.cpu.toL2Bus.trans_dist::ReadSharedReq 542244 # Transaction distribution 1487system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 1488system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5665772 # Packet count per connected master and slave (bytes) 1489system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2640441 # Packet count per connected master and slave (bytes) 1490system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30896 # Packet count per connected master and slave (bytes) 1491system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 133904 # Packet count per connected master and slave (bytes) 1492system.cpu.toL2Bus.pkt_count::total 8471013 # Packet count per connected master and slave (bytes) 1493system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241517552 # Cumulative packet size per connected master and slave (bytes) 1494system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98498985 # Cumulative packet size per connected master and slave (bytes) 1495system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 48264 # Cumulative packet size per connected master and slave (bytes) 1496system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 232368 # Cumulative packet size per connected master and slave (bytes) 1497system.cpu.toL2Bus.pkt_size::total 340297169 # Cumulative packet size per connected master and slave (bytes) 1498system.cpu.toL2Bus.snoops 194360 # Total snoops (count) 1499system.cpu.toL2Bus.snoop_fanout::samples 3054889 # Request fanout histogram 1500system.cpu.toL2Bus.snoop_fanout::mean 0.024700 # Request fanout histogram 1501system.cpu.toL2Bus.snoop_fanout::stdev 0.155211 # Request fanout histogram 1502system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1503system.cpu.toL2Bus.snoop_fanout::0 2979432 97.53% 97.53% # Request fanout histogram 1504system.cpu.toL2Bus.snoop_fanout::1 75457 2.47% 100.00% # Request fanout histogram 1505system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1506system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1507system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1508system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1509system.cpu.toL2Bus.snoop_fanout::total 3054889 # Request fanout histogram 1510system.cpu.toL2Bus.reqLayer0.occupancy 5401923998 # Layer occupancy (ticks) 1511system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 1512system.cpu.toL2Bus.snoopLayer0.occupancy 258877 # Layer occupancy (ticks) 1513system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1514system.cpu.toL2Bus.respLayer0.occupancy 2834168078 # Layer occupancy (ticks) 1515system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1516system.cpu.toL2Bus.respLayer1.occupancy 1305452066 # Layer occupancy (ticks) 1517system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1518system.cpu.toL2Bus.respLayer2.occupancy 18839481 # Layer occupancy (ticks) 1519system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1520system.cpu.toL2Bus.respLayer3.occupancy 75872379 # Layer occupancy (ticks) 1521system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1522system.iobus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1523system.iobus.trans_dist::ReadReq 30172 # Transaction distribution 1524system.iobus.trans_dist::ReadResp 30172 # Transaction distribution 1525system.iobus.trans_dist::WriteReq 59014 # Transaction distribution 1526system.iobus.trans_dist::WriteResp 59014 # Transaction distribution 1527system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) 1528system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1529system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1530system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1531system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1532system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1533system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1534system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1535system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1536system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1537system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1538system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1539system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1540system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1541system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1542system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1543system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1544system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1545system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1546system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) 1547system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72894 # Packet count per connected master and slave (bytes) 1548system.iobus.pkt_count_system.realview.ide.dma::total 72894 # Packet count per connected master and slave (bytes) 1549system.iobus.pkt_count::total 178372 # Packet count per connected master and slave (bytes) 1550system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) 1551system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1552system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 1553system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1554system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1555system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1556system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1557system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1558system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1559system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1560system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1561system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1562system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1563system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1564system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1565system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1566system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1567system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1568system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1569system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) 1570system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) 1571system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) 1572system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) 1573system.iobus.reqLayer0.occupancy 43093500 # Layer occupancy (ticks) 1574system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1575system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) 1576system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1577system.iobus.reqLayer2.occupancy 326500 # Layer occupancy (ticks) 1578system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1579system.iobus.reqLayer3.occupancy 27500 # Layer occupancy (ticks) 1580system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1581system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) 1582system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1583system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) 1584system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1585system.iobus.reqLayer8.occupancy 652000 # Layer occupancy (ticks) 1586system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1587system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) 1588system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1589system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) 1590system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1591system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1592system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1593system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 1594system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1595system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) 1596system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1597system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1598system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1599system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) 1600system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1601system.iobus.reqLayer19.occupancy 3000 # Layer occupancy (ticks) 1602system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1603system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 1604system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1605system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) 1606system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1607system.iobus.reqLayer23.occupancy 6160000 # Layer occupancy (ticks) 1608system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1609system.iobus.reqLayer24.occupancy 33076500 # Layer occupancy (ticks) 1610system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1611system.iobus.reqLayer25.occupancy 187162988 # Layer occupancy (ticks) 1612system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1613system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) 1614system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1615system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) 1616system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1617system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1618system.iocache.tags.replacements 36413 # number of replacements 1619system.iocache.tags.tagsinuse 1.005739 # Cycle average of tags in use 1620system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1621system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. 1622system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1623system.iocache.tags.warmup_cycle 256498269000 # Cycle when the warmup percentage was hit. 1624system.iocache.tags.occ_blocks::realview.ide 1.005739 # Average occupied blocks per requestor 1625system.iocache.tags.occ_percent::realview.ide 0.062859 # Average percentage of cache occupancy 1626system.iocache.tags.occ_percent::total 0.062859 # Average percentage of cache occupancy 1627system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1628system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1629system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1630system.iocache.tags.tag_accesses 328023 # Number of tag accesses 1631system.iocache.tags.data_accesses 328023 # Number of data accesses 1632system.iocache.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1633system.iocache.ReadReq_misses::realview.ide 223 # number of ReadReq misses 1634system.iocache.ReadReq_misses::total 223 # number of ReadReq misses 1635system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1636system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1637system.iocache.demand_misses::realview.ide 36447 # number of demand (read+write) misses 1638system.iocache.demand_misses::total 36447 # number of demand (read+write) misses 1639system.iocache.overall_misses::realview.ide 36447 # number of overall misses 1640system.iocache.overall_misses::total 36447 # number of overall misses 1641system.iocache.ReadReq_miss_latency::realview.ide 28153877 # number of ReadReq miss cycles 1642system.iocache.ReadReq_miss_latency::total 28153877 # number of ReadReq miss cycles 1643system.iocache.WriteLineReq_miss_latency::realview.ide 4551268111 # number of WriteLineReq miss cycles 1644system.iocache.WriteLineReq_miss_latency::total 4551268111 # number of WriteLineReq miss cycles 1645system.iocache.demand_miss_latency::realview.ide 4579421988 # number of demand (read+write) miss cycles 1646system.iocache.demand_miss_latency::total 4579421988 # number of demand (read+write) miss cycles 1647system.iocache.overall_miss_latency::realview.ide 4579421988 # number of overall miss cycles 1648system.iocache.overall_miss_latency::total 4579421988 # number of overall miss cycles 1649system.iocache.ReadReq_accesses::realview.ide 223 # number of ReadReq accesses(hits+misses) 1650system.iocache.ReadReq_accesses::total 223 # number of ReadReq accesses(hits+misses) 1651system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1652system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1653system.iocache.demand_accesses::realview.ide 36447 # number of demand (read+write) accesses 1654system.iocache.demand_accesses::total 36447 # number of demand (read+write) accesses 1655system.iocache.overall_accesses::realview.ide 36447 # number of overall (read+write) accesses 1656system.iocache.overall_accesses::total 36447 # number of overall (read+write) accesses 1657system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1658system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1659system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1660system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1661system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1662system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1663system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1664system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1665system.iocache.ReadReq_avg_miss_latency::realview.ide 126250.569507 # average ReadReq miss latency 1666system.iocache.ReadReq_avg_miss_latency::total 126250.569507 # average ReadReq miss latency 1667system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125642.339637 # average WriteLineReq miss latency 1668system.iocache.WriteLineReq_avg_miss_latency::total 125642.339637 # average WriteLineReq miss latency 1669system.iocache.demand_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency 1670system.iocache.demand_avg_miss_latency::total 125646.061075 # average overall miss latency 1671system.iocache.overall_avg_miss_latency::realview.ide 125646.061075 # average overall miss latency 1672system.iocache.overall_avg_miss_latency::total 125646.061075 # average overall miss latency 1673system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1674system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1675system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1676system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1677system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1678system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1679system.iocache.writebacks::writebacks 36190 # number of writebacks 1680system.iocache.writebacks::total 36190 # number of writebacks 1681system.iocache.ReadReq_mshr_misses::realview.ide 223 # number of ReadReq MSHR misses 1682system.iocache.ReadReq_mshr_misses::total 223 # number of ReadReq MSHR misses 1683system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 1684system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 1685system.iocache.demand_mshr_misses::realview.ide 36447 # number of demand (read+write) MSHR misses 1686system.iocache.demand_mshr_misses::total 36447 # number of demand (read+write) MSHR misses 1687system.iocache.overall_mshr_misses::realview.ide 36447 # number of overall MSHR misses 1688system.iocache.overall_mshr_misses::total 36447 # number of overall MSHR misses 1689system.iocache.ReadReq_mshr_miss_latency::realview.ide 17003877 # number of ReadReq MSHR miss cycles 1690system.iocache.ReadReq_mshr_miss_latency::total 17003877 # number of ReadReq MSHR miss cycles 1691system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2738656099 # number of WriteLineReq MSHR miss cycles 1692system.iocache.WriteLineReq_mshr_miss_latency::total 2738656099 # number of WriteLineReq MSHR miss cycles 1693system.iocache.demand_mshr_miss_latency::realview.ide 2755659976 # number of demand (read+write) MSHR miss cycles 1694system.iocache.demand_mshr_miss_latency::total 2755659976 # number of demand (read+write) MSHR miss cycles 1695system.iocache.overall_mshr_miss_latency::realview.ide 2755659976 # number of overall MSHR miss cycles 1696system.iocache.overall_mshr_miss_latency::total 2755659976 # number of overall MSHR miss cycles 1697system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1698system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1699system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1700system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1701system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1702system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1703system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1704system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1705system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76250.569507 # average ReadReq mshr miss latency 1706system.iocache.ReadReq_avg_mshr_miss_latency::total 76250.569507 # average ReadReq mshr miss latency 1707system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75603.359623 # average WriteLineReq mshr miss latency 1708system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75603.359623 # average WriteLineReq mshr miss latency 1709system.iocache.demand_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1710system.iocache.demand_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1711system.iocache.overall_avg_mshr_miss_latency::realview.ide 75607.319560 # average overall mshr miss latency 1712system.iocache.overall_avg_mshr_miss_latency::total 75607.319560 # average overall mshr miss latency 1713system.membus.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1714system.membus.trans_dist::ReadReq 34132 # Transaction distribution 1715system.membus.trans_dist::ReadResp 67490 # Transaction distribution 1716system.membus.trans_dist::WriteReq 27585 # Transaction distribution 1717system.membus.trans_dist::WriteResp 27585 # Transaction distribution 1718system.membus.trans_dist::WritebackDirty 125412 # Transaction distribution 1719system.membus.trans_dist::CleanEvict 7777 # Transaction distribution 1720system.membus.trans_dist::UpgradeReq 4588 # Transaction distribution 1721system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1722system.membus.trans_dist::UpgradeResp 2 # Transaction distribution 1723system.membus.trans_dist::ReadExReq 133639 # Transaction distribution 1724system.membus.trans_dist::ReadExResp 133639 # Transaction distribution 1725system.membus.trans_dist::ReadSharedReq 33359 # Transaction distribution 1726system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1727system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) 1728system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) 1729system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) 1730system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450505 # Packet count per connected master and slave (bytes) 1731system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558073 # Packet count per connected master and slave (bytes) 1732system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) 1733system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) 1734system.membus.pkt_count::total 630948 # Packet count per connected master and slave (bytes) 1735system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) 1736system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 112 # Cumulative packet size per connected master and slave (bytes) 1737system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) 1738system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16433756 # Cumulative packet size per connected master and slave (bytes) 1739system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16597145 # Cumulative packet size per connected master and slave (bytes) 1740system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 1741system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 1742system.membus.pkt_size::total 18914265 # Cumulative packet size per connected master and slave (bytes) 1743system.membus.snoops 487 # Total snoops (count) 1744system.membus.snoop_fanout::samples 402739 # Request fanout histogram 1745system.membus.snoop_fanout::mean 1 # Request fanout histogram 1746system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1747system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1748system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1749system.membus.snoop_fanout::1 402739 100.00% 100.00% # Request fanout histogram 1750system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1751system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1752system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1753system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1754system.membus.snoop_fanout::total 402739 # Request fanout histogram 1755system.membus.reqLayer0.occupancy 83678000 # Layer occupancy (ticks) 1756system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1757system.membus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1758system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1759system.membus.reqLayer2.occupancy 1737499 # Layer occupancy (ticks) 1760system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1761system.membus.reqLayer5.occupancy 875953366 # Layer occupancy (ticks) 1762system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1763system.membus.respLayer2.occupancy 978576250 # Layer occupancy (ticks) 1764system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1765system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) 1766system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1767system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1768system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1769system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1770system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1771system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1772system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1773system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1774system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1775system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1776system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1777system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1778system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1779system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1780system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1781system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1782system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1783system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1784system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1785system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1786system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1787system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1788system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1789system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1790system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1791system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1792system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1793system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1794system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1795system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1796system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1797system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1798system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1799system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1800system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1801system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1802system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1803system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1804system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1805system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1806system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1807system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1808system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1809system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1810system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1811system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1812system.realview.ethernet.droppedPackets 0 # number of packets dropped 1813system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1814system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1815system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1816system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1817system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1818system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1819system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1820system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1821system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1822system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1823system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1824system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1825system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1826system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1827system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1828system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1829system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1830system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1831system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1832system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1833system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1834system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1835system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2832862976500 # Cumulative time (in ticks) in various power states 1836system.cpu.kern.inst.arm 0 # number of arm instructions executed 1837system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed 1838 1839---------- End Simulation Statistics ----------