| stats.txt (10220:9eab5efc02e8) | stats.txt (10229:aae7735450a9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.526192 # Number of seconds simulated 4sim_ticks 2526192217500 # Number of ticks simulated 5final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56578 # Simulator instruction rate (inst/s) 8host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2369913329 # Simulator tick rate (ticks/s) 10host_mem_usage 467016 # Number of bytes of host memory used 11host_seconds 1065.94 # Real time elapsed on the host 12sim_insts 60309034 # Number of instructions simulated 13sim_ops 77600502 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory 21system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15096864 # Number of read requests accepted 55system.physmem.writeReqs 813148 # Number of write requests accepted 56system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 943480 # Per bank write bursts 67system.physmem.perBankRdBursts::1 937980 # Per bank write bursts 68system.physmem.perBankRdBursts::2 937559 # Per bank write bursts 69system.physmem.perBankRdBursts::3 937528 # Per bank write bursts 70system.physmem.perBankRdBursts::4 943087 # Per bank write bursts 71system.physmem.perBankRdBursts::5 937982 # Per bank write bursts 72system.physmem.perBankRdBursts::6 937070 # Per bank write bursts 73system.physmem.perBankRdBursts::7 936990 # Per bank write bursts 74system.physmem.perBankRdBursts::8 943982 # Per bank write bursts 75system.physmem.perBankRdBursts::9 938303 # Per bank write bursts 76system.physmem.perBankRdBursts::10 937119 # Per bank write bursts 77system.physmem.perBankRdBursts::11 936407 # Per bank write bursts 78system.physmem.perBankRdBursts::12 943924 # Per bank write bursts 79system.physmem.perBankRdBursts::13 938214 # Per bank write bursts 80system.physmem.perBankRdBursts::14 937241 # Per bank write bursts 81system.physmem.perBankRdBursts::15 937211 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6601 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6388 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6528 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6554 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6464 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6726 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6713 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6652 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7031 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6803 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6461 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6104 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7064 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6684 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6965 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6836 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2526191083500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 38 # Read request sizes (log2) 104system.physmem.readPktSize::3 14942208 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 154618 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 59130 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads 248system.physmem.totQLat 389908010000 # Total ticks spent queuing 249system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 253system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s 255system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s 256system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s 257system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 2.99 # Data bus utilization in percentage 260system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 262system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing 264system.physmem.readRowHits 14044000 # Number of row buffer hits during reads 265system.physmem.writeRowHits 91096 # Number of row buffer hits during writes 266system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 267system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes 268system.physmem.avgGap 158779.96 # Average gap between requests 269system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined 270system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states 271system.physmem.memoryStateTime::REF 84354920000 # Time in different power states 272system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states 274system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 276system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 277system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 278system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 279system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 280system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 281system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 282system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 283system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 284system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 285system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 286system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 287system.membus.throughput 54877773 # Throughput (bytes/s) 288system.membus.trans_dist::ReadReq 16149486 # Transaction distribution 289system.membus.trans_dist::ReadResp 16149486 # Transaction distribution 290system.membus.trans_dist::WriteReq 763349 # Transaction distribution 291system.membus.trans_dist::WriteResp 763349 # Transaction distribution 292system.membus.trans_dist::Writeback 59130 # Transaction distribution 293system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution 294system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 295system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution 296system.membus.trans_dist::ReadExReq 131451 # Transaction distribution 297system.membus.trans_dist::ReadExResp 131451 # Transaction distribution 298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) 307system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 138631802 # Total data (bytes) 317system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 318system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) 319system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 320system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 321system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 322system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) 323system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 325system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 326system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) 327system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 328system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) 329system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 330system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) 331system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 0 # Number of DMA write transactions. 338system.iobus.throughput 48265574 # Throughput (bytes/s) 339system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution 340system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution 341system.iobus.trans_dist::WriteReq 8174 # Transaction distribution 342system.iobus.trans_dist::WriteResp 8174 # Transaction distribution 343system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) 369system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.data_through_bus 121928118 # Total data (bytes) 398system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 399system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 400system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 401system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 403system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 404system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 405system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 406system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 407system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 408system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 409system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 410system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 411system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 412system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 413system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 414system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 415system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 416system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 417system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 418system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 419system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 420system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 421system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 422system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 423system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 424system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 425system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 426system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 427system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 428system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 429system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 430system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 431system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 432system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 435system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 436system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 437system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 438system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 439system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 440system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 441system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 442system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 443system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 444system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 445system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 446system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) 447system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 448system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) 449system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 450system.cpu_clk_domain.clock 500 # Clock period in ticks 451system.cpu.branchPred.lookups 14753661 # Number of BP lookups 452system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted 453system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect 454system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups 455system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits 456system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 457system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage 458system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. 459system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. 460system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 461system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 462system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 463system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 464system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 465system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 466system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 467system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 468system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 469system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 470system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 471system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 472system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 473system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 475system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 476system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 477system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 478system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 479system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 480system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 481system.cpu.dtb.inst_hits 0 # ITB inst hits 482system.cpu.dtb.inst_misses 0 # ITB inst misses 483system.cpu.dtb.read_hits 51183231 # DTB read hits 484system.cpu.dtb.read_misses 65223 # DTB read misses 485system.cpu.dtb.write_hits 11700953 # DTB write hits 486system.cpu.dtb.write_misses 15725 # DTB write misses 487system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 488system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 489system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 490system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 491system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB 492system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions 493system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch 494system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 495system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions 496system.cpu.dtb.read_accesses 51248454 # DTB read accesses 497system.cpu.dtb.write_accesses 11716678 # DTB write accesses 498system.cpu.dtb.inst_accesses 0 # ITB inst accesses 499system.cpu.dtb.hits 62884184 # DTB hits 500system.cpu.dtb.misses 80948 # DTB misses 501system.cpu.dtb.accesses 62965132 # DTB accesses 502system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 503system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 504system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 505system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 506system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 507system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 508system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 509system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 510system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 511system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 512system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 513system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 518system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 519system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 520system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 521system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 522system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 523system.cpu.itb.inst_hits 11525561 # ITB inst hits 524system.cpu.itb.inst_misses 11159 # ITB inst misses 525system.cpu.itb.read_hits 0 # DTB read hits 526system.cpu.itb.read_misses 0 # DTB read misses 527system.cpu.itb.write_hits 0 # DTB write hits 528system.cpu.itb.write_misses 0 # DTB write misses 529system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 530system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 531system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 532system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 533system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB 534system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 535system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 536system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 537system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions 538system.cpu.itb.read_accesses 0 # DTB read accesses 539system.cpu.itb.write_accesses 0 # DTB write accesses 540system.cpu.itb.inst_accesses 11536720 # ITB inst accesses 541system.cpu.itb.hits 11525561 # DTB hits 542system.cpu.itb.misses 11159 # DTB misses 543system.cpu.itb.accesses 11536720 # DTB accesses 544system.cpu.numCycles 477128882 # number of cpu cycles simulated 545system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 546system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 547system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss 548system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed 549system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered 550system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken 551system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked 552system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing 553system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb 554system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked 555system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 556system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps 557system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions 558system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR 559system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched 560system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed 561system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed 562system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) 563system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) 564system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) 565system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 566system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) 567system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) 568system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle 580system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle 581system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle 582system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked 583system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running 584system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking 585system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing 586system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch 587system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction 588system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode 589system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode 590system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing 591system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle 592system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking 593system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst 594system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running 595system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking 596system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename 597system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full 598system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full 599system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full 600system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers 601system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed 602system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made 603system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups 604system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups 605system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed 606system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing 607system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed 608system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed 609system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer 610system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. 611system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. 612system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. 613system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. 614system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) 615system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ 616system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued 617system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued 618system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling 619system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph 620system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed 621system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle 622system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle 638system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 639system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available 640system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available 641system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 642system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 643system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 648system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 668system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available 669system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available 670system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 671system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 672system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued 673system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued 674system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued 675system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued 676system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued 677system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued 678system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued 679system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued 680system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued 681system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued 702system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued 703system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued 704system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 705system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued 707system.cpu.iq.rate 0.257622 # Inst issue rate 708system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested 709system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) 710system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads 711system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes 712system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses 713system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads 714system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes 715system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses 716system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses 717system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses 718system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores 719system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 720system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed 721system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed 722system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations 723system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed 724system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 725system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 726system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled 727system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked 728system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 729system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing 730system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking 731system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking 732system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ 733system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch 734system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions 735system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions 736system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions 737system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall 738system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall 739system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations 740system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly 741system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly 742system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute 743system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions 744system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed 745system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute 746system.cpu.iew.exec_swp 0 # number of swp insts executed 747system.cpu.iew.exec_nop 222849 # number of nop insts executed 748system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed 749system.cpu.iew.exec_branches 11822089 # Number of branches executed 750system.cpu.iew.exec_stores 12212847 # Number of stores executed 751system.cpu.iew.exec_rate 0.253272 # Inst execution rate 752system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit 753system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back 754system.cpu.iew.wb_producers 47017508 # num instructions producing a value 755system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value 756system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 757system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle 758system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back 759system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 760system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit 761system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards 762system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted 763system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle 780system.cpu.commit.committedInsts 60459415 # Number of instructions committed 781system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed 782system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 783system.cpu.commit.refs 27386618 # Number of memory references committed 784system.cpu.commit.loads 15654647 # Number of loads committed 785system.cpu.commit.membars 403571 # Number of memory barriers committed 786system.cpu.commit.branches 10306311 # Number of branches committed 787system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 788system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. 789system.cpu.commit.function_calls 991245 # Number of function calls committed. 790system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 791system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction 792system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction 793system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction 794system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction 795system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction 796system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction 797system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction 798system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction 799system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction 800system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction 801system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction 803system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction 805system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction 806system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction 809system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction 810system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction 814system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction 815system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction 816system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction 820system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction 821system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction 822system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 823system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 824system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction 825system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached 826system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 827system.cpu.rob.rob_reads 243007370 # The number of ROB reads 828system.cpu.rob.rob_writes 195993770 # The number of ROB writes 829system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself 830system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling 831system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 832system.cpu.committedInsts 60309034 # Number of Instructions Simulated 833system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.526192 # Number of seconds simulated 4sim_ticks 2526192217500 # Number of ticks simulated 5final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 56578 # Simulator instruction rate (inst/s) 8host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2369913329 # Simulator tick rate (ticks/s) 10host_mem_usage 467016 # Number of bytes of host memory used 11host_seconds 1065.94 # Real time elapsed on the host 12sim_insts 60309034 # Number of instructions simulated 13sim_ops 77600502 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory 21system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 15096864 # Number of read requests accepted 55system.physmem.writeReqs 813148 # Number of write requests accepted 56system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue 60system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 943480 # Per bank write bursts 67system.physmem.perBankRdBursts::1 937980 # Per bank write bursts 68system.physmem.perBankRdBursts::2 937559 # Per bank write bursts 69system.physmem.perBankRdBursts::3 937528 # Per bank write bursts 70system.physmem.perBankRdBursts::4 943087 # Per bank write bursts 71system.physmem.perBankRdBursts::5 937982 # Per bank write bursts 72system.physmem.perBankRdBursts::6 937070 # Per bank write bursts 73system.physmem.perBankRdBursts::7 936990 # Per bank write bursts 74system.physmem.perBankRdBursts::8 943982 # Per bank write bursts 75system.physmem.perBankRdBursts::9 938303 # Per bank write bursts 76system.physmem.perBankRdBursts::10 937119 # Per bank write bursts 77system.physmem.perBankRdBursts::11 936407 # Per bank write bursts 78system.physmem.perBankRdBursts::12 943924 # Per bank write bursts 79system.physmem.perBankRdBursts::13 938214 # Per bank write bursts 80system.physmem.perBankRdBursts::14 937241 # Per bank write bursts 81system.physmem.perBankRdBursts::15 937211 # Per bank write bursts 82system.physmem.perBankWrBursts::0 6601 # Per bank write bursts 83system.physmem.perBankWrBursts::1 6388 # Per bank write bursts 84system.physmem.perBankWrBursts::2 6528 # Per bank write bursts 85system.physmem.perBankWrBursts::3 6554 # Per bank write bursts 86system.physmem.perBankWrBursts::4 6464 # Per bank write bursts 87system.physmem.perBankWrBursts::5 6726 # Per bank write bursts 88system.physmem.perBankWrBursts::6 6713 # Per bank write bursts 89system.physmem.perBankWrBursts::7 6652 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7031 # Per bank write bursts 91system.physmem.perBankWrBursts::9 6803 # Per bank write bursts 92system.physmem.perBankWrBursts::10 6461 # Per bank write bursts 93system.physmem.perBankWrBursts::11 6104 # Per bank write bursts 94system.physmem.perBankWrBursts::12 7064 # Per bank write bursts 95system.physmem.perBankWrBursts::13 6684 # Per bank write bursts 96system.physmem.perBankWrBursts::14 6965 # Per bank write bursts 97system.physmem.perBankWrBursts::15 6836 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 2526191083500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 38 # Read request sizes (log2) 104system.physmem.readPktSize::3 14942208 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 154618 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 754018 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 59130 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads 248system.physmem.totQLat 389908010000 # Total ticks spent queuing 249system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM 250system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers 251system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst 252system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 253system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst 254system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s 255system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s 256system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s 257system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s 258system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 259system.physmem.busUtil 2.99 # Data bus utilization in percentage 260system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 261system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 262system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing 263system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing 264system.physmem.readRowHits 14044000 # Number of row buffer hits during reads 265system.physmem.writeRowHits 91096 # Number of row buffer hits during writes 266system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads 267system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes 268system.physmem.avgGap 158779.96 # Average gap between requests 269system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined 270system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states 271system.physmem.memoryStateTime::REF 84354920000 # Time in different power states 272system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states 274system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory 276system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory 277system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory 278system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory 279system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory 280system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory 281system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) 282system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) 283system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) 284system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) 285system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) 286system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) 287system.membus.throughput 54877773 # Throughput (bytes/s) 288system.membus.trans_dist::ReadReq 16149486 # Transaction distribution 289system.membus.trans_dist::ReadResp 16149486 # Transaction distribution 290system.membus.trans_dist::WriteReq 763349 # Transaction distribution 291system.membus.trans_dist::WriteResp 763349 # Transaction distribution 292system.membus.trans_dist::Writeback 59130 # Transaction distribution 293system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution 294system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 295system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution 296system.membus.trans_dist::ReadExReq 131451 # Transaction distribution 297system.membus.trans_dist::ReadExResp 131451 # Transaction distribution 298system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) 299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) 300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) 301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 302system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) 303system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) 304system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) 305system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) 307system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) 308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) 309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) 310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) 312system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) 313system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) 314system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) 315system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) 316system.membus.data_through_bus 138631802 # Total data (bytes) 317system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 318system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) 319system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 320system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) 321system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 322system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) 323system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) 325system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 326system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) 327system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 328system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) 329system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 330system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) 331system.membus.respLayer2.utilization 1.5 # Layer utilization (%) 332system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 333system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 334system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 335system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 336system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 337system.cf0.dma_write_txs 0 # Number of DMA write transactions. 338system.iobus.throughput 48265574 # Throughput (bytes/s) 339system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution 340system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution 341system.iobus.trans_dist::WriteReq 8174 # Transaction distribution 342system.iobus.trans_dist::WriteResp 8174 # Transaction distribution 343system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) 344system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) 345system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes) 346system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes) 347system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes) 369system.iobus.pkt_count::total 32267460 # Packet count per connected master and slave (bytes) 370system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.tot_pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.tot_pkt_size::total 121928118 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.data_through_bus 121928118 # Total data (bytes) 398system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) 399system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 400system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) 401system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 402system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks) 403system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 404system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks) 405system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 406system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 407system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 408system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 409system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 410system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) 411system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 412system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 413system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 414system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 415system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 416system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 417system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 418system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 419system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 420system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 421system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 422system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 423system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 424system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 425system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 426system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 427system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 428system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 429system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 430system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 431system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 432system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 433system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 434system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 435system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 436system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 437system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 438system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 439system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 440system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 441system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 442system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 443system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 444system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks) 445system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 446system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) 447system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) 448system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) 449system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 450system.cpu_clk_domain.clock 500 # Clock period in ticks 451system.cpu.branchPred.lookups 14753661 # Number of BP lookups 452system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted 453system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect 454system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups 455system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits 456system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 457system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage 458system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. 459system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. 460system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 461system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 462system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 463system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 464system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 465system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 466system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 467system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 468system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 469system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 470system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 471system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 472system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 473system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 474system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 475system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 476system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 477system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 478system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 479system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 480system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 481system.cpu.dtb.inst_hits 0 # ITB inst hits 482system.cpu.dtb.inst_misses 0 # ITB inst misses 483system.cpu.dtb.read_hits 51183231 # DTB read hits 484system.cpu.dtb.read_misses 65223 # DTB read misses 485system.cpu.dtb.write_hits 11700953 # DTB write hits 486system.cpu.dtb.write_misses 15725 # DTB write misses 487system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 488system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 489system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 490system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 491system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB 492system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions 493system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch 494system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 495system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions 496system.cpu.dtb.read_accesses 51248454 # DTB read accesses 497system.cpu.dtb.write_accesses 11716678 # DTB write accesses 498system.cpu.dtb.inst_accesses 0 # ITB inst accesses 499system.cpu.dtb.hits 62884184 # DTB hits 500system.cpu.dtb.misses 80948 # DTB misses 501system.cpu.dtb.accesses 62965132 # DTB accesses 502system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 503system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 504system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 505system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 506system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 507system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 508system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 509system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 510system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 511system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 512system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 513system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 518system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 519system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 520system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 521system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 522system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 523system.cpu.itb.inst_hits 11525561 # ITB inst hits 524system.cpu.itb.inst_misses 11159 # ITB inst misses 525system.cpu.itb.read_hits 0 # DTB read hits 526system.cpu.itb.read_misses 0 # DTB read misses 527system.cpu.itb.write_hits 0 # DTB write hits 528system.cpu.itb.write_misses 0 # DTB write misses 529system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 530system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 531system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 532system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 533system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB 534system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 535system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 536system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 537system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions 538system.cpu.itb.read_accesses 0 # DTB read accesses 539system.cpu.itb.write_accesses 0 # DTB write accesses 540system.cpu.itb.inst_accesses 11536720 # ITB inst accesses 541system.cpu.itb.hits 11525561 # DTB hits 542system.cpu.itb.misses 11159 # DTB misses 543system.cpu.itb.accesses 11536720 # DTB accesses 544system.cpu.numCycles 477128882 # number of cpu cycles simulated 545system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 546system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 547system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss 548system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed 549system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered 550system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken 551system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked 552system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing 553system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb 554system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked 555system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 556system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps 557system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions 558system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR 559system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched 560system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed 561system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed 562system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) 563system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) 564system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) 565system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 566system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) 567system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) 568system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) 569system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) 570system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) 571system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) 572system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) 573system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) 574system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) 575system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 576system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 577system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 578system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) 579system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle 580system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle 581system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle 582system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked 583system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running 584system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking 585system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing 586system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch 587system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction 588system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode 589system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode 590system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing 591system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle 592system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking 593system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst 594system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running 595system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking 596system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename 597system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full 598system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full 599system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full 600system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers 601system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed 602system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made 603system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups 604system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups 605system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed 606system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing 607system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed 608system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed 609system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer 610system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. 611system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. 612system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. 613system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. 614system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) 615system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ 616system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued 617system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued 618system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling 619system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph 620system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed 621system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle 622system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle 623system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle 624system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 625system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle 626system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle 627system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle 628system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle 629system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle 630system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle 631system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle 632system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle 633system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle 634system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 635system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 636system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 637system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle 638system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 639system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available 640system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available 641system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available 642system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available 643system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available 644system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available 645system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available 646system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available 647system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 648system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available 649system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available 650system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available 651system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available 652system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available 653system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available 654system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available 655system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available 656system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available 657system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available 658system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available 659system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available 660system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available 661system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available 662system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available 663system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available 664system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available 665system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available 666system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available 667system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available 668system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available 669system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available 670system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 671system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 672system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued 673system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued 674system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued 675system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued 676system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued 677system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued 678system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.26% # Type of FU issued 679system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.26% # Type of FU issued 680system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.26% # Type of FU issued 681system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.26% # Type of FU issued 682system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.26% # Type of FU issued 683system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Type of FU issued 684system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued 685system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued 686system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued 687system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued 688system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued 689system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued 690system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued 691system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued 692system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued 693system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued 694system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued 695system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.26% # Type of FU issued 696system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Type of FU issued 697system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued 698system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued 699system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued 700system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued 701system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued 702system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued 703system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued 704system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 705system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 706system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued 707system.cpu.iq.rate 0.257622 # Inst issue rate 708system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested 709system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) 710system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads 711system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes 712system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses 713system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads 714system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes 715system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses 716system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses 717system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses 718system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores 719system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 720system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed 721system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed 722system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations 723system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed 724system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 725system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 726system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled 727system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked 728system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 729system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing 730system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking 731system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking 732system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ 733system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch 734system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions 735system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions 736system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions 737system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall 738system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall 739system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations 740system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly 741system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly 742system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute 743system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions 744system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed 745system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute 746system.cpu.iew.exec_swp 0 # number of swp insts executed 747system.cpu.iew.exec_nop 222849 # number of nop insts executed 748system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed 749system.cpu.iew.exec_branches 11822089 # Number of branches executed 750system.cpu.iew.exec_stores 12212847 # Number of stores executed 751system.cpu.iew.exec_rate 0.253272 # Inst execution rate 752system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit 753system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back 754system.cpu.iew.wb_producers 47017508 # num instructions producing a value 755system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value 756system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 757system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle 758system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back 759system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 760system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit 761system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards 762system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted 763system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle 764system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle 765system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle 766system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 767system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle 768system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle 769system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle 770system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle 771system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle 772system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle 773system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle 774system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle 775system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle 776system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 777system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 778system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 779system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle 780system.cpu.commit.committedInsts 60459415 # Number of instructions committed 781system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed 782system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 783system.cpu.commit.refs 27386618 # Number of memory references committed 784system.cpu.commit.loads 15654647 # Number of loads committed 785system.cpu.commit.membars 403571 # Number of memory barriers committed 786system.cpu.commit.branches 10306311 # Number of branches committed 787system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. 788system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. 789system.cpu.commit.function_calls 991245 # Number of function calls committed. 790system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 791system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction 792system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction 793system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction 794system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction 795system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction 796system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction 797system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction 798system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction 799system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction 800system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction 801system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction 802system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction 803system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction 804system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction 805system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction 806system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction 807system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction 808system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction 809system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction 810system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction 811system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction 812system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction 813system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction 814system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction 815system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction 816system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction 817system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction 818system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction 819system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction 820system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction 821system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction 822system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 823system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 824system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction 825system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached 826system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 827system.cpu.rob.rob_reads 243007370 # The number of ROB reads 828system.cpu.rob.rob_writes 195993770 # The number of ROB writes 829system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself 830system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling 831system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 832system.cpu.committedInsts 60309034 # Number of Instructions Simulated 833system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated |
| 834system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated | |
| 835system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction 836system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads 837system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle 838system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads 839system.cpu.int_regfile_reads 548643015 # number of integer regfile reads 840system.cpu.int_regfile_writes 87545924 # number of integer regfile writes 841system.cpu.fp_regfile_reads 8332 # number of floating regfile reads 842system.cpu.fp_regfile_writes 2902 # number of floating regfile writes 843system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads 844system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes 845system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) 846system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution 848system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution 849system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution 855system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution 856system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) 857system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) 858system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) 859system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) 860system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) 861system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) 862system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) 863system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) 864system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) 865system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) 866system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) 867system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) 868system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) 869system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 870system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) 871system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 872system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) 873system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 874system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) 875system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 876system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) 877system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 878system.cpu.icache.tags.replacements 981488 # number of replacements 879system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use 880system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. 881system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. 882system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. 883system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. 884system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor 885system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy 886system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy 887system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 888system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 889system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 890system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id 891system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 892system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 893system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses 894system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses 895system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits 896system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits 897system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits 898system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits 899system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits 900system.cpu.icache.overall_hits::total 10460581 # number of overall hits 901system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses 902system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses 903system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses 904system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses 905system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses 906system.cpu.icache.overall_misses::total 1061360 # number of overall misses 907system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles 908system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles 909system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles 910system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles 911system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles 912system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles 913system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) 914system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) 915system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses 916system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses 917system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses 918system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses 919system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses 920system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses 921system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses 922system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses 923system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses 924system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses 925system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency 926system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency 927system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency 928system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency 929system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency 930system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency 931system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked 932system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 933system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked 934system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 935system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked 936system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 937system.cpu.icache.fast_writes 0 # number of fast writes performed 938system.cpu.icache.cache_copies 0 # number of cache copies performed 939system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits 940system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits 941system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits 942system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits 943system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits 944system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits 945system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses 946system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses 947system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses 948system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses 949system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses 950system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses 951system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles 952system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles 953system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles 954system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles 955system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles 956system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles 957system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles 958system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles 959system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles 960system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles 961system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses 962system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses 963system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses 964system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses 965system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses 966system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses 967system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency 968system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency 969system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency 970system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency 971system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency 972system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency 973system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 974system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 975system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 976system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 977system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 978system.cpu.l2cache.tags.replacements 64387 # number of replacements 979system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use 980system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks. 981system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks. 982system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks. 983system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit. 984system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor 985system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor 986system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor 988system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor 989system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy 991system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 992system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy 993system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy 994system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy 995system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id 996system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 998system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 999system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1000system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 1001system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id 1002system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id 1003system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id 1004system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id 1005system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id 1006system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses 1007system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses 1008system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits 1009system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits 1010system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits 1011system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits 1012system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits 1013system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits 1014system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits 1015system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits 1016system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits 1017system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 1018system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits 1019system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits 1020system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits 1021system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits 1022system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits 1023system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits 1024system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits 1025system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits 1026system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits 1027system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits 1028system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits 1029system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits 1030system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits 1031system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses 1032system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1033system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses 1034system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses 1035system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses 1036system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses 1037system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses 1038system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1039system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1040system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses 1041system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses 1042system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses 1043system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1044system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses 1046system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses 1047system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses 1048system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1049system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses 1050system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses 1051system.cpu.l2cache.overall_misses::total 156349 # number of overall misses 1052system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles 1053system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles 1054system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles 1055system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles 1056system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles 1057system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles 1058system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles 1059system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles 1060system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles 1061system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles 1062system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles 1063system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles 1064system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles 1065system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles 1066system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles 1067system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles 1068system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles 1069system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles 1070system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles 1071system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses) 1072system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses) 1073system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses) 1074system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses) 1075system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses) 1076system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses) 1077system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses) 1078system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) 1079system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) 1080system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) 1081system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) 1082system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses) 1083system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses) 1084system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses 1085system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses 1086system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses 1087system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses 1088system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses 1089system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses 1090system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses 1091system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses 1092system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses 1093system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses 1094system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses 1095system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses 1096system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses 1097system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses 1098system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses 1099system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses 1100system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses 1101system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 1102system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 1103system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses 1104system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses 1105system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses 1106system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses 1107system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses 1108system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses 1109system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses 1110system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses 1111system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses 1112system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses 1113system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses 1114system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses 1115system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency 1116system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency 1117system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency 1118system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency 1119system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency 1120system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency 1121system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency 1122system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency 1123system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency 1124system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency 1125system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency 1126system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency 1127system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency 1128system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency 1129system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency 1130system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency 1131system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency 1132system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency 1133system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency 1134system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1135system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1136system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1137system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1138system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1139system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1140system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1141system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1142system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks 1143system.cpu.l2cache.writebacks::total 59130 # number of writebacks 1144system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits 1145system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 1146system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 1147system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits 1148system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits 1149system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits 1150system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1151system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits 1152system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits 1153system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses 1154system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1155system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses 1156system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses 1157system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses 1158system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses 1159system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses 1160system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1161system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # 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number of overall MSHR misses 1173system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses 1174system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles 1175system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles 1176system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles 1177system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles 1178system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles 1179system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles 1180system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles 1181system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1182system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # 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number of overall MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles 1194system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles 1195system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles 1196system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles 1197system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles 1198system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles 1199system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles 1202system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses 1205system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses 1206system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses 1207system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses 1208system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses 1209system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses 1210system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 1211system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 1212system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses 1213system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses 1214system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses 1215system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses 1216system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses 1217system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses 1218system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses 1219system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses 1220system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses 1221system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses 1222system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses 1223system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses 1224system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency 1225system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency 1226system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency 1227system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency 1228system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency 1229system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency 1230system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency 1231system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1232system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1233system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency 1234system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency 1235system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency 1236system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency 1237system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency 1238system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency 1239system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency 1240system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency 1241system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency 1242system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency 1243system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency 1244system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency 1245system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1246system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1247system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1248system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1249system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1250system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1251system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1252system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1253system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1254system.cpu.dcache.tags.replacements 643320 # number of replacements 1255system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use 1256system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks. 1257system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. 1258system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. 1259system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. 1260system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor 1261system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1262system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy 1263system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1264system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1265system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 1266system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 1267system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1268system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses 1269system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses 1270system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits 1271system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits 1272system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits 1273system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits 1274system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits 1275system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits 1276system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits 1277system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits 1278system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits 1279system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits 1280system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits 1281system.cpu.dcache.overall_hits::total 21015072 # number of overall hits 1282system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses 1283system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses 1284system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses 1285system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses 1286system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses 1287system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses 1288system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses 1289system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses 1290system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses 1291system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses 1292system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses 1293system.cpu.dcache.overall_misses::total 3699212 # number of overall misses 1294system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles 1295system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles 1296system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles 1297system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles 1298system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles 1299system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles 1300system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles 1301system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles 1302system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles 1303system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles 1304system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles 1305system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles 1306system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) 1307system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) 1308system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) 1309system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) 1310system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) 1311system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) 1312system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) 1313system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) 1314system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses 1315system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses 1316system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses 1317system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses 1318system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses 1319system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses 1320system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses 1321system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses 1322system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses 1323system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses 1324system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses 1325system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses 1326system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses 1327system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses 1328system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses 1329system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses 1330system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency 1331system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency 1332system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency 1333system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency 1334system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency 1335system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency 1336system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency 1337system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency 1338system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency 1339system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency 1340system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency 1341system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency 1342system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked 1343system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked 1344system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked 1345system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked 1346system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked 1347system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked 1348system.cpu.dcache.fast_writes 0 # number of fast writes performed 1349system.cpu.dcache.cache_copies 0 # number of cache copies performed 1350system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks 1351system.cpu.dcache.writebacks::total 607456 # number of writebacks 1352system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits 1353system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits 1354system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits 1355system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits 1356system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits 1357system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits 1358system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits 1359system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits 1360system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits 1361system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits 1362system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses 1363system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses 1364system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses 1365system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses 1366system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses 1367system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses 1368system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses 1369system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses 1370system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses 1371system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses 1372system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses 1373system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses 1374system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles 1375system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles 1376system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles 1377system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles 1378system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles 1379system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles 1380system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles 1381system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles 1382system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles 1383system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles 1384system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles 1385system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles 1386system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles 1387system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles 1388system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles 1389system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles 1390system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles 1391system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles 1392system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses 1393system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses 1394system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses 1395system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses 1396system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses 1397system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses 1398system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses 1399system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses 1400system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses 1401system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses 1402system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses 1403system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses 1404system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency 1405system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency 1406system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency 1407system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency 1408system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency 1409system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency 1410system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency 1411system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency 1412system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency 1413system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency 1414system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency 1415system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency 1416system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1417system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1418system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1419system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1420system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1421system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1422system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1423system.iocache.tags.replacements 0 # number of replacements 1424system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1425system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1426system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1427system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1428system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1429system.iocache.tags.tag_accesses 0 # Number of tag accesses 1430system.iocache.tags.data_accesses 0 # Number of data accesses 1431system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1432system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1433system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1434system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1435system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1436system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1437system.iocache.fast_writes 0 # number of fast writes performed 1438system.iocache.cache_copies 0 # number of cache copies performed 1439system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles 1440system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles 1441system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles 1442system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles 1443system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1444system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1445system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1446system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1447system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1448system.cpu.kern.inst.arm 0 # number of arm instructions executed 1449system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed 1450 1451---------- End Simulation Statistics ---------- | 834system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction 835system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads 836system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle 837system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads 838system.cpu.int_regfile_reads 548643015 # number of integer regfile reads 839system.cpu.int_regfile_writes 87545924 # number of integer regfile writes 840system.cpu.fp_regfile_reads 8332 # number of floating regfile reads 841system.cpu.fp_regfile_writes 2902 # number of floating regfile writes 842system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads 843system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes 844system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) 845system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution 846system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution 847system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution 848system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution 849system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution 850system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution 851system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution 852system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution 853system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution 854system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution 855system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) 856system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) 857system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) 858system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) 859system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) 860system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) 861system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) 862system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) 863system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) 864system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) 865system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) 866system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) 867system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) 868system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 869system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) 870system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 871system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) 872system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 873system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) 874system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 875system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) 876system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 877system.cpu.icache.tags.replacements 981488 # number of replacements 878system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use 879system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. 880system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. 881system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. 882system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. 883system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor 884system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy 885system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy 886system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 887system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 888system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id 889system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id 890system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 891system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 892system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses 893system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses 894system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits 895system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits 896system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits 897system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits 898system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits 899system.cpu.icache.overall_hits::total 10460581 # number of overall hits 900system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses 901system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses 902system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses 903system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses 904system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses 905system.cpu.icache.overall_misses::total 1061360 # number of overall misses 906system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles 907system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles 908system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles 909system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles 910system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles 911system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles 912system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) 913system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) 914system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses 915system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses 916system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses 917system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses 918system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses 919system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses 920system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses 921system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses 922system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses 923system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses 924system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency 925system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency 926system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency 927system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency 928system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency 929system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency 930system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked 931system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 932system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked 933system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 934system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked 935system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 936system.cpu.icache.fast_writes 0 # number of fast writes performed 937system.cpu.icache.cache_copies 0 # number of cache copies performed 938system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits 939system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits 940system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits 941system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits 942system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits 943system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits 944system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses 945system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses 946system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses 947system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses 948system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses 949system.cpu.icache.overall_mshr_misses::total 982041 # number of overall MSHR misses 950system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583712225 # number of ReadReq MSHR miss cycles 951system.cpu.icache.ReadReq_mshr_miss_latency::total 11583712225 # number of ReadReq MSHR miss cycles 952system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583712225 # number of demand (read+write) MSHR miss cycles 953system.cpu.icache.demand_mshr_miss_latency::total 11583712225 # number of demand (read+write) MSHR miss cycles 954system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583712225 # number of overall MSHR miss cycles 955system.cpu.icache.overall_mshr_miss_latency::total 11583712225 # number of overall MSHR miss cycles 956system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8965500 # number of ReadReq MSHR uncacheable cycles 957system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8965500 # number of ReadReq MSHR uncacheable cycles 958system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8965500 # number of overall MSHR uncacheable cycles 959system.cpu.icache.overall_mshr_uncacheable_latency::total 8965500 # number of overall MSHR uncacheable cycles 960system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses 961system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses 962system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses 963system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses 964system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses 965system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses 966system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency 967system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency 968system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency 969system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency 970system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency 971system.cpu.icache.overall_avg_mshr_miss_latency::total 11795.548480 # average overall mshr miss latency 972system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 973system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 974system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 975system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 976system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 977system.cpu.l2cache.tags.replacements 64387 # number of replacements 978system.cpu.l2cache.tags.tagsinuse 51384.068329 # Cycle average of tags in use 979system.cpu.l2cache.tags.total_refs 1888247 # Total number of references to valid blocks. 980system.cpu.l2cache.tags.sampled_refs 129781 # Sample count of references to valid blocks. 981system.cpu.l2cache.tags.avg_refs 14.549487 # Average number of references to valid blocks. 982system.cpu.l2cache.tags.warmup_cycle 2490875317000 # Cycle when the warmup percentage was hit. 983system.cpu.l2cache.tags.occ_blocks::writebacks 36937.693378 # Average occupied blocks per requestor 984system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 37.347999 # Average occupied blocks per requestor 985system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor 986system.cpu.l2cache.tags.occ_blocks::cpu.inst 8175.789418 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_blocks::cpu.data 6233.237161 # Average occupied blocks per requestor 988system.cpu.l2cache.tags.occ_percent::writebacks 0.563624 # Average percentage of cache occupancy 989system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000570 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 991system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124753 # Average percentage of cache occupancy 992system.cpu.l2cache.tags.occ_percent::cpu.data 0.095112 # Average percentage of cache occupancy 993system.cpu.l2cache.tags.occ_percent::total 0.784059 # Average percentage of cache occupancy 994system.cpu.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id 995system.cpu.l2cache.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 998system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 999system.cpu.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 1000system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3046 # Occupied blocks per task id 1001system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6928 # Occupied blocks per task id 1002system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54999 # Occupied blocks per task id 1003system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id 1004system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id 1005system.cpu.l2cache.tags.tag_accesses 18797143 # Number of tag accesses 1006system.cpu.l2cache.tags.data_accesses 18797143 # Number of data accesses 1007system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53905 # number of ReadReq hits 1008system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10470 # number of ReadReq hits 1009system.cpu.l2cache.ReadReq_hits::cpu.inst 968525 # number of ReadReq hits 1010system.cpu.l2cache.ReadReq_hits::cpu.data 386928 # number of ReadReq hits 1011system.cpu.l2cache.ReadReq_hits::total 1419828 # number of ReadReq hits 1012system.cpu.l2cache.Writeback_hits::writebacks 607456 # number of Writeback hits 1013system.cpu.l2cache.Writeback_hits::total 607456 # number of Writeback hits 1014system.cpu.l2cache.UpgradeReq_hits::cpu.data 45 # number of UpgradeReq hits 1015system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits 1016system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 1017system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits 1018system.cpu.l2cache.ReadExReq_hits::cpu.data 112956 # number of ReadExReq hits 1019system.cpu.l2cache.ReadExReq_hits::total 112956 # number of ReadExReq hits 1020system.cpu.l2cache.demand_hits::cpu.dtb.walker 53905 # number of demand (read+write) hits 1021system.cpu.l2cache.demand_hits::cpu.itb.walker 10470 # number of demand (read+write) hits 1022system.cpu.l2cache.demand_hits::cpu.inst 968525 # number of demand (read+write) hits 1023system.cpu.l2cache.demand_hits::cpu.data 499884 # number of demand (read+write) hits 1024system.cpu.l2cache.demand_hits::total 1532784 # number of demand (read+write) hits 1025system.cpu.l2cache.overall_hits::cpu.dtb.walker 53905 # number of overall hits 1026system.cpu.l2cache.overall_hits::cpu.itb.walker 10470 # number of overall hits 1027system.cpu.l2cache.overall_hits::cpu.inst 968525 # number of overall hits 1028system.cpu.l2cache.overall_hits::cpu.data 499884 # number of overall hits 1029system.cpu.l2cache.overall_hits::total 1532784 # number of overall hits 1030system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses 1031system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 1032system.cpu.l2cache.ReadReq_misses::cpu.inst 12346 # number of ReadReq misses 1033system.cpu.l2cache.ReadReq_misses::cpu.data 10726 # number of ReadReq misses 1034system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses 1035system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses 1036system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses 1037system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1038system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1039system.cpu.l2cache.ReadExReq_misses::cpu.data 133222 # number of ReadExReq misses 1040system.cpu.l2cache.ReadExReq_misses::total 133222 # number of ReadExReq misses 1041system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses 1042system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 1043system.cpu.l2cache.demand_misses::cpu.inst 12346 # number of demand (read+write) misses 1044system.cpu.l2cache.demand_misses::cpu.data 143948 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::total 156349 # number of demand (read+write) misses 1046system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses 1047system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 1048system.cpu.l2cache.overall_misses::cpu.inst 12346 # number of overall misses 1049system.cpu.l2cache.overall_misses::cpu.data 143948 # number of overall misses 1050system.cpu.l2cache.overall_misses::total 156349 # number of overall misses 1051system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4489500 # number of ReadReq miss cycles 1052system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 430000 # number of ReadReq miss cycles 1053system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 894766750 # number of ReadReq miss cycles 1054system.cpu.l2cache.ReadReq_miss_latency::cpu.data 805694000 # number of ReadReq miss cycles 1055system.cpu.l2cache.ReadReq_miss_latency::total 1705380250 # number of ReadReq miss cycles 1056system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 465480 # number of UpgradeReq miss cycles 1057system.cpu.l2cache.UpgradeReq_miss_latency::total 465480 # number of UpgradeReq miss cycles 1058system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9848665479 # number of ReadExReq miss cycles 1059system.cpu.l2cache.ReadExReq_miss_latency::total 9848665479 # number of ReadExReq miss cycles 1060system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4489500 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 430000 # number of demand (read+write) miss cycles 1062system.cpu.l2cache.demand_miss_latency::cpu.inst 894766750 # number of demand (read+write) miss cycles 1063system.cpu.l2cache.demand_miss_latency::cpu.data 10654359479 # number of demand (read+write) miss cycles 1064system.cpu.l2cache.demand_miss_latency::total 11554045729 # number of demand (read+write) miss cycles 1065system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4489500 # number of overall miss cycles 1066system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 430000 # number of overall miss cycles 1067system.cpu.l2cache.overall_miss_latency::cpu.inst 894766750 # number of overall miss cycles 1068system.cpu.l2cache.overall_miss_latency::cpu.data 10654359479 # number of overall miss cycles 1069system.cpu.l2cache.overall_miss_latency::total 11554045729 # number of overall miss cycles 1070system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53958 # number of ReadReq accesses(hits+misses) 1071system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10472 # number of ReadReq accesses(hits+misses) 1072system.cpu.l2cache.ReadReq_accesses::cpu.inst 980871 # number of ReadReq accesses(hits+misses) 1073system.cpu.l2cache.ReadReq_accesses::cpu.data 397654 # number of ReadReq accesses(hits+misses) 1074system.cpu.l2cache.ReadReq_accesses::total 1442955 # number of ReadReq accesses(hits+misses) 1075system.cpu.l2cache.Writeback_accesses::writebacks 607456 # number of Writeback accesses(hits+misses) 1076system.cpu.l2cache.Writeback_accesses::total 607456 # number of Writeback accesses(hits+misses) 1077system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses) 1078system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses) 1079system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 12 # number of SCUpgradeReq accesses(hits+misses) 1080system.cpu.l2cache.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) 1081system.cpu.l2cache.ReadExReq_accesses::cpu.data 246178 # number of ReadExReq accesses(hits+misses) 1082system.cpu.l2cache.ReadExReq_accesses::total 246178 # number of ReadExReq accesses(hits+misses) 1083system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53958 # number of demand (read+write) accesses 1084system.cpu.l2cache.demand_accesses::cpu.itb.walker 10472 # number of demand (read+write) accesses 1085system.cpu.l2cache.demand_accesses::cpu.inst 980871 # number of demand (read+write) accesses 1086system.cpu.l2cache.demand_accesses::cpu.data 643832 # number of demand (read+write) accesses 1087system.cpu.l2cache.demand_accesses::total 1689133 # number of demand (read+write) accesses 1088system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53958 # number of overall (read+write) accesses 1089system.cpu.l2cache.overall_accesses::cpu.itb.walker 10472 # number of overall (read+write) accesses 1090system.cpu.l2cache.overall_accesses::cpu.inst 980871 # number of overall (read+write) accesses 1091system.cpu.l2cache.overall_accesses::cpu.data 643832 # number of overall (read+write) accesses 1092system.cpu.l2cache.overall_accesses::total 1689133 # number of overall (read+write) accesses 1093system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000982 # miss rate for ReadReq accesses 1094system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000191 # miss rate for ReadReq accesses 1095system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012587 # miss rate for ReadReq accesses 1096system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026973 # miss rate for ReadReq accesses 1097system.cpu.l2cache.ReadReq_miss_rate::total 0.016028 # miss rate for ReadReq accesses 1098system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984828 # miss rate for UpgradeReq accesses 1099system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984828 # miss rate for UpgradeReq accesses 1100system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for SCUpgradeReq accesses 1101system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses 1102system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541161 # miss rate for ReadExReq accesses 1103system.cpu.l2cache.ReadExReq_miss_rate::total 0.541161 # miss rate for ReadExReq accesses 1104system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses 1105system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000191 # miss rate for demand accesses 1106system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012587 # miss rate for demand accesses 1107system.cpu.l2cache.demand_miss_rate::cpu.data 0.223580 # miss rate for demand accesses 1108system.cpu.l2cache.demand_miss_rate::total 0.092562 # miss rate for demand accesses 1109system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses 1110system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000191 # miss rate for overall accesses 1111system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012587 # miss rate for overall accesses 1112system.cpu.l2cache.overall_miss_rate::cpu.data 0.223580 # miss rate for overall accesses 1113system.cpu.l2cache.overall_miss_rate::total 0.092562 # miss rate for overall accesses 1114system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 84707.547170 # average ReadReq miss latency 1115system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 215000 # average ReadReq miss latency 1116system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72474.222420 # average ReadReq miss latency 1117system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75115.979862 # average ReadReq miss latency 1118system.cpu.l2cache.ReadReq_avg_miss_latency::total 73739.795477 # average ReadReq miss latency 1119system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.356385 # average UpgradeReq miss latency 1120system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.356385 # average UpgradeReq miss latency 1121system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73926.719904 # average ReadExReq miss latency 1122system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73926.719904 # average ReadExReq miss latency 1123system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency 1124system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency 1125system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency 1126system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency 1127system.cpu.l2cache.demand_avg_miss_latency::total 73899.070215 # average overall miss latency 1128system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 84707.547170 # average overall miss latency 1129system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 215000 # average overall miss latency 1130system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72474.222420 # average overall miss latency 1131system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74015.335253 # average overall miss latency 1132system.cpu.l2cache.overall_avg_miss_latency::total 73899.070215 # average overall miss latency 1133system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1134system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1135system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1136system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1137system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1138system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1139system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1140system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1141system.cpu.l2cache.writebacks::writebacks 59130 # number of writebacks 1142system.cpu.l2cache.writebacks::total 59130 # number of writebacks 1143system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 14 # number of ReadReq MSHR hits 1144system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits 1145system.cpu.l2cache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits 1146system.cpu.l2cache.demand_mshr_hits::cpu.inst 14 # number of demand (read+write) MSHR hits 1147system.cpu.l2cache.demand_mshr_hits::cpu.data 67 # number of demand (read+write) MSHR hits 1148system.cpu.l2cache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits 1149system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits 1150system.cpu.l2cache.overall_mshr_hits::cpu.data 67 # number of overall MSHR hits 1151system.cpu.l2cache.overall_mshr_hits::total 81 # number of overall MSHR hits 1152system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses 1153system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 1154system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12332 # number of ReadReq MSHR misses 1155system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10659 # number of ReadReq MSHR misses 1156system.cpu.l2cache.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses 1157system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses 1158system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses 1159system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1160system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1161system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133222 # number of ReadExReq MSHR misses 1162system.cpu.l2cache.ReadExReq_mshr_misses::total 133222 # number of ReadExReq MSHR misses 1163system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses 1164system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 1165system.cpu.l2cache.demand_mshr_misses::cpu.inst 12332 # number of demand (read+write) MSHR misses 1166system.cpu.l2cache.demand_mshr_misses::cpu.data 143881 # number of demand (read+write) MSHR misses 1167system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses 1168system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses 1169system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 1170system.cpu.l2cache.overall_mshr_misses::cpu.inst 12332 # number of overall MSHR misses 1171system.cpu.l2cache.overall_mshr_misses::cpu.data 143881 # number of overall MSHR misses 1172system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses 1173system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3834000 # number of ReadReq MSHR miss cycles 1174system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 405500 # number of ReadReq MSHR miss cycles 1175system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 738779500 # number of ReadReq MSHR miss cycles 1176system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 668273250 # number of ReadReq MSHR miss cycles 1177system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1411292250 # number of ReadReq MSHR miss cycles 1178system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29213921 # number of UpgradeReq MSHR miss cycles 1179system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29213921 # number of UpgradeReq MSHR miss cycles 1180system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles 1181system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles 1182system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8190370021 # number of ReadExReq MSHR miss cycles 1183system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8190370021 # number of ReadExReq MSHR miss cycles 1184system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3834000 # number of demand (read+write) MSHR miss cycles 1185system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 405500 # number of demand (read+write) MSHR miss cycles 1186system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 738779500 # number of demand (read+write) MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8858643271 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::total 9601662271 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3834000 # number of overall MSHR miss cycles 1190system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 405500 # number of overall MSHR miss cycles 1191system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 738779500 # number of overall MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8858643271 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::total 9601662271 # number of overall MSHR miss cycles 1194system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6434999 # number of ReadReq MSHR uncacheable cycles 1195system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942201250 # number of ReadReq MSHR uncacheable cycles 1196system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948636249 # number of ReadReq MSHR uncacheable cycles 1197system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17456853479 # number of WriteReq MSHR uncacheable cycles 1198system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17456853479 # number of WriteReq MSHR uncacheable cycles 1199system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6434999 # number of overall MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles 1202system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses 1205system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses 1206system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses 1207system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses 1208system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses 1209system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses 1210system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses 1211system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses 1212system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses 1213system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses 1214system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses 1215system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses 1216system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses 1217system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses 1218system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses 1219system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses 1220system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses 1221system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses 1222system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses 1223system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency 1224system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency 1225system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency 1226system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency 1227system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency 1228system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency 1229system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency 1230system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1231system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1232system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency 1233system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency 1234system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency 1235system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency 1236system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency 1237system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency 1238system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency 1239system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency 1240system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency 1241system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency 1242system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61569.236181 # average overall mshr miss latency 1243system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61443.560236 # average overall mshr miss latency 1244system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1245system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1246system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1247system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1248system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1249system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1250system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1251system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1252system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1253system.cpu.dcache.tags.replacements 643320 # number of replacements 1254system.cpu.dcache.tags.tagsinuse 511.993245 # Cycle average of tags in use 1255system.cpu.dcache.tags.total_refs 21508532 # Total number of references to valid blocks. 1256system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. 1257system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. 1258system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. 1259system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor 1260system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy 1261system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy 1262system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1263system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 1264system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 1265system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 1266system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1267system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses 1268system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses 1269system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits 1270system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits 1271system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits 1272system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits 1273system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits 1274system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits 1275system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits 1276system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits 1277system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits 1278system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits 1279system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits 1280system.cpu.dcache.overall_hits::total 21015072 # number of overall hits 1281system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses 1282system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses 1283system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses 1284system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses 1285system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses 1286system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses 1287system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses 1288system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses 1289system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses 1290system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses 1291system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses 1292system.cpu.dcache.overall_misses::total 3699212 # number of overall misses 1293system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles 1294system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles 1295system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles 1296system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles 1297system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles 1298system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles 1299system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles 1300system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles 1301system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles 1302system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles 1303system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles 1304system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles 1305system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) 1306system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) 1307system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) 1308system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) 1309system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) 1310system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) 1311system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) 1312system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) 1313system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses 1314system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses 1315system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses 1316system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses 1317system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses 1318system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses 1319system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses 1320system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses 1321system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses 1322system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses 1323system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses 1324system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses 1325system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses 1326system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses 1327system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses 1328system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses 1329system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency 1330system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency 1331system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency 1332system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency 1333system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency 1334system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency 1335system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency 1336system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency 1337system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency 1338system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency 1339system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency 1340system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency 1341system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked 1342system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked 1343system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked 1344system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked 1345system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked 1346system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked 1347system.cpu.dcache.fast_writes 0 # number of fast writes performed 1348system.cpu.dcache.cache_copies 0 # number of cache copies performed 1349system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks 1350system.cpu.dcache.writebacks::total 607456 # number of writebacks 1351system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits 1352system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits 1353system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits 1354system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits 1355system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits 1356system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits 1357system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits 1358system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits 1359system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits 1360system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits 1361system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses 1362system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses 1363system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses 1364system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses 1365system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses 1366system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses 1367system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses 1368system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses 1369system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses 1370system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses 1371system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses 1372system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses 1373system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles 1374system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles 1375system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles 1376system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles 1377system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles 1378system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles 1379system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles 1380system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles 1381system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles 1382system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles 1383system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles 1384system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles 1385system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles 1386system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles 1387system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles 1388system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles 1389system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles 1390system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles 1391system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses 1392system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses 1393system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses 1394system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses 1395system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses 1396system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses 1397system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses 1398system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses 1399system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses 1400system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses 1401system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses 1402system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses 1403system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency 1404system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency 1405system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency 1406system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency 1407system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency 1408system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency 1409system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency 1410system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency 1411system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency 1412system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency 1413system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency 1414system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency 1415system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1416system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1417system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1418system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1419system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1420system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1421system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1422system.iocache.tags.replacements 0 # number of replacements 1423system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1424system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1425system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1426system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1427system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1428system.iocache.tags.tag_accesses 0 # Number of tag accesses 1429system.iocache.tags.data_accesses 0 # Number of data accesses 1430system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1431system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1432system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1433system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1434system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1435system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1436system.iocache.fast_writes 0 # number of fast writes performed 1437system.iocache.cache_copies 0 # number of cache copies performed 1438system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles 1439system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles 1440system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles 1441system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles 1442system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1443system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1444system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1445system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1446system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1447system.cpu.kern.inst.arm 0 # number of arm instructions executed 1448system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed 1449 1450---------- End Simulation Statistics ---------- |