1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.524310 # Number of seconds simulated
4sim_ticks 2524309551500 # Number of ticks simulated
5final_tick 2524309551500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 65403 # Simulator instruction rate (inst/s)
8host_op_rate 84155 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2737677908 # Simulator tick rate (ticks/s)
10host_mem_usage 401408 # Number of bytes of host memory used
11host_seconds 922.06 # Real time elapsed on the host
12sim_insts 60305560 # Number of instructions simulated
13sim_ops 77596391 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory
19system.physmem.bytes_read::total 129431632 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6799624 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 15096835 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 813136 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47354598 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 1293 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 315575 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3602557 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 51274073 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 315575 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 315575 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1498846 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1194811 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2693657 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1498846 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47354598 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 1293 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 315575 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 4797367 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 53967730 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.readReqs 15096835 # Total number of read requests accepted by DRAM controller
53system.physmem.writeReqs 813136 # Total number of write requests accepted by DRAM controller
54system.physmem.readBursts 15096835 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
55system.physmem.writeBursts 813136 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
56system.physmem.bytesRead 966197440 # Total number of bytes read from memory
57system.physmem.bytesWritten 52040704 # Total number of bytes written to memory
58system.physmem.bytesConsumedRd 129431632 # bytesRead derated as per pkt->getSize()
59system.physmem.bytesConsumedWr 6799624 # bytesWritten derated as per pkt->getSize()
60system.physmem.servicedByWrQ 6192 # Number of DRAM read bursts serviced by write Q
61system.physmem.neitherReadNorWrite 4675 # Reqs where no action is needed
62system.physmem.perBankRdReqs::0 943576 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::1 943244 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::2 943285 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::3 942562 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::4 943112 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::5 943339 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::6 943114 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::7 941930 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::9 943651 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::10 943211 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::11 941608 # Track reads on a per bank basis
74system.physmem.perBankRdReqs::12 943926 # Track reads on a per bank basis
75system.physmem.perBankRdReqs::13 943681 # Track reads on a per bank basis
76system.physmem.perBankRdReqs::14 943781 # Track reads on a per bank basis
77system.physmem.perBankRdReqs::15 942622 # Track reads on a per bank basis
78system.physmem.perBankWrReqs::0 6701 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::1 6473 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::2 6622 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::3 6647 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::4 6560 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::5 6809 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::6 6802 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::7 6725 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::8 7149 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::9 6889 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::10 6554 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::11 6197 # Track writes on a per bank basis
90system.physmem.perBankWrReqs::12 7152 # Track writes on a per bank basis
91system.physmem.perBankWrReqs::13 6775 # Track writes on a per bank basis
92system.physmem.perBankWrReqs::14 7049 # Track writes on a per bank basis
93system.physmem.perBankWrReqs::15 6917 # Track writes on a per bank basis
94system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
95system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
96system.physmem.totGap 2524308440000 # Total gap between requests
97system.physmem.readPktSize::0 0 # Categorize read packet sizes
98system.physmem.readPktSize::1 0 # Categorize read packet sizes
99system.physmem.readPktSize::2 36 # Categorize read packet sizes
100system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
101system.physmem.readPktSize::4 0 # Categorize read packet sizes
102system.physmem.readPktSize::5 0 # Categorize read packet sizes
103system.physmem.readPktSize::6 154591 # Categorize read packet sizes
104system.physmem.writePktSize::0 0 # Categorize write packet sizes
105system.physmem.writePktSize::1 0 # Categorize write packet sizes
106system.physmem.writePktSize::2 754018 # Categorize write packet sizes
107system.physmem.writePktSize::3 0 # Categorize write packet sizes
108system.physmem.writePktSize::4 0 # Categorize write packet sizes
109system.physmem.writePktSize::5 0 # Categorize write packet sizes
110system.physmem.writePktSize::6 59118 # Categorize write packet sizes
111system.physmem.rdQLenPdf::0 1057147 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::1 988434 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::2 981496 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::3 3682842 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::4 2771885 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::5 2756532 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::6 2709889 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::7 18251 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::8 16218 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::9 29451 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::10 42435 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::11 28819 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::12 1928 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::13 1827 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::14 1752 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::15 1697 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
143system.physmem.wrQLenPdf::0 4688 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::1 4695 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::2 4697 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::3 4697 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::4 4697 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::5 4697 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::6 4697 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::7 4697 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::8 4697 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::9 4697 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::10 4697 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::11 4697 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::12 4697 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::13 4696 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::14 4696 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::15 4696 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::16 4696 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::17 4696 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::18 4696 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::19 4696 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::20 4696 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::22 4696 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
175system.physmem.bytesPerActivate::samples 39039 # Bytes accessed per row activation
176system.physmem.bytesPerActivate::mean 24916.423474 # Bytes accessed per row activation
177system.physmem.bytesPerActivate::gmean 2046.440838 # Bytes accessed per row activation
178system.physmem.bytesPerActivate::stdev 31393.496682 # Bytes accessed per row activation
179system.physmem.bytesPerActivate::64-79 6673 17.09% 17.09% # Bytes accessed per row activation
180system.physmem.bytesPerActivate::128-143 3432 8.79% 25.88% # Bytes accessed per row activation
181system.physmem.bytesPerActivate::192-207 2242 5.74% 31.63% # Bytes accessed per row activation
182system.physmem.bytesPerActivate::256-271 1810 4.64% 36.26% # Bytes accessed per row activation
183system.physmem.bytesPerActivate::320-335 1230 3.15% 39.41% # Bytes accessed per row activation
184system.physmem.bytesPerActivate::384-399 1032 2.64% 42.06% # Bytes accessed per row activation
185system.physmem.bytesPerActivate::448-463 839 2.15% 44.21% # Bytes accessed per row activation
186system.physmem.bytesPerActivate::512-527 821 2.10% 46.31% # Bytes accessed per row activation
187system.physmem.bytesPerActivate::576-591 572 1.47% 47.78% # Bytes accessed per row activation
188system.physmem.bytesPerActivate::640-655 506 1.30% 49.07% # Bytes accessed per row activation
189system.physmem.bytesPerActivate::704-719 409 1.05% 50.12% # Bytes accessed per row activation
190system.physmem.bytesPerActivate::768-783 444 1.14% 51.26% # Bytes accessed per row activation
191system.physmem.bytesPerActivate::832-847 300 0.77% 52.02% # Bytes accessed per row activation
192system.physmem.bytesPerActivate::896-911 247 0.63% 52.66% # Bytes accessed per row activation
193system.physmem.bytesPerActivate::960-975 176 0.45% 53.11% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::1024-1039 206 0.53% 53.64% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::1088-1103 143 0.37% 54.00% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::1152-1167 146 0.37% 54.38% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::1216-1231 98 0.25% 54.63% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::1280-1295 114 0.29% 54.92% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::1344-1359 72 0.18% 55.10% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1408-1423 399 1.02% 56.13% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1472-1487 280 0.72% 56.84% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1536-1551 475 1.22% 58.06% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::1600-1615 79 0.20% 58.26% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1664-1679 157 0.40% 58.66% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::1728-1743 41 0.11% 58.77% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::1792-1807 100 0.26% 59.03% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::1856-1871 28 0.07% 59.10% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1920-1935 78 0.20% 59.30% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::1984-1999 27 0.07% 59.37% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::2048-2063 49 0.13% 59.49% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::2112-2127 25 0.06% 59.56% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::2176-2191 51 0.13% 59.69% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::2240-2255 21 0.05% 59.74% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::2304-2319 30 0.08% 59.82% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::2368-2383 17 0.04% 59.86% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::2432-2447 27 0.07% 59.93% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::2496-2511 11 0.03% 59.96% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::2560-2575 21 0.05% 60.01% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::2624-2639 5 0.01% 60.02% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::2688-2703 18 0.05% 60.07% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::2752-2767 7 0.02% 60.09% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::2816-2831 11 0.03% 60.12% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::2880-2895 7 0.02% 60.13% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::2944-2959 14 0.04% 60.17% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::3008-3023 6 0.02% 60.19% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::3072-3087 22 0.06% 60.24% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::3136-3151 6 0.02% 60.26% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::3200-3215 7 0.02% 60.28% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::3264-3279 4 0.01% 60.29% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::3328-3343 12 0.03% 60.32% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::3392-3407 5 0.01% 60.33% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::3456-3471 8 0.02% 60.35% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::3520-3535 5 0.01% 60.36% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::3584-3599 9 0.02% 60.39% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::3648-3663 4 0.01% 60.40% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::3712-3727 6 0.02% 60.41% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::3776-3791 3 0.01% 60.42% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::3840-3855 8 0.02% 60.44% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::3904-3919 3 0.01% 60.45% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::3968-3983 10 0.03% 60.47% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::4032-4047 5 0.01% 60.49% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::4096-4111 44 0.11% 60.60% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::4160-4175 3 0.01% 60.61% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::4224-4239 1 0.00% 60.61% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::4288-4303 5 0.01% 60.62% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::4352-4367 9 0.02% 60.64% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::4416-4431 4 0.01% 60.65% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::4480-4495 1 0.00% 60.66% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::4544-4559 3 0.01% 60.66% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::4608-4623 9 0.02% 60.69% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::4672-4687 1 0.00% 60.69% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::4736-4751 4 0.01% 60.70% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::4800-4815 1 0.00% 60.70% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::4864-4879 2 0.01% 60.71% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::4928-4943 2 0.01% 60.71% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::4992-5007 4 0.01% 60.72% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::5120-5135 7 0.02% 60.74% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::5248-5263 3 0.01% 60.75% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::5312-5327 1 0.00% 60.75% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::5376-5391 4 0.01% 60.76% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::5440-5455 1 0.00% 60.76% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::5504-5519 3 0.01% 60.77% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::5632-5647 2 0.01% 60.78% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::5696-5711 1 0.00% 60.78% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::5760-5775 3 0.01% 60.79% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::5888-5903 3 0.01% 60.80% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::5952-5967 1 0.00% 60.80% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::6016-6031 1 0.00% 60.80% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::6144-6159 6 0.02% 60.82% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::6208-6223 1 0.00% 60.82% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::6272-6287 3 0.01% 60.83% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::6400-6415 3 0.01% 60.83% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::6464-6479 4 0.01% 60.84% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::6528-6543 3 0.01% 60.85% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::6592-6607 2 0.01% 60.86% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::6720-6735 2 0.01% 60.86% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::6784-6799 18 0.05% 60.91% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::6848-6863 4 0.01% 60.92% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::7040-7055 3 0.01% 60.93% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::7168-7183 4 0.01% 60.94% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::7296-7311 4 0.01% 60.95% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::7360-7375 1 0.00% 60.95% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::7424-7439 12 0.03% 60.98% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::7488-7503 1 0.00% 60.98% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::7552-7567 2 0.01% 60.99% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::7680-7695 9 0.02% 61.01% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::7808-7823 3 0.01% 61.02% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::7872-7887 2 0.01% 61.02% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::7936-7951 5 0.01% 61.04% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::8000-8015 1 0.00% 61.04% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::8064-8079 7 0.02% 61.06% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::8128-8143 2 0.01% 61.06% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::8192-8207 325 0.83% 61.89% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::8448-8463 41 0.11% 62.00% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::8512-8527 123 0.32% 62.31% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::8576-8591 7 0.02% 62.33% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::8704-8719 1 0.00% 62.34% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::8768-8783 1 0.00% 62.34% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::8832-8847 2 0.01% 62.34% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::9216-9231 8 0.02% 62.36% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::9472-9487 2 0.01% 62.37% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::9728-9743 1 0.00% 62.37% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::9984-9999 1 0.00% 62.37% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::10240-10255 2 0.01% 62.38% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::12288-12303 3 0.01% 62.39% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::12544-12559 2 0.01% 62.39% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::13056-13071 1 0.00% 62.39% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::13312-13327 3 0.01% 62.40% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::13568-13583 2 0.01% 62.41% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::13824-13839 1 0.00% 62.41% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::14080-14095 1 0.00% 62.41% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::14336-14351 4 0.01% 62.42% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::14592-14607 2 0.01% 62.43% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::14976-14991 1 0.00% 62.43% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::15104-15119 1 0.00% 62.43% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::15360-15375 1 0.00% 62.44% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::16384-16399 1 0.00% 62.44% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::17152-17167 3 0.01% 62.45% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::17408-17423 3 0.01% 62.45% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::17664-17679 2 0.01% 62.46% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::17920-17935 1 0.00% 62.46% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::18176-18191 2 0.01% 62.47% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::18432-18447 2 0.01% 62.47% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::18688-18703 1 0.00% 62.47% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::19200-19215 2 0.01% 62.48% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::19456-19471 3 0.01% 62.49% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::19712-19727 1 0.00% 62.49% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::21504-21519 1 0.00% 62.49% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::21760-21775 1 0.00% 62.49% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::22208-22223 1 0.00% 62.50% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::22272-22287 2 0.01% 62.50% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::22528-22543 4 0.01% 62.51% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::22784-22799 3 0.01% 62.52% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::23296-23311 1 0.00% 62.52% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::23552-23567 3 0.01% 62.53% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::23616-23631 1 0.00% 62.53% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::23680-23695 1 0.00% 62.53% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::24320-24335 1 0.00% 62.54% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::24576-24591 2 0.01% 62.54% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::25344-25359 2 0.01% 62.55% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::25600-25615 3 0.01% 62.56% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::26112-26127 2 0.01% 62.56% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::26368-26383 1 0.00% 62.56% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::26624-26639 1 0.00% 62.57% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::27136-27151 1 0.00% 62.57% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::27648-27663 2 0.01% 62.57% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::27904-27919 4 0.01% 62.58% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::28416-28431 1 0.00% 62.59% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::28672-28687 1 0.00% 62.59% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::28928-28943 1 0.00% 62.59% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::29184-29199 2 0.01% 62.60% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::29440-29455 1 0.00% 62.60% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::30464-30479 1 0.00% 62.60% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::30720-30735 4 0.01% 62.61% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::30976-30991 1 0.00% 62.61% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::31360-31375 1 0.00% 62.62% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::31744-31759 3 0.01% 62.62% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::32768-32783 2 0.01% 62.63% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::33536-33551 12 0.03% 62.66% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::33600-33615 1 0.00% 62.66% # Bytes accessed per row activation
361system.physmem.bytesPerActivate::33728-33743 1 0.00% 62.67% # Bytes accessed per row activation
362system.physmem.bytesPerActivate::33792-33807 45 0.12% 62.78% # Bytes accessed per row activation
363system.physmem.bytesPerActivate::34816-34831 1 0.00% 62.78% # Bytes accessed per row activation
364system.physmem.bytesPerActivate::36352-36367 1 0.00% 62.79% # Bytes accessed per row activation
365system.physmem.bytesPerActivate::37632-37647 1 0.00% 62.79% # Bytes accessed per row activation
366system.physmem.bytesPerActivate::39424-39439 1 0.00% 62.79% # Bytes accessed per row activation
367system.physmem.bytesPerActivate::40256-40271 1 0.00% 62.79% # Bytes accessed per row activation
368system.physmem.bytesPerActivate::41216-41231 1 0.00% 62.80% # Bytes accessed per row activation
369system.physmem.bytesPerActivate::41728-41743 1 0.00% 62.80% # Bytes accessed per row activation
370system.physmem.bytesPerActivate::42752-42767 1 0.00% 62.80% # Bytes accessed per row activation
371system.physmem.bytesPerActivate::44288-44303 1 0.00% 62.80% # Bytes accessed per row activation
372system.physmem.bytesPerActivate::45184-45199 1 0.00% 62.81% # Bytes accessed per row activation
373system.physmem.bytesPerActivate::46080-46095 1 0.00% 62.81% # Bytes accessed per row activation
374system.physmem.bytesPerActivate::47232-47247 1 0.00% 62.81% # Bytes accessed per row activation
375system.physmem.bytesPerActivate::47360-47375 1 0.00% 62.81% # Bytes accessed per row activation
376system.physmem.bytesPerActivate::47616-47631 1 0.00% 62.82% # Bytes accessed per row activation
377system.physmem.bytesPerActivate::48384-48399 1 0.00% 62.82% # Bytes accessed per row activation
378system.physmem.bytesPerActivate::49728-49743 1 0.00% 62.82% # Bytes accessed per row activation
379system.physmem.bytesPerActivate::50240-50255 1 0.00% 62.82% # Bytes accessed per row activation
380system.physmem.bytesPerActivate::50304-50319 1 0.00% 62.83% # Bytes accessed per row activation
381system.physmem.bytesPerActivate::50560-50575 1 0.00% 62.83% # Bytes accessed per row activation
382system.physmem.bytesPerActivate::50752-50767 1 0.00% 62.83% # Bytes accessed per row activation
383system.physmem.bytesPerActivate::51392-51407 1 0.00% 62.83% # Bytes accessed per row activation
384system.physmem.bytesPerActivate::51712-51727 1 0.00% 62.84% # Bytes accessed per row activation
385system.physmem.bytesPerActivate::51968-51983 1 0.00% 62.84% # Bytes accessed per row activation
386system.physmem.bytesPerActivate::52224-52239 1 0.00% 62.84% # Bytes accessed per row activation
387system.physmem.bytesPerActivate::53248-53263 1 0.00% 62.84% # Bytes accessed per row activation
388system.physmem.bytesPerActivate::53824-53839 1 0.00% 62.85% # Bytes accessed per row activation
389system.physmem.bytesPerActivate::56320-56335 2 0.01% 62.85% # Bytes accessed per row activation
390system.physmem.bytesPerActivate::58368-58383 1 0.00% 62.86% # Bytes accessed per row activation
391system.physmem.bytesPerActivate::59392-59407 2 0.01% 62.86% # Bytes accessed per row activation
392system.physmem.bytesPerActivate::60416-60431 2 0.01% 62.87% # Bytes accessed per row activation
393system.physmem.bytesPerActivate::61120-61135 1 0.00% 62.87% # Bytes accessed per row activation
394system.physmem.bytesPerActivate::61184-61199 1 0.00% 62.87% # Bytes accessed per row activation
395system.physmem.bytesPerActivate::61440-61455 1 0.00% 62.87% # Bytes accessed per row activation
396system.physmem.bytesPerActivate::63936-63951 1 0.00% 62.88% # Bytes accessed per row activation
397system.physmem.bytesPerActivate::64512-64527 1 0.00% 62.88% # Bytes accessed per row activation
398system.physmem.bytesPerActivate::65024-65039 192 0.49% 63.37% # Bytes accessed per row activation
399system.physmem.bytesPerActivate::65280-65295 6 0.02% 63.39% # Bytes accessed per row activation
400system.physmem.bytesPerActivate::65536-65551 14116 36.16% 99.54% # Bytes accessed per row activation
401system.physmem.bytesPerActivate::66048-66063 1 0.00% 99.55% # Bytes accessed per row activation
402system.physmem.bytesPerActivate::69760-69775 1 0.00% 99.55% # Bytes accessed per row activation
403system.physmem.bytesPerActivate::73536-73551 1 0.00% 99.55% # Bytes accessed per row activation
404system.physmem.bytesPerActivate::73856-73871 2 0.01% 99.56% # Bytes accessed per row activation
405system.physmem.bytesPerActivate::73920-73935 24 0.06% 99.62% # Bytes accessed per row activation
406system.physmem.bytesPerActivate::73984-73999 78 0.20% 99.82% # Bytes accessed per row activation
407system.physmem.bytesPerActivate::74048-74063 68 0.17% 99.99% # Bytes accessed per row activation
408system.physmem.bytesPerActivate::74112-74127 3 0.01% 100.00% # Bytes accessed per row activation
409system.physmem.bytesPerActivate::total 39039 # Bytes accessed per row activation
410system.physmem.totQLat 291463008250 # Total cycles spent in queuing delays
411system.physmem.totMemAccLat 382223273250 # Sum of mem lat for all requests
412system.physmem.totBusLat 75453215000 # Total cycles spent in databus access
413system.physmem.totBankLat 15307050000 # Total cycles spent in bank access
414system.physmem.avgQLat 19314.15 # Average queueing delay per request
415system.physmem.avgBankLat 1014.34 # Average bank access latency per request
416system.physmem.avgBusLat 5000.00 # Average bus latency per request
417system.physmem.avgMemAccLat 25328.49 # Average memory access latency
418system.physmem.avgRdBW 382.76 # Average achieved read bandwidth in MB/s
419system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s
420system.physmem.avgConsumedRdBW 51.27 # Average consumed read bandwidth in MB/s
421system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s
422system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
423system.physmem.busUtil 3.15 # Data bus utilization in percentage
424system.physmem.avgRdQLen 0.15 # Average read queue length over time
425system.physmem.avgWrQLen 14.41 # Average write queue length over time
426system.physmem.readRowHits 15065383 # Number of row buffer hits during reads
427system.physmem.writeRowHits 94229 # Number of row buffer hits during writes
428system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
429system.physmem.writeRowHitRate 11.59 # Row buffer hit rate for writes
430system.physmem.avgGap 158662.04 # Average gap between requests
431system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
432system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
433system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
434system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
435system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
436system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
437system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
438system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
439system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
440system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
441system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
442system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
443system.membus.throughput 54917647 # Throughput (bytes/s)
444system.membus.trans_dist::ReadReq 16149440 # Transaction distribution
445system.membus.trans_dist::ReadResp 16149440 # Transaction distribution
446system.membus.trans_dist::WriteReq 763332 # Transaction distribution
447system.membus.trans_dist::WriteResp 763332 # Transaction distribution
448system.membus.trans_dist::Writeback 59118 # Transaction distribution
449system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution
450system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
451system.membus.trans_dist::UpgradeResp 4675 # Transaction distribution
452system.membus.trans_dist::ReadExReq 131433 # Transaction distribution
453system.membus.trans_dist::ReadExResp 131433 # Transaction distribution
454system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382940 # Packet count per connected master and slave (bytes)
455system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
456system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
457system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
458system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885758 # Packet count per connected master and slave (bytes)
459system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272462 # Packet count per connected master and slave (bytes)
460system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
461system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
462system.membus.pkt_count::total 34156878 # Packet count per connected master and slave (bytes)
463system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390297 # Cumulative packet size per connected master and slave (bytes)
464system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
465system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
466system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
467system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
468system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091477 # Cumulative packet size per connected master and slave (bytes)
469system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
470system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
471system.membus.tot_pkt_size::total 138629141 # Cumulative packet size per connected master and slave (bytes)
472system.membus.data_through_bus 138629141 # Total data (bytes)
473system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
474system.membus.reqLayer0.occupancy 1475500000 # Layer occupancy (ticks)
475system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
476system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
477system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
478system.membus.reqLayer2.occupancy 3702500 # Layer occupancy (ticks)
479system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
480system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
481system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
482system.membus.reqLayer6.occupancy 17367026000 # Layer occupancy (ticks)
483system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
484system.membus.respLayer1.occupancy 4748565769 # Layer occupancy (ticks)
485system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
486system.membus.respLayer2.occupancy 33728733739 # Layer occupancy (ticks)
487system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
488system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
489system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
490system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
491system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
492system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
493system.cf0.dma_write_txs 0 # Number of DMA write transactions.
494system.iobus.throughput 48301509 # Throughput (bytes/s)
495system.iobus.trans_dist::ReadReq 16125521 # Transaction distribution
496system.iobus.trans_dist::ReadResp 16125521 # Transaction distribution
497system.iobus.trans_dist::WriteReq 8157 # Transaction distribution
498system.iobus.trans_dist::WriteResp 8157 # Transaction distribution
499system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
500system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
501system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
502system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
503system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
504system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
505system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
506system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
507system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
508system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)

--- 5 unchanged lines hidden (view full) ---

514system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
515system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
516system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
517system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
518system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
519system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
520system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
521system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
522system.iobus.pkt_count_system.bridge.master::total 2382940 # Packet count per connected master and slave (bytes)
523system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
524system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
525system.iobus.pkt_count::total 32267356 # Packet count per connected master and slave (bytes)
526system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
527system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
528system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
529system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
530system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
531system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
532system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
533system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
534system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
535system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 5 unchanged lines hidden (view full) ---

541system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
542system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
543system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
544system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
545system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
546system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
547system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
548system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
549system.iobus.tot_pkt_size_system.bridge.master::total 2390297 # Cumulative packet size per connected master and slave (bytes)
550system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
551system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
552system.iobus.tot_pkt_size::total 121927961 # Cumulative packet size per connected master and slave (bytes)
553system.iobus.data_through_bus 121927961 # Total data (bytes)
554system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
555system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
556system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
557system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
558system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
559system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
560system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
561system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
562system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
563system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
564system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)

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594system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
595system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
596system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
597system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
598system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
599system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
600system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
601system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
602system.iobus.respLayer0.occupancy 2374783000 # Layer occupancy (ticks)
603system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
604system.iobus.respLayer1.occupancy 40954817261 # Layer occupancy (ticks)
605system.iobus.respLayer1.utilization 1.6 # Layer utilization (%)
606system.cpu.branchPred.lookups 14390442 # Number of BP lookups
607system.cpu.branchPred.condPredicted 11476977 # Number of conditional branches predicted
608system.cpu.branchPred.condIncorrect 705087 # Number of conditional branches incorrect
609system.cpu.branchPred.BTBLookups 9493942 # Number of BTB lookups
610system.cpu.branchPred.BTBHits 7662575 # Number of BTB hits
611system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
612system.cpu.branchPred.BTBHitPct 80.710152 # BTB Hit Percentage
613system.cpu.branchPred.usedRAS 1400623 # Number of times the RAS was used to get a target.
614system.cpu.branchPred.RASInCorrect 72808 # Number of incorrect RAS predictions.
615system.cpu.dtb.inst_hits 0 # ITB inst hits
616system.cpu.dtb.inst_misses 0 # ITB inst misses
617system.cpu.dtb.read_hits 51188083 # DTB read hits
618system.cpu.dtb.read_misses 64353 # DTB read misses
619system.cpu.dtb.write_hits 11697459 # DTB write hits
620system.cpu.dtb.write_misses 15788 # DTB write misses
621system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
622system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
623system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
624system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
625system.cpu.dtb.flush_entries 3561 # Number of entries that have been flushed from TLB
626system.cpu.dtb.align_faults 2446 # Number of TLB faults due to alignment restrictions
627system.cpu.dtb.prefetch_faults 415 # Number of TLB faults due to prefetch
628system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
629system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions
630system.cpu.dtb.read_accesses 51252436 # DTB read accesses
631system.cpu.dtb.write_accesses 11713247 # DTB write accesses
632system.cpu.dtb.inst_accesses 0 # ITB inst accesses
633system.cpu.dtb.hits 62885542 # DTB hits
634system.cpu.dtb.misses 80141 # DTB misses
635system.cpu.dtb.accesses 62965683 # DTB accesses
636system.cpu.itb.inst_hits 11520428 # ITB inst hits
637system.cpu.itb.inst_misses 11439 # ITB inst misses
638system.cpu.itb.read_hits 0 # DTB read hits
639system.cpu.itb.read_misses 0 # DTB read misses
640system.cpu.itb.write_hits 0 # DTB write hits
641system.cpu.itb.write_misses 0 # DTB write misses
642system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
643system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
644system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
645system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
646system.cpu.itb.flush_entries 2486 # Number of entries that have been flushed from TLB
647system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
648system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
649system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
650system.cpu.itb.perms_faults 2948 # Number of TLB faults due to permissions restrictions
651system.cpu.itb.read_accesses 0 # DTB read accesses
652system.cpu.itb.write_accesses 0 # DTB write accesses
653system.cpu.itb.inst_accesses 11531867 # ITB inst accesses
654system.cpu.itb.hits 11520428 # DTB hits
655system.cpu.itb.misses 11439 # DTB misses
656system.cpu.itb.accesses 11531867 # DTB accesses
657system.cpu.numCycles 473080437 # number of cpu cycles simulated
658system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
659system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
660system.cpu.fetch.icacheStallCycles 29726178 # Number of cycles fetch is stalled on an Icache miss
661system.cpu.fetch.Insts 90285458 # Number of instructions fetch has processed
662system.cpu.fetch.Branches 14390442 # Number of branches that fetch encountered
663system.cpu.fetch.predictedBranches 9063198 # Number of branches that fetch has predicted taken
664system.cpu.fetch.Cycles 20148067 # Number of cycles fetch has run and was not squashing or blocked
665system.cpu.fetch.SquashCycles 4655224 # Number of cycles fetch has spent squashing
666system.cpu.fetch.TlbCycles 122776 # Number of cycles fetch has spent waiting for tlb
667system.cpu.fetch.BlockedCycles 94622822 # Number of cycles fetch has spent blocked
668system.cpu.fetch.MiscStallCycles 2576 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
669system.cpu.fetch.PendingTrapStallCycles 87000 # Number of stall cycles due to pending traps
670system.cpu.fetch.PendingQuiesceStallCycles 2672031 # Number of stall cycles due to pending quiesce instructions
671system.cpu.fetch.IcacheWaitRetryStallCycles 423 # Number of stall cycles due to full MSHR
672system.cpu.fetch.CacheLines 11516980 # Number of cache lines fetched
673system.cpu.fetch.IcacheSquashes 710202 # Number of outstanding Icache misses that were squashed
674system.cpu.fetch.ItlbSquashes 5463 # Number of outstanding ITLB misses that were squashed
675system.cpu.fetch.rateDist::samples 150589774 # Number of instructions fetched each cycle (Total)
676system.cpu.fetch.rateDist::mean 0.747645 # Number of instructions fetched each cycle (Total)
677system.cpu.fetch.rateDist::stdev 2.103384 # Number of instructions fetched each cycle (Total)
678system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
679system.cpu.fetch.rateDist::0 130457024 86.63% 86.63% # Number of instructions fetched each cycle (Total)
680system.cpu.fetch.rateDist::1 1304262 0.87% 87.50% # Number of instructions fetched each cycle (Total)
681system.cpu.fetch.rateDist::2 1711201 1.14% 88.63% # Number of instructions fetched each cycle (Total)
682system.cpu.fetch.rateDist::3 2296542 1.53% 90.16% # Number of instructions fetched each cycle (Total)
683system.cpu.fetch.rateDist::4 2101589 1.40% 91.55% # Number of instructions fetched each cycle (Total)
684system.cpu.fetch.rateDist::5 1109749 0.74% 92.29% # Number of instructions fetched each cycle (Total)
685system.cpu.fetch.rateDist::6 2556764 1.70% 93.99% # Number of instructions fetched each cycle (Total)
686system.cpu.fetch.rateDist::7 745428 0.50% 94.48% # Number of instructions fetched each cycle (Total)
687system.cpu.fetch.rateDist::8 8307215 5.52% 100.00% # Number of instructions fetched each cycle (Total)
688system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
689system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
690system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
691system.cpu.fetch.rateDist::total 150589774 # Number of instructions fetched each cycle (Total)
692system.cpu.fetch.branchRate 0.030419 # Number of branch fetches per cycle
693system.cpu.fetch.rate 0.190846 # Number of inst fetches per cycle
694system.cpu.decode.IdleCycles 31488393 # Number of cycles decode is idle
695system.cpu.decode.BlockedCycles 96724206 # Number of cycles decode is blocked
696system.cpu.decode.RunCycles 18371972 # Number of cycles decode is running
697system.cpu.decode.UnblockCycles 966714 # Number of cycles decode is unblocking
698system.cpu.decode.SquashCycles 3038489 # Number of cycles decode is squashing
699system.cpu.decode.BranchResolved 1954982 # Number of times decode resolved a branch
700system.cpu.decode.BranchMispred 171905 # Number of times decode detected a branch misprediction
701system.cpu.decode.DecodedInsts 107292337 # Number of instructions handled by decode
702system.cpu.decode.SquashedInsts 568657 # Number of squashed instructions handled by decode
703system.cpu.rename.SquashCycles 3038489 # Number of cycles rename is squashing
704system.cpu.rename.IdleCycles 33240542 # Number of cycles rename is idle
705system.cpu.rename.BlockCycles 38064536 # Number of cycles rename is blocking
706system.cpu.rename.serializeStallCycles 52670739 # count of cycles rename stalled for serializing inst
707system.cpu.rename.RunCycles 17528991 # Number of cycles rename is running
708system.cpu.rename.UnblockCycles 6046477 # Number of cycles rename is unblocking
709system.cpu.rename.RenamedInsts 102291911 # Number of instructions processed by rename
710system.cpu.rename.ROBFullEvents 20574 # Number of times rename has blocked due to ROB full
711system.cpu.rename.IQFullEvents 1004468 # Number of times rename has blocked due to IQ full
712system.cpu.rename.LSQFullEvents 4066422 # Number of times rename has blocked due to LSQ full
713system.cpu.rename.FullRegisterEvents 675 # Number of times there has been no free registers
714system.cpu.rename.RenamedOperands 106031051 # Number of destination operands rename has renamed
715system.cpu.rename.RenameLookups 466975975 # Number of register rename lookups that rename has made
716system.cpu.rename.int_rename_lookups 432104229 # Number of integer rename lookups
717system.cpu.rename.fp_rename_lookups 10389 # Number of floating rename lookups
718system.cpu.rename.CommittedMaps 78387144 # Number of HB maps that are committed
719system.cpu.rename.UndoneMaps 27643906 # Number of HB maps that are undone due to squashing
720system.cpu.rename.serializingInsts 830126 # count of serializing insts renamed
721system.cpu.rename.tempSerializingInsts 736572 # count of temporary serializing insts renamed
722system.cpu.rename.skidInsts 12200321 # count of insts added to the skid buffer
723system.cpu.memDep0.insertedLoads 19725062 # Number of loads inserted to the mem dependence unit.
724system.cpu.memDep0.insertedStores 13304379 # Number of stores inserted to the mem dependence unit.
725system.cpu.memDep0.conflictingLoads 1973962 # Number of conflicting loads.
726system.cpu.memDep0.conflictingStores 2485771 # Number of conflicting stores.
727system.cpu.iq.iqInstsAdded 95123211 # Number of instructions added to the IQ (excludes non-spec)
728system.cpu.iq.iqNonSpecInstsAdded 1983556 # Number of non-speculative instructions added to the IQ
729system.cpu.iq.iqInstsIssued 122912009 # Number of instructions issued
730system.cpu.iq.iqSquashedInstsIssued 167105 # Number of squashed instructions issued
731system.cpu.iq.iqSquashedInstsExamined 18943027 # Number of squashed instructions iterated over during squash; mainly for profiling
732system.cpu.iq.iqSquashedOperandsExamined 47293965 # Number of squashed operands that are examined and possibly removed from graph
733system.cpu.iq.iqSquashedNonSpecRemoved 501256 # Number of squashed non-spec instructions that were removed
734system.cpu.iq.issued_per_cycle::samples 150589774 # Number of insts issued each cycle
735system.cpu.iq.issued_per_cycle::mean 0.816204 # Number of insts issued each cycle
736system.cpu.iq.issued_per_cycle::stdev 1.532969 # Number of insts issued each cycle
737system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
738system.cpu.iq.issued_per_cycle::0 106863631 70.96% 70.96% # Number of insts issued each cycle
739system.cpu.iq.issued_per_cycle::1 13450296 8.93% 79.90% # Number of insts issued each cycle
740system.cpu.iq.issued_per_cycle::2 6941050 4.61% 84.50% # Number of insts issued each cycle
741system.cpu.iq.issued_per_cycle::3 5871130 3.90% 88.40% # Number of insts issued each cycle
742system.cpu.iq.issued_per_cycle::4 12365050 8.21% 96.61% # Number of insts issued each cycle
743system.cpu.iq.issued_per_cycle::5 2809227 1.87% 98.48% # Number of insts issued each cycle
744system.cpu.iq.issued_per_cycle::6 1693786 1.12% 99.60% # Number of insts issued each cycle
745system.cpu.iq.issued_per_cycle::7 467660 0.31% 99.92% # Number of insts issued each cycle
746system.cpu.iq.issued_per_cycle::8 127944 0.08% 100.00% # Number of insts issued each cycle
747system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
748system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
749system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
750system.cpu.iq.issued_per_cycle::total 150589774 # Number of insts issued each cycle
751system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
752system.cpu.iq.fu_full::IntAlu 62506 0.71% 0.71% # attempts to use FU when none available
753system.cpu.iq.fu_full::IntMult 5 0.00% 0.71% # attempts to use FU when none available
754system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available
755system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available
756system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available
757system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available
758system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available
759system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available
760system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
761system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available

--- 11 unchanged lines hidden (view full) ---

773system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available
774system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available
775system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available
776system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available
777system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available
778system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available
779system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available
780system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available
781system.cpu.iq.fu_full::MemRead 8370674 94.63% 95.33% # attempts to use FU when none available
782system.cpu.iq.fu_full::MemWrite 412716 4.67% 100.00% # attempts to use FU when none available
783system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
784system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
785system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued
786system.cpu.iq.FU_type_0::IntAlu 57621227 46.88% 47.18% # Type of FU issued
787system.cpu.iq.FU_type_0::IntMult 93185 0.08% 47.25% # Type of FU issued
788system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued
789system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued
790system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued
791system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.25% # Type of FU issued
792system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.25% # Type of FU issued
793system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.25% # Type of FU issued
794system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.25% # Type of FU issued
795system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.25% # Type of FU issued
796system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Type of FU issued
797system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued
798system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued
799system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued
800system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.25% # Type of FU issued
801system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued
802system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued
803system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued
804system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.25% # Type of FU issued
805system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued
806system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued
807system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued
808system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued
809system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued
810system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued
811system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.25% # Type of FU issued
812system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued
813system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.25% # Type of FU issued
814system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued
815system.cpu.iq.FU_type_0::MemRead 52514471 42.73% 89.98% # Type of FU issued
816system.cpu.iq.FU_type_0::MemWrite 12317293 10.02% 100.00% # Type of FU issued
817system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
818system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
819system.cpu.iq.FU_type_0::total 122912009 # Type of FU issued
820system.cpu.iq.rate 0.259812 # Inst issue rate
821system.cpu.iq.fu_busy_cnt 8845901 # FU busy when requested
822system.cpu.iq.fu_busy_rate 0.071969 # FU busy rate (busy events/executed inst)
823system.cpu.iq.int_inst_queue_reads 405483238 # Number of integer instruction queue reads
824system.cpu.iq.int_inst_queue_writes 116066435 # Number of integer instruction queue writes
825system.cpu.iq.int_inst_queue_wakeup_accesses 85469374 # Number of integer instruction queue wakeup accesses
826system.cpu.iq.fp_inst_queue_reads 23342 # Number of floating instruction queue reads
827system.cpu.iq.fp_inst_queue_writes 12510 # Number of floating instruction queue writes
828system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
829system.cpu.iq.int_alu_accesses 131381798 # Number of integer alu accesses
830system.cpu.iq.fp_alu_accesses 12446 # Number of floating point alu accesses
831system.cpu.iew.lsq.thread0.forwLoads 624501 # Number of loads that had data forwarded from stores
832system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
833system.cpu.iew.lsq.thread0.squashedLoads 4071224 # Number of loads squashed
834system.cpu.iew.lsq.thread0.ignoredResponses 6576 # Number of memory responses ignored because the instruction is squashed
835system.cpu.iew.lsq.thread0.memOrderViolation 30290 # Number of memory ordering violations
836system.cpu.iew.lsq.thread0.squashedStores 1572736 # Number of stores squashed
837system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
838system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
839system.cpu.iew.lsq.thread0.rescheduledLoads 34107774 # Number of loads that were rescheduled
840system.cpu.iew.lsq.thread0.cacheBlocked 679836 # Number of times an access to memory failed due to the cache being blocked
841system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
842system.cpu.iew.iewSquashCycles 3038489 # Number of cycles IEW is squashing
843system.cpu.iew.iewBlockCycles 29300006 # Number of cycles IEW is blocking
844system.cpu.iew.iewUnblockCycles 434231 # Number of cycles IEW is unblocking
845system.cpu.iew.iewDispatchedInsts 97327801 # Number of instructions dispatched to IQ
846system.cpu.iew.iewDispSquashedInsts 206590 # Number of squashed instructions skipped by dispatch
847system.cpu.iew.iewDispLoadInsts 19725062 # Number of dispatched load instructions
848system.cpu.iew.iewDispStoreInsts 13304379 # Number of dispatched store instructions
849system.cpu.iew.iewDispNonSpecInsts 1410590 # Number of dispatched non-speculative instructions
850system.cpu.iew.iewIQFullEvents 113060 # Number of times the IQ has become full, causing a stall
851system.cpu.iew.iewLSQFullEvents 3500 # Number of times the LSQ has become full, causing a stall
852system.cpu.iew.memOrderViolationEvents 30290 # Number of memory order violations
853system.cpu.iew.predictedTakenIncorrect 351701 # Number of branches that were predicted taken incorrectly
854system.cpu.iew.predictedNotTakenIncorrect 268555 # Number of branches that were predicted not taken incorrectly
855system.cpu.iew.branchMispredicts 620256 # Number of branch mispredicts detected at execute
856system.cpu.iew.iewExecutedInsts 120832629 # Number of executed instructions
857system.cpu.iew.iewExecLoadInsts 51875152 # Number of load instructions executed
858system.cpu.iew.iewExecSquashedInsts 2079380 # Number of squashed instructions skipped in execute
859system.cpu.iew.exec_swp 0 # number of swp insts executed
860system.cpu.iew.exec_nop 221034 # number of nop insts executed
861system.cpu.iew.exec_refs 64084349 # number of memory reference insts executed
862system.cpu.iew.exec_branches 11474602 # Number of branches executed
863system.cpu.iew.exec_stores 12209197 # Number of stores executed
864system.cpu.iew.exec_rate 0.255417 # Inst execution rate
865system.cpu.iew.wb_sent 119890042 # cumulative count of insts sent to commit
866system.cpu.iew.wb_count 85479670 # cumulative count of insts written-back
867system.cpu.iew.wb_producers 47030253 # num instructions producing a value
868system.cpu.iew.wb_consumers 87881540 # num instructions consuming a value
869system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
870system.cpu.iew.wb_rate 0.180687 # insts written-back per cycle
871system.cpu.iew.wb_fanout 0.535155 # average fanout of values written-back
872system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
873system.cpu.commit.commitSquashedInsts 18673473 # The number of squashed insts skipped by commit
874system.cpu.commit.commitNonSpecStalls 1482300 # The number of times commit has been forced to stall to communicate backwards
875system.cpu.commit.branchMispredicts 535675 # The number of times a branch was mispredicted
876system.cpu.commit.committed_per_cycle::samples 147551285 # Number of insts commited each cycle
877system.cpu.commit.committed_per_cycle::mean 0.526914 # Number of insts commited each cycle
878system.cpu.commit.committed_per_cycle::stdev 1.516633 # Number of insts commited each cycle
879system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
880system.cpu.commit.committed_per_cycle::0 120109216 81.40% 81.40% # Number of insts commited each cycle
881system.cpu.commit.committed_per_cycle::1 13315885 9.02% 90.43% # Number of insts commited each cycle
882system.cpu.commit.committed_per_cycle::2 3896468 2.64% 93.07% # Number of insts commited each cycle
883system.cpu.commit.committed_per_cycle::3 2118661 1.44% 94.50% # Number of insts commited each cycle
884system.cpu.commit.committed_per_cycle::4 1945134 1.32% 95.82% # Number of insts commited each cycle
885system.cpu.commit.committed_per_cycle::5 977268 0.66% 96.48% # Number of insts commited each cycle
886system.cpu.commit.committed_per_cycle::6 1587082 1.08% 97.56% # Number of insts commited each cycle
887system.cpu.commit.committed_per_cycle::7 719968 0.49% 98.05% # Number of insts commited each cycle
888system.cpu.commit.committed_per_cycle::8 2881603 1.95% 100.00% # Number of insts commited each cycle
889system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
890system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
891system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
892system.cpu.commit.committed_per_cycle::total 147551285 # Number of insts commited each cycle
893system.cpu.commit.committedInsts 60455941 # Number of instructions committed
894system.cpu.commit.committedOps 77746772 # Number of ops (including micro ops) committed
895system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
896system.cpu.commit.refs 27385481 # Number of memory references committed
897system.cpu.commit.loads 15653838 # Number of loads committed
898system.cpu.commit.membars 403568 # Number of memory barriers committed
899system.cpu.commit.branches 9961054 # Number of branches committed
900system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
901system.cpu.commit.int_insts 68852229 # Number of committed integer instructions.
902system.cpu.commit.function_calls 991205 # Number of function calls committed.
903system.cpu.commit.bw_lim_events 2881603 # number cycles where commit BW limit reached
904system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
905system.cpu.rob.rob_reads 239241509 # The number of ROB reads
906system.cpu.rob.rob_writes 195965670 # The number of ROB writes
907system.cpu.timesIdled 1778644 # Number of times that the entire CPU went into an idle state and unscheduled itself
908system.cpu.idleCycles 322490663 # Total number of cycles that the CPU has spent unscheduled due to idling
909system.cpu.quiesceCycles 4575455632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
910system.cpu.committedInsts 60305560 # Number of Instructions Simulated
911system.cpu.committedOps 77596391 # Number of Ops (including micro ops) Simulated
912system.cpu.committedInsts_total 60305560 # Number of Instructions Simulated
913system.cpu.cpi 7.844723 # CPI: Cycles Per Instruction
914system.cpu.cpi_total 7.844723 # CPI: Total CPI of All Threads
915system.cpu.ipc 0.127474 # IPC: Instructions Per Cycle
916system.cpu.ipc_total 0.127474 # IPC: Total IPC of All Threads
917system.cpu.int_regfile_reads 547265501 # number of integer regfile reads
918system.cpu.int_regfile_writes 87536109 # number of integer regfile writes
919system.cpu.fp_regfile_reads 8349 # number of floating regfile reads
920system.cpu.fp_regfile_writes 2916 # number of floating regfile writes
921system.cpu.misc_regfile_reads 30123194 # number of misc regfile reads
922system.cpu.misc_regfile_writes 831835 # number of misc regfile writes
923system.cpu.toL2Bus.throughput 58892076 # Throughput (bytes/s)
924system.cpu.toL2Bus.trans_dist::ReadReq 2657368 # Transaction distribution
925system.cpu.toL2Bus.trans_dist::ReadResp 2657367 # Transaction distribution
926system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution
927system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution
928system.cpu.toL2Bus.trans_dist::Writeback 607864 # Transaction distribution
929system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution
930system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
931system.cpu.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution
932system.cpu.toL2Bus.trans_dist::ReadExReq 246095 # Transaction distribution
933system.cpu.toL2Bus.trans_dist::ReadExResp 246095 # Transaction distribution
934system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1959479 # Packet count per connected master and slave (bytes)
935system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796858 # Packet count per connected master and slave (bytes)
936system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30970 # Packet count per connected master and slave (bytes)
937system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 126903 # Packet count per connected master and slave (bytes)
938system.cpu.toL2Bus.pkt_count::total 7914210 # Packet count per connected master and slave (bytes)
939system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62665920 # Cumulative packet size per connected master and slave (bytes)
940system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85541397 # Cumulative packet size per connected master and slave (bytes)
941system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42108 # Cumulative packet size per connected master and slave (bytes)
942system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 209624 # Cumulative packet size per connected master and slave (bytes)
943system.cpu.toL2Bus.tot_pkt_size::total 148459049 # Cumulative packet size per connected master and slave (bytes)
944system.cpu.toL2Bus.data_through_bus 148459049 # Total data (bytes)
945system.cpu.toL2Bus.snoop_data_through_bus 202780 # Total snoop data (bytes)
946system.cpu.toL2Bus.reqLayer0.occupancy 3128672900 # Layer occupancy (ticks)
947system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
948system.cpu.toL2Bus.respLayer0.occupancy 1473318251 # Layer occupancy (ticks)
949system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
950system.cpu.toL2Bus.respLayer1.occupancy 2559248308 # Layer occupancy (ticks)
951system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
952system.cpu.toL2Bus.respLayer2.occupancy 20450735 # Layer occupancy (ticks)
953system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
954system.cpu.toL2Bus.respLayer3.occupancy 74607301 # Layer occupancy (ticks)
955system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
956system.cpu.icache.tags.replacements 979660 # number of replacements
957system.cpu.icache.tags.tagsinuse 511.583533 # Cycle average of tags in use
958system.cpu.icache.tags.total_refs 10456897 # Total number of references to valid blocks.
959system.cpu.icache.tags.sampled_refs 980172 # Sample count of references to valid blocks.
960system.cpu.icache.tags.avg_refs 10.668431 # Average number of references to valid blocks.
961system.cpu.icache.tags.warmup_cycle 6854161250 # Cycle when the warmup percentage was hit.
962system.cpu.icache.tags.occ_blocks::cpu.inst 511.583533 # Average occupied blocks per requestor
963system.cpu.icache.tags.occ_percent::cpu.inst 0.999187 # Average percentage of cache occupancy
964system.cpu.icache.tags.occ_percent::total 0.999187 # Average percentage of cache occupancy
965system.cpu.icache.ReadReq_hits::cpu.inst 10456897 # number of ReadReq hits
966system.cpu.icache.ReadReq_hits::total 10456897 # number of ReadReq hits
967system.cpu.icache.demand_hits::cpu.inst 10456897 # number of demand (read+write) hits
968system.cpu.icache.demand_hits::total 10456897 # number of demand (read+write) hits
969system.cpu.icache.overall_hits::cpu.inst 10456897 # number of overall hits
970system.cpu.icache.overall_hits::total 10456897 # number of overall hits
971system.cpu.icache.ReadReq_misses::cpu.inst 1059959 # number of ReadReq misses
972system.cpu.icache.ReadReq_misses::total 1059959 # number of ReadReq misses
973system.cpu.icache.demand_misses::cpu.inst 1059959 # number of demand (read+write) misses
974system.cpu.icache.demand_misses::total 1059959 # number of demand (read+write) misses
975system.cpu.icache.overall_misses::cpu.inst 1059959 # number of overall misses
976system.cpu.icache.overall_misses::total 1059959 # number of overall misses
977system.cpu.icache.ReadReq_miss_latency::cpu.inst 14263664434 # number of ReadReq miss cycles
978system.cpu.icache.ReadReq_miss_latency::total 14263664434 # number of ReadReq miss cycles
979system.cpu.icache.demand_miss_latency::cpu.inst 14263664434 # number of demand (read+write) miss cycles
980system.cpu.icache.demand_miss_latency::total 14263664434 # number of demand (read+write) miss cycles
981system.cpu.icache.overall_miss_latency::cpu.inst 14263664434 # number of overall miss cycles
982system.cpu.icache.overall_miss_latency::total 14263664434 # number of overall miss cycles
983system.cpu.icache.ReadReq_accesses::cpu.inst 11516856 # number of ReadReq accesses(hits+misses)
984system.cpu.icache.ReadReq_accesses::total 11516856 # number of ReadReq accesses(hits+misses)
985system.cpu.icache.demand_accesses::cpu.inst 11516856 # number of demand (read+write) accesses
986system.cpu.icache.demand_accesses::total 11516856 # number of demand (read+write) accesses
987system.cpu.icache.overall_accesses::cpu.inst 11516856 # number of overall (read+write) accesses
988system.cpu.icache.overall_accesses::total 11516856 # number of overall (read+write) accesses
989system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092035 # miss rate for ReadReq accesses
990system.cpu.icache.ReadReq_miss_rate::total 0.092035 # miss rate for ReadReq accesses
991system.cpu.icache.demand_miss_rate::cpu.inst 0.092035 # miss rate for demand accesses
992system.cpu.icache.demand_miss_rate::total 0.092035 # miss rate for demand accesses
993system.cpu.icache.overall_miss_rate::cpu.inst 0.092035 # miss rate for overall accesses
994system.cpu.icache.overall_miss_rate::total 0.092035 # miss rate for overall accesses
995system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13456.807701 # average ReadReq miss latency
996system.cpu.icache.ReadReq_avg_miss_latency::total 13456.807701 # average ReadReq miss latency
997system.cpu.icache.demand_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
998system.cpu.icache.demand_avg_miss_latency::total 13456.807701 # average overall miss latency
999system.cpu.icache.overall_avg_miss_latency::cpu.inst 13456.807701 # average overall miss latency
1000system.cpu.icache.overall_avg_miss_latency::total 13456.807701 # average overall miss latency
1001system.cpu.icache.blocked_cycles::no_mshrs 7134 # number of cycles access was blocked
1002system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1003system.cpu.icache.blocked::no_mshrs 370 # number of cycles access was blocked
1004system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
1005system.cpu.icache.avg_blocked_cycles::no_mshrs 19.281081 # average number of cycles each access was blocked
1006system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1007system.cpu.icache.fast_writes 0 # number of fast writes performed
1008system.cpu.icache.cache_copies 0 # number of cache copies performed
1009system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79754 # number of ReadReq MSHR hits
1010system.cpu.icache.ReadReq_mshr_hits::total 79754 # number of ReadReq MSHR hits
1011system.cpu.icache.demand_mshr_hits::cpu.inst 79754 # number of demand (read+write) MSHR hits
1012system.cpu.icache.demand_mshr_hits::total 79754 # number of demand (read+write) MSHR hits
1013system.cpu.icache.overall_mshr_hits::cpu.inst 79754 # number of overall MSHR hits
1014system.cpu.icache.overall_mshr_hits::total 79754 # number of overall MSHR hits
1015system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980205 # number of ReadReq MSHR misses
1016system.cpu.icache.ReadReq_mshr_misses::total 980205 # number of ReadReq MSHR misses
1017system.cpu.icache.demand_mshr_misses::cpu.inst 980205 # number of demand (read+write) MSHR misses
1018system.cpu.icache.demand_mshr_misses::total 980205 # number of demand (read+write) MSHR misses
1019system.cpu.icache.overall_mshr_misses::cpu.inst 980205 # number of overall MSHR misses
1020system.cpu.icache.overall_mshr_misses::total 980205 # number of overall MSHR misses
1021system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11579661493 # number of ReadReq MSHR miss cycles
1022system.cpu.icache.ReadReq_mshr_miss_latency::total 11579661493 # number of ReadReq MSHR miss cycles
1023system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11579661493 # number of demand (read+write) MSHR miss cycles
1024system.cpu.icache.demand_mshr_miss_latency::total 11579661493 # number of demand (read+write) MSHR miss cycles
1025system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11579661493 # number of overall MSHR miss cycles
1026system.cpu.icache.overall_mshr_miss_latency::total 11579661493 # number of overall MSHR miss cycles
1027system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8708000 # number of ReadReq MSHR uncacheable cycles
1028system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8708000 # number of ReadReq MSHR uncacheable cycles
1029system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8708000 # number of overall MSHR uncacheable cycles
1030system.cpu.icache.overall_mshr_uncacheable_latency::total 8708000 # number of overall MSHR uncacheable cycles
1031system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for ReadReq accesses
1032system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085110 # mshr miss rate for ReadReq accesses
1033system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for demand accesses
1034system.cpu.icache.demand_mshr_miss_rate::total 0.085110 # mshr miss rate for demand accesses
1035system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085110 # mshr miss rate for overall accesses
1036system.cpu.icache.overall_mshr_miss_rate::total 0.085110 # mshr miss rate for overall accesses
1037system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11813.509922 # average ReadReq mshr miss latency
1038system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11813.509922 # average ReadReq mshr miss latency
1039system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
1040system.cpu.icache.demand_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
1041system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11813.509922 # average overall mshr miss latency
1042system.cpu.icache.overall_avg_mshr_miss_latency::total 11813.509922 # average overall mshr miss latency
1043system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1044system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1045system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1046system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1047system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1048system.cpu.l2cache.tags.replacements 64363 # number of replacements
1049system.cpu.l2cache.tags.tagsinuse 51374.109919 # Cycle average of tags in use
1050system.cpu.l2cache.tags.total_refs 1885226 # Total number of references to valid blocks.
1051system.cpu.l2cache.tags.sampled_refs 129755 # Sample count of references to valid blocks.
1052system.cpu.l2cache.tags.avg_refs 14.529120 # Average number of references to valid blocks.
1053system.cpu.l2cache.tags.warmup_cycle 2489241302000 # Cycle when the warmup percentage was hit.
1054system.cpu.l2cache.tags.occ_blocks::writebacks 36927.111680 # Average occupied blocks per requestor
1055system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 38.632288 # Average occupied blocks per requestor
1056system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000370 # Average occupied blocks per requestor
1057system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.183198 # Average occupied blocks per requestor
1058system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.182382 # Average occupied blocks per requestor
1059system.cpu.l2cache.tags.occ_percent::writebacks 0.563463 # Average percentage of cache occupancy
1060system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000589 # Average percentage of cache occupancy
1061system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
1062system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124713 # Average percentage of cache occupancy
1063system.cpu.l2cache.tags.occ_percent::cpu.data 0.095141 # Average percentage of cache occupancy
1064system.cpu.l2cache.tags.occ_percent::total 0.783907 # Average percentage of cache occupancy
1065system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52355 # number of ReadReq hits
1066system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10525 # number of ReadReq hits
1067system.cpu.l2cache.ReadReq_hits::cpu.inst 966696 # number of ReadReq hits
1068system.cpu.l2cache.ReadReq_hits::cpu.data 387308 # number of ReadReq hits
1069system.cpu.l2cache.ReadReq_hits::total 1416884 # number of ReadReq hits
1070system.cpu.l2cache.Writeback_hits::writebacks 607864 # number of Writeback hits
1071system.cpu.l2cache.Writeback_hits::total 607864 # number of Writeback hits
1072system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits
1073system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits
1074system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits
1075system.cpu.l2cache.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits
1076system.cpu.l2cache.ReadExReq_hits::cpu.data 112905 # number of ReadExReq hits
1077system.cpu.l2cache.ReadExReq_hits::total 112905 # number of ReadExReq hits
1078system.cpu.l2cache.demand_hits::cpu.dtb.walker 52355 # number of demand (read+write) hits
1079system.cpu.l2cache.demand_hits::cpu.itb.walker 10525 # number of demand (read+write) hits
1080system.cpu.l2cache.demand_hits::cpu.inst 966696 # number of demand (read+write) hits
1081system.cpu.l2cache.demand_hits::cpu.data 500213 # number of demand (read+write) hits
1082system.cpu.l2cache.demand_hits::total 1529789 # number of demand (read+write) hits
1083system.cpu.l2cache.overall_hits::cpu.dtb.walker 52355 # number of overall hits
1084system.cpu.l2cache.overall_hits::cpu.itb.walker 10525 # number of overall hits
1085system.cpu.l2cache.overall_hits::cpu.inst 966696 # number of overall hits
1086system.cpu.l2cache.overall_hits::cpu.data 500213 # number of overall hits
1087system.cpu.l2cache.overall_hits::total 1529789 # number of overall hits
1088system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses
1089system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
1090system.cpu.l2cache.ReadReq_misses::cpu.inst 12341 # number of ReadReq misses
1091system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses
1092system.cpu.l2cache.ReadReq_misses::total 23117 # number of ReadReq misses
1093system.cpu.l2cache.UpgradeReq_misses::cpu.data 2916 # number of UpgradeReq misses
1094system.cpu.l2cache.UpgradeReq_misses::total 2916 # number of UpgradeReq misses
1095system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
1096system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
1097system.cpu.l2cache.ReadExReq_misses::cpu.data 133190 # number of ReadExReq misses
1098system.cpu.l2cache.ReadExReq_misses::total 133190 # number of ReadExReq misses
1099system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses
1100system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
1101system.cpu.l2cache.demand_misses::cpu.inst 12341 # number of demand (read+write) misses
1102system.cpu.l2cache.demand_misses::cpu.data 143913 # number of demand (read+write) misses
1103system.cpu.l2cache.demand_misses::total 156307 # number of demand (read+write) misses
1104system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses
1105system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
1106system.cpu.l2cache.overall_misses::cpu.inst 12341 # number of overall misses
1107system.cpu.l2cache.overall_misses::cpu.data 143913 # number of overall misses
1108system.cpu.l2cache.overall_misses::total 156307 # number of overall misses
1109system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4640000 # number of ReadReq miss cycles
1110system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 130250 # number of ReadReq miss cycles
1111system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 910966750 # number of ReadReq miss cycles
1112system.cpu.l2cache.ReadReq_miss_latency::cpu.data 788627999 # number of ReadReq miss cycles
1113system.cpu.l2cache.ReadReq_miss_latency::total 1704364999 # number of ReadReq miss cycles
1114system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395483 # number of UpgradeReq miss cycles
1115system.cpu.l2cache.UpgradeReq_miss_latency::total 395483 # number of UpgradeReq miss cycles
1116system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9130512743 # number of ReadExReq miss cycles
1117system.cpu.l2cache.ReadExReq_miss_latency::total 9130512743 # number of ReadExReq miss cycles
1118system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4640000 # number of demand (read+write) miss cycles
1119system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 130250 # number of demand (read+write) miss cycles
1120system.cpu.l2cache.demand_miss_latency::cpu.inst 910966750 # number of demand (read+write) miss cycles
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1122system.cpu.l2cache.demand_miss_latency::total 10834877742 # number of demand (read+write) miss cycles
1123system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4640000 # number of overall miss cycles
1124system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 130250 # number of overall miss cycles
1125system.cpu.l2cache.overall_miss_latency::cpu.inst 910966750 # number of overall miss cycles
1126system.cpu.l2cache.overall_miss_latency::cpu.data 9919140742 # number of overall miss cycles
1127system.cpu.l2cache.overall_miss_latency::total 10834877742 # number of overall miss cycles
1128system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 52406 # number of ReadReq accesses(hits+misses)
1129system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10527 # number of ReadReq accesses(hits+misses)
1130system.cpu.l2cache.ReadReq_accesses::cpu.inst 979037 # number of ReadReq accesses(hits+misses)
1131system.cpu.l2cache.ReadReq_accesses::cpu.data 398031 # number of ReadReq accesses(hits+misses)
1132system.cpu.l2cache.ReadReq_accesses::total 1440001 # number of ReadReq accesses(hits+misses)
1133system.cpu.l2cache.Writeback_accesses::writebacks 607864 # number of Writeback accesses(hits+misses)
1134system.cpu.l2cache.Writeback_accesses::total 607864 # number of Writeback accesses(hits+misses)
1135system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2955 # number of UpgradeReq accesses(hits+misses)
1136system.cpu.l2cache.UpgradeReq_accesses::total 2955 # number of UpgradeReq accesses(hits+misses)
1137system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
1138system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
1139system.cpu.l2cache.ReadExReq_accesses::cpu.data 246095 # number of ReadExReq accesses(hits+misses)
1140system.cpu.l2cache.ReadExReq_accesses::total 246095 # number of ReadExReq accesses(hits+misses)
1141system.cpu.l2cache.demand_accesses::cpu.dtb.walker 52406 # number of demand (read+write) accesses
1142system.cpu.l2cache.demand_accesses::cpu.itb.walker 10527 # number of demand (read+write) accesses
1143system.cpu.l2cache.demand_accesses::cpu.inst 979037 # number of demand (read+write) accesses
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1146system.cpu.l2cache.overall_accesses::cpu.dtb.walker 52406 # number of overall (read+write) accesses
1147system.cpu.l2cache.overall_accesses::cpu.itb.walker 10527 # number of overall (read+write) accesses
1148system.cpu.l2cache.overall_accesses::cpu.inst 979037 # number of overall (read+write) accesses
1149system.cpu.l2cache.overall_accesses::cpu.data 644126 # number of overall (read+write) accesses
1150system.cpu.l2cache.overall_accesses::total 1686096 # number of overall (read+write) accesses
1151system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000973 # miss rate for ReadReq accesses
1152system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000190 # miss rate for ReadReq accesses
1153system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012605 # miss rate for ReadReq accesses
1154system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026940 # miss rate for ReadReq accesses
1155system.cpu.l2cache.ReadReq_miss_rate::total 0.016053 # miss rate for ReadReq accesses
1156system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986802 # miss rate for UpgradeReq accesses
1157system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986802 # miss rate for UpgradeReq accesses
1158system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.181818 # miss rate for SCUpgradeReq accesses
1159system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses
1160system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541214 # miss rate for ReadExReq accesses
1161system.cpu.l2cache.ReadExReq_miss_rate::total 0.541214 # miss rate for ReadExReq accesses
1162system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000973 # miss rate for demand accesses
1163system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000190 # miss rate for demand accesses
1164system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012605 # miss rate for demand accesses
1165system.cpu.l2cache.demand_miss_rate::cpu.data 0.223424 # miss rate for demand accesses
1166system.cpu.l2cache.demand_miss_rate::total 0.092703 # miss rate for demand accesses
1167system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000973 # miss rate for overall accesses
1168system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000190 # miss rate for overall accesses
1169system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012605 # miss rate for overall accesses
1170system.cpu.l2cache.overall_miss_rate::cpu.data 0.223424 # miss rate for overall accesses
1171system.cpu.l2cache.overall_miss_rate::total 0.092703 # miss rate for overall accesses
1172system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 90980.392157 # average ReadReq miss latency
1173system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65125 # average ReadReq miss latency
1174system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73816.283121 # average ReadReq miss latency
1175system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73545.462930 # average ReadReq miss latency
1176system.cpu.l2cache.ReadReq_avg_miss_latency::total 73727.776052 # average ReadReq miss latency
1177system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 135.625171 # average UpgradeReq miss latency
1178system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 135.625171 # average UpgradeReq miss latency
1179system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68552.539553 # average ReadExReq miss latency
1180system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68552.539553 # average ReadExReq miss latency
1181system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
1182system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
1183system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
1184system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
1185system.cpu.l2cache.demand_avg_miss_latency::total 69317.930368 # average overall miss latency
1186system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 90980.392157 # average overall miss latency
1187system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65125 # average overall miss latency
1188system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73816.283121 # average overall miss latency
1189system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68924.563743 # average overall miss latency
1190system.cpu.l2cache.overall_avg_miss_latency::total 69317.930368 # average overall miss latency
1191system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1192system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1193system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1194system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1195system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1196system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1197system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1198system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1199system.cpu.l2cache.writebacks::writebacks 59118 # number of writebacks
1200system.cpu.l2cache.writebacks::total 59118 # number of writebacks
1201system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits
1202system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
1203system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
1204system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits
1205system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits
1206system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
1207system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits
1208system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # number of overall MSHR hits
1209system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
1210system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses
1211system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
1212system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12329 # number of ReadReq MSHR misses
1213system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10658 # number of ReadReq MSHR misses
1214system.cpu.l2cache.ReadReq_mshr_misses::total 23040 # number of ReadReq MSHR misses
1215system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2916 # number of UpgradeReq MSHR misses
1216system.cpu.l2cache.UpgradeReq_mshr_misses::total 2916 # number of UpgradeReq MSHR misses
1217system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
1218system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
1219system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133190 # number of ReadExReq MSHR misses
1220system.cpu.l2cache.ReadExReq_mshr_misses::total 133190 # number of ReadExReq MSHR misses
1221system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses
1222system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
1223system.cpu.l2cache.demand_mshr_misses::cpu.inst 12329 # number of demand (read+write) MSHR misses
1224system.cpu.l2cache.demand_mshr_misses::cpu.data 143848 # number of demand (read+write) MSHR misses
1225system.cpu.l2cache.demand_mshr_misses::total 156230 # number of demand (read+write) MSHR misses
1226system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses
1227system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
1228system.cpu.l2cache.overall_mshr_misses::cpu.inst 12329 # number of overall MSHR misses
1229system.cpu.l2cache.overall_mshr_misses::cpu.data 143848 # number of overall MSHR misses
1230system.cpu.l2cache.overall_mshr_misses::total 156230 # number of overall MSHR misses
1231system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3990500 # number of ReadReq MSHR miss cycles
1232system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 105750 # number of ReadReq MSHR miss cycles
1233system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 754066500 # number of ReadReq MSHR miss cycles
1234system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 649417249 # number of ReadReq MSHR miss cycles
1235system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1407579999 # number of ReadReq MSHR miss cycles
1236system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29164415 # number of UpgradeReq MSHR miss cycles
1237system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29164415 # number of UpgradeReq MSHR miss cycles
1238system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
1239system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
1240system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7443119257 # number of ReadExReq MSHR miss cycles
1241system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7443119257 # number of ReadExReq MSHR miss cycles
1242system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3990500 # number of demand (read+write) MSHR miss cycles
1243system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 105750 # number of demand (read+write) MSHR miss cycles
1244system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 754066500 # number of demand (read+write) MSHR miss cycles
1245system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8092536506 # number of demand (read+write) MSHR miss cycles
1246system.cpu.l2cache.demand_mshr_miss_latency::total 8850699256 # number of demand (read+write) MSHR miss cycles
1247system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3990500 # number of overall MSHR miss cycles
1248system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 105750 # number of overall MSHR miss cycles
1249system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 754066500 # number of overall MSHR miss cycles
1250system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8092536506 # number of overall MSHR miss cycles
1251system.cpu.l2cache.overall_mshr_miss_latency::total 8850699256 # number of overall MSHR miss cycles
1252system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6234999 # number of ReadReq MSHR uncacheable cycles
1253system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166923461500 # number of ReadReq MSHR uncacheable cycles
1254system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166929696499 # number of ReadReq MSHR uncacheable cycles
1255system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17446167056 # number of WriteReq MSHR uncacheable cycles
1256system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17446167056 # number of WriteReq MSHR uncacheable cycles
1257system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6234999 # number of overall MSHR uncacheable cycles
1258system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184369628556 # number of overall MSHR uncacheable cycles
1259system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184375863555 # number of overall MSHR uncacheable cycles
1260system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for ReadReq accesses
1261system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses
1262system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for ReadReq accesses
1263system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026777 # mshr miss rate for ReadReq accesses
1264system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016000 # mshr miss rate for ReadReq accesses
1265system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986802 # mshr miss rate for UpgradeReq accesses
1266system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986802 # mshr miss rate for UpgradeReq accesses
1267system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.181818 # mshr miss rate for SCUpgradeReq accesses
1268system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses
1269system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541214 # mshr miss rate for ReadExReq accesses
1270system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541214 # mshr miss rate for ReadExReq accesses
1271system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for demand accesses
1272system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses
1273system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for demand accesses
1274system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for demand accesses
1275system.cpu.l2cache.demand_mshr_miss_rate::total 0.092658 # mshr miss rate for demand accesses
1276system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000973 # mshr miss rate for overall accesses
1277system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses
1278system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012593 # mshr miss rate for overall accesses
1279system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223323 # mshr miss rate for overall accesses
1280system.cpu.l2cache.overall_mshr_miss_rate::total 0.092658 # mshr miss rate for overall accesses
1281system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average ReadReq mshr miss latency
1282system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52875 # average ReadReq mshr miss latency
1283system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61162.016384 # average ReadReq mshr miss latency
1284system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60932.374648 # average ReadReq mshr miss latency
1285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61092.881901 # average ReadReq mshr miss latency
1286system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.514060 # average UpgradeReq mshr miss latency
1287system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.514060 # average UpgradeReq mshr miss latency
1288system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
1289system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
1290system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55883.469157 # average ReadExReq mshr miss latency
1291system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55883.469157 # average ReadExReq mshr miss latency
1292system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
1293system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
1294system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
1295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
1296system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
1297system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 78245.098039 # average overall mshr miss latency
1298system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52875 # average overall mshr miss latency
1299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61162.016384 # average overall mshr miss latency
1300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56257.553153 # average overall mshr miss latency
1301system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56651.726659 # average overall mshr miss latency
1302system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
1303system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1304system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1305system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1306system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1307system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
1308system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1309system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1310system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1311system.cpu.dcache.tags.replacements 643614 # number of replacements
1312system.cpu.dcache.tags.tagsinuse 511.993425 # Cycle average of tags in use
1313system.cpu.dcache.tags.total_refs 21512206 # Total number of references to valid blocks.
1314system.cpu.dcache.tags.sampled_refs 644126 # Sample count of references to valid blocks.
1315system.cpu.dcache.tags.avg_refs 33.397512 # Average number of references to valid blocks.
1316system.cpu.dcache.tags.warmup_cycle 41599250 # Cycle when the warmup percentage was hit.
1317system.cpu.dcache.tags.occ_blocks::cpu.data 511.993425 # Average occupied blocks per requestor
1318system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
1319system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
1320system.cpu.dcache.ReadReq_hits::cpu.data 13760275 # number of ReadReq hits
1321system.cpu.dcache.ReadReq_hits::total 13760275 # number of ReadReq hits
1322system.cpu.dcache.WriteReq_hits::cpu.data 7258497 # number of WriteReq hits
1323system.cpu.dcache.WriteReq_hits::total 7258497 # number of WriteReq hits
1324system.cpu.dcache.LoadLockedReq_hits::cpu.data 242759 # number of LoadLockedReq hits
1325system.cpu.dcache.LoadLockedReq_hits::total 242759 # number of LoadLockedReq hits
1326system.cpu.dcache.StoreCondReq_hits::cpu.data 247596 # number of StoreCondReq hits
1327system.cpu.dcache.StoreCondReq_hits::total 247596 # number of StoreCondReq hits
1328system.cpu.dcache.demand_hits::cpu.data 21018772 # number of demand (read+write) hits
1329system.cpu.dcache.demand_hits::total 21018772 # number of demand (read+write) hits
1330system.cpu.dcache.overall_hits::cpu.data 21018772 # number of overall hits
1331system.cpu.dcache.overall_hits::total 21018772 # number of overall hits
1332system.cpu.dcache.ReadReq_misses::cpu.data 737490 # number of ReadReq misses
1333system.cpu.dcache.ReadReq_misses::total 737490 # number of ReadReq misses
1334system.cpu.dcache.WriteReq_misses::cpu.data 2963456 # number of WriteReq misses
1335system.cpu.dcache.WriteReq_misses::total 2963456 # number of WriteReq misses
1336system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
1337system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
1338system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
1339system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
1340system.cpu.dcache.demand_misses::cpu.data 3700946 # number of demand (read+write) misses
1341system.cpu.dcache.demand_misses::total 3700946 # number of demand (read+write) misses
1342system.cpu.dcache.overall_misses::cpu.data 3700946 # number of overall misses
1343system.cpu.dcache.overall_misses::total 3700946 # number of overall misses
1344system.cpu.dcache.ReadReq_miss_latency::cpu.data 9976636292 # number of ReadReq miss cycles
1345system.cpu.dcache.ReadReq_miss_latency::total 9976636292 # number of ReadReq miss cycles
1346system.cpu.dcache.WriteReq_miss_latency::cpu.data 134760113834 # number of WriteReq miss cycles
1347system.cpu.dcache.WriteReq_miss_latency::total 134760113834 # number of WriteReq miss cycles
1348system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184874750 # number of LoadLockedReq miss cycles
1349system.cpu.dcache.LoadLockedReq_miss_latency::total 184874750 # number of LoadLockedReq miss cycles
1350system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 168002 # number of StoreCondReq miss cycles
1351system.cpu.dcache.StoreCondReq_miss_latency::total 168002 # number of StoreCondReq miss cycles
1352system.cpu.dcache.demand_miss_latency::cpu.data 144736750126 # number of demand (read+write) miss cycles
1353system.cpu.dcache.demand_miss_latency::total 144736750126 # number of demand (read+write) miss cycles
1354system.cpu.dcache.overall_miss_latency::cpu.data 144736750126 # number of overall miss cycles
1355system.cpu.dcache.overall_miss_latency::total 144736750126 # number of overall miss cycles
1356system.cpu.dcache.ReadReq_accesses::cpu.data 14497765 # number of ReadReq accesses(hits+misses)
1357system.cpu.dcache.ReadReq_accesses::total 14497765 # number of ReadReq accesses(hits+misses)
1358system.cpu.dcache.WriteReq_accesses::cpu.data 10221953 # number of WriteReq accesses(hits+misses)
1359system.cpu.dcache.WriteReq_accesses::total 10221953 # number of WriteReq accesses(hits+misses)
1360system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256268 # number of LoadLockedReq accesses(hits+misses)
1361system.cpu.dcache.LoadLockedReq_accesses::total 256268 # number of LoadLockedReq accesses(hits+misses)
1362system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses)
1363system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses)
1364system.cpu.dcache.demand_accesses::cpu.data 24719718 # number of demand (read+write) accesses
1365system.cpu.dcache.demand_accesses::total 24719718 # number of demand (read+write) accesses
1366system.cpu.dcache.overall_accesses::cpu.data 24719718 # number of overall (read+write) accesses
1367system.cpu.dcache.overall_accesses::total 24719718 # number of overall (read+write) accesses
1368system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050869 # miss rate for ReadReq accesses
1369system.cpu.dcache.ReadReq_miss_rate::total 0.050869 # miss rate for ReadReq accesses
1370system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289911 # miss rate for WriteReq accesses
1371system.cpu.dcache.WriteReq_miss_rate::total 0.289911 # miss rate for WriteReq accesses
1372system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052714 # miss rate for LoadLockedReq accesses
1373system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052714 # miss rate for LoadLockedReq accesses
1374system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
1375system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
1376system.cpu.dcache.demand_miss_rate::cpu.data 0.149716 # miss rate for demand accesses
1377system.cpu.dcache.demand_miss_rate::total 0.149716 # miss rate for demand accesses
1378system.cpu.dcache.overall_miss_rate::cpu.data 0.149716 # miss rate for overall accesses
1379system.cpu.dcache.overall_miss_rate::total 0.149716 # miss rate for overall accesses
1380system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13527.825858 # average ReadReq miss latency
1381system.cpu.dcache.ReadReq_avg_miss_latency::total 13527.825858 # average ReadReq miss latency
1382system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45473.971550 # average WriteReq miss latency
1383system.cpu.dcache.WriteReq_avg_miss_latency::total 45473.971550 # average WriteReq miss latency
1384system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.302391 # average LoadLockedReq miss latency
1385system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.302391 # average LoadLockedReq miss latency
1386system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15272.909091 # average StoreCondReq miss latency
1387system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15272.909091 # average StoreCondReq miss latency
1388system.cpu.dcache.demand_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
1389system.cpu.dcache.demand_avg_miss_latency::total 39108.041600 # average overall miss latency
1390system.cpu.dcache.overall_avg_miss_latency::cpu.data 39108.041600 # average overall miss latency
1391system.cpu.dcache.overall_avg_miss_latency::total 39108.041600 # average overall miss latency
1392system.cpu.dcache.blocked_cycles::no_mshrs 31555 # number of cycles access was blocked
1393system.cpu.dcache.blocked_cycles::no_targets 26598 # number of cycles access was blocked
1394system.cpu.dcache.blocked::no_mshrs 2653 # number of cycles access was blocked
1395system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked
1396system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.894082 # average number of cycles each access was blocked
1397system.cpu.dcache.avg_blocked_cycles::no_targets 95.333333 # average number of cycles each access was blocked
1398system.cpu.dcache.fast_writes 0 # number of fast writes performed
1399system.cpu.dcache.cache_copies 0 # number of cache copies performed
1400system.cpu.dcache.writebacks::writebacks 607864 # number of writebacks
1401system.cpu.dcache.writebacks::total 607864 # number of writebacks
1402system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351528 # number of ReadReq MSHR hits
1403system.cpu.dcache.ReadReq_mshr_hits::total 351528 # number of ReadReq MSHR hits
1404system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714505 # number of WriteReq MSHR hits
1405system.cpu.dcache.WriteReq_mshr_hits::total 2714505 # number of WriteReq MSHR hits
1406system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits
1407system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits
1408system.cpu.dcache.demand_mshr_hits::cpu.data 3066033 # number of demand (read+write) MSHR hits
1409system.cpu.dcache.demand_mshr_hits::total 3066033 # number of demand (read+write) MSHR hits
1410system.cpu.dcache.overall_mshr_hits::cpu.data 3066033 # number of overall MSHR hits
1411system.cpu.dcache.overall_mshr_hits::total 3066033 # number of overall MSHR hits
1412system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385962 # number of ReadReq MSHR misses
1413system.cpu.dcache.ReadReq_mshr_misses::total 385962 # number of ReadReq MSHR misses
1414system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248951 # number of WriteReq MSHR misses
1415system.cpu.dcache.WriteReq_mshr_misses::total 248951 # number of WriteReq MSHR misses
1416system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12168 # number of LoadLockedReq MSHR misses
1417system.cpu.dcache.LoadLockedReq_mshr_misses::total 12168 # number of LoadLockedReq MSHR misses
1418system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
1419system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
1420system.cpu.dcache.demand_mshr_misses::cpu.data 634913 # number of demand (read+write) MSHR misses
1421system.cpu.dcache.demand_mshr_misses::total 634913 # number of demand (read+write) MSHR misses
1422system.cpu.dcache.overall_mshr_misses::cpu.data 634913 # number of overall MSHR misses
1423system.cpu.dcache.overall_mshr_misses::total 634913 # number of overall MSHR misses
1424system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4950861635 # number of ReadReq MSHR miss cycles
1425system.cpu.dcache.ReadReq_mshr_miss_latency::total 4950861635 # number of ReadReq MSHR miss cycles
1426system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10610319031 # number of WriteReq MSHR miss cycles
1427system.cpu.dcache.WriteReq_mshr_miss_latency::total 10610319031 # number of WriteReq MSHR miss cycles
1428system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144937500 # number of LoadLockedReq MSHR miss cycles
1429system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144937500 # number of LoadLockedReq MSHR miss cycles
1430system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 145998 # number of StoreCondReq MSHR miss cycles
1431system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 145998 # number of StoreCondReq MSHR miss cycles
1432system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15561180666 # number of demand (read+write) MSHR miss cycles
1433system.cpu.dcache.demand_mshr_miss_latency::total 15561180666 # number of demand (read+write) MSHR miss cycles
1434system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15561180666 # number of overall MSHR miss cycles
1435system.cpu.dcache.overall_mshr_miss_latency::total 15561180666 # number of overall MSHR miss cycles
1436system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182316666500 # number of ReadReq MSHR uncacheable cycles
1437system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182316666500 # number of ReadReq MSHR uncacheable cycles
1438system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26837116532 # number of WriteReq MSHR uncacheable cycles
1439system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26837116532 # number of WriteReq MSHR uncacheable cycles
1440system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209153783032 # number of overall MSHR uncacheable cycles
1441system.cpu.dcache.overall_mshr_uncacheable_latency::total 209153783032 # number of overall MSHR uncacheable cycles
1442system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026622 # mshr miss rate for ReadReq accesses
1443system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026622 # mshr miss rate for ReadReq accesses
1444system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses
1445system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses
1446system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047482 # mshr miss rate for LoadLockedReq accesses
1447system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047482 # mshr miss rate for LoadLockedReq accesses
1448system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
1449system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
1450system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for demand accesses
1451system.cpu.dcache.demand_mshr_miss_rate::total 0.025684 # mshr miss rate for demand accesses
1452system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025684 # mshr miss rate for overall accesses
1453system.cpu.dcache.overall_mshr_miss_rate::total 0.025684 # mshr miss rate for overall accesses
1454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12827.329206 # average ReadReq mshr miss latency
1455system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12827.329206 # average ReadReq mshr miss latency
1456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42620.110106 # average WriteReq mshr miss latency
1457system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42620.110106 # average WriteReq mshr miss latency
1458system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11911.365878 # average LoadLockedReq mshr miss latency
1459system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.365878 # average LoadLockedReq mshr miss latency
1460system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13272.545455 # average StoreCondReq mshr miss latency
1461system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13272.545455 # average StoreCondReq mshr miss latency
1462system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
1463system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
1464system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.154272 # average overall mshr miss latency
1465system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.154272 # average overall mshr miss latency
1466system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1467system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1468system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1469system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1470system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1471system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1473system.iocache.tags.replacements 0 # number of replacements

--- 5 unchanged lines hidden (view full) ---

1479system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1480system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1481system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1482system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1483system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1484system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1485system.iocache.fast_writes 0 # number of fast writes performed
1486system.iocache.cache_copies 0 # number of cache copies performed
1487system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of ReadReq MSHR uncacheable cycles
1488system.iocache.ReadReq_mshr_uncacheable_latency::total 1424415639261 # number of ReadReq MSHR uncacheable cycles
1489system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1424415639261 # number of overall MSHR uncacheable cycles
1490system.iocache.overall_mshr_uncacheable_latency::total 1424415639261 # number of overall MSHR uncacheable cycles
1491system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1492system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1493system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1494system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1495system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1496system.cpu.kern.inst.arm 0 # number of arm instructions executed
1497system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed
1498
1499---------- End Simulation Statistics ----------